Display substrate and preparation method therefor, and display

Abstract

A display substrate and a preparation method therefor, and a display. The display substrate comprises: a first trace (81) disposed on a substrate (10), a first transistor disposed on the side of the first trace (81) away from the substrate (10), and a second trace (82) disposed on the side of the first transistor away from the substrate (10), wherein the first transistor comprises a third trace (71); at least one of the first trace (81), the second trace (82) and the third trace (71) comprises an optical auxiliary structure, the optical auxiliary structure comprising n auxiliary layers, the refractive indexes and materials of adjacent auxiliary layers being different, and n being a natural number greater than or equal to two; and the transmittance of the optical auxiliary structure for natural light is less than 10%.

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Liquid crystal displays (LCDs) have rapidly developed due to their small size, low power consumption, and zero radiation. An LCD panel consists of a cell-aligned thin-film transistor (TFT) array substrate and a color filter (CF) substrate. Liquid crystal (LC) molecules are positioned between the array and CF substrates. Controlling the common electrode and pixel electrodes creates an electric field that drives the liquid crystal deflection, achieving grayscale display.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, including a first routing line arranged on a substrate, a first transistor arranged on a side of the first routing line away from the substrate, a second routing line arranged on a side of the first transistor away from the substrate, the first transistor including a third routing line, at least one of the first routing line, the second routing line and the third routing line including an optical auxiliary structure, the optical auxiliary structure including n auxiliary layers, the refractive index and material between adjacent auxiliary layers being different, n being a natural number greater than or equal to 2; the transmittance of the optical auxiliary structure to natural light is less than 10%.

[0006] In an exemplary embodiment, the optical auxiliary structure includes a first auxiliary layer and a second auxiliary layer, the first auxiliary layer is closer to the substrate than the second auxiliary layer, and the first auxiliary layer has a lower refractive index than the second auxiliary layer.

[0007] In an exemplary embodiment, a difference between a refractive index of the second auxiliary layer and a refractive index of the first auxiliary layer is greater than or equal to 0.7 and less than or equal to 2.5.

[0008] In an exemplary embodiment, the optical auxiliary structure further includes a third auxiliary layer and a fourth auxiliary layer, the third auxiliary layer being located on a side of the second auxiliary layer away from the substrate, the fourth auxiliary layer being located on a side of the third auxiliary layer away from the substrate, the refractive index of the third auxiliary layer being smaller than that of the second auxiliary layer, and the refractive index of the third auxiliary layer being smaller than that of the fourth auxiliary layer.

[0009] In an exemplary embodiment, a difference between a refractive index of the second auxiliary layer and a refractive index of the third auxiliary layer is greater than or equal to 0.7 and less than or equal to 2.5.

[0010] In an exemplary embodiment, a difference between a refractive index of the fourth auxiliary layer and a refractive index of the third auxiliary layer is greater than or equal to 0.7 and less than or equal to 2.5.

[0011] In an exemplary embodiment, a ratio of the thickness of the first auxiliary layer to the thickness of the second auxiliary layer is greater than or equal to 0.8 and less than or equal to 50.

[0012] In an exemplary embodiment, a ratio of the thickness of the second auxiliary layer to the thickness of the third auxiliary layer is greater than or equal to 0.1 and less than or equal to 100.

[0013] In an exemplary embodiment, a ratio of the thickness of the fourth auxiliary layer to the thickness of the third auxiliary layer is greater than or equal to 0.1 and less than or equal to 300.

[0014] In an exemplary embodiment, the first auxiliary layer, the second auxiliary layer, and the third auxiliary layer form a stack pattern, and the fourth auxiliary layer wraps a side surface of the stack pattern and a surface of the stack pattern away from the substrate.

[0015] In an exemplary embodiment, the stacking pattern has a regular trapezoidal shape in a cross section perpendicular to the substrate.

[0016] In an exemplary embodiment, the first auxiliary layer and the third auxiliary layer both extend along a first direction, a minimum distance in a second direction between an edge of an orthographic projection of the third auxiliary layer on the substrate and an edge of an orthographic projection of the first auxiliary layer on the substrate is greater than or equal to 0.01 microns and less than or equal to 0.05 microns, and the first direction intersects the second direction.

[0017] In an exemplary embodiment, an angle formed between a side surface of the stacking pattern and a plane where the substrate is located is greater than or equal to 30 degrees and less than or equal to 80 degrees.

[0018] In an exemplary embodiment, a display area and a non-display area are included, the display area includes the first transistor, the first transistor includes a first active layer arranged on a side of the first routing away from the substrate, the third routing arranged on a side of the first active layer away from the substrate, and a first electrode and a fourth electrode arranged on a side of the third routing away from the substrate; the non-display area includes a second transistor arranged on the substrate, the second transistor includes a second active layer arranged on the substrate, a fourth routing arranged on a side of the second active layer away from the substrate, and a second electrode and a third electrode arranged on a side of the fourth routing away from the substrate.

[0019] In an exemplary embodiment, the fourth trace includes an optical auxiliary structure.

[0020] In an exemplary embodiment, the fourth trace is oxidized.

[0021] In an exemplary embodiment, the first trace and the fourth trace are located in the same film layer.

[0022] In an exemplary embodiment, the first active layer overlaps with the orthographic projection of the third trace on the substrate; and the second active layer overlaps with the orthographic projection of the fourth trace on the substrate.

[0023] In an exemplary embodiment, at least one of the first electrode and the fourth electrode is oxidized.

[0024] In an exemplary embodiment, the second trace overlaps with an orthographic projection of the first electrode on the substrate.

[0025] In an exemplary embodiment, the first electrode is connected to the first active layer through a first via hole, a light shielding block is provided on the second trace, and an orthographic projection of the light shielding block on the substrate includes an orthographic projection of the first via hole on the substrate.

[0026] In an exemplary embodiment, a minimum distance between an edge of an orthographic projection of the light shielding block on the substrate and an edge of an orthographic projection of the first via hole on the substrate is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers.

[0027] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0028] In an exemplary embodiment, a color filter substrate is further included. The color filter substrate is arranged in a cell with the display substrate, and a reflection reduction structure layer is provided on a side of the color filter substrate away from the display substrate.

[0029] In another aspect, the present disclosure further provides a method for preparing a display substrate, comprising:

[0030] forming a first trace on a substrate;

[0031] forming a first transistor on a side of the first wiring away from the substrate, wherein the first transistor includes a third wiring;

[0032] forming a second wiring on a side of the first transistor away from the substrate;

[0033] At least one of the first routing, the second routing and the third routing includes an optical auxiliary structure, the optical auxiliary structure includes n auxiliary layers, the refractive index and material of adjacent auxiliary layers are different, n is a natural number greater than or equal to 2; the transmittance of the optical auxiliary structure to natural light is less than 10%.

[0034] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0036] FIG1 is a schematic diagram of a cross-sectional structure of a display device;

[0037] FIG2 is a schematic diagram of a planar structure of a display device;

[0038] FIG3 is a schematic diagram of a planar structure of a display substrate;

[0039] FIG4 a is a schematic diagram of a reflection reduction mechanism of an optical auxiliary structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0040] FIG4 b is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0041] FIG4c is a schematic cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure;

[0042] FIG5 a is a cross-sectional schematic diagram of a manufacturing process of a display substrate after forming a second active layer according to an exemplary embodiment of the present disclosure;

[0043] FIG5 b is a cross-sectional view of a display substrate manufacturing process after forming a first auxiliary film, a second auxiliary film, and a third auxiliary film according to an exemplary embodiment of the present disclosure;

[0044] FIG5 c is a cross-sectional view of a display substrate after forming a first optical auxiliary structure and a second optical auxiliary structure in a preparation process of an exemplary embodiment of the present disclosure;

[0045] FIG5 d is a cross-sectional schematic diagram of a display substrate preparation process after forming a second optical auxiliary structure according to an exemplary embodiment of the present disclosure;

[0046] FIG5e is a cross-sectional schematic diagram of a manufacturing process of a display substrate after forming a first active layer and a third optical auxiliary structure according to an exemplary embodiment of the present disclosure;

[0047] FIG6 a is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0048] FIG6 b is a schematic diagram of a planar structure of a display substrate after forming a first active layer according to an exemplary embodiment of the present disclosure;

[0049] 6c and 6d are schematic diagrams of a planar structure of a display substrate after a third trace is formed according to an exemplary embodiment of the present disclosure;

[0050] 6e and 6f are schematic diagrams of a planar structure of a display substrate after forming a first electrode according to an exemplary embodiment of the present disclosure;

[0051] 6g and 6h are schematic diagrams of a planar structure of a display substrate after forming a fourth electrode according to an exemplary embodiment of the present disclosure;

[0052] 6i and 6j are schematic planar structural diagrams of a display substrate after pixel electrodes are formed according to an exemplary embodiment of the present disclosure;

[0053] 6k and 61 are schematic diagrams of a planar structure of a display substrate after forming a second wiring according to an exemplary embodiment of the present disclosure;

[0054] FIG6m is a schematic diagram of a planar structure of a display substrate after forming a common electrode according to an exemplary embodiment of the present disclosure;

[0055] FIG6n is a schematic planar structural diagram of a second wiring of another display substrate according to an exemplary embodiment of the present disclosure;

[0056] FIG7 is a schematic diagram of a planar structure of a display device according to an exemplary embodiment of the present disclosure;

[0057] FIG8 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure;

[0058] FIG9 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure;

[0059] FIG10 is a schematic diagram of a planar structure of a display device according to an exemplary embodiment of the present disclosure;

[0060] FIG11 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure;

[0061] FIG12 is a schematic plan view showing the structure of a third optical auxiliary structure and a fourth optical auxiliary structure in a substrate according to an exemplary embodiment of the present disclosure;

[0062] FIG13 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure;

[0063] FIG14 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure;

[0064] FIG15 is a schematic diagram showing a planar structure of a seventh auxiliary layer and a fifth auxiliary layer in a substrate according to an exemplary embodiment of the present disclosure;

[0065] FIG16 is a schematic cross-sectional view of another display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0067] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0068] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0069] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0070] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0071] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0072] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0073] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0074] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0075] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0076] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0077] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0078] Through research conducted by the inventors of the present disclosure, it was found that the metal wires in the display substrate will increase the light reflectivity of the display device and affect the display effect. Generally, a black matrix is ​​provided in the color film substrate to block the light. However, as the resolution of the display device increases, the line width of the black matrix (BM) will reduce the transmittance of the light of the display device. For display devices with ultra-high pixel density (PPI), the black matrix (BM) is limited by the material, the line width of the black matrix (BM) cannot be reduced, and the transmittance of light is low, which affects the display effect. In addition, for display devices with ultra-high pixel density (PPI), the pixel electrode is generally provided below the common electrode, and the distance between the gate and the pixel electrode is relatively close, so crosstalk between the gate and the pixel electrode is likely to occur, affecting the picture quality. For head-mounted display devices with ultra-high pixel density (PPI), such as VR (Virtual Reality) / AR (Augmented Reality) / MR (Mixed Reality) display devices, regulating light transmittance and light reflectivity is particularly important. The inventors of the present disclosure have found that in existing head-mounted display devices, the metal wires of the display substrate are prone to high reflectivity of light, which affects image quality.

[0079] Figure 1 is a schematic cross-sectional view of a display device. As shown in Figure 1, the display device may include a first substrate 100 and a second substrate 200 disposed opposite each other, and a liquid crystal layer 300 disposed between the first substrate 100 and the second substrate 200. The first substrate 100 may include a first structural layer 102 disposed on the side of the first base 10 facing the second substrate 200, and the second substrate 200 may include a second structural layer 202 disposed on the side of the second base 201 facing the first substrate 100.

[0080] In an exemplary embodiment, the first substrate 100 may serve as an array substrate, and the first structure layer 102 may include a third trace, a fifth trace, a thin film transistor, a pixel electrode, and a common electrode. The second substrate 200 may serve as a color filter substrate, and the second structure layer 202 may include a filter layer. The liquid crystal layer 300 may include a plurality of liquid crystal molecules having dielectric anisotropy. In response to an electric field applied between the array substrate and the color filter substrate, the liquid crystal molecules may rotate in a predetermined direction between the array substrate and the color filter substrate, thereby allowing or blocking light transmission.

[0081] Figure 2 is a schematic diagram of the planar structure of a display device. As shown in Figure 2, the display device may include a plurality of pixel units P arranged in a matrix manner, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the three sub-pixels may each include a thin film transistor, a pixel electrode, and a common electrode. In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel emitting red (R) light, the second sub-pixel P2 may be a green sub-pixel emitting green (G) light, and the third sub-pixel P3 may be a blue sub-pixel emitting blue (B) light. The shape of the sub-pixels in the pixel unit may be rectangular, diamond, pentagonal, or hexagonal, etc. The sub-pixels in the pixel unit may be arranged horizontally, vertically, or in a herringbone manner, which is not limited in this disclosure. In an exemplary embodiment, the pixel unit may include four sub-pixels, which is not limited in this disclosure.

[0082] Figure 3 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 3, in an exemplary embodiment, the display substrate includes a display area and a frame area. The display area may include multiple third lines (S1 to Sm) and multiple fifth lines (D1 to Dn). The multiple third lines may extend horizontally and are arranged in sequence along the vertical direction. The multiple fifth lines may extend vertically and are arranged in sequence along the horizontal direction. The multiple intersecting third lines and the multiple fifth lines define a plurality of regularly arranged sub-pixels Pxij, where i and j may be natural numbers. In an exemplary embodiment, at least one sub-pixel Pxij may include a thin film transistor, a pixel electrode, and a common electrode, with the thin film transistor being connected to the third line, the fifth line, and the pixel electrode, respectively.

[0083] In an exemplary embodiment, the display substrate may further include a plurality of common electrode lines (E1 to Eo), which may extend horizontally and be sequentially arranged vertically, and are correspondingly connected to common electrodes in the plurality of sub-pixels Pxij.

[0084] In an exemplary embodiment, a plurality of third lines are led out to the border area and connected to the scan driver, a plurality of fifth lines are led out to the border area and connected to the data driver, and at least a portion of the scan driver and the data driver can be formed on the array substrate.

[0085] In an exemplary embodiment, an external control device (such as a timing controller) may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver. The data driver may use the received grayscale values ​​and control signals to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data driver may use a clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel row basis, where n may be a natural number. The external control device may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The scan driver may use the clock signal, the scan start signal, etc. to generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., and Sm. For example, the scan driver may sequentially provide scan signals having on-level pulses to the scan signal lines S1 to Sm, where m may be a natural number. For example, the scan driver may be configured as a shift register and may generate scan signals by sequentially transmitting the scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of the clock signal.

[0086] The present disclosure provides a display substrate, including a first routing line arranged on a substrate, a first transistor arranged on a side of the first routing line away from the substrate, a second routing line arranged on a side of the first transistor away from the substrate, the first transistor including a third routing line, at least one of the first routing line, the second routing line, and the third routing line including an optical auxiliary structure, the optical auxiliary structure including n auxiliary layers, adjacent auxiliary layers having different refractive indices and materials, where n is a natural number greater than or equal to 2; the optical auxiliary structure has a transmittance of less than 10% to natural light.

[0087] In an exemplary embodiment, natural light includes light having a wavelength of 400 nm to 700 nm.

[0088] In an exemplary embodiment, the optical auxiliary structure includes a first auxiliary layer and a second auxiliary layer, the first auxiliary layer is closer to the substrate than the second auxiliary layer, and the first auxiliary layer has a lower refractive index than the second auxiliary layer.

[0089] In an exemplary embodiment, a difference between a refractive index of the second auxiliary layer and a refractive index of the first auxiliary layer is greater than or equal to 0.7 and less than or equal to 2.5.

[0090] The embodiment of the present disclosure shows that the substrate realizes total reflection adjustment of light by controlling the refractive index difference between the second auxiliary layer and the first auxiliary layer.

[0091] In an exemplary embodiment, the optical auxiliary structure further includes a third auxiliary layer and a fourth auxiliary layer, the third auxiliary layer being located on a side of the second auxiliary layer away from the substrate, the fourth auxiliary layer being located on a side of the third auxiliary layer away from the substrate, the refractive index of the third auxiliary layer being smaller than that of the second auxiliary layer, and the refractive index of the third auxiliary layer being smaller than that of the fourth auxiliary layer.

[0092] In an exemplary embodiment, a difference between a refractive index of the second auxiliary layer and a refractive index of the third auxiliary layer is greater than or equal to 0.7 and less than or equal to 2.5.

[0093] The embodiment of the present disclosure shows that the substrate realizes total reflection adjustment of light by controlling the refractive index difference between the second auxiliary layer and the third auxiliary layer.

[0094] In an exemplary embodiment, a difference between a refractive index of the fourth auxiliary layer and a refractive index of the third auxiliary layer is greater than or equal to 0.7 and less than or equal to 2.5.

[0095] The embodiment of the present disclosure shows that the substrate realizes total reflection adjustment of light by controlling the refractive index difference between the fourth auxiliary layer and the third auxiliary layer.

[0096] Figure 4a is a schematic diagram illustrating the anti-reflection mechanism of an optical auxiliary structure of a display substrate according to an exemplary embodiment of the present disclosure. The anti-reflection mechanism of an optical auxiliary structure comprising four film layers is described as an example. As shown in Figure 4a, the optical auxiliary structure includes a first auxiliary layer 411 disposed on the substrate 10, a second auxiliary layer 412 disposed on the side of the first auxiliary layer 411 facing away from the substrate 10, a third auxiliary layer 413 disposed on the side of the second auxiliary layer 412 facing away from the substrate 10, and a fourth auxiliary layer 414 disposed on the side of the third auxiliary layer 413 facing away from the substrate 10.

[0097] In an exemplary embodiment, the first auxiliary layer 411 and the third auxiliary layer 413 serve as low-refractive-index layers of the optical auxiliary structure, while the second auxiliary layer 412 and the fourth auxiliary layer 414 serve as high-refractive-index layers of the optical auxiliary structure. The refractive index of the first auxiliary layer 411 is lower than that of the second auxiliary layer 412, the refractive index of the third auxiliary layer 413 is lower than that of the second auxiliary layer 412, and the refractive index of the third auxiliary layer 413 is lower than that of the fourth auxiliary layer 414. The film layer of the optical auxiliary structure on the side closest to the substrate 10 is the first auxiliary layer 411, and the film layer on the side away from the substrate 10 is the fourth auxiliary layer 414.

[0098] In the embodiment of the present disclosure, the display substrate is alternately arranged along the direction away from the substrate 10 through the first auxiliary layer 411, the second auxiliary layer 412, the third auxiliary layer 413 and the fourth auxiliary layer 414, so that at least part of the light Li is totally reflected at the surface of the fourth auxiliary layer 414 on the side away from the substrate 10, at the junction of the third auxiliary layer 413 and the fourth auxiliary layer 414, and at the junction of the first auxiliary layer 411 and the second auxiliary layer 412, thereby reducing the light from entering the metal layer in the display substrate, thereby reducing the reflectivity of the metal layer.

[0099] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0100] Figure 4b is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate according to the present disclosure may include a display area 400 and a non-display area 500 surrounding the display area 400. The display area 400 includes a plurality of sub-pixels Pxij forming a pixel array. The plurality of sub-pixels Pxij can be configured to display dynamic images or still images. The display area 100 may be referred to as an active area (AA). The non-display area 500 may include a driver device such as a second transistor.

[0101] In an exemplary embodiment, the display panel includes a display area 100 having a rectangular shape. In some embodiments, the display area 100 may also have a circular shape, an elliptical shape, or a polygonal shape such as a triangle, a pentagon, or the like.

[0102] Figure 4c is a schematic diagram of the cross-sectional structure of a display substrate of an exemplary embodiment of the present disclosure. For a liquid crystal display device, 400 and 500 may be a display area and a non-display area surrounding the display area, respectively. In the display area 400, the active layer of the first transistor may be an oxide material, and in the non-display area 500, for example, the active layer of the second transistor may be a low-temperature polysilicon material. In an exemplary embodiment, the exemplary display substrate of the present disclosure may be an array substrate. As shown in Figure 4c, on a plane perpendicular to the display substrate, the display area 400 includes a first wiring 81 arranged on a substrate 10, a first transistor arranged on a side of the first wiring 81 away from the substrate 10, a pixel electrode 55 and a second wiring 82 arranged on a side of the first transistor away from the substrate 10, and a common electrode 56 arranged on a side of the pixel electrode 55 and the second wiring 82 away from the substrate 10. The non-display area 500 includes a second transistor arranged on the substrate 10.

[0103] In an exemplary embodiment, substrate 10 may include glass, metal, or a polymer resin. When substrate 10 is flexible or bendable, substrate 10 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Various modifications are possible. For example, substrate 10 may have a multilayer structure including two layers each containing such a polymer resin and a barrier layer containing an inorganic material (e.g., silicon oxide, silicon nitride, or silicon oxynitride) between the two layers.

[0104] In an exemplary embodiment, the first transistor includes a first active layer 21 disposed on a side of the first trace 81 away from the substrate 10, a third trace 71 disposed on a side of the first active layer 21 away from the substrate 10, and a first electrode 51 and a fourth electrode 54 disposed on a side of the third trace 71 away from the substrate 10. The first electrode 51 is connected to a first contact terminal of the first active layer 21 through a first via 91. The fourth electrode 54 is connected to a second contact terminal of the first active layer 21 through a fourth via 94, and the fourth electrode 54 is connected to a pixel electrode 55 through a fifth via 95.

[0105] In the exemplary embodiment, both the first trace 81 and the second trace 82 have a light shielding function. The first trace 81 overlaps with the orthographic projection of the first active layer 21 on the substrate, thereby shielding light emitted toward the first active layer 21. The second trace 82 overlaps with the orthographic projection of the first electrode 51 on the substrate, thereby shielding light emitted toward the first electrode 51.

[0106] In an exemplary embodiment, the third wiring 71 overlaps with an orthographic projection of the first active layer 21 on the substrate, and the overlapping region of the third wiring 71 and the first active layer 21 serves as a gate of the first transistor.

[0107] In an exemplary embodiment, the common electrode 56 overlaps with the orthographic projection of the pixel electrode 55 on the substrate 10 . The common electrode 56 overlaps with the orthographic projection of the second trace 82 on the substrate 10 .

[0108] In an exemplary embodiment, the second transistor includes a second active layer 22 disposed on the substrate 10, a fourth trace 72 disposed on a side of the second active layer 22 away from the substrate 10, and a second electrode 52 and a third electrode 53 disposed on a side of the fourth trace 72 away from the substrate 10. The second electrode 52 is connected to the third contact terminal of the second active layer 22 through a second via hole, and the third electrode 53 is connected to the fourth contact terminal of the second active layer 22 through a third via hole.

[0109] In an exemplary embodiment, the fourth wiring 72 overlaps with an orthographic projection of the second active layer 22 on the substrate, and the overlapping region of the fourth wiring 72 and the second active layer 22 serves as a gate of the second transistor.

[0110] In an exemplary embodiment, the first wiring 81 and the fourth wiring 72 are located in the same film layer and can be made of the same material, thereby simplifying the process and reducing production costs.

[0111] In an exemplary embodiment, the first active layer 21 may be made of low-temperature polysilicon (LTPS) or an oxide semiconductor. The second active layer 22 may be made of low-temperature polysilicon (LTPS) or an oxide semiconductor. For example, the first active layer 21 may be made of oxide semiconductor (Oxide), and the second active layer 22 may be made of low-temperature polysilicon (LTPS). The first active layer 21 made of oxide semiconductor (Oxide) has advantages such as low leakage current, and the second active layer 22 made of low-temperature polysilicon has advantages such as high mobility and fast charging. Integrating the first active layer 21 made of oxide semiconductor (Oxide) and the second active layer 22 made of low-temperature polysilicon on a display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0112] In an exemplary embodiment, the exemplary display substrate of the present disclosure includes a substrate 10, a first insulating layer 11 disposed on the substrate 10, a second active layer 22 disposed on a side of the first insulating layer 11 away from the substrate 10, a second insulating layer 12 disposed on a side of the second active layer 22 away from the substrate 10, a first trace 81 and a fourth trace 72 disposed on a side of the second insulating layer 12 away from the substrate 10, a third insulating layer 13 disposed on a side of the first trace 81 and the fourth trace 72 away from the substrate 10, a first active layer 21 disposed on a side of the third insulating layer 13 away from the substrate 10, a fourth insulating layer 14 disposed on a side of the first active layer 21 away from the substrate 10, and a first trace 81 disposed on a side of the fourth insulating layer 14 away from the substrate 10. A third routing line 71 away from the substrate 10, a fifth insulating layer 15 arranged on the side of the third routing line 71 away from the substrate 10, a first conductive layer arranged on the side of the fifth insulating layer 15 away from the substrate 10, a sixth insulating layer 16 arranged on the side of the first conductive layer away from the substrate 10, a second conductive layer arranged on the side of the sixth insulating layer 16 away from the substrate 10, an organic dielectric layer 31 arranged on the side of the second conductive layer away from the substrate 10, a third conductive layer and a second routing line 82 arranged on the side of the organic dielectric layer 31 away from the substrate 10, a seventh insulating layer 17 arranged on the side of the third conductive layer and the second routing line 82 away from the substrate 10, and a fourth conductive layer arranged on the side of the seventh insulating layer 17 away from the substrate 10.

[0113] In an exemplary embodiment, the first conductive layer includes a first electrode 51, a second electrode 52, and a third electrode 53. The first electrode 51, the second electrode 52, and the third electrode 53 can be made of the same material and through the same manufacturing process. The second conductive layer includes a fourth electrode 54, which is connected to the first active layer 21 through a fourth via 94 and is connected to the pixel electrode 55 through a fifth via 95. The third conductive layer includes a pixel electrode 55, which is connected to the fourth electrode 54 through a fifth via 95.

[0114] In an exemplary embodiment, the first electrode 51 is connected to the fifth trace. For example, the first electrode 51 and the fifth trace are connected as one body and include the same material. The first electrode 51 can serve as a part of the fifth trace.

[0115] In an exemplary embodiment, the orthographic projections of the first electrode 51 and the second trace 82 on the substrate 10 overlap. For example, the orthographic projection of the first electrode 51 on the substrate 10 is located within the orthographic projection of the second trace 82 on the substrate 10. The second trace 82 can block light emitted toward the first electrode 51.

[0116] In an exemplary embodiment, the fourth electrode 54 may employ a transparent conductive material, for example, indium tin oxide (ITO).

[0117] In an exemplary embodiment, the pixel electrode 55 may employ a transparent conductive material, for example, indium tin oxide (ITO).

[0118] In an exemplary embodiment, the common electrode 56 may employ a transparent conductive material, for example, indium tin oxide (ITO).

[0119] In an exemplary embodiment, at least one of the first routing 81, the second routing 82, the third routing 71 and the fourth routing 72 includes an optical auxiliary structure, wherein the optical auxiliary structure includes n auxiliary layers, the refractive index and material between adjacent auxiliary layers are different, and n is a natural number greater than or equal to 2; the transmittance of the optical auxiliary structure to natural light is less than 10%.

[0120] In an exemplary embodiment, natural light includes light having a wavelength of 400 nm to 700 nm.

[0121] In an exemplary embodiment, the first trace 81 includes a first optical auxiliary structure 41 , the side of the first optical auxiliary structure 41 close to the substrate 10 is in direct contact with the second insulating layer 12 ; the side of the first optical auxiliary structure 41 away from the substrate 10 is connected to the third insulating layer 13 as a whole.

[0122] In an exemplary embodiment, the first optical auxiliary structure 41 includes a first auxiliary layer 411 disposed on a side of the second insulating layer 12 away from the substrate 10, a second auxiliary layer 412 disposed on a side of the first auxiliary layer 411 away from the substrate 10, a third auxiliary layer 413 disposed on a side of the second auxiliary layer 412 away from the substrate 10, and a fourth auxiliary layer 414 disposed on a side of the third auxiliary layer 413 away from the substrate 10. The refractive index of the first auxiliary layer 411 is lower than that of the second auxiliary layer 412, the refractive index of the third auxiliary layer 413 is lower than that of the fourth auxiliary layer 414, and the refractive index of the third auxiliary layer 413 is lower than that of the second auxiliary layer 412.

[0123] In an exemplary embodiment, the first auxiliary layer 411 is in direct contact with the second insulating layer 12. The fourth auxiliary layer 414 is integrally connected to the third insulating layer 13 and includes the same material. The fourth auxiliary layer 414 may serve as a part of the third insulating layer 13.

[0124] The display substrate of the disclosed embodiment is alternately provided with auxiliary layers, so that at least part of the light is totally reflected at the junction of adjacent auxiliary layers, locking the light in the first optical auxiliary structure 41 and reducing the reflectivity of the light in the display substrate.

[0125] In an exemplary embodiment, a difference between a refractive index of the second auxiliary layer 412 and a refractive index of the first auxiliary layer 411 is greater than or equal to 0.7 and less than or equal to 2.5.

[0126] The embodiment of the present disclosure shows that the substrate realizes total reflection adjustment of light by controlling the refractive index difference between the second auxiliary layer and the first auxiliary layer.

[0127] In an exemplary embodiment, a difference between a refractive index of the second auxiliary layer 412 and a refractive index of the third auxiliary layer 413 is greater than or equal to 0.7 and less than or equal to 2.5.

[0128] The embodiment of the present disclosure shows that the substrate realizes total reflection adjustment of light by controlling the refractive index difference between the second auxiliary layer and the third auxiliary layer.

[0129] In an exemplary embodiment, a difference between a refractive index of the fourth auxiliary layer 414 and a refractive index of the third auxiliary layer 413 is greater than or equal to 0.7 and less than or equal to 2.5.

[0130] The embodiment of the present disclosure shows that the substrate realizes total reflection adjustment of light by controlling the refractive index difference between the fourth auxiliary layer and the third auxiliary layer.

[0131] In an exemplary embodiment, the first optical auxiliary structure 41 overlaps with the orthographic projection of the first active layer 21 on the substrate, so that the first optical auxiliary structure 41 can shield the first active layer 21 and prevent reflected light from directly irradiating the first active layer 21 .

[0132] In an exemplary embodiment, the first auxiliary layer 411 may include a metal material, for example, at least one of molybdenum, tungsten, copper, and aluminum.

[0133] In example embodiments, the second auxiliary layer 412 may include an inorganic material, such as silicon nitride, silicon oxide, aluminum oxide, or titanium dioxide.

[0134] In an exemplary embodiment, the third auxiliary layer 413 may include a metal material, for example, the third auxiliary layer 413 may include at least one of molybdenum, tungsten, copper, and aluminum.

[0135] In example embodiments, the fourth auxiliary layer 414 may include an inorganic material, for example, silicon nitride, silicon oxide, aluminum oxide, or titanium dioxide.

[0136] In an exemplary embodiment, the ratio of the thickness of the first auxiliary layer 411 to the thickness of the second auxiliary layer 412 is greater than or equal to 0.8 and less than or equal to 50. In an exemplary embodiment, the ratio of the thickness of the first auxiliary layer 411 to the thickness of the second auxiliary layer 412 is greater than or equal to 10 and less than or equal to 30. The ratio of the thickness of the second auxiliary layer 412 to the thickness of the third auxiliary layer 413 is greater than or equal to 0.1 and less than or equal to 100. In an exemplary embodiment, the ratio of the thickness of the second auxiliary layer 412 to the thickness of the third auxiliary layer 413 is greater than or equal to 20 and less than or equal to 70. The ratio of the thickness of the fourth auxiliary layer 414 to the thickness of the third auxiliary layer 413 is greater than or equal to 0.1 and less than or equal to 300. In an exemplary embodiment, the ratio of the thickness of the fourth auxiliary layer 414 to the thickness of the third auxiliary layer 413 is greater than or equal to 50 and less than or equal to 150. For example, the thickness of the first auxiliary layer 411 can be greater than or equal to 800 angstroms and less than or equal to 5000 angstroms; the thickness of the second auxiliary layer 412 can be greater than or equal to 100 angstroms and less than or equal to 1000 angstroms; the thickness of the third auxiliary layer 413 can be greater than or equal to 10 angstroms and less than or equal to 1000 angstroms; the thickness of the fourth auxiliary layer 414 can be greater than or equal to 100 angstroms and less than or equal to 3000 angstroms.

[0137] In an exemplary embodiment, the orthographic projections of the first auxiliary layer 411, the second auxiliary layer 412, and the third auxiliary layer 413 on the substrate overlap to form a first stacking pattern. For example, the orthographic projection of the first auxiliary layer 411 on the substrate includes the orthographic projection of the second auxiliary layer 412 on the substrate, and the orthographic projection of the second auxiliary layer 412 on the substrate includes the orthographic projection of the third auxiliary layer 413 on the substrate.

[0138] In an exemplary embodiment, the cross section of the first stack pattern perpendicular to the substrate is a regular trapezoid. In some embodiments, the cross section of the first stack pattern perpendicular to the substrate may be a polygon such as an inverted trapezoid, a rectangle, or a pentagon.

[0139] In an exemplary embodiment, the first stacking pattern includes a side surface and a surface away from the substrate 10, and an angle a1 formed between the side surface of the first stacking pattern and the plane on which the substrate 10 is located is greater than or equal to 30 degrees and less than or equal to 80 degrees. For example, the angle a1 formed between the side surface of the first stacking pattern and the plane on which the substrate 10 is located is greater than or equal to 40 degrees and less than or equal to 80 degrees. Alternatively, the angle a1 formed between the side surface of the first stacking pattern and the plane on which the substrate 10 is located is greater than or equal to 50 degrees and less than or equal to 80 degrees. Alternatively, the angle a1 formed between the side surface of the first stacking pattern and the plane on which the substrate 10 is located is greater than or equal to 60 degrees and less than or equal to 80 degrees.

[0140] The display substrate of the present disclosure reduces the line width of the first stacking pattern by making the angle a1 formed between the side of the first stacking pattern and the plane where the substrate 10 is located greater than or equal to 30 degrees and less than or equal to 80 degrees, reducing the influence of the first stacking pattern on the pixel opening of the display device, and ensuring the area of ​​the pixel opening of the display device on the positive projection of the substrate. The higher the pixel density / resolution of the display device, the larger the value of the angle a1 can be set to reduce the influence on the opening. For example, for a display device with a pixel density (PPI) of 1000+PPI, the angle a1 formed between the side of the first stacking pattern and the plane where the substrate 10 is located is greater than or equal to 40 degrees and less than or equal to 80 degrees; for a display device with a pixel density (PPI) of 1500+PPI, the angle a1 formed between the side of the first stacking pattern and the plane where the substrate 10 is located is greater than or equal to 50 degrees and less than or equal to 80 degrees; for a display device with a pixel density (PPI) of 2000+PPI, the angle a1 formed between the side of the first stacking pattern and the plane where the substrate 10 is located is greater than or equal to 60 degrees and less than or equal to 80 degrees.

[0141] In an exemplary embodiment, the fourth auxiliary layer 414 is connected to the third insulating layer 13 as a whole and may serve as a part of the third insulating layer 13. The fourth auxiliary layer 414 wraps the side surface of the first stack pattern and the surface away from the substrate.

[0142] In an exemplary embodiment, the third trace 71 includes a third optical auxiliary structure 43. The side of the third optical auxiliary structure 43 close to the substrate 10 is in direct contact with the fourth insulating layer 14, and the side of the third optical auxiliary structure 43 away from the substrate 10 is integrally connected with the fifth insulating layer 15.

[0143] In an exemplary embodiment, the third optical auxiliary structure 43 includes a fifth auxiliary layer 431 disposed on a side of the fourth insulating layer 14 away from the substrate 10, a sixth auxiliary layer 432 disposed on a side of the fifth auxiliary layer 431 away from the substrate 10, a seventh auxiliary layer 433 disposed on a side of the sixth auxiliary layer 432 away from the substrate 10, and an eighth auxiliary layer 434 disposed on a side of the seventh auxiliary layer 433 away from the substrate 10. The refractive index of the fifth auxiliary layer 431 is smaller than the refractive index of the sixth auxiliary layer 432, the refractive index of the seventh auxiliary layer 433 is smaller than the refractive index of the eighth auxiliary layer 434, and the refractive index of the seventh auxiliary layer 433 is smaller than the refractive index of the sixth auxiliary layer 432.

[0144] In an exemplary embodiment, the fifth auxiliary layer 431 is in direct contact with the fourth insulating layer 14. The eighth auxiliary layer 434 is integrally connected with the fifth insulating layer 15 and includes the same material. The eighth auxiliary layer 434 may serve as a part of the fifth insulating layer 15.

[0145] The display substrate of the disclosed embodiment is alternately provided with auxiliary layers, so that at least part of the light is totally reflected at the junction of adjacent auxiliary layers, locking the light in the third optical auxiliary structure 43 and reducing the reflectivity of the light in the display substrate.

[0146] In an exemplary embodiment, a difference between a refractive index of the sixth auxiliary layer 432 and a refractive index of the fifth auxiliary layer 431 is greater than or equal to 0.7 and less than or equal to 2.5.

[0147] The embodiment of the present disclosure shows that the substrate realizes total reflection adjustment of light by controlling the refractive index difference between the sixth auxiliary layer and the fifth auxiliary layer.

[0148] In an exemplary embodiment, a difference between a refractive index of the sixth auxiliary layer 432 and a refractive index of the seventh auxiliary layer 433 is greater than or equal to 0.7 and less than or equal to 2.5.

[0149] The embodiment of the present disclosure shows that the substrate adjusts the total reflection of light by controlling the refractive index difference between the sixth auxiliary layer and the seventh auxiliary layer 433 .

[0150] In an exemplary embodiment, a difference between a refractive index of the eighth auxiliary layer 434 and a refractive index of the seventh auxiliary layer 433 is greater than or equal to 0.7 and less than or equal to 2.5.

[0151] The embodiment of the present disclosure shows that the substrate adjusts the total reflection of light by controlling the refractive index difference between the eighth auxiliary layer and the seventh auxiliary layer 433 .

[0152] In an exemplary embodiment, the third optical auxiliary structure 43 overlaps with the orthographic projection of the first active layer 21 on the substrate, so that the third optical auxiliary structure 43 can shield the first active layer 21 and prevent reflected light from directly irradiating the first active layer 21 .

[0153] In an exemplary embodiment, the fifth auxiliary layer 431 may include a metal material. For example, the fifth auxiliary layer 431 may include at least one of molybdenum, tungsten, copper, and aluminum.

[0154] In example embodiments, the sixth auxiliary layer 432 may include an inorganic material, for example, silicon nitride, silicon oxide, aluminum oxide, or titanium dioxide.

[0155] In example embodiments, the seventh auxiliary layer 433 may include a metal material, for example, at least one of molybdenum, tungsten, copper, and aluminum.

[0156] In example embodiments, the eighth auxiliary layer 114 may include an inorganic material, for example, silicon nitride, silicon oxide, aluminum oxide, or titanium dioxide.

[0157] In an exemplary embodiment, the ratio of the thickness of the fifth auxiliary layer 431 to the thickness of the sixth auxiliary layer 432 is greater than or equal to 0.8 and less than or equal to 50. In an exemplary embodiment, the ratio of the thickness of the fifth auxiliary layer 431 to the thickness of the sixth auxiliary layer 432 is greater than or equal to 10 and less than or equal to 30. The ratio of the thickness of the sixth auxiliary layer 432 to the thickness of the seventh auxiliary layer 433 is greater than or equal to 0.1 and less than or equal to 100. In an exemplary embodiment, the ratio of the thickness of the sixth auxiliary layer 432 to the thickness of the seventh auxiliary layer 433 is greater than or equal to 20 and less than or equal to 70. The ratio of the thickness of the eighth auxiliary layer 114 to the thickness of the seventh auxiliary layer 433 is greater than or equal to 0.1 and less than or equal to 300. In an exemplary embodiment, the ratio of the thickness of the eighth auxiliary layer 114 to the thickness of the seventh auxiliary layer 433 is greater than or equal to 50 and less than or equal to 150. For example, the thickness of the fifth auxiliary layer 431 can be greater than or equal to 800 angstroms and less than or equal to 5000 angstroms; the thickness of the sixth auxiliary layer 432 can be greater than or equal to 100 angstroms and less than or equal to 1000 angstroms; the thickness of the seventh auxiliary layer 433 can be greater than or equal to 10 angstroms and less than or equal to 1000 angstroms; the thickness of the eighth auxiliary layer 114 can be greater than or equal to 100 angstroms and less than or equal to 3000 angstroms.

[0158] In an exemplary embodiment, the orthographic projections of the fifth auxiliary layer 431, the sixth auxiliary layer 432, and the seventh auxiliary layer 433 on the substrate overlap, forming a second stacking pattern. For example, the orthographic projection of the fifth auxiliary layer 431 on the substrate includes the orthographic projection of the sixth auxiliary layer 432 on the substrate, and the orthographic projection of the sixth auxiliary layer 432 on the substrate includes the orthographic projection of the seventh auxiliary layer 433 on the substrate.

[0159] In an exemplary embodiment, the cross section of the second stack pattern perpendicular to the substrate is a regular trapezoid. In some embodiments, the cross section of the second stack pattern perpendicular to the substrate may be a polygon such as an inverted trapezoid, a rectangle, or a pentagon.

[0160] In an exemplary embodiment, the second stacking pattern includes a side surface and a surface away from the substrate 10, and an angle a1 formed between the side surface of the second stacking pattern and the plane where the substrate 10 is located is greater than or equal to 30 degrees and less than or equal to 80 degrees. For example, the angle a1 formed between the side surface of the second stacking pattern and the plane where the substrate 10 is located is greater than or equal to 40 degrees and less than or equal to 80 degrees. Alternatively, the angle a1 formed between the side surface of the second stacking pattern and the plane where the substrate 10 is located is greater than or equal to 50 degrees and less than or equal to 80 degrees. Alternatively, the angle a1 formed between the side surface of the second stacking pattern and the plane where the substrate 10 is located is greater than or equal to 60 degrees and less than or equal to 80 degrees.

[0161] The embodiment of the present disclosure displays a substrate that reduces the line width of the second stacked pattern by making the angle a1 formed between the side of the second stacked pattern and the plane where the substrate 10 is located greater than or equal to 30 degrees and less than or equal to 80 degrees, reducing the influence of the second stacked pattern on the pixel opening of the display device, and ensuring the area of ​​the pixel opening of the display device on the substrate. The higher the pixel density / resolution of the display device, the larger the value of the angle a1 can be set to reduce the influence on the opening. For example, for a display device with a pixel density (PPI) of 1000+PPI, the angle a1 formed between the side of the second stacked pattern and the plane where the substrate 10 is located is greater than or equal to 40 degrees and less than or equal to 80 degrees; for a display device with a pixel density (PPI) of 1500+PPI, the angle a1 formed between the side of the second stacked pattern and the plane where the substrate 10 is located is greater than or equal to 50 degrees and less than or equal to 80 degrees; for a display device with a pixel density (PPI) of 2000+PPI, the angle a1 formed between the side of the second stacked pattern and the plane where the substrate 10 is located is greater than or equal to 60 degrees and less than or equal to 80 degrees.

[0162] In an exemplary embodiment, the eighth auxiliary layer 434 is connected to the fifth insulating layer 15 as a whole and can be used as a part of the fifth insulating layer 15. The eighth auxiliary layer 434 wraps the side surface of the second stack pattern and the surface away from the substrate.

[0163] In an exemplary embodiment, the second trace 82 includes a fourth optical auxiliary structure 44 . The side of the fourth optical auxiliary structure 44 close to the substrate 10 is in direct contact with the organic medium layer 31 , and the side of the fourth optical auxiliary structure 44 away from the substrate 10 is integrally connected to the seventh insulating layer 17 .

[0164] In an exemplary embodiment, the fourth optical auxiliary structure 44 includes a ninth auxiliary layer 441 disposed on a side of the organic medium layer 31 away from the substrate 10, a tenth auxiliary layer 442 disposed on a side of the ninth auxiliary layer 441 away from the substrate 10, an eleventh auxiliary layer 443 disposed on a side of the tenth auxiliary layer 442 away from the substrate 10, and a twelfth auxiliary layer 444 disposed on a side of the eleventh auxiliary layer 443 away from the substrate 10. The refractive index of the ninth auxiliary layer 441 is smaller than that of the tenth auxiliary layer 442, the refractive index of the eleventh auxiliary layer 443 is smaller than that of the twelfth auxiliary layer 444, and the refractive index of the eleventh auxiliary layer 443 is smaller than that of the tenth auxiliary layer 442.

[0165] In an exemplary embodiment, the ninth auxiliary layer 441 is in direct contact with the organic dielectric layer 31. The twelfth auxiliary layer 444 is integrally connected to the seventh insulating layer 17 and includes the same material. The twelfth auxiliary layer 444 may serve as a part of the seventh insulating layer 17.

[0166] The display substrate of the disclosed embodiment is alternately provided with auxiliary layers, so that at least part of the light is totally reflected at the junction of adjacent auxiliary layers, locking the light in the fourth optical auxiliary structure 44 and reducing the reflectivity of the light in the display substrate.

[0167] In an exemplary embodiment, a difference between a refractive index of the tenth auxiliary layer 442 and a refractive index of the ninth auxiliary layer 441 is greater than or equal to 0.7 and less than or equal to 2.5.

[0168] The embodiment of the present disclosure shows that the substrate realizes total reflection adjustment of light by controlling the refractive index difference between the tenth auxiliary layer and the ninth auxiliary layer.

[0169] In an exemplary embodiment, a difference between a refractive index of the tenth auxiliary layer 442 and a refractive index of the eleventh auxiliary layer 443 is greater than or equal to 0.7 and less than or equal to 2.5.

[0170] The embodiment of the present disclosure shows that the substrate realizes total reflection adjustment of light by controlling the refractive index difference between the tenth auxiliary layer and the eleventh auxiliary layer 443 .

[0171] In an exemplary embodiment, a difference between a refractive index of the twelfth auxiliary layer 444 and a refractive index of the eleventh auxiliary layer 443 is greater than or equal to 0.7 and less than or equal to 2.5.

[0172] The embodiment of the present disclosure shows that the substrate adjusts the total reflection of light by controlling the refractive index difference between the twelfth auxiliary layer and the eleventh auxiliary layer 443 .

[0173] In an exemplary embodiment, the fourth optical auxiliary structure 44 overlaps with the orthographic projection of the first electrode 51 on the substrate, so that the fourth optical auxiliary structure 44 can shield the first electrode 51 and prevent reflected light from directly irradiating the first electrode 51 .

[0174] In example embodiments, the ninth auxiliary layer 441 may include a metal material, for example, molybdenum, tungsten, copper, or aluminum.

[0175] In example embodiments, the tenth auxiliary layer 442 may include an inorganic material, for example, silicon nitride, silicon oxide, aluminum oxide, or titanium dioxide.

[0176] In example embodiments, the eleventh auxiliary layer 443 may include a metal material, for example, at least one of molybdenum, tungsten, copper, and aluminum.

[0177] In example embodiments, the twelfth auxiliary layer 114 may include an inorganic material, for example, silicon nitride, silicon oxide, aluminum oxide, or titanium dioxide.

[0178] In an exemplary embodiment, the ratio of the thickness of the ninth auxiliary layer 441 to the thickness of the tenth auxiliary layer 442 is greater than or equal to 0.8 and less than or equal to 50. In an exemplary embodiment, the ratio of the thickness of the ninth auxiliary layer 441 to the thickness of the tenth auxiliary layer 442 is greater than or equal to 10 and less than or equal to 30. The ratio of the thickness of the tenth auxiliary layer 442 to the thickness of the eleventh auxiliary layer 443 is greater than or equal to 0.1 and less than or equal to 100. In an exemplary embodiment, the ratio of the thickness of the tenth auxiliary layer 442 to the thickness of the eleventh auxiliary layer 443 is greater than or equal to 20 and less than or equal to 70. The ratio of the thickness of the twelfth auxiliary layer 114 to the thickness of the eleventh auxiliary layer 443 is greater than or equal to 0.1 and less than or equal to 300. In an exemplary embodiment, the ratio of the thickness of the twelfth auxiliary layer 114 to the thickness of the eleventh auxiliary layer 443 is greater than or equal to 50 and less than or equal to 150. For example, the thickness of the ninth auxiliary layer 441 may be greater than or equal to 800 angstroms and less than or equal to 5000 angstroms; the thickness of the tenth auxiliary layer 442 may be greater than or equal to 100 angstroms and less than or equal to 1000 angstroms; the thickness of the eleventh auxiliary layer 443 may be greater than or equal to 10 angstroms and less than or equal to 1000 angstroms; the thickness of the twelfth auxiliary layer 114 may be greater than or equal to 100 angstroms and less than or equal to 3000 angstroms.

[0179] In an exemplary embodiment, the orthographic projections of the ninth auxiliary layer 441, the tenth auxiliary layer 442, and the eleventh auxiliary layer 443 on the substrate overlap, forming a fourth stacking pattern. For example, the orthographic projection of the ninth auxiliary layer 441 on the substrate includes the orthographic projection of the tenth auxiliary layer 442 on the substrate, and the orthographic projection of the tenth auxiliary layer 442 on the substrate includes the orthographic projection of the eleventh auxiliary layer 443 on the substrate.

[0180] In an exemplary embodiment, the cross section of the fourth stacking pattern perpendicular to the substrate is a regular trapezoid. In some embodiments, the cross section of the fourth stacking pattern perpendicular to the substrate may be a polygon such as an inverted trapezoid, a rectangle, or a pentagon.

[0181] In an exemplary embodiment, the fourth stacking pattern includes a side surface and a surface away from the substrate 10, and an angle a1 formed between the side surface of the fourth stacking pattern and the plane where the substrate 10 is located is greater than or equal to 30 degrees and less than or equal to 80 degrees. For example, the angle a1 formed between the side surface of the fourth stacking pattern and the plane where the substrate 10 is located is greater than or equal to 40 degrees and less than or equal to 80 degrees. Alternatively, the angle a1 formed between the side surface of the fourth stacking pattern and the plane where the substrate 10 is located is greater than or equal to 50 degrees and less than or equal to 80 degrees. Alternatively, the angle a1 formed between the side surface of the fourth stacking pattern and the plane where the substrate 10 is located is greater than or equal to 60 degrees and less than or equal to 80 degrees.

[0182] The display substrate of the present disclosure reduces the line width of the fourth stacking pattern by making the angle a1 formed between the side of the fourth stacking pattern and the plane where the substrate 10 is located greater than or equal to 30 degrees and less than or equal to 80 degrees, reducing the influence of the fourth stacking pattern on the pixel opening of the display device, and ensuring the area of ​​the pixel opening of the display device on the substrate. The higher the pixel density / resolution of the display device, the larger the value of the angle a1 can be set to reduce the influence on the opening. For example, for a display device with a pixel density (PPI) of 1000+PPI, the angle a1 formed between the side of the fourth stacking pattern and the plane where the substrate 10 is located is greater than or equal to 40 degrees and less than or equal to 80 degrees; for a display device with a pixel density (PPI) of 1500+PPI, the angle a1 formed between the side of the fourth stacking pattern and the plane where the substrate 10 is located is greater than or equal to 50 degrees and less than or equal to 80 degrees; for a display device with a pixel density (PPI) of 2000+PPI, the angle a1 formed between the side of the fourth stacking pattern and the plane where the substrate 10 is located is greater than or equal to 60 degrees and less than or equal to 80 degrees.

[0183] In an exemplary embodiment, the twelfth auxiliary layer 444 is connected to the seventh insulating layer 17 as a whole and may serve as a part of the seventh insulating layer 17. The twelfth auxiliary layer 444 wraps the side surface of the fourth stack pattern and the surface away from the substrate.

[0184] In an exemplary embodiment, the fourth trace 72 includes a second optical auxiliary structure 42 . The side of the second optical auxiliary structure 42 close to the substrate 10 is in direct contact with the second insulating layer 12 . The side of the second optical auxiliary structure 42 away from the substrate 10 is integrally connected with the third insulating layer 13 .

[0185] In an exemplary embodiment, the second optical auxiliary structure 42 includes a thirteenth auxiliary layer 421 disposed on a side of the second insulating layer 12 away from the substrate 10, a fourteenth auxiliary layer 422 disposed on a side of the thirteenth auxiliary layer 421 away from the substrate 10, a fifteenth auxiliary layer 423 disposed on a side of the fourteenth auxiliary layer 422 away from the substrate 10, and a sixteenth auxiliary layer 424 disposed on a side of the fifteenth auxiliary layer 423 away from the substrate 10. The refractive index of the thirteenth auxiliary layer 421 is smaller than the refractive index of the fourteenth auxiliary layer 422, the refractive index of the fifteenth auxiliary layer 423 is smaller than the refractive index of the sixteenth auxiliary layer 424, and the refractive index of the fifteenth auxiliary layer 423 is smaller than the refractive index of the fourteenth auxiliary layer 422.

[0186] In an exemplary embodiment, the thirteenth auxiliary layer 421 is in direct contact with the second insulating layer 12. The sixteenth auxiliary layer 424 is integrally connected with the third insulating layer 13 and includes the same material. The sixteenth auxiliary layer 424 may serve as a part of the third insulating layer 13.

[0187] The display substrate of the disclosed embodiment is alternately provided with auxiliary layers, so that at least part of the light is totally reflected at the junction of adjacent auxiliary layers, locking the light in the second optical auxiliary structure 42 and reducing the reflectivity of the light in the display substrate.

[0188] In an exemplary embodiment, a difference between a refractive index of the fourteenth auxiliary layer 422 and a refractive index of the thirteenth auxiliary layer 421 is greater than or equal to 0.7 and less than or equal to 2.5.

[0189] The embodiment of the present disclosure shows that the substrate realizes total reflection adjustment of light by controlling the refractive index difference between the fourteenth auxiliary layer and the thirteenth auxiliary layer.

[0190] In an exemplary embodiment, a difference between a refractive index of the fourteenth auxiliary layer 422 and a refractive index of the fifteenth auxiliary layer 423 is greater than or equal to 0.7 and less than or equal to 2.5.

[0191] The embodiment of the present disclosure shows that the substrate adjusts the total reflection of light by controlling the refractive index difference between the fourteenth auxiliary layer and the fifteenth auxiliary layer 423 .

[0192] In an exemplary embodiment, a difference between a refractive index of the sixteenth auxiliary layer 424 and a refractive index of the fifteenth auxiliary layer 423 is greater than or equal to 0.7 and less than or equal to 2.5.

[0193] The embodiment of the present disclosure shows that the substrate adjusts the total reflection of light by controlling the refractive index difference between the sixteenth auxiliary layer and the fifteenth auxiliary layer 423 .

[0194] In an exemplary embodiment, the orthographic projections of the second optical auxiliary structure 42 and the first electrode 51 on the substrate overlap, so that the second optical auxiliary structure 42 can shield the first electrode 51 and prevent reflected light from directly irradiating the first electrode 51 .

[0195] In example embodiments, the thirteenth auxiliary layer 421 may include a metal material, for example, the thirteenth auxiliary layer 421 may include at least one of molybdenum, tungsten, copper, and aluminum.

[0196] In example embodiments, the fourteenth auxiliary layer 422 may include an inorganic material, for example, silicon nitride, silicon oxide, aluminum oxide, or titanium dioxide.

[0197] In an exemplary embodiment, the fifteenth auxiliary layer 423 may include a metal material. For example, the fifteenth auxiliary layer 423 may include at least one of molybdenum, tungsten, copper, and aluminum.

[0198] In example embodiments, the sixteenth auxiliary layer 114 may include an inorganic material, for example, silicon nitride, silicon oxide, aluminum oxide, or titanium dioxide.

[0199] In an exemplary embodiment, the ratio of the thickness of the thirteenth auxiliary layer 421 to the thickness of the fourteenth auxiliary layer 422 is greater than or equal to 0.8 and less than or equal to 50. In an exemplary embodiment, the ratio of the thickness of the thirteenth auxiliary layer 421 to the thickness of the fourteenth auxiliary layer 422 is greater than or equal to 10 and less than or equal to 30. The ratio of the thickness of the fourteenth auxiliary layer 422 to the thickness of the fifteenth auxiliary layer 423 is greater than or equal to 0.1 and less than or equal to 100. In an exemplary embodiment, the ratio of the thickness of the fourteenth auxiliary layer 422 to the thickness of the fifteenth auxiliary layer 423 is greater than or equal to 20 and less than or equal to 70. The ratio of the thickness of the sixteenth auxiliary layer 114 to the thickness of the fifteenth auxiliary layer 423 is greater than or equal to 0.1 and less than or equal to 300. In an exemplary embodiment, the ratio of the thickness of the sixteenth auxiliary layer 114 to the thickness of the fifteenth auxiliary layer 423 is greater than or equal to 50 and less than or equal to 150. For example, the thickness of the thirteenth auxiliary layer 421 may be greater than or equal to 800 angstroms and less than or equal to 5000 angstroms; the thickness of the fourteenth auxiliary layer 422 may be greater than or equal to 100 angstroms and less than or equal to 1000 angstroms; the thickness of the fifteenth auxiliary layer 423 may be greater than or equal to 10 angstroms and less than or equal to 1000 angstroms; the thickness of the sixteenth auxiliary layer 114 may be greater than or equal to 100 angstroms and less than or equal to 3000 angstroms.

[0200] In an exemplary embodiment, the orthographic projections of the thirteenth auxiliary layer 421, the fourteenth auxiliary layer 422, and the fifteenth auxiliary layer 423 on the substrate overlap, forming a second stacking pattern. For example, the orthographic projection of the thirteenth auxiliary layer 421 on the substrate includes the orthographic projection of the fourteenth auxiliary layer 422 on the substrate, and the orthographic projection of the fourteenth auxiliary layer 422 on the substrate includes the orthographic projection of the fifteenth auxiliary layer 423 on the substrate.

[0201] In an exemplary embodiment, the cross section of the second stack pattern perpendicular to the substrate is a regular trapezoid. In some embodiments, the cross section of the second stack pattern perpendicular to the substrate may be a polygon such as an inverted trapezoid, a rectangle, or a pentagon.

[0202] In an exemplary embodiment, the second stacking pattern includes a side surface and a surface away from the substrate 10, and an angle a1 formed between the side surface of the second stacking pattern and the plane where the substrate 10 is located is greater than or equal to 30 degrees and less than or equal to 80 degrees. For example, the angle a1 formed between the side surface of the second stacking pattern and the plane where the substrate 10 is located is greater than or equal to 40 degrees and less than or equal to 80 degrees. Alternatively, the angle a1 formed between the side surface of the second stacking pattern and the plane where the substrate 10 is located is greater than or equal to 50 degrees and less than or equal to 80 degrees. Alternatively, the angle a1 formed between the side surface of the second stacking pattern and the plane where the substrate 10 is located is greater than or equal to 60 degrees and less than or equal to 80 degrees.

[0203] The embodiment of the present disclosure displays a substrate that reduces the line width of the second stacked pattern by making the angle a1 formed between the side of the second stacked pattern and the plane where the substrate 10 is located greater than or equal to 30 degrees and less than or equal to 80 degrees, reducing the influence of the second stacked pattern on the pixel opening of the display device, and ensuring the area of ​​the pixel opening of the display device on the substrate. The higher the pixel density / resolution of the display device, the larger the value of the angle a1 can be set to reduce the influence on the opening. For example, for a display device with a pixel density (PPI) of 1000+PPI, the angle a1 formed between the side of the second stacked pattern and the plane where the substrate 10 is located is greater than or equal to 40 degrees and less than or equal to 80 degrees; for a display device with a pixel density (PPI) of 1500+PPI, the angle a1 formed between the side of the second stacked pattern and the plane where the substrate 10 is located is greater than or equal to 50 degrees and less than or equal to 80 degrees; for a display device with a pixel density (PPI) of 2000+PPI, the angle a1 formed between the side of the second stacked pattern and the plane where the substrate 10 is located is greater than or equal to 60 degrees and less than or equal to 80 degrees.

[0204] In an exemplary embodiment, the sixteenth auxiliary layer 424 is connected to the third insulating layer 13 as a whole and may serve as a part of the third insulating layer 13. The sixteenth auxiliary layer 424 wraps the side surface of the second stack pattern and the surface away from the substrate.

[0205] In some embodiments, the second active layer of the second transistor may be an oxide semiconductor. A sixth wiring is provided on a side of the second active layer close to the substrate, and the structure of the sixth wiring may be the same as that of the first wiring. The structure of the fourth wiring of the second transistor may be the same as that of the third wiring of the first transistor.

[0206] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0207] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0208] (11) Forming a second active layer. In an exemplary embodiment, forming the second active layer pattern may include: sequentially depositing a first insulating layer 11 and a second semiconductor thin film on a substrate 10, and patterning the second semiconductor thin film through a patterning process to form a second active layer 22 disposed on the first insulating layer 11, as shown in FIG. 5a.

[0209] In an exemplary embodiment, the first insulating layer 11 may include a first inorganic dielectric layer and a second inorganic dielectric layer stacked together. The first inorganic dielectric layer may be silicon nitride, and the thickness of the first inorganic dielectric layer may be greater than or equal to 200 angstroms and less than or equal to 2000 angstroms. The second inorganic dielectric layer may be silicon oxide, and the thickness of the second inorganic dielectric layer may be greater than or equal to 1000 angstroms and less than or equal to 6000 angstroms. In some embodiments, the first insulating layer may have a single-layer structure, and the first insulating layer may be silicon nitride or silicon oxide.

[0210] In an exemplary embodiment, the second active layer 22 may be made of low temperature polysilicon (LTPS), and may have a thickness of greater than or equal to 200 angstroms and less than or equal to 1000 angstroms.

[0211] (12) Forming a first auxiliary film, a second auxiliary film, and a third auxiliary film. In an exemplary embodiment, forming the first auxiliary film, the second auxiliary film, and the third auxiliary film may include: on the substrate having the aforementioned pattern formed thereon, sequentially depositing the second insulating layer 12, the first auxiliary film 61, the second auxiliary film 62, and the third auxiliary film 63 on the first insulating layer 11, as shown in FIG. 5b .

[0212] In an exemplary embodiment, the material of the first auxiliary film 61 may include a metal material, such as at least one of molybdenum, tungsten, copper, and aluminum. The thickness of the first auxiliary film 61 may be greater than or equal to 800 angstroms and less than or equal to 5000 angstroms. The material of the second auxiliary film 62 may include at least one of silicon nitride, silicon oxide, aluminum oxide, and titanium dioxide. The thickness of the second auxiliary film 62 may be greater than or equal to 100 angstroms and less than or equal to 1000 angstroms. The material of the third auxiliary film 63 may include a metal material, such as at least one of molybdenum, tungsten, copper, and aluminum. The thickness of the third auxiliary film 63 may be greater than or equal to 10 angstroms and less than or equal to 1000 angstroms.

[0213] (13) Forming the first and fourth routing lines. In an exemplary embodiment, forming the first and fourth routing lines may include: on the substrate on which the aforementioned pattern is formed, performing a dry etching process on the first auxiliary film, the second auxiliary film, and the third auxiliary film, so that the first auxiliary film forms a first auxiliary layer 411 and a thirteenth auxiliary layer 421, the second auxiliary film forms a second auxiliary layer 412 and a fourteenth auxiliary layer 422, and the third auxiliary film forms a third auxiliary layer 413 and a fifteenth auxiliary layer 423, as shown in FIG5c.

[0214] In an exemplary embodiment, the orthographic projections of the first auxiliary layer 411, the second auxiliary layer 412, and the third auxiliary layer 413 on the substrate overlap to form a first stacking pattern. For example, the orthographic projection of the first auxiliary layer 411 on the substrate includes the orthographic projection of the second auxiliary layer 412 on the substrate, and the orthographic projection of the second auxiliary layer 412 on the substrate includes the orthographic projection of the third auxiliary layer 413 on the substrate.

[0215] In an exemplary embodiment, the orthographic projections of the thirteenth auxiliary layer 421, the fourteenth auxiliary layer 422, and the fifteenth auxiliary layer 423 on the substrate overlap, forming a second stacking pattern. For example, the orthographic projection of the thirteenth auxiliary layer 421 on the substrate includes the orthographic projection of the fourteenth auxiliary layer 422 on the substrate, and the orthographic projection of the fourteenth auxiliary layer 422 on the substrate includes the orthographic projection of the fifteenth auxiliary layer 423 on the substrate.

[0216] Subsequently, a third insulating layer 13 is deposited on the second insulating layer 12, covering the first and second stacked patterns. The third insulating layer 13 covers the side surfaces and the surface away from the substrate of the first stacked pattern, and the third insulating layer 13 covers the side surfaces and the surface away from the substrate of the second stacked pattern. The portion where the third insulating layer 13 overlaps with the first stacked pattern can serve as a fourth auxiliary layer 414. The fourth auxiliary layer 414 and the first stacked pattern form a first optical auxiliary structure 41, and the first optical auxiliary structure 41 serves as a first trace 81. The portion where the third insulating layer 13 overlaps with the second stacked pattern can serve as a sixteenth auxiliary layer 424. The sixteenth auxiliary layer 424 and the second stacked pattern form a second optical auxiliary structure 42, and the second optical auxiliary structure 42 serves as a fourth trace 72, as shown in FIG. 5 d.

[0217] In an exemplary embodiment, the material of the third insulating layer 13 may include at least one of silicon nitride, silicon oxide, aluminum oxide, and titanium dioxide. The thickness of the third insulating layer 13 may be greater than or equal to 100 angstroms and less than or equal to 3000 angstroms.

[0218] This embodiment shows that the preparation process of the substrate can form a first stacking pattern including a first auxiliary layer 411, a second auxiliary layer 412 and a third auxiliary layer 413 through a dry etching process, thereby improving the refinement of the patterning process and reducing the line width of the first stacking pattern.

[0219] This embodiment shows that the preparation process of the substrate can form a second stacking pattern including the thirteenth auxiliary layer 421, the fourteenth auxiliary layer 422 and the fifteenth auxiliary layer 423 through a dry etching process, thereby improving the refinement of the patterning process and reducing the line width of the first stacking pattern.

[0220] This embodiment shows that the preparation process of the substrate can simultaneously form a first stacking pattern including a first auxiliary layer 411, a second auxiliary layer 412 and a third auxiliary layer 413, and a second stacking pattern including a thirteenth auxiliary layer 421, a fourteenth auxiliary layer 422 and a fifteenth auxiliary layer 423 through a single dry etching process, thereby simplifying the process flow and reducing production costs.

[0221] (14) Forming a first active layer and a third wiring. In an exemplary embodiment, forming the first active layer and the third wiring may include: forming a first active layer 21 and a fourth insulating layer 14 on the third insulating layer 13 on the substrate having the aforementioned pattern formed thereon; subsequently, sequentially depositing a fifth auxiliary film, a sixth auxiliary film, and a seventh auxiliary film on the fourth insulating layer 14; performing a dry etching process on the fifth auxiliary film, the sixth auxiliary film, and the seventh auxiliary film, so that the fifth auxiliary film forms the fifth auxiliary layer 431, the sixth auxiliary film forms the sixth auxiliary layer, and the seventh auxiliary film forms the seventh auxiliary layer 433.

[0222] In an exemplary embodiment, the orthographic projections of the fifth auxiliary layer 431, the sixth auxiliary layer, and the seventh auxiliary layer 433 on the substrate overlap, forming a third stacking pattern. For example, the orthographic projection of the fifth auxiliary layer 431 on the substrate includes the orthographic projection of the sixth auxiliary layer on the substrate, and the orthographic projection of the sixth auxiliary layer on the substrate includes the orthographic projection of the seventh auxiliary layer 433 on the substrate.

[0223] Subsequently, a fifth insulating layer 15 is deposited on the fourth insulating layer 14, covering the third stacked pattern. The fifth insulating layer 15 covers the side surfaces of the third stacked pattern and the surface facing away from the substrate. The portion where the fifth insulating layer 15 overlaps with the third stacked pattern serves as an eighth auxiliary layer 434. The eighth auxiliary layer 434 and the third stacked pattern form a third optical auxiliary structure 43, which serves as a third trace 71, as shown in FIG5e.

[0224] (15) Forming a second wiring, a pixel electrode, and a common electrode. In an exemplary embodiment, forming the second wiring, the pixel electrode, and the common electrode may include: forming, on the substrate having the aforementioned pattern, a first via hole exposing the first active layer 21, a second via hole exposing the second active layer 22, and a third via hole exposing the second active layer 22 by an etching process; subsequently, forming a first conductive film on the fifth insulating layer 15, and patterning the first conductive film by a patterning process to form a first electrode 51, a second electrode 52, and a third electrode 53 disposed on the fifth insulating layer 15, the first electrode 51 being connected to the first active layer 21 through the first via hole, the second electrode 52 being connected to the second active layer 22 through the second via hole, and the third electrode 53 being connected to the side away from the substrate 22 through the third via hole.

[0225] Subsequently, a sixth insulating layer 16 covering the first electrode 51, the second electrode 52 and the third electrode 53 is formed on the fifth insulating layer 15; a fourth via hole exposing the first active layer 21 is formed through an etching process; a second conductive film is formed on the sixth insulating layer 16, and the second conductive film is patterned through a patterning process to form a fourth electrode 54 arranged on the sixth insulating layer 16, and the fourth electrode 54 is connected to the first active layer 21 through the fourth via hole.

[0226] Subsequently, an organic dielectric layer 31 covering the fourth electrode 54 is formed on the fifth insulating layer 15; a pixel electrode 55 is formed on the organic dielectric layer 31; subsequently, a ninth auxiliary film, a tenth auxiliary film, and an eleventh auxiliary film are sequentially deposited on the fifth insulating layer 15; the ninth auxiliary film, the tenth auxiliary film, and the eleventh auxiliary film are dry-etched to form the ninth auxiliary film into a ninth auxiliary layer 441, the tenth auxiliary film into a tenth auxiliary layer 442, and the eleventh auxiliary film into an eleventh auxiliary layer 443.

[0227] In an exemplary embodiment, the orthographic projections of the ninth auxiliary layer 441, the tenth auxiliary layer 442, and the eleventh auxiliary layer 443 on the substrate overlap, forming a fourth stacking pattern. For example, the orthographic projection of the ninth auxiliary layer 441 on the substrate includes the orthographic projection of the tenth auxiliary layer 442 on the substrate, and the orthographic projection of the tenth auxiliary layer 442 on the substrate includes the orthographic projection of the eleventh auxiliary layer 443 on the substrate.

[0228] Subsequently, a seventh insulating layer 17 is deposited on the organic dielectric layer 31, covering the fourth stacked pattern and the pixel electrode 55. The seventh insulating layer 17 covers the side surfaces of the fourth stacked pattern and the surface facing away from the substrate. The portion where the seventh insulating layer 17 overlaps with the fourth stacked pattern serves as a twelfth auxiliary layer 444. The twelfth auxiliary layer 444 and the fourth stacked pattern form a fourth optical auxiliary structure 44, which serves as a second trace 82. Subsequently, a common electrode 56 is formed on the seventh insulating layer 17, as shown in FIG4c.

[0229] Figure 6a is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a first circuit unit of the display substrate. In this exemplary embodiment, as shown in Figure 6a, the first circuit unit includes a first transistor disposed on a substrate, a second trace 82 and a pixel electrode 55 disposed on a side of the first transistor away from the substrate, and a common electrode 56 disposed on a side of the second trace 82 and the pixel electrode 55 away from the substrate. The first transistor includes a first active layer disposed on the substrate, a third trace disposed on a side of the first active layer away from the substrate, a first electrode disposed on a side of the third trace away from the substrate, and a fourth electrode 54 disposed on a side of the first electrode away from the substrate.

[0230] Figure 6b is a schematic diagram of the planar structure of a display substrate after forming a first active layer according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in Figure 6b, on a plane parallel to the display substrate, the first active layer 21 may include a first channel 211, a second channel 212, and an extension 213 connecting the first channel 211 and the second channel 212. The first channel 211 and the second channel 212 may be rectangular in shape, with the second channel 212 located on one side of the first channel 211 in the second direction D2. The first end of the extension 213 is integrally connected to the first channel 211, and the second end of the extension 213 extends along a third direction D3 and is integrally connected to the second channel 212. The third direction D3 intersects both the first direction D1 and the second direction D2, and the first direction D1 is perpendicular to the second direction D2.

[0231] Figures 6c and 6d are schematic diagrams of the planar structure of a display substrate after forming a third trace according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in Figures 6c and 6d, on a plane parallel to the display substrate, the shape of the third trace 71 can be strip-shaped. For example, the shape of the third trace 71 can be a rectangular strip, and the third trace 71 can extend along the first direction D1. The third trace 71 overlaps with the orthographic projection of the first active layer 21 on the substrate. For example, the third trace 71 overlaps with the orthographic projection of the first channel or the second channel of the first active layer 21 on the substrate, and the orthographic projection of the first channel or the second channel on the substrate is located within the orthographic projection of the third trace 71 on the substrate.

[0232] Figures 6e and 6f illustrate a planar structure of a display substrate after forming a first electrode according to an exemplary embodiment of the present disclosure. In exemplary embodiments, as shown in Figures 6e and 6f, the first electrode 51 can be strip-shaped, for example, a rectangular strip, in a plane parallel to the display substrate. The first electrode 51 can extend along the second direction D2. The first electrode 51 overlaps with the orthographic projection of the first active layer 21 on the substrate and is connected to the first active layer 21 via a first via.

[0233] Figures 6g and 6h are schematic planar structural diagrams of a display substrate after forming a fourth electrode according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in Figures 6g and 6h, the fourth electrode 54 can be strip-shaped, for example, rectangular, in a plane parallel to the display substrate. The fourth electrode 54 can extend along the second direction D2. The fourth electrode 54 does not overlap with the orthographic projection of the first electrode 51 on the substrate. Instead, the fourth electrode 54 overlaps with the orthographic projection of the first active layer 21 on the substrate and is connected to the first active layer 21 via a fourth via 94.

[0234] Figures 6i and 6j are schematic diagrams of the planar structure of a display substrate after pixel electrodes are formed in an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in Figures 6i and 6j, on a plane parallel to the display substrate, the shape of the pixel electrode 55 can be strip-shaped. For example, the shape of the pixel electrode 55 can be a rectangular strip, and the pixel electrode 55 can extend along the second direction D2. The pixel electrode 55 overlaps with the orthographic projection of the third trace 71 on the substrate. The pixel electrode 55 overlaps with the orthographic projection of the fourth electrode 54 on the substrate and is connected to the fourth electrode 54 through the fifth via 95.

[0235] Figures 6k and 6l are schematic diagrams of a planar structure of a display substrate after forming a second trace in an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in Figures 6k and 6l, on a plane parallel to the display substrate, the shape of the second trace 82 can be strip-shaped. For example, the shape of the second trace 82 can be a rectangular strip, and the second trace 82 can extend along the second direction D2. The second trace 82 does not overlap with the orthographic projection of the pixel electrode 55 on the substrate. The second trace 82 does overlap with the orthographic projection of the first electrode on the substrate. For example, the orthographic projection of the second trace 82 on the substrate includes the orthographic projection of the first electrode on the substrate.

[0236] In the disclosed embodiment, the second trace 82 of the display substrate overlaps with the orthographic projection of the first electrode on the substrate, shielding the first electrode. This eliminates the need for a black matrix at the intersection of the color filter substrate and the second trace 82, simplifying the process. For example, the second trace 82 extends along the second direction, while the black matrix of the color filter substrate extends along the first direction.

[0237] Figure 6m is a schematic diagram of the planar structure of a display substrate after forming a common electrode according to an exemplary embodiment of the present disclosure. In exemplary embodiments, as shown in Figures 6a and 6m, the common electrode 56 can be plate-shaped, for example, rectangular, on a plane parallel to the display substrate. Slits 561 are provided in the common electrode 56, and the extension directions of the slits 561 intersect both the second direction D2 and the first direction D1. The orthographic projections of the common electrode 56 and the pixel electrode 55 on the substrate overlap.

[0238] Figure 6n is a schematic plan view of the second trace of another display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in Figure 6n, the second trace 82 can be rectangular and extend along a second direction D2. A light shielding block 821 is provided on the second trace 82, protruding from the edge of the second trace 82 in a first direction D1. The first direction D1 intersects the second direction D2, and for example, the first direction D1 is perpendicular to the second direction D2.

[0239] In an exemplary embodiment, the first electrode is connected to the first active layer through a first via hole 91. The orthographic projection of the light shielding block 821 on the substrate includes the orthographic projection of the first via hole 91 on the substrate.

[0240] In an exemplary embodiment, the minimum distance between the edge of the light shielding block 821 and the edge of the first via hole 91 is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers.

[0241] FIG7 is a schematic diagram of a planar structure of a display device according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in FIG7 , this embodiment further provides a display device comprising the above-mentioned display substrate and a color filter substrate arranged in a box. The display substrate further comprises a fifth trace, which is integrally connected to the first electrode. The second trace 82 in the display substrate extends along the second direction D2 and overlaps with the orthographic projection of the fifth trace in the display substrate on the substrate. For example, the orthographic projection of the second trace 82 on the substrate completely overlaps with the orthographic projection of the fifth trace on the substrate; alternatively, the orthographic projection of the second trace 82 on the substrate includes the orthographic projection of the fifth trace on the substrate. The color filter substrate comprises a filter layer and a black matrix 90, and the black matrix 90 extends along a first direction D1. The first direction D1 intersects with the second direction D1, and for example, the first direction D1 is perpendicular to the second direction D2.

[0242] The display device of the embodiment of the present disclosure can replace a portion of the black matrix in the color filter substrate through the second wiring 82, so that the color filter substrate can remove the black matrix extending along the second direction D2 and only include the black matrix extending along the first direction D1, thereby simplifying the process.

[0243] Figure 8 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure, illustrating a first circuit unit and a second circuit unit in the display substrate. As shown in Figure 8, the structure of the display substrate of this exemplary embodiment is substantially the same as that of the display substrate of the embodiment shown in Figure 4c, with the difference that the first trace 81 of the display substrate of this embodiment can be a single-layer structure made of a light-shielding material, and the first trace 81 does not include a first optical auxiliary structure. The third trace 71 and the fourth trace 72 can both be single-layer structures made of a conductive material, and the third trace 71 does not include a third optical auxiliary structure, and the fourth trace 72 does not include a second optical auxiliary structure. The second trace 82 includes a fourth optical auxiliary structure 44.

[0244] FIG9 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure, illustrating a first circuit unit and a second circuit unit in the display substrate. As shown in FIG9 , the structure of the display substrate of this exemplary embodiment is substantially the same as that of the display substrate of the embodiment shown in FIG4 c , with the difference being that the first trace 81 and the second trace 82 of the display substrate of this embodiment can both be single-layer structures made of light-shielding material, the first trace 81 does not include the first optical auxiliary structure, and the second trace 82 does not include the fourth optical auxiliary structure. The fourth trace 72 can be a single-layer structure made of conductive material, and the fourth trace 72 does not include the second optical auxiliary structure. The third trace 71 includes the third optical auxiliary structure 43.

[0245] Figure 10 is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in Figure 10 , this embodiment further provides a display device comprising a display substrate as shown in Figure 9 and a color filter substrate, arranged in a cell-like arrangement. The third optical auxiliary structure 43 in the display substrate extends along a first direction D1. The color filter substrate includes a black matrix 90, which extends along a second direction D2. The first direction D1 intersects the second direction D2. For example, the first direction D1 is perpendicular to the second direction D2.

[0246] The display device of the embodiment of the present disclosure can replace a portion of the black matrix in the color filter substrate through the third optical auxiliary structure, so that the color filter substrate can remove the black matrix extending along the first direction D1 and only include the black matrix extending along the second direction D2, thereby simplifying the process.

[0247] Figure 11 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 11, the structure of the display substrate of this exemplary embodiment is substantially identical to that of the display substrate of the embodiment shown in Figure 4c, with the difference that the first trace 81 of the display substrate of this embodiment can be a single-layer structure made of a light-shielding material, and the first trace 81 does not include a first optical auxiliary structure. The fourth trace 72 can be a single-layer structure made of a conductive material, and the fourth trace 72 does not include a second optical auxiliary structure. The third trace 71 includes a third optical auxiliary structure 43. The second trace 82 includes a fourth optical auxiliary structure 44.

[0248] In an exemplary embodiment, the fifth auxiliary layer 431 and the seventh auxiliary layer 433 in the third optical auxiliary structure 43 may include a metal material, and at least one of the fifth auxiliary layer 431 and the seventh auxiliary layer 433 is oxidized to form a black metal oxide.

[0249] In an exemplary embodiment, the ninth auxiliary layer 441 and the eleventh auxiliary layer 443 in the fourth optical auxiliary structure 44 may include a metal material, and at least one of the ninth auxiliary layer 441 and the eleventh auxiliary layer 443 is oxidized to form a black metal oxide.

[0250] Figure 12 is a schematic plan view of the third and fourth optical auxiliary structures in a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in Figure 12 , the third optical auxiliary structure 43 of the display substrate extends along a first direction D1, and the fourth optical auxiliary structure 44 extends along a second direction D2. The first direction D1 intersects the second direction D2, and for example, the first direction D1 is perpendicular to the second direction D2.

[0251] The display device of the embodiment of the present disclosure can replace the black matrix in the color filter substrate through the third optical auxiliary structure and the fourth optical auxiliary structure, so that the black matrix can be removed from the color filter substrate, simplifying the process.

[0252] Figure 13 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 13, the structure of the display substrate in this exemplary embodiment is substantially the same as that of the display substrate in the embodiment shown in Figure 11, with the difference being that fourth trace 72 in this embodiment is oxidized to form a black metal oxide, thereby reducing light reflection from the display substrate.

[0253] In some embodiments, the first trace in the substrate is oxidized to form a black metal oxide. Furthermore, the first electrode in the substrate is oxidized to form a black metal oxide. Furthermore, the fourth electrode in the substrate is oxidized to form a black metal oxide.

[0254] Figure 14 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 14, the structure of the display substrate according to this exemplary embodiment is substantially identical to that of the display substrate according to the exemplary embodiment shown in Figure 4c. The difference is that, in the third optical auxiliary structure 43 of the display substrate according to this embodiment, the orthographic projection of the fifth auxiliary layer 431 on the substrate is located within the orthographic projection of the seventh auxiliary layer 433 on the substrate, and the orthographic projection of the fifth auxiliary layer 431 on the substrate is smaller than the orthographic projection of the seventh auxiliary layer 433 on the substrate. For example, the third stacking pattern formed by the fifth auxiliary layer 431, the sixth auxiliary layer 433, and the seventh auxiliary layer 433 has an inverted trapezoidal cross-section perpendicular to the substrate.

[0255] Figure 15 is a schematic diagram showing the planar structure of the seventh auxiliary layer and the fifth auxiliary layer in a substrate according to an exemplary embodiment of the present disclosure. In this exemplary embodiment, as shown in Figure 15 , both the fifth auxiliary layer 431 and the seventh auxiliary layer 433 extend along a first direction D1. In a second direction D2, the edge of the orthographic projection of the seventh auxiliary layer 433 on the substrate extends relative to the edge of the orthographic projection of the fifth auxiliary layer 431 on the substrate. The minimum distance between the edge of the orthographic projection of the seventh auxiliary layer 433 on the substrate and the edge of the orthographic projection of the fifth auxiliary layer 431 on the substrate in the second direction D2 is greater than or equal to 0.01 microns and less than or equal to 0.05 microns.

[0256] The embodiment of the present disclosure shows that the substrate is located in the orthographic projection of the seventh auxiliary layer 433 on the substrate through the orthographic projection of the fifth auxiliary layer 431 on the substrate, so that the seventh auxiliary layer 433 completely blocks the fifth auxiliary layer 431, thereby improving the shielding effect of the seventh auxiliary layer 433 and preventing the pixel electrode from crosstalking with the fifth auxiliary layer 431.

[0257] Figure 16 is a schematic cross-sectional view of another display device according to an exemplary embodiment of the present disclosure. As shown in Figure 16, the present disclosure further provides a display device comprising a first substrate 100 and a second substrate 200 arranged in a pair, and a liquid crystal layer 300 disposed between the first substrate 100 and the second substrate 200. The first substrate 100 may be the aforementioned display substrate, and the second substrate 200 may be a color filter substrate. The display device may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, although the present invention is not limited thereto.

[0258] In an exemplary embodiment, a reflection reducing structure layer 80 is provided on a side of the second substrate 200 away from the first substrate 100 . The reflection reducing structure layer 80 can reduce light reflection of the display device.

[0259] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the present invention. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the present invention shall still be based on the scope defined by the appended claims.

Claims

1. A display substrate, comprising: a first trace disposed on a base, a first transistor disposed on a side of the first trace away from the base, a second trace disposed on a side of the first transistor away from the base, the first transistor including a third trace, at least one of the first trace, the second trace, and the third trace comprising an optical auxiliary structure, the optical auxiliary structure comprising n auxiliary layers, adjacent auxiliary layers having different refractive indices and materials, where n is a natural number greater than or equal to 2; and the optical auxiliary structure having a transmittance of less than 10% to natural light.

2. The display substrate according to claim 1, wherein: The optical auxiliary structure includes a first auxiliary layer and a second auxiliary layer. The first auxiliary layer is closer to the substrate than the second auxiliary layer. The refractive index of the first auxiliary layer is smaller than that of the second auxiliary layer.

3. The display substrate according to claim 2, wherein: A difference between a refractive index of the second auxiliary layer and a refractive index of the first auxiliary layer is greater than or equal to 0.7 and less than or equal to 2.

5.

4. The display substrate according to claim 2, wherein: The optical auxiliary structure also includes a third auxiliary layer and a fourth auxiliary layer, the third auxiliary layer is located on the side of the second auxiliary layer away from the substrate, the fourth auxiliary layer is located on the side of the third auxiliary layer away from the substrate, the refractive index of the third auxiliary layer is smaller than that of the second auxiliary layer, and the refractive index of the third auxiliary layer is smaller than that of the fourth auxiliary layer.

5. The display substrate according to claim 4, wherein: A difference between a refractive index of the second auxiliary layer and a refractive index of the third auxiliary layer is greater than or equal to 0.7 and less than or equal to 2.

5.

6. The display substrate according to claim 4, wherein: A difference between a refractive index of the fourth auxiliary layer and a refractive index of the third auxiliary layer is greater than or equal to 0.7 and less than or equal to 2.

5.

7. The display substrate according to claim 2, wherein: The ratio of the thickness of the first auxiliary layer to the thickness of the second auxiliary layer is greater than or equal to 0.8 and less than or equal to 50.

8. The display substrate according to claim 4, wherein: The ratio of the thickness of the second auxiliary layer to the thickness of the third auxiliary layer is greater than or equal to 0.1 and less than or equal to 100.

9. The display substrate according to claim 4, wherein: The ratio of the thickness of the fourth auxiliary layer to the thickness of the third auxiliary layer is greater than or equal to 0.1 and less than or equal to 300.

10. The display substrate according to claim 4, wherein: The first auxiliary layer, the second auxiliary layer, and the third auxiliary layer form a stack pattern, and the fourth auxiliary layer wraps a side surface of the stack pattern and a surface of the stack pattern away from the substrate.

11. The display substrate according to claim 10, wherein: The stacking pattern has a regular trapezoidal shape in a cross section perpendicular to the substrate.

12. The display substrate according to claim 11, wherein: The first auxiliary layer and the third auxiliary layer both extend along a first direction, and a minimum distance in a second direction between an edge of an orthographic projection of the third auxiliary layer on the substrate and an edge of an orthographic projection of the first auxiliary layer on the substrate is greater than or equal to 0.01 microns and less than or equal to 0.05 microns, and the first direction intersects the second direction.

13. The display substrate according to claim 11, wherein: An angle formed between a side surface of the stacking pattern and a plane where the substrate is located is greater than or equal to 30 degrees and less than or equal to 80 degrees.

14. The display substrate according to any one of claims 1 to 13, comprising a display area and a non-display area, the display area comprising the first transistor, the first transistor comprising a first active layer arranged on a side of the first routing away from the substrate, the third routing arranged on a side of the first active layer away from the substrate, and a first electrode and a fourth electrode arranged on a side of the third routing away from the substrate; the non-display area comprising a second transistor arranged on the substrate, the second transistor comprising a second active layer arranged on the substrate, a fourth routing arranged on a side of the second active layer away from the substrate, and a second electrode and a third electrode arranged on a side of the fourth routing away from the substrate.

15. The display substrate according to claim 14, wherein: The fourth wiring includes an optical auxiliary structure.

16. The display substrate according to claim 14, wherein: The fourth wiring is oxidized.

17. The display substrate according to claim 14, wherein: The first routing line and the fourth routing line are located in the same film layer.

18. The display substrate according to claim 14, wherein: The orthographic projections of the first active layer and the third wiring on the substrate overlap; the orthographic projections of the second active layer and the fourth wiring on the substrate overlap.

19. The display substrate according to claim 14, wherein: At least one of the first electrode and the fourth electrode is oxidized.

20. The display substrate according to claim 14, wherein The second wiring overlaps with an orthographic projection of the first electrode on the substrate.

21. The display substrate according to claim 20, wherein: The first electrode is connected to the first active layer through a first via hole. A light shielding block is provided on the second trace. The orthographic projection of the light shielding block on the substrate includes the orthographic projection of the first via hole on the substrate.

22. The display substrate according to claim 21, wherein A minimum distance between an edge of an orthographic projection of the light shielding block on the substrate and an edge of an orthographic projection of the first via hole on the substrate is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers.

23. A display device comprising the display substrate according to any one of claims 1 to 22. 24 . The display device according to claim 23 , further comprising a color filter substrate, wherein the color filter substrate is arranged in a cell-matched arrangement with the display substrate, and a anti-reflection structure layer is provided on a side of the color filter substrate away from the display substrate.

25. A method for preparing a display substrate, comprising: forming a first trace on a substrate; forming a first transistor on a side of the first wiring away from the substrate, wherein the first transistor includes a third wiring; forming a second wiring on a side of the first transistor away from the substrate; At least one of the first routing, the second routing and the third routing includes an optical auxiliary structure, the optical auxiliary structure includes n auxiliary layers, the refractive index and material of adjacent auxiliary layers are different, n is a natural number greater than or equal to 2; the transmittance of the optical auxiliary structure to natural light is less than 10%.

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