Switching converter and zero-crossing detection circuit thereof

Abstract

Disclosed in the present invention are a switching converter and a zero-crossing detection circuit thereof. The zero-crossing detection circuit comprises: a low-side transistor control circuit used for generating a low-side transistor control signal on the basis of a high-side transistor control signal; a switching node voltage detection circuit used for generating a first pulse signal having a first pulse width when a synchronous power transistor is turned off in each switching cycle, and generating a second pulse signal having a second pulse width on the basis of a comparison result between a turn-off moment of the synchronous power transistor and an inductor current zero-crossing moment; and a phase-locked loop circuit used for providing a delayed current signal to the low-side transistor control circuit on the basis of the first pulse signal and the second pulse signal, so that the low-side transistor control circuit controls an effective level time of the low-side transistor control signal in a next switching cycle on the basis of the delayed current signal. Therefore, the inductor current can fluctuate within a tiny interval near 0 A, improving the accuracy of zero-crossing detection, reducing the circuit loss of the switching converter, and improving the efficiency of the switching converter.

Description

Switching converter and its zero-crossing detection circuit

[0001] This application claims priority to a Chinese invention application filed on December 27, 2023, with application number 2023118261221, entitled “Switching converter and zero-crossing detection circuit thereof,” and incorporates the entire specification, claims, drawings, and abstract of the above-mentioned Chinese invention application into this application by reference. Technical Field

[0002] The present invention relates to the technical field of switching power supplies, and more particularly to a switching converter and a zero-crossing detection circuit thereof. Background Art

[0003] Currently, wearable devices and IoT devices are mostly powered by lithium batteries, making the efficiency of switching power supplies increasingly important. Power supplies used in modern electronic devices are broadly categorized as linear regulated power supplies and switching regulated power supplies. Linear regulated power supplies operate in the amplifier region, offering advantages such as reduced interference, improved reliability, and lower cost. However, they also suffer from larger size and lower conversion efficiency. Compared to linear regulated power supplies, switching regulated power supplies can both step up and step down voltage, resulting in higher power efficiency. Switching converters use switching transistors to control the transfer of power from the input to the output, thereby providing a constant output voltage and / or current. These converters offer excellent light-load efficiency, fast transient response, and ease of implementation, leading to their widespread use in recent years.

[0004] To improve the conversion efficiency of switching converters, existing switching converters generally employ a synchronous rectification structure, using synchronous rectifier transistors instead of traditional diodes to rectify the inductor current. However, when the output load is light, the inductor current in a synchronous rectifier switching converter can reverse, causing energy loss. Therefore, a zero-crossing detection circuit is required to detect the reverse current in the synchronous rectifier transistor. When the zero-crossing detection circuit detects a reverse current in the synchronous rectifier transistor, it sends a signal to shut down the synchronous rectifier transistor to prevent the inductor current from reversely flowing.

[0005] FIG1 is a schematic circuit diagram of a conventional switching converter. As shown in FIG1 , the conventional switching converter 100 includes a power circuit, a switch node voltage detection circuit 110, a zero-crossing comparator 120, and a logic drive circuit 130. The power circuit is connected between the input and output terminals, and uses at least one inductive element and at least one switching element to regulate the current supplied to the load connected to the output terminal, thereby providing a stable and continuous output voltage Vout to the load according to the input voltage Vin. For example, the power circuit includes a main power transistor S1 and a synchronous power transistor S2 connected in series between the input terminal and the ground, as well as an inductor L1 and an output capacitor Cout. As the main power transistor S1 and the synchronous power transistor S2 continuously switch, the circuit generates an output voltage Vout, which is then smoothed and filtered by the output capacitor Cout before being provided to the load RL connected to the output terminal.

[0006] The zero-crossing comparator 120 is used to compare the switching node voltage Vsw with a zero-crossing reference value (e.g., a reference ground voltage). When it detects that the switching node voltage Vsw is greater than the zero-crossing reference value, it determines that the inductor current IL has become negative and provides a zero-crossing indication signal ZCD to the logic drive circuit 130. The logic drive circuit 130 then shuts off the synchronous power transistor S2 based on the zero-crossing indication signal ZCD, thereby preventing the inductor current from flowing in the reverse direction. However, due to the inherent delay of the comparator, the accuracy of zero-crossing detection is affected by the inherent delay of the zero-crossing comparator. When the switching converter is under light load, the zero-crossing point may advance or lag. When the zero-crossing point advances, the inductor current loses energy in the body diode of the rectifier. When the zero-crossing point lags, the inductor current may reverse direction, affecting the overall performance of the system and reducing the efficiency of the entire circuit.

[0007] To address the aforementioned issues, a conventional solution is to superimpose an offset voltage Vos on the input of the zero-crossing comparator 120 and control the magnitude of the offset voltage Vos via the switch node voltage detection circuit 110 based on the switch node voltage Vsw. When the synchronous power transistor S2 is on, if the zero-crossing comparator 120 turns off the synchronous power transistor S2 before the inductor current IL drops to 0A, the switch node SW will become a negative voltage due to the inductor current IL. The switch node voltage detection circuit 110 will reduce the offset voltage Vos based on the detected switch node voltage Vsw, thereby triggering zero-crossing detection in the next switching cycle at a lower inductor current threshold. Similarly, if the zero-crossing comparator 120 turns off the synchronous power transistor S2 only after the inductor current IL drops to 0A, the switch node voltage detection circuit 110 will increase the offset voltage Vos, allowing the zero-crossing comparator 120 to trigger zero-crossing detection in the next switching cycle at a higher inductor current threshold.

[0008] The disadvantage of the zero-crossing detection solution in the prior art is that a high-speed comparator and a corresponding offset voltage control circuit need to be provided in the circuit, which increases the complexity and area of ​​the circuit and increases the power consumption of the circuit. Summary of the Invention

[0009] In view of this, an object of the present invention is to provide a switching converter and a zero-crossing detection circuit thereof, which can improve the accuracy and efficiency of zero-crossing detection.

[0010] According to one aspect of the present invention, a zero-crossing detection circuit for a switching converter is provided. The switching converter includes a main power transistor, a synchronous power transistor, and an inductor connected between an input terminal and an output terminal. The zero-crossing detection circuit is configured to control the on-time of the synchronous power transistor based on voltage feedback at a switch node between the main power transistor and the synchronous power transistor. The zero-crossing detection circuit includes: a lower tube control circuit configured to generate a lower tube control signal based on an upper tube control signal, wherein the upper tube control signal is used to control the on-time and off-time of the main power transistor, and the lower tube control signal is used to control the on-time and off-time of the synchronous power transistor; a switch node voltage detection circuit configured to generate a first pulse signal having a first pulse width when the synchronous power transistor is turned off in each switching cycle, and to generate a second pulse signal having a second pulse width based on a comparison result between the turn-off time of the synchronous power transistor and the zero-crossing time of the inductor current; and a phase-locked loop circuit configured to provide a delayed current signal to the lower tube control circuit based on the first pulse signal and the second pulse signal, wherein the lower tube control circuit controls the effective level time of the lower tube control signal in the next switching cycle based on the delayed current signal.

[0011] Optionally, the zero-crossing detection circuit also includes: a load detection circuit, which is used to detect the load of the switching converter and provide a valid indication signal to the phase-locked loop circuit when the load is greater than a set threshold. The phase-locked loop circuit controls the lower tube control signal and the upper tube control signal to be inverted signals according to the valid indication signal.

[0012] Optionally, the switch node voltage detection circuit includes: a first pulse generating module, used to generate the first pulse signal according to the inverted signal of the lower tube drive signal when the synchronous power tube is turned off; and a second pulse generating module, used to generate the second pulse signal according to the lower tube drive signal and the switch node voltage when the synchronous power tube is turned off, the second pulse generating module is used to generate a valid pulse of the second pulse signal according to the switch node voltage when the turn-off moment of the synchronous power tube is ahead of the zero-crossing moment of the inductor current, and to set the second pulse signal to invalid when the turn-off moment of the synchronous power tube lags behind the zero-crossing moment of the inductor current, wherein the first pulse width of the first pulse signal is a fixed value, and the second pulse width of the second pulse signal is equal to the negative pulse width of the switch node voltage.

[0013] Optionally, the first pulse generating module includes: a pulse generator, used to receive the inverted signal of the lower tube driving signal, and generate a positive pulse signal when the rising edge of the inverted signal of the lower tube driving signal appears; an RS trigger, whose set end is connected to the output of the pulse generator, and whose output end is used to output the first pulse signal; and a delay device, whose input end is connected to the output end of the RS trigger, and whose output end is connected to the reset end of the RS trigger, and the output end of the delay device is used to flip to a high level after a set delay time after a rising edge appears at the output end of the RS trigger.

[0014] Optionally, the first pulse width of the first pulse signal is equal to the delay time set by the delay device.

[0015] Optionally, the second pulse generating module includes: a first inverter, whose input end is used to receive the lower tube drive signal, and whose output end is used to output the inverted signal of the lower tube drive signal; a first resistor, whose first end is connected to the power supply voltage; a first transistor, whose first end is connected to the second end of the first resistor, and whose control end is used to receive the inverted signal of the lower tube drive signal; a second resistor, whose first end is connected to the power supply voltage; a second transistor, whose first end is connected to the second end of the second resistor, and whose control end is used to receive a reference voltage; a third transistor, whose first end is used to receive the switch node voltage, whose control end is used to receive the inverted signal of the lower tube drive signal, and whose second end is connected to the second ends of the first transistor and the second transistor; a fourth transistor, whose first end is connected to the power supply voltage, and whose control end is connected to the middle node between the second resistor and the second transistor; a third resistor, whose first end is connected to the second end of the fourth transistor, and whose second end is connected to ground; and a first Schmitt trigger, whose input end is connected to the middle node between the fourth transistor and the third resistor, and whose output end is used to provide the second pulse signal.

[0016] Optionally, the phase-locked loop circuit includes: a charge and discharge module, used to charge and discharge the capacitor according to the first pulse signal and the second pulse signal to generate a voltage control signal; a voltage-to-current conversion module, used to convert the voltage control signal into a current signal; a current mirror module, used to mirror the current signal output by the voltage-to-current conversion module into the delayed current signal; and an enable control transistor, connected to the voltage-to-current conversion module, used to control the voltage-to-current conversion module to be closed when the indication signal is valid.

[0017] Optionally, the charge and discharge module includes: a first current source, a first control switch, a second control switch and a second current source connected in series between the power supply voltage and the ground, the control end of the first control switch is used to receive the first pulse signal, and the control end of the second control switch is used to receive the second pulse signal; a first capacitor and a fourth resistor connected in series between the intermediate node of the first control switch and the second control switch and the ground; and a second capacitor connected between the intermediate node of the first control switch and the second control switch and the ground, the first end of the second capacitor is used to output the voltage control signal, wherein the voltage-to-current conversion module includes: a fifth transistor, whose control end is used to receive the voltage control signal, and whose first end is used to output the current signal; and a fifth resistor, a first end of which is connected to the second end of the fifth transistor, and a second end of which is connected to the ground, wherein the enable control transistor includes a sixth transistor, the control end of the sixth transistor is used to receive the indication signal, the first end of the sixth transistor is connected to the control end of the fifth transistor, and the second end of the sixth transistor is connected to the ground, wherein the current mirror module includes: a seventh transistor and an eighth transistor, the first ends of the seventh transistor and the eighth transistor are connected to the power supply voltage, the control end and the second end of the seventh transistor are connected to the control end of the eighth transistor, the second end of the seventh transistor is also connected to the first end of the fifth transistor, and the second end of the eighth transistor is used to output the delayed current signal.

[0018] Optionally, the lower tube control circuit includes: a ninth transistor and a tenth transistor connected in series between the input end of the delayed current signal and the ground, the control ends of the ninth transistor and the tenth transistor being used to receive the upper tube control signal; a third capacitor, a first end of which is connected to the intermediate node between the ninth transistor and the tenth transistor, and a second end of which is connected to the ground; a second Schmitt trigger, an input end of which is connected to the first end of the third capacitor; and a NOR gate circuit, a first input end of which is connected to the output end of the second Schmitt trigger, a second input end of which is used to receive the upper tube control signal, and an output end of which is used to output the lower tube control signal.

[0019] According to another aspect of the present invention, a switching converter is provided, comprising: a main power tube connected between an input terminal and a switching node of the switching converter; a synchronous power tube connected between the switching node and ground; an inductor connected between the switching node and an output terminal of the switching converter; a logic drive circuit, configured to generate an upper tube drive signal for controlling the on / off of the main power tube according to an upper tube control signal, and to generate a lower tube drive signal for controlling the on / off of the synchronous power tube according to a lower tube control signal; and the above-mentioned zero-crossing detection circuit, configured to generate the lower tube control signal according to the upper tube control signal, and to control the effective level time of the lower tube control signal according to voltage feedback of the switching node.

[0020] In summary, the zero-crossing detection circuit of the switching converter provided by the embodiment of the present invention generates a first pulse signal with a fixed pulse width and a second pulse signal with a pulse width equal to the negative pulse width of the switching node voltage in each switching cycle when the synchronous power tube is turned off, and compares the pulse widths of the first pulse signal and the second pulse signal. If the pulse width of the second pulse signal is greater than the pulse width of the first pulse signal, the on-time of the synchronous power tube is increased in the next switching cycle; if the pulse width of the second pulse signal is less than the pulse width of the first pulse signal, the on-time of the synchronous power tube is reduced in the next switching cycle. After adjustment of multiple switching cycles, the negative pulse width of the switching node voltage Vsw is finally made to swing around the set delay time, and then the inductor current fluctuates around 0A±Vout*td / L, thereby improving the accuracy of zero-crossing detection, reducing the circuit loss of the switching converter, and improving the efficiency of the switching converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0022] FIG1 is a schematic circuit diagram of a conventional switching converter.

[0023] FIG2 is a schematic circuit diagram of a switching converter according to an embodiment of the present invention.

[0024] FIG3 is a schematic circuit diagram of a switch node voltage detection circuit according to an embodiment of the present invention.

[0025] FIG4 is a schematic circuit diagram of a phase-locked loop circuit according to an embodiment of the present invention.

[0026] FIG5 is a schematic circuit diagram of a low-side tube control circuit according to an embodiment of the present invention.

[0027] FIG6 is a working waveform diagram of a zero-crossing detection circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0029] Many specific details of the present invention are described below, such as component structures, materials, dimensions, processing techniques, and technologies, to provide a clearer understanding of the present invention. However, as will be appreciated by those skilled in the art, the present invention may be practiced without these specific details.

[0030] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by a programmable circuit. When an element or circuit is said to be "connected to" or "coupled to" another element, or when an element / circuit is said to be "connected to" or "coupled between" two nodes, it may be directly coupled or connected to the other element or there may be an intermediate element between the two. The connection or coupling between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0031] In the context of this application, when a transistor is in an "off state" or "disconnected," the transistor blocks current and / or does not substantially conduct current. Conversely, when the transistor is in an "on state" or "conducting," the transistor is able to conduct current significantly. For example, in one embodiment, the high voltage transistor comprises an N-channel metal oxide semiconductor (NMOS) field effect transistor (FET), wherein the high voltage is provided between a first terminal (i.e., drain) and a second terminal (i.e., source) of the transistor. In some embodiments, an integrated controller circuit can be used to drive the power switch when regulating the energy provided to the load. Additionally, for the purposes of this disclosure, "ground" or "ground potential" in this application refers to a reference voltage or potential relative to which all other voltages or potentials of an electronic circuit or integrated circuit (IC) are defined or measured.

[0032] FIG2 is a schematic circuit diagram of a switching converter according to an embodiment of the present invention. It should be noted that the buck converter shown in FIG2 is for illustration purposes only. Other embodiments of the buck converter 200 may be used without departing from the scope of the present invention.

[0033] As shown in FIG2 , the buck converter 200 includes a power circuit (also referred to as a "step-down synchronous rectification circuit") and a control circuit. The power circuit includes a power transistor S1, a power transistor S2, and an inductor L1. Power transistor S1 is also referred to as a main power transistor (or a high-side power transistor), and power transistor S2 is also referred to as a synchronous power transistor (or a low-side power transistor). Power transistors S1 and S2 are connected between the input terminal (e.g., input voltage Vin) and ground of the buck converter 200. The first end of the inductor L1 is connected to the switching node SW between the power transistors S1 and S2, and the second end of the inductor L1 is connected to the output voltage Vout. Furthermore, the power circuit of this embodiment further includes an output capacitor Cout connected between the output terminal of the buck converter 200 and ground. The output capacitor Cout is used to smooth and filter the output voltage Vout.

[0034] For example, either of the aforementioned power transistors S1 and S2 is a metal oxide semiconductor field effect transistor (MOSFET, hereinafter referred to as a MOS transistor). Without departing from the teachings of the present invention, other types of field effect transistors and / or other types of transistors known to those skilled in the art may also be used.

[0035] The control circuit is used to generate switching control signals (also known as pulse-width modulation (PWM) signals) for power transistors S1 and S2. Based on the switching control signals, it generates an upper transistor drive signal Hsdr applied to the gate of power transistor S1 and a lower transistor drive signal Lsdr applied to the gate of power transistor S2 to control power transistors S1 and S2 to alternately switch between an on state and an off state. For example, the PWM signal is a time-varying square wave that alternately transitions between a lower level and a higher level. This alternating transition causes power transistors S1 and S2 to alternately switch on and off.

[0036] For example, the control circuit alternately turns power transistors S1 and S2 on and off, utilizing inductor L1 for energy conversion. This results in a step-down of the input voltage Vin. The stepped-down voltage is then smoothed by inductor L1 and output capacitor Cout, and is then output as output voltage Vout. For example, when the PWM signal is at a high level, the main power transistor S1 is turned on, connecting the input voltage Vin to the output terminal through inductor L1. This causes current to flow through inductor L1, generating a magnetic field that stores energy within inductor L1. When the PWM signal is at a low level, the main power transistor S1 is turned off, causing the magnetic field to decay. Conversely, the energy stored in inductor L1 flows through synchronous power transistor S2 to the output load RL (e.g., output capacitor Cout connected across the output terminal). Ideally, if the switching of the main power transistor S1 and synchronous power transistor S2 is fast enough, the voltage converter can maintain a constant voltage level at the output voltage node.

[0037] For example, under light load conditions, the buck converter 200 has two conduction modes: discontinuous conduction mode (DCM) and continuous conduction mode (CCM). In DCM mode, the synchronous power transistor S2 is turned off when the inductor current IL decreases to 0A through the body diode freewheeling. In CCM mode, after the inductor current IL freewheels to 0A, the synchronous power transistor S2 is not controlled to turn off. Instead, it is turned off only when the inductor current IL reaches the maximum allowable negative current or the main power transistor S1 turns on, allowing the inductor current IL to continue flowing. Of course, a dead time is required between the conduction of the main power transistor S1 and the synchronous power transistor S2 to prevent shoot-through.

[0038] Specifically, the control circuit includes a zero-crossing detection circuit 210 and a logic drive circuit 220. The zero-crossing detection circuit 210 is configured to generate a lower-tube control signal Lson based on an upper-tube control signal Hson. The upper-tube control signal Hson is used to control the on-off of the power transistor S1, and the duration of its active level (e.g., high level) defines the on-time of the power transistor S1. The lower-tube control signal Lson is used to control the on-off of the power transistor S2, and the duration of its active level (e.g., high level) defines the on-time of the power transistor S2. Furthermore, the zero-crossing detection circuit 210 is configured to adjust the active level duration of the lower-tube control signal Lson based on the voltage Vsw at the switching node SW to control the on-time of the power transistor S2. The logic drive circuit 220 is configured to generate an upper-tube drive signal Hsdr applied to the gate of the power transistor S1 and a lower-tube drive signal Lsdr applied to the gate of the power transistor S2 based on the upper-tube control signal Hson and the lower-tube control signal Lson, respectively.

[0039] Specifically, the zero-crossing detection circuit 210 of this embodiment includes a lower tube control circuit 211 , a switch node voltage detection circuit 212 , a phase-locked loop circuit 213 , and a load detection circuit 214 .

[0040] The lower-side control circuit 211 is configured to generate a lower-side control signal Lson based on the upper-side control signal Hson. The switch node voltage detection circuit 212 is configured to generate a first pulse signal UP having a first pulse width when the synchronous power transistor S2 is turned off during each switching cycle, and to generate a second pulse signal DN having a second pulse width based on a comparison between the turn-off instant of the synchronous power transistor S2 and the zero-crossing instant of the inductor current IL. The phase-locked loop circuit 213 is configured to provide a delayed current signal Idly to the lower-side control circuit 211 based on the first pulse signal UP and the second pulse signal DN. The lower-side control circuit 211 controls the active level duration of the lower-side control signal Lson during the next switching cycle based on the delayed current signal Idly. The load detection circuit 214 is configured to detect the load of the switching converter 200 and, when the load exceeds a set threshold, provide a valid indication signal CCM to the phase-locked loop circuit 213. Based on the valid indication signal CCM, the phase-locked loop circuit 213 controls the lower-side control signal Lson to be inversely proportional to the upper-side control signal Hson.

[0041] For example, the load detection unit 214 of this embodiment is configured to detect the load status of the switching converter by detecting the on-current of the main power transistor S1. For example, when the on-current of the main power transistor S1 is too large, it is determined that the load of the switching converter is heavy. The load detection unit 214 then outputs a valid (e.g., high) indication signal CCM. The phase-locked loop circuit 213 outputs a delayed current signal Idly of 0 based on the valid indication signal CCM, causing the lower transistor control signal Lson to change in accordance with the upper transistor control signal Hson. At this point, the switching converter 200 operates in CCM mode, and the circuit no longer triggers zero-crossing detection. Specifically, when the indication signal CCM is valid, the synchronous power transistor S2 and the main power transistor S1 can be turned on in a complementary manner, thereby ensuring continuous inductor current.

[0042] For example, the load detection circuit 214 can reuse other signals in the switching converter 200. For example, for a peak current mode switching converter, the load detection circuit 214 can determine the converter's load status based on the output of the error amplifier. For another example, the load detection circuit 214 can also determine the converter's load status based on the current sampling signal of the main power transistor S1 or the current sampling signal of the synchronous power transistor S2. This eliminates the need for a new sampling module in the circuit, reducing circuit area, complexity, and cost.

[0043] Figure 3 is a schematic circuit diagram of a switch node voltage detection circuit according to an embodiment of the present invention. As shown in Figure 3, the switch node voltage detection circuit 212 of this embodiment includes a first pulse generation module 2121 and a second pulse generation module 2122. The first pulse generation module 2121 is configured to generate a first pulse signal UP based on the inverted signal Lsdrb of the lower-side drive signal Lsdr when the synchronous power transistor S2 is turned off, wherein the pulse width of the first pulse signal UP is a fixed value. The second pulse generation module 2122 is configured to generate a second pulse signal DN based on the lower-side drive signal Lsdr and the switch node voltage Vsw when the synchronous power transistor S2 is turned off. For example, the second pulse generation module 2122 is configured to generate an active pulse of the second pulse signal DN based on the switch node voltage Vsw when the turn-off time of the synchronous power transistor S2 precedes the zero-crossing time of the inductor current IL, wherein the pulse width of the second pulse signal DN is equal to the negative-going pulse width of the switch node SW after the synchronous power transistor S2 is turned off. The second pulse generating module 2122 is further configured to set the second pulse signal DN to be invalid (eg, low level) when the turn-off moment of the synchronous power transistor S2 lags behind the zero-crossing moment of the inductor current IL.

[0044] Specifically, the first pulse generation module 2121 includes a pulse generator X1, an RS flip-flop consisting of NOR gates NOR1 and NOR2, and a delay device D1. The pulse generator X1 is configured to receive the inverted signal Lsdrb of the lower tube drive signal and generate a positive pulse signal when the rising edge of the inverted signal Lsdrb of the lower tube drive signal occurs. The set terminal S of the RS flip-flop is connected to the output of the pulse generator X1, and its output terminal is configured to output the first pulse signal UP. The input terminal of the delay device D1 is connected to the output terminal Q of the RS flip-flop, and its output terminal is connected to the reset terminal R of the RS flip-flop. The output terminal of the delay device D1 is configured to flip to a high level after a set delay time td following a rising edge at the output terminal Q of the RS flip-flop. When the synchronous power transistor S2 is turned off, the lower tube drive signal Lsdr becomes low, and the inverted signal Lsdrb of the lower tube drive signal Lsdr becomes high. The pulse generator X1 generates a positive pulse signal at the set terminal S of the RS flip-flop based on the rising edge change of the signal Lsdrb. The pulse width of the positive pulse signal is, for example, 5 ns. The RS flip-flop flips the output terminal Q to a high level based on the pulse signal at the set terminal S, that is, the first pulse signal UP flips to a high level. Simultaneously, after the output terminal Q of the RS flip-flop flips to a high level, after a set delay time td, the delay device D1 flips the reset terminal R of the RS flip-flop to a high level, thereby causing the first pulse signal UP to flip to a low level. Therefore, the pulse width of the first pulse signal UP generated by the first pulse generation module 2121 is actually equal to the delay time td set by the delay device D1. The pulse width of the first pulse signal UP can be adjusted by adjusting the internal delay of the delay device D1.

[0045] The second pulse generation module 2122 includes an inverter INV1, resistors R1 to R3, PMOS transistors M1 and M4, NMOS transistors M2 and M3, and a Schmitt trigger SMIT1. The input of inverter INV1 is used to receive the lower tube drive signal Lsdr, and the output of inverter INV1 is used to output the inverted lower tube drive signal Lsdrb. A first end of resistor R1 is connected to the power supply voltage Vdd, a second end of resistor R1 is connected to the source of transistor M1, and a gate of transistor M1 is connected to the signal Lsdrb. A drain of transistor M3 is connected to the switch node voltage Vsw, a gate of transistor M3 is connected to the signal Lsdrb, and a source of transistor M3 is connected to the drain of transistor M1. A first end of resistor R2 is connected to the power supply voltage Vdd, a second end of resistor R2 is connected to the drain of transistor M2, a gate of transistor M2 is connected to the reference voltage Vref, and a source of transistor M2 is connected to the source of transistor M3. The source of the transistor M4 is connected to the power supply voltage Vdd, the gate of the transistor M4 is connected to the resistor R2 and the intermediate node of the transistor M2, the drain of the transistor M4 is connected to the first end of the resistor R3 and the input of the Schmitt trigger SMIT1, the second end of the resistor R3 is connected to the ground, and the output end of the Schmitt trigger SMIT1 is used to output the second pulse signal DN.

[0046] For example, the second pulse generation module 2122 of this embodiment utilizes a common-source amplifier circuit, which is faster than a conventional comparator. When the synchronous power transistor S2 is turned off, the low-side transistor drive signal Lsdr becomes low, and thus the signal Lsdrb becomes high. Transistor M1 turns off, and transistor M3 turns on. Transistor M3 applies the switch node voltage Vsw to the source of transistor M2. At this time, if the inductor current IL has not yet crossed zero, the switch node voltage Vsw is pulled to a negative voltage, and transistor M2 turns on. Transistor M2 pulls down the gate of transistor M4, allowing transistor M4 to conduct. Subsequently, the input of the Schmitt trigger SMIT1 is pulled high by transistor M4, causing the second pulse signal DN to flip to a high level. The high-level duration (i.e., pulse width) of the second pulse signal DN depends on the time the switch node voltage Vsw remains negative after the power transistor S2 is turned off. Once the switch node voltage Vsw is pulled above zero, transistors M2 and M4 are turned off, causing the second pulse signal DN to flip to a low level. When the synchronous power transistor S2 is turned off, if the inductor current IL has passed zero, the switch node voltage Vsw is a positive voltage. As mentioned above, the transistors M2 and M4 are not turned on, so the second pulse signal DN is always at a low level.

[0047] FIG4 is a schematic circuit diagram of a phase-locked loop circuit according to an embodiment of the present invention. As shown in FIG4 , the phase-locked loop circuit 213 of this embodiment includes a charge-discharge module 2131, a voltage-current conversion module 2132, a current mirror module 2133, and an enable control transistor M6. The charge-discharge module 2131 is used to charge and discharge the capacitor according to the first pulse signal UP and the second pulse signal DN to generate a voltage control signal Vctrl. The voltage-current conversion module 2133 is used to convert the voltage control signal Vctrl into a current signal. The current mirror module 2133 is used to mirror the current signal output by the voltage-current conversion module 2132 as the delayed current signal Idly. The enable control transistor M6 is connected to the voltage-current conversion module 2132 and is used to control the voltage-current conversion module 2132 to be turned off when the indication signal CCM is at a high level.

[0048] Specifically, the charge and discharge module 2131 includes current sources I1 and I2, control switches K1 and K2, capacitors C1 and C2, and resistor R4. The current source I1, the control switch K1, the control switch K2, and the current source I2 are connected in series between the power supply voltage Vdd and the ground, the control end of the control switch K1 is connected to the first pulse signal UP, and the control end of the control switch K2 is connected to the second pulse signal DN. The capacitor C1 and the resistor R4 are connected in series between the middle node of the control switches K1 and K2 and the ground, the capacitor C2 is connected between the middle node of the control switches K1 and K2 and the ground, and the first end of the capacitor C2 is used to output the voltage control signal Vctrl. The charge and discharge module 2131 is used to control the voltage of the voltage control signal Vctrl according to the pulse width between the first pulse signal UP and the second pulse signal DN. For example, when the pulse width of the second pulse signal DN is greater than the pulse width of the first pulse signal UP, the capacitor C1 and the capacitor C2 will discharge to the ground through the current source I2, so the voltage control signal Vctrl will decrease; when the pulse width of the second pulse signal DN is less than the pulse width of the first pulse signal UP, the capacitor C1 and the capacitor C2 will be charged by the current source I1, so the voltage control signal Vctrl will increase.

[0049] The voltage-to-current conversion module 2132 includes an NMOS transistor M5 and a resistor R5. The gate of the transistor M5 is connected to the voltage control signal Vctrl, the source of the transistor M5 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected to ground. The transistor M5 and the resistor R5 are used to convert the voltage control signal Vctrl into a current signal and output it through the drain of the transistor M5.

[0050] The current mirror module 2133 includes PMOS transistors M7 and M8. The sources of transistors M7 and M8 are connected to the power supply voltage Vdd, the gate and drain of transistor M7 are connected to the gate of transistor M8, the drain of transistor M7 is also connected to the drain of transistor M5 to receive the current signal output by the transistor M5, and the drain of transistor M8 is used to output the delayed current signal Idly.

[0051] The enable control transistor M6 is, for example, an NMOS transistor, whose drain is connected to the gate of the transistor M5, whose gate is connected to the indication signal CCM, and whose source is connected to ground. When the indication signal CCM is high, the transistor M6 is turned on, thereby pulling the gate of the transistor M5 low.

[0052] FIG5 is a schematic circuit diagram of a lower tube control circuit according to an embodiment of the present invention. As shown in FIG5 , the lower tube control circuit 211 includes a PMOS transistor M9, an NMOS transistor M10, a capacitor C3, a Schmitt trigger SMIT2, and a NOR gate NOR3. The source of transistor M9 is connected to the delayed current signal Idly, the drain of transistor M9 is connected to the drain of transistor M10 and the first end of capacitor C3, the source of transistor M10 is connected to ground, the gates of transistors M9 and M10 are connected to the upper tube control signal Hson, the second end of capacitor C3 is connected to ground, the input of Schmitt trigger SMIT2 is connected to the first end of capacitor C3, the output of Schmitt trigger SMIT2 is connected to one input of NOR gate NOR3, the other input of NOR gate NOR3 is connected to the upper tube control signal Hson, and the output of NOR gate NOR3 is used to output the lower tube control signal Lson.

[0053] In this embodiment, when the indication signal CCM output by the load detection unit 214 is valid, the delayed current signal Idly is 0, and the voltage on the capacitor C3 is also equal to 0. Therefore, the output of the Schmitt trigger SMIT2 is low, and the lower tube control signal Lson is controlled only by the upper tube control signal Hson. That is, when the upper tube control signal Hson is high, the lower tube control signal Lson is low; when the upper tube control signal Hson is low, the lower tube control signal Lson is high.

[0054] When indication signal CCM is inactive and power transistor S1 is turned off, the upper control signal Hson changes from a high level to a low level. Since the output of Schmitt trigger SMIT2 is also initially low, the lower control signal Lson is high. Simultaneously, transistor M9 turns on, and transistor M10 turns off. Transistor M9 charges capacitor C3 based on the delayed current signal Idly. When the voltage on capacitor C3 exceeds the flip threshold of Schmitt trigger SMIT2, the output of Schmitt trigger SMIT2 flips to a high level, which in turn flips the lower control signal Lson to a low level. Therefore, the magnitude of the delayed current signal Idly can be used to control the charging time of capacitor C3, and thus the high level duration of the lower control signal Lson.

[0055] Figure 6 is a working waveform diagram of the zero-crossing detection circuit according to an embodiment of the present invention. Figure 6 shows waveform diagrams of the inductor current IL, the switch node voltage Vsw, the first pulse signal UP, and the second pulse signal DN.

[0056] As shown in part A of Figure 6, the synchronous power tube S2 is turned on in time period t1, and the inductor current IL gradually decreases. If the inductor current IL has not yet crossed zero when the power tube S2 is turned off, the pulse width of the second pulse signal DN is t4. At this time, the pulse width t4 of the second pulse signal DN is greater than the pulse width td of the first pulse signal UP. Therefore, the voltage control signal Vctrl and the delayed current signal Idly are reduced, thereby increasing the on-time of the lower tube control signal Lson in the next switching cycle.

[0057] As shown in part B of Figure 6, the synchronous power tube S2 is turned on in time period t2, and the inductor current IL gradually decreases. If the inductor current IL has not yet crossed zero when the power tube S2 is turned off, the pulse width of the second pulse signal DN is time t5, and at this time the pulse width t5 of the second pulse signal DN is smaller than the pulse width td of the first pulse signal UP. Therefore, the voltage control signal Vctrl and the delayed current signal Idly are increased, and the on-time of the lower tube control signal Lson is reduced in the next switching cycle.

[0058] As shown in part C of FIG6 , during time period t3, the synchronous power tube S2 is turned off, and the inductor current IL gradually decreases. If the inductor current IL has passed zero when the power tube S2 is turned off, the second pulse signal DN is at a low level, and its pulse width is 0, which is smaller than the pulse width td of the first pulse signal UP. Therefore, the voltage control signal Vctrl and the delayed current signal Idly are increased, and the on-time of the lower tube control signal Lson is reduced in the next switching cycle.

[0059] In summary, the zero-crossing detection circuit of the switching converter provided by the embodiment of the present invention generates a first pulse signal with a fixed pulse width and a second pulse signal with a pulse width equal to the negative pulse width of the switching node voltage in each switching cycle when the synchronous power tube is turned off, and compares the pulse widths of the first pulse signal and the second pulse signal. If the pulse width of the second pulse signal is greater than the pulse width of the first pulse signal, the on-time of the synchronous power tube is increased in the next switching cycle; if the pulse width of the second pulse signal is less than the pulse width of the first pulse signal, the on-time of the synchronous power tube is reduced in the next switching cycle. After adjustment of multiple switching cycles, the negative pulse width of the switching node voltage Vsw is finally made to swing around the set delay time, and then the inductor current fluctuates around 0A±Vout*td / L, thereby improving the accuracy of zero-crossing detection, reducing the circuit loss of the switching converter, and improving the efficiency of the switching converter.

[0060] In addition, the zero-crossing detection circuit of the present invention does not need to provide a high-speed comparator and a corresponding offset voltage control circuit in the circuit, which reduces the complexity and area of ​​the circuit and can also reduce the power consumption of the circuit.

[0061] In the above embodiment, although a buck-type topology switching converter is described in conjunction with FIG2 , it can be understood that the zero-crossing detection circuit 210 of the embodiment of the present invention can also be used in switching converters of other topologies, including but not limited to buck-type, boost-type, buck-boost, forward-type, flyback-type and other topologies.

[0062] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0063] While embodiments of the present invention have been described above, these embodiments do not exhaustively describe all details and do not limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A zero-crossing detection circuit for a switching converter, the switching converter including a main power transistor, a synchronous power transistor, and an inductor connected between an input terminal and an output terminal, the zero-crossing detection circuit being configured to feedback-control the conduction time of the synchronous power transistor according to the switching node voltage between the main power transistor and the synchronous power transistor. Among them, The zero-crossing detection circuit includes: A lower transistor control circuit configured to generate a lower transistor control signal according to an upper transistor control signal, where the upper transistor control signal is used to control the conduction and turn-off of the main power transistor, and the lower transistor control signal is used to control the conduction and turn-off of the synchronous power transistor; A switching node voltage detection circuit configured to generate a first pulse signal with a first pulse width when the synchronous power transistor is turned off in each switching cycle, and generate a second pulse signal with a second pulse width according to a comparison result between the turn-off moment of the synchronous power transistor and the zero-crossing moment of the inductor current; A phase-locked loop circuit configured to provide a delay current signal to the lower transistor control circuit based on the first pulse signal and the second pulse signal, and the lower transistor control circuit controls the effective level time of the lower transistor control signal in the next switching cycle according to the delay current signal.

2. The zero-crossing detection circuit according to claim 1, wherein, It further includes: A load detection circuit configured to detect the load of the switching converter and provide a valid indication signal to the phase-locked loop circuit when the load is greater than a set threshold, and the phase-locked loop circuit controls the lower transistor control signal and the upper transistor control signal to be anti-phase signals according to the valid indication signal.

3. The zero-crossing detection circuit according to claim 1, wherein, The switching node voltage detection circuit includes: A first pulse generation module configured to generate the first pulse signal according to the inverted signal of the lower transistor drive signal when the synchronous power transistor is turned off; and A second pulse generation module configured to generate the second pulse signal according to the lower transistor drive signal and the switching node voltage when the synchronous power transistor is turned off, the second pulse generation module is configured to generate a valid pulse of the second pulse signal according to the switching node voltage when the turn-off moment of the synchronous power transistor is earlier than the zero-crossing moment of the inductor current, and set the second pulse signal to be invalid when the turn-off moment of the synchronous power transistor is later than the zero-crossing moment of the inductor current. Wherein, the first pulse width of the first pulse signal is a fixed value, and the second pulse width of the second pulse signal is equal to the negative pulse width of the switching node voltage.

4. The zero-crossing detection circuit according to claim 3, wherein, The first pulse generation module includes: A pulse generator configured to receive the inverted signal of the lower transistor drive signal and generate a positive pulse signal when the rising edge of the inverted signal of the lower transistor drive signal appears; An RS flip-flop, whose set terminal is connected to the output of the pulse generator, and whose output terminal is used to output the first pulse signal; and A delay element, whose input terminal is connected to the output terminal of the RS flip-flop, and whose output terminal is connected to the reset terminal of the RS flip-flop, and the output terminal of the delay element is configured to flip to a high level after a set delay time after the rising edge appears at the output terminal of the RS flip-flop.

5. The zero-crossing detection circuit according to claim 4, wherein, The first pulse width of the first pulse signal is equal to the delay time set by the delay element.

6. The zero-crossing detection circuit according to claim 3, wherein, The second pulse generation module includes: A first inverter, whose input terminal is used to receive the lower transistor driving signal, and whose output terminal is used to output the inverted signal of the lower transistor driving signal; A first resistor, whose first end is connected to the power supply voltage; A first transistor, whose first end is connected to the second end of the first resistor, and whose control terminal is used to receive the inverted signal of the lower transistor driving signal; A second resistor, whose first end is connected to the power supply voltage; A second transistor, whose first end is connected to the second end of the second resistor, and whose control terminal is used to receive a reference voltage; A third transistor, whose first end is used to receive the switch node voltage, whose control terminal is used to receive the inverted signal of the lower transistor driving signal, and whose second end is connected to the second ends of the first transistor and the second transistor; A fourth transistor, whose first end is connected to the power supply voltage, and whose control terminal is connected to the intermediate node between the second resistor and the second transistor; A third resistor, whose first end is connected to the second end of the fourth transistor, and whose second end is connected to the ground; and A first Schmitt trigger, whose input terminal is connected to the intermediate node between the fourth transistor and the third resistor, and whose output terminal is used to provide the second pulse signal.

7. The zero-crossing detection circuit according to claim 2, wherein, The phase-locked loop circuit includes: A charge and discharge module, which is used to charge and discharge a capacitor according to the first pulse signal and the second pulse signal to generate a voltage control signal; A voltage-to-current conversion module, which is used to convert the voltage control signal into a current signal; A current mirror module, which is used to mirror the current signal output by the voltage-to-current conversion module as the delay current signal; and An enable control transistor, which is connected to the voltage-to-current conversion module and is used to control the voltage-to-current conversion module to turn off when the indication signal is valid.

8. The zero-crossing detection circuit according to claim 7, wherein The charge and discharge module includes: A first current source, a first control switch, a second control switch, and a second current source connected in series between the power supply voltage and the ground. The control terminal of the first control switch is used to receive the first pulse signal, and the control terminal of the second control switch is used to receive the second pulse signal; A first capacitor and a fourth resistor connected in series between the intermediate node of the first control switch and the second control switch and the ground; and A second capacitor connected between the intermediate node of the first control switch and the second control switch and the ground. The first end of the second capacitor is used to output the voltage control signal, Wherein, the voltage-to-current conversion module includes: A fifth transistor, whose control terminal is used to receive the voltage control signal, and whose first end is used to output the current signal; and A fifth resistor, whose first end is connected to the second end of the fifth transistor, and whose second end is connected to the ground, Wherein, the enable control transistor includes a sixth transistor. The control terminal of the sixth transistor is used to receive the indication signal. The first end of the sixth transistor is connected to the control terminal of the fifth transistor, and the second end of the sixth transistor is connected to the ground, Wherein, the current mirror module includes: A seventh transistor and an eighth transistor, a first end of the seventh transistor and the eighth transistor being connected to the power supply voltage, a control end and a second end of the seventh transistor being connected to a control end of the eighth transistor, the second end of the seventh transistor further being connected to a first end of the fifth transistor, and the second end of the eighth transistor being configured to output the delay current signal.

9. The zero-crossing detection circuit according to claim 1, wherein, The lower transistor control circuit includes: A ninth transistor and a tenth transistor connected in series between an input end of the delay current signal and ground, control ends of the ninth transistor and the tenth transistor being configured to receive the upper transistor control signal; A third capacitor, a first end thereof being connected to an intermediate node between the ninth transistor and the tenth transistor, and a second end thereof being connected to ground; A second Schmitt trigger, an input end thereof being connected to the first end of the third capacitor; and A NOR gate circuit, a first input end thereof being connected to an output end of the second Schmitt trigger, a second input end thereof being configured to receive the upper transistor control signal, and an output end thereof being configured to output the lower transistor control signal.

10. A switching converter, comprising: A main power transistor connected between an input end of the switching converter and a switching node; A synchronous power transistor connected between the switching node and ground; An inductor connected between the switching node and an output end of the switching converter; A logic drive circuit configured to generate an upper transistor drive signal for controlling conduction and cutoff of the main power transistor according to an upper transistor control signal, and generate a lower transistor drive signal for controlling conduction and cutoff of the synchronous power transistor according to a lower transistor control signal; And The zero-crossing detection circuit according to any one of claims 1-9, the zero-crossing detection circuit being configured to generate the lower transistor control signal according to the upper transistor control signal, and control an effective level time of the lower transistor control signal according to a voltage feedback of the switching node.

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