Current bias circuit and power amplifier system

Abstract

The present invention provides a current bias circuit and a power amplifier system. The current bias circuit comprises a measurement unit, a conversion unit, and a detection current injection unit; the measurement unit is used for measuring a differential input voltage of gates of transistors in a power amplifier so as to output a first voltage and a second voltage; the first voltage comprises a static working voltage and a detection voltage; the detection voltage is increased along with the increase of the differential input voltage; the second voltage comprises a static working voltage; the conversion unit is used for converting the first voltage and the second voltage into a first current and a second current, respectively, and solving a difference between the first current and the second current to obtain a detection current; and the detection current injection unit is used for injecting the detection current into the power amplifier. The bias current of transistors in the power amplifier can be adaptively adjusted, so that the linear working range of the power amplifier is expanded.

Description

Current bias circuit and power amplifier system

[0001] Cross-references

[0002] This application claims priority to Chinese application No. 2023118162461, filed on December 26, 2023. The contents of the above application are incorporated herein by reference. Technical Field

[0003] The present invention relates to the technical field of power amplifiers, and in particular to a current bias circuit and a power amplifier system. Background Art

[0004] A power amplifier is a device that extracts energy from a DC power supply and converts it into power based on an input electrical signal. Its basic principle is to use a transistor to control the current of the power supply, causing the current to change with the input signal, thereby amplifying the signal's power. Its function is to enable signals to be transmitted farther and more clearly.

[0005] Power amplifier linearity is a key performance metric and plays a decisive role in circuit system performance. In mobile communication systems, power amplifiers amplify RF signals between base stations and end devices. Linearity is crucial in these systems because it ensures high-quality signal transmission, reducing bit error rates, increasing data rates and network capacity, while also ensuring signal accuracy and reliability. This is crucial for measuring target distance, speed, and direction, as well as accurately analyzing spectrum. In RF front-end modules, power amplifiers are often a key component of the signal chain, amplifying weak RF signals from the receiving antenna or converting digital signals into suitable RF signals. High linearity minimizes distortion, ensuring high sensitivity and a high signal-to-noise ratio.

[0006] The primary source of power amplifier nonlinearity is the nonlinear current-voltage characteristics of transistors. As the drain output voltage swing of a transistor increases, the transistor partially enters its linear region within a signal cycle. During this period, the transistor's voltage-to-current conversion capability weakens, reducing its equivalent transconductance and exhibiting gain compression. This nonlinearity is particularly severe for amplifiers designed using advanced silicon processes, where the supply voltage is limited by the device's breakdown voltage.

[0007] Existing technologies for improving power amplifier linearity include negative feedback and dynamic biasing. Negative feedback reduces the amplifier's gain's dependence on transistor transconductance by introducing resistor-based negative feedback, thereby improving linearity. However, the negative feedback resistor reduces gain, which in turn reduces the power amplifier's output power and efficiency. Existing dynamic biasing technology detects the power amplifier's input voltage swing and directly regulates the differential input voltage at the gate terminal. However, direct voltage-based gain control suffers from difficulties in gain adjustment and sensitivity to process, temperature, and voltage variations.

[0008] Therefore, it is necessary to provide a new current bias circuit and power amplifier system to solve the above problems existing in the prior art.

[0009] Summary of the Invention

[0010] The object of the present invention is to provide a current bias circuit and a power amplifier system, which can adaptively adjust the bias current of a transistor in a power amplifier, thereby expanding the linear operating range of the power amplifier.

[0011] To achieve the above objectives, the current bias circuit of the present invention is applied to a power amplifier and includes a detection unit, a conversion unit, and a detection current injection unit. The detection unit is used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage and a second voltage, wherein the first voltage includes a static operating voltage and a detection voltage, and the detection voltage increases as the differential input voltage increases. The second voltage includes a static operating voltage. The conversion unit is used to convert the first voltage and the second voltage into a first current and a second current, and calculate the difference between the first current and the second current to obtain the detection current. The detection current injection unit is used to inject the detection current into the power amplifier.

[0012] Optionally, the detection unit includes a first detection unit and a second detection unit, the input end of the first detection unit is connected to the power amplifier, used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage, and the input end of the second detection subunit is suspended, used to output a second voltage.

[0013] Optionally, the first detection unit includes a DC blocking capacitor unit, a first detector and a first filtering unit, the input end of the first detector is connected to the power amplifier through the DC blocking capacitor unit, the output end of the first detector is connected to the first filtering unit, and the first filtering unit is used to filter the output of the first detector to obtain the first voltage.

[0014] Optionally, the first detector includes a third NMOS transistor, a fourth NMOS transistor and a third resistor, the drain of the third NMOS transistor and the drain of the fourth NMOS transistor are both connected to the power supply voltage, the source of the third NMOS transistor and the source of the fourth NMOS transistor are connected, serving as the output end of the first detector, the gate of the third NMOS transistor is connected to one end of the third resistor, serving as the first input end of the first detector, and the gate of the fourth NMOS transistor is connected to the other end of the third resistor, serving as the second input end of the first detector.

[0015] Optionally, the first filtering unit includes a first resistor and a first capacitor, one end of the first resistor and one end of the first capacitor are both connected to the source of the third NMOS tube, and the other end of the first resistor and the other end of the first capacitor are both grounded.

[0016] Optionally, the DC blocking capacitor unit includes a third capacitor and a fourth capacitor, one end of the third capacitor and one end of the fourth capacitor are both connected to the power amplifier, the other end of the third capacitor is connected to the gate of the third NMOS tube, and the other end of the fourth capacitor is connected to the gate of the fourth NMOS tube.

[0017] Optionally, the second detection unit includes a second detector and a second filtering unit, the input end of the second detector is suspended, and the second filtering unit is used to filter the output of the second detector to obtain the second voltage.

[0018] Optionally, the second detector includes a fifth NMOS transistor, a sixth NMOS transistor and a fourth resistor, the drain of the fifth NMOS transistor and the drain of the sixth NMOS transistor are both connected to the power supply voltage, the source of the fifth NMOS transistor and the source of the sixth NMOS transistor are connected, serving as the output end of the second detector, the gate of the fifth NMOS transistor is connected to one end of the fourth resistor, serving as the first input end of the second detector, and the gate of the sixth NMOS transistor is connected to the other end of the fourth resistor, serving as the second input end of the second detector.

[0019] Optionally, the second filtering unit includes a second resistor and a second capacitor, one end of the second resistor and one end of the second capacitor are both connected to the source of the fifth NMOS tube, and the other end of the second resistor and the other end of the second capacitor are both grounded.

[0020] Optionally, the conversion unit includes a first cascode current mirror, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, and a tenth NMOS tube, the source of the seventh NMOS tube, the source of the eighth NMOS tube, the source of the ninth NMOS tube, and the source of the tenth NMOS tube are all grounded, the gate of the tenth NMOS tube is connected to the second voltage, the drain of the tenth NMOS tube is connected to the first output end of the first cascode current mirror, the gate of the seventh NMOS tube is connected to the first voltage, the drain of the first NMOS tube is connected to the drain of the eighth NMOS tube, the gate of the eighth NMOS tube, the gate of the ninth NMOS tube, and the second output end of the first cascode current mirror.

[0021] Optionally, the first cascode current mirror includes a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube, the source of the first PMOS tube and the source of the second PMOS tube are both connected to the power supply voltage, the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the drain of the second PMOS tube, and the source of the fourth PMOS tube, the drain of the first PMOS tube is connected to the source of the third PMOS tube, the drain of the third PMOS tube serves as the second output end of the first cascode current mirror, the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube and the drain of the fourth PMOS tube, serving as the first output end of the first cascode current mirror.

[0022] Optionally, the detection current injection unit includes a second cascode current mirror, an eleventh NMOS tube and a current source, the first output end of the second cascode current mirror is connected to the detection current, the second output end of the second cascode current mirror is connected to the drain of the eleventh NMOS tube, the gate of the eleventh NMOS tube and the positive electrode of the current source, and is connected to the power amplifier as the output end of the detection current injection unit, the negative electrode of the current source is connected to the power supply voltage, and the source of the eleventh NMOS tube is grounded.

[0023] Optionally, the second cascode current mirror includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube, the source of the fifth PMOS tube and the source of the sixth PMOS tube are both connected to the power supply voltage, the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube, the drain of the sixth PMOS tube, and the source of the eighth PMOS tube, the drain of the fifth PMOS tube is connected to the source of the seventh PMOS tube, the gate of the seventh PMOS tube is connected to the gate of the eighth PMOS tube and the drain of the eighth PMOS tube, serving as the first output end of the second cascode current mirror, and the drain of the seventh PMOS tube is connected to the drain of the eleventh NMOS tube.

[0024] The present invention also provides a power amplifier system, comprising a power amplifier and the current bias circuit.

[0025] Optionally, the power amplifier includes a first NMOS transistor, a second NMOS transistor, a first transformer, and a second transformer. The source of the first NMOS transistor and the source of the second NMOS transistor are both grounded. The first transformer includes a first main coil and a first secondary coil. One end of the first main coil serves as the input end of the power amplifier, and the other end of the first main coil is grounded. One end of the first secondary coil is connected to the gate of the first NMOS transistor and the detection unit, and the other end of the first secondary coil is connected to the gate of the second NMOS transistor and the detection unit. A center tap of the first secondary coil is connected to the output end of the detection current injection unit to receive the detection current. The second transformer includes a second main coil and a second secondary coil. One end of the second main coil is connected to the drain of the first NMOS transistor, and the other end of the second main coil is connected to the drain of the second NMOS transistor. The center tap of the second main coil is connected to the power supply voltage. One end of the second secondary coil serves as the output end of the power amplifier, and the other end of the second secondary coil is grounded.

[0026] The beneficial effects of the present invention are as follows: the current bias circuit includes a detection unit, a conversion unit and a detection current injection unit, the detection unit is used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage and a second voltage, the first voltage includes a static operating voltage and a detection voltage, the detection voltage increases as the differential input voltage increases, and the second voltage includes a static operating voltage; the conversion unit is used to convert the first voltage and the second voltage into a first current and a second current, and calculate the difference between the first current and the second current to obtain the detection current; the detection current injection unit is used to inject the detection current into the power amplifier, and can adaptively adjust the bias current of the transistor in the power amplifier, thereby expanding the linear operating range of the power amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is a circuit diagram of a power amplifier system according to some embodiments of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the present invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0029] In order to solve the problems in the prior art, an embodiment of the present invention provides a power amplifier system. Referring to FIG1 , the power amplifier system includes a power amplifier 100 and a current bias circuit 110 .

[0030] 1 , the power amplifier 100 includes a first NMOS transistor N1, a second NMOS transistor N2, a first transformer TF1, and a second transformer TF2. The source of the first NMOS transistor N1 and the source of the second NMOS transistor N2 are both grounded. The first transformer TF1 includes a first main winding and a first secondary winding. One end of the first main winding serves as the input terminal Pin of the power amplifier 100, and the other end of the first main winding is grounded. One end of the first secondary winding is connected to the gate of the first NMOS transistor N1 and the detection unit, and the other end of the first secondary winding is connected to the gate of the second NMOS transistor N2 and the detection unit. A center tap of the first secondary winding is connected to the output terminal of the detection current injection unit to receive the detection current. The second transformer TF2 includes a second main winding and a second secondary winding. One end of the second main winding is connected to the drain of the first NMOS transistor N1, and the other end of the second main winding is connected to the drain of the second NMOS transistor N2. The center tap of the second main winding is connected to the power supply voltage VDD. One end of the second secondary winding serves as the output terminal Pout of the power amplifier 100, and the other end of the second secondary winding is grounded.

[0031] In some embodiments, the current bias circuit includes a detection unit, a conversion unit, and a detection current injection unit. The detection unit is used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage and a second voltage. The first voltage includes a static operating voltage and a detection voltage. The detection voltage increases as the differential input voltage increases. The second voltage includes a static operating voltage. The conversion unit is used to convert the first voltage and the second voltage into a first current and a second current, and calculate the difference between the first current and the second current to obtain a detection current. The detection current injection unit is used to inject the detection current into the power amplifier.

[0032] In some embodiments, the detection unit includes a first detection unit and a second detection unit, the input end of the first detection unit is connected to the power amplifier, and is used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage, and the input end of the second detection subunit is suspended, and is used to output a second voltage.

[0033] In some embodiments, the first detection unit includes a DC blocking capacitor unit, a first detector and a first filtering unit, the input end of the first detector is connected to the power amplifier through the DC blocking capacitor unit, the output end of the first detector is connected to the first filtering unit, and the first filtering unit is used to filter the output of the first detector to obtain the first voltage.

[0034] 1 , the first detector includes a third NMOS transistor N3, a fourth NMOS transistor N4, and a third resistor R3. The drain of the third NMOS transistor N3 and the drain of the fourth NMOS transistor N4 are both connected to the power supply voltage VDD. The source of the third NMOS transistor N3 and the source of the fourth NMOS transistor N4 are connected to each other, serving as the output of the first detector. The gate of the third NMOS transistor N3 is connected to one end of the third resistor R3, serving as the first input of the first detector. The gate of the fourth NMOS transistor N4 is connected to the other end of the third resistor R3, serving as the second input of the first detector.

[0035] 1 , the first filtering unit includes a first resistor R1 and a first capacitor C1 , one end of the first resistor R1 and one end of the first capacitor C1 are both connected to the source of the third NMOS transistor N3 , and the other end of the first resistor R1 and the other end of the first capacitor C1 are both grounded.

[0036] In some embodiments, the DC blocking capacitor unit includes a third capacitor and a fourth capacitor, one end of the third capacitor and one end of the fourth capacitor are both connected to the power amplifier, the other end of the third capacitor is connected to the gate of the third NMOS transistor, and the other end of the fourth capacitor is connected to the gate of the fourth NMOS transistor. The third capacitor and the fourth capacitor are DC blocking capacitors.

[0037] 1 , one end of the third capacitor C3 is connected to the gate of the first NMOS transistor N1, one end of the fourth capacitor C4 is connected to the gate of the second NMOS transistor N2, the other end of the third capacitor C3 is connected to the gate of the third NMOS transistor N3, and the other end of the fourth capacitor C4 is connected to the gate of the fourth NMOS transistor N4.

[0038] In some embodiments, the second detection unit includes a second detector and a second filtering unit, the input end of the second detector is suspended, and the second filtering unit is used to filter the output of the second detector to obtain the second voltage.

[0039] 1 , the second detector includes a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a fourth resistor R4. The drain of the fifth NMOS transistor N5 and the drain of the sixth NMOS transistor N6 are both connected to the power supply voltage VDD. The source of the fifth NMOS transistor N5 and the source of the sixth NMOS transistor N6 are connected to serve as the output of the second detector. The gate of the fifth NMOS transistor N5 is connected to one end of the fourth resistor R4, serving as the first input of the second detector. The gate of the sixth NMOS transistor N6 is connected to the other end of the fourth resistor R4, serving as the second input of the second detector.

[0040] 1 , the second filtering unit includes a second resistor R2 and a second capacitor C2, one end of the second resistor R2 and one end of the second capacitor C2 are both connected to the source of the fifth NMOS transistor N5, and the other end of the second resistor R2 and the other end of the second capacitor C2 are both grounded.

[0041] 1 , the third resistor R3 and the fourth resistor R4 act as bias resistors and are configured through a digital to analog converter (DAC) to achieve multi-bit adjustability, the purpose of which is to adjust the detection threshold of the detection unit.

[0042] 1 , the conversion unit includes a first cascode current mirror, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, and a tenth NMOS transistor N10. The source of the seventh NMOS transistor N7, the source of the eighth NMOS transistor N8, the source of the ninth NMOS transistor N9, and the source of the tenth NMOS transistor N10 are all grounded. The gate of the tenth NMOS transistor N10 is connected to the second voltage. The drain of the tenth NMOS transistor N10 is connected to the first output end of the first cascode current mirror. The gate of the seventh NMOS transistor N7 is connected to the first voltage. The drain of the first NMOS transistor N1 is connected to the drain of the eighth NMOS transistor N8, the gate of the eighth NMOS transistor N8, the gate of the ninth NMOS transistor N9, and the second output end of the first cascode current mirror.

[0043] 1 , the first cascode current mirror includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4. The source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are both connected to the power supply voltage VDD. The gate of the first PMOS transistor P1 is connected to the gate of the second PMOS transistor P2, the drain of the second PMOS transistor P2, and the source of the fourth PMOS transistor P4. The drain of the first PMOS transistor P1 is connected to the source of the third PMOS transistor P3. The drain of the third PMOS transistor P3 serves as the second output end of the first cascode current mirror. The gate of the third PMOS transistor P3 is connected to the gate of the fourth PMOS transistor P4 and the drain of the fourth PMOS transistor P4, serving as the first output end of the first cascode current mirror.

[0044] 1 , the detection current injection unit includes a second cascode current mirror, an eleventh NMOS transistor N11, and a current source. A first output end of the second cascode current mirror is connected to the drain of the ninth NMOS transistor N9 to receive the detection current. A second output end of the second cascode current mirror is connected to the drain of the eleventh NMOS transistor N11, the gate of the eleventh NMOS transistor N11, and the positive electrode of the current source, and serves as the output end of the detection current injection unit and is connected to the center tap of the first secondary winding. The negative electrode of the current source is connected to the power supply voltage VDD, and the source of the eleventh NMOS transistor N11 is grounded.

[0045] 1 , the second cascode current mirror includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, and an eighth PMOS transistor P8. The source of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 are both connected to the power supply voltage VDD. The gate of the fifth PMOS transistor P5 is connected to the gate of the sixth PMOS transistor P6, the drain of the sixth PMOS transistor P6, and the source of the eighth PMOS transistor P8. The drain of the fifth PMOS transistor P5 is connected to the source of the seventh PMOS transistor P7. The gate of the seventh PMOS transistor P7 is connected to the gate of the eighth PMOS transistor P8 and the drain of the eighth PMOS transistor P8, serving as the first output end of the second cascode current mirror. The drain of the seventh PMOS transistor P7 is connected to the drain of the eleventh NMOS transistor N11.

[0046] 1 , the fifth PMOS transistor P5 and the seventh PMOS transistor P7 form an array, and their actual effective sizes are configured by control bits, so as to adjust the intensity of the detection current injected into the power amplifier 100 .

[0047] Referring to Figure 1 , the output voltage of the first detector is filtered by the first filtering unit to obtain a first voltage that is approximately DC. This first voltage increases with the gate voltage of the first NMOS transistor N1 and the gate voltage of the second NMOS transistor N2. The first voltage includes a static operating voltage and a detection voltage. The second detector, serving as a reference for the first detector, is capable of independently extracting the second voltage, namely, the static operating voltage. The tenth NMOS transistor N10 and the seventh NMOS transistor N7 convert the first and second voltages into a first current and a second current, respectively. These currents are then subtracted using the current mirror subtractor function of the conversion unit to obtain a detection current that is positively correlated with the gate voltage of the first NMOS transistor N1 and the gate voltage of the second NMOS transistor N2 and does not include the static operating current. The detection current and the reference current of the current source are injected into the eleventh NMOS transistor N11 together, and the first NMOS transistor N1 and the second NMOS transistor N2 of the power amplifier 100 mirror a channel bias current that is adjusted in real time with the gate voltage of the first NMOS transistor N1 and the gate voltage of the second NMOS transistor N2, thereby achieving linear enhancement of the power amplifier 100. The fifth PMOS transistor P5 and the seventh PMOS transistor P7 can adjust the injection intensity of the detection current; the third resistor R3 and the fourth resistor R4 function as bias resistors and, through configuration using a digital-to-analog converter, can adjust the detection threshold, thereby achieving linear enhancement effects of varying intensities and starting points; the first cascode current mirror and the second cascode current mirror are limited by their own voltage margins, thereby preventing transistor reliability issues caused by an unlimited increase in the output voltage and current of the current bias circuit 110.

[0048] While the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.

Claims

1. A current bias circuit, applied to a power amplifier, characterized in that It includes a detection unit, a conversion unit, and a detection current injection unit. The detection unit is used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage and a second voltage. The first voltage includes a static operating voltage and a detection voltage, and the detection voltage increases as the differential input voltage increases. The second voltage includes a static operating voltage. The conversion unit is used to convert the first voltage and the second voltage into a first current and a second current, and calculate the difference between the first current and the second current to obtain a detection current. The detection current injection unit is used to inject the detection current into the power amplifier.

2. The current biasing circuit according to claim 1, wherein The detection unit includes a first detection unit and a second detection unit. The input end of the first detection unit is connected to the power amplifier and is used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage. The input end of the second detection sub-unit is AC floating and is used to output a second voltage.

3. The current bias circuit according to claim 2, wherein The first detection unit includes a DC-blocking capacitor unit, a first detector, and a first filtering unit. The input end of the first detector is connected to the power amplifier through the DC-blocking capacitor unit. The output end of the first detector is connected to the first filtering unit. The first filtering unit is used to filter the output of the first detector to obtain the first voltage.

4. The current biasing circuit according to claim 3, wherein The first detector includes a third NMOS transistor, a fourth NMOS transistor, and a third resistor. The drains of the third NMOS transistor and the fourth NMOS transistor are both connected to the power supply voltage. The sources of the third NMOS transistor and the fourth NMOS transistor are connected as the output end of the first detector. The gate of the third NMOS transistor is connected to one end of the third resistor as the first input end of the first detector. The gate of the fourth NMOS transistor is connected to the other end of the third resistor as the second input end of the first detector.

5. The current biasing circuit according to claim 4, wherein, The first filtering unit includes a first resistor and a first capacitor. One end of the first resistor and one end of the first capacitor are both connected to the source of the third NMOS transistor. The other end of the first resistor and the other end of the first capacitor are both grounded.

6. The current bias circuit according to claim 4, wherein The DC-blocking capacitor unit includes a third capacitor and a fourth capacitor. One end of the third capacitor and one end of the fourth capacitor are both connected to the power amplifier. The other end of the third capacitor is connected to the gate of the third NMOS transistor. The other end of the fourth capacitor is connected to the gate of the fourth NMOS transistor.

7. The current bias circuit according to claim 2, wherein The second detection unit includes a second detector and a second filtering unit. The input end of the second detector is AC floating. The second filtering unit is used to filter the output of the second detector to obtain the second voltage.

8. The current bias circuit according to claim 7, characterized in that The second detector includes a fifth NMOS transistor, a sixth NMOS transistor, and a fourth resistor. The drains of the fifth NMOS transistor and the sixth NMOS transistor are both connected to the power supply voltage. The sources of the fifth NMOS transistor and the sixth NMOS transistor are connected to serve as the output terminal of the second detector. The gate of the fifth NMOS transistor is connected to one end of the fourth resistor to serve as the first input terminal of the second detector. The gate of the sixth NMOS transistor is connected to the other end of the fourth resistor to serve as the second input terminal of the second detector.

9. The current bias circuit according to claim 8, wherein The second filtering unit includes a second resistor and a second capacitor. One end of the second resistor and one end of the second capacitor are both connected to the source of the fifth NMOS transistor. The other end of the second resistor and the other end of the second capacitor are both grounded.

10. The current bias circuit according to claim 1, characterized in that, The conversion unit includes a first cascode current mirror, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor. The sources of the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are all grounded. The gate of the tenth NMOS transistor is connected to the second voltage. The drain of the tenth NMOS transistor is connected to the first output terminal of the first cascode current mirror. The gate of the seventh NMOS transistor is connected to the first voltage. The drain of the first NMOS transistor is connected to the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor, the gate of the ninth NMOS transistor, and the second output terminal of the first cascode current mirror.

11. The current bias circuit according to claim 10, wherein The first cascode current mirror includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply voltage. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the second PMOS transistor, and the source of the fourth PMOS transistor. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor. The drain of the third PMOS transistor serves as the second output terminal of the first cascode current mirror. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor and the drain of the fourth PMOS transistor to serve as the first output terminal of the first cascode current mirror.

12. The current biasing circuit according to claim 1, wherein The detection current injection unit includes a second cascode current mirror, an eleventh NMOS transistor, and a current source. The first output terminal of the second cascode current mirror is connected to the detection current. The second output terminal of the second cascode current mirror is connected to the drain of the eleventh NMOS transistor, the gate of the eleventh NMOS transistor, and the positive electrode of the current source to serve as the output terminal of the detection current injection unit and is connected to the power amplifier. The negative electrode of the current source is connected to the power supply voltage. The source of the eleventh NMOS transistor is grounded.

13. The current bias circuit according to claim 12, wherein The second cascode current mirror includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The sources of the fifth PMOS transistor and the sixth PMOS transistor are both connected to the power supply voltage. The gate of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor, the drain of the sixth PMOS transistor, and the source of the eighth PMOS transistor. The drain of the fifth PMOS transistor is connected to the source of the seventh PMOS transistor. The gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor and the drain of the eighth PMOS transistor, serving as the first output terminal of the second cascode current mirror. The drain of the seventh PMOS transistor is connected to the drain of the eleventh NMOS transistor.

14. A power amplifier system, characterized in that, It includes a power amplifier and the current bias circuit according to any one of claims 1 to 13.

15. The power amplifier system according to claim 14, wherein, The power amplifier includes a first NMOS transistor, a second NMOS transistor, a first transformer, and a second transformer. The sources of the first NMOS transistor and the second NMOS transistor are both grounded. The first transformer includes a first primary coil and a first secondary coil. One end of the first primary coil serves as the input terminal of the power amplifier, and the other end of the first primary coil is grounded. One end of the first secondary coil is connected to the gate of the first NMOS transistor and the detection unit, and the other end of the first secondary coil is connected to the gate of the second NMOS transistor and the detection unit. The center tap of the first secondary coil is connected to the output terminal of the detection current injection unit to receive the detection current. The second transformer includes a second primary coil and a second secondary coil. One end of the second primary coil is connected to the drain of the first NMOS transistor, and the other end of the second primary coil is connected to the drain of the second NMOS transistor. The center tap of the second primary coil is connected to the power supply voltage. One end of the second secondary coil serves as the output terminal of the power amplifier, and the other end of the second secondary coil is grounded.

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