Memory, manufacturing method therefor, and electronic device

Abstract

The present disclosure provides a memory, a manufacturing method therefor, and an electronic device. The memory comprises a plurality of bit line function groups, a plurality of storage units, and a stepped structure, each bit line function group comprising a first bit line structure, a plurality of second bit line structures, and a plurality of selection transistors. The first bit line structure comprises a first isolation layer and a first bit line circumferentially surrounding the first isolation layer. The plurality of second bit line structures are arranged on a first side of the first bit line in a third direction, the stepped structure is arranged on a second side of the first bit line in the third direction, and a plurality of conductive steps of the stepped structure are coupled with corresponding first bit lines, respectively.

Description

Memory and manufacturing method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 25, 2023, with application number 202311804212.0 and application name “Memory and its manufacturing method, electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a memory, a manufacturing method thereof, and an electronic device. Background Art

[0003] With the continuous development of semiconductor technology and storage technology, electronic devices are constantly moving towards miniaturization and integration. Dynamic Random Access Memory (DRAM) is widely used in various electronic devices due to its high storage density and fast read and write speed.

[0004] A dynamic random access memory (DRAM) consists of word lines (WLs), bit lines (BLs), and multiple memory cells. Each memory cell typically includes an access transistor and a capacitor. The gate of the access transistor is electrically connected to the word line, one of its source and drain is electrically connected to the bit line, and the other of its source and drain is electrically connected to the capacitor. The voltage on the word line can control the on and off of the access transistor, allowing data information in the capacitor to be read or written to the capacitor through the bit line.

[0005] To increase storage density, bit lines typically include common bit lines and local bit lines, with the local bit lines coupled to corresponding memory cells. The common bit lines are coupled to the local bit lines via select transistors and externally connected via a ladder structure. However, during the fabrication process, the common bit lines are prone to disconnection, resulting in poor memory performance.

[0006] Summary of the Invention

[0007] In view of the above problems, embodiments of the present disclosure provide a memory, a method for manufacturing the same, and an electronic device, for improving the performance of the memory.

[0008] According to some embodiments, the present disclosure provides a memory comprising: a plurality of bit line functional groups arranged at intervals along a first direction, a plurality of memory cells, and a stepped structure; each of the bit line functional groups comprising: a first bit line structure comprising a first isolation layer extending along a second direction and a first bit line circumferentially surrounding the first isolation layer; a plurality of second bit line structures, the plurality of second bit line structures being located on a first side of the first bit line in a third direction and arranged at intervals along the second direction, each second bit line structure comprising a second bit line, the second direction, the third direction, and the first direction intersecting in pairs; a plurality of selection transistors, the plurality of selection transistors being located between the first bit line structure and the plurality of second bit line structures, the second bit lines in the plurality of second bit line structures being coupled to the first bit line respectively through the plurality of selection transistors; the plurality of memory cells being coupled to corresponding second bit line structures respectively; the stepped structure being located on a second side of the first bit line in the third direction and comprising a plurality of conductive steps, the plurality of conductive steps being coupled to the first bit lines in the plurality of bit line functional groups respectively.

[0009] In some possible implementations, the first bit line in at least one of the bit line functional groups includes a first bit line portion and a second bit line portion, the first bit line portion is in the shape of a non-closed ring, the opening of the non-closed ring is located on the second side of the first bit line structure in the third direction, the second bit line portion is located at the opening of the non-closed ring, and the second bit line portion and the conductive step have the same material composition.

[0010] In some possible implementations, the first bit lines in some of the bit line functional groups include a first bit line portion and a second bit line portion, and the first bit lines in the remaining bit line functional groups are in a closed ring shape; each of the second bit line structures also includes a second isolation layer extending along the third direction, and the second bit line circumferentially surrounds the second isolation layer.

[0011] In some possible implementations, the second isolation layer and the first isolation layer have the same material composition, and the first bit line portion and the second bit line have the same material composition.

[0012] In some possible implementations, the first isolation layers opposite to each other along the first direction are connected to form an integrated structure, and the first bit lines opposite to each other along the first direction are spaced apart from each other; the second isolation layers opposite to each other along the first direction are connected to form an integrated structure, and the second bit lines opposite to each other along the first direction are spaced apart from each other.

[0013] In some possible implementations, the multiple storage cells are arranged at intervals along the first direction, at intervals along the second direction, and at intervals along the third direction, and each of the second bit line structures is provided with a corresponding storage cell on at least one of the two opposite sides along the second direction.

[0014] In some possible implementations, each of the memory cells includes a coupled access transistor and a capacitor, the access transistor is coupled to the corresponding second bit line structure, and the capacitor is arranged on a side of the access transistor away from the corresponding second bit line structure.

[0015] In some possible implementations, the selection transistor and the access transistor include a gate, a gate dielectric layer surrounding the gate, and an active layer surrounding the gate dielectric layer; the gates opposite to each other along the first direction are connected to form a word line, the gate dielectric layers opposite to each other along the first direction are connected to form an integrated structure, and the active layers opposite to each other along the first direction are spaced apart from each other and coupled to the corresponding second bit line structure.

[0016] In some possible implementations, the capacitor includes a first electrode, a capacitor dielectric layer surrounding the first electrode, and a second electrode surrounding the capacitor dielectric layer; the first electrodes opposite to each other along the first direction are connected to form an integral structure, the capacitor dielectric layers opposite to each other along the first direction are connected to form an integral structure, and the second electrodes opposite to each other along the first direction are spaced apart from each other and coupled to the corresponding active layer.

[0017] In some possible implementations, each of the conductive steps has a groove, which separates the corresponding conductive step into a first segment and a second segment spaced apart along the second direction, the grooves are connected, and each of the grooves has a first end and a second end opposite to each other along the second direction; among any three adjacent grooves along the first direction, the first end of the middle groove is opposite to the first end of one of the remaining two grooves, and the second end is opposite to the second end of the other of the remaining two grooves, so that alternate rows of the first segments form a first step, alternate rows of the second segments form a second step, and the step surface of the first step and the step surface of the second step are staggered along the first direction, and the first step and the second step form the step structure.

[0018] In some possible implementations, each of the conductive steps has a first end and a second end opposite to each other along the second direction; among any three adjacent conductive steps along the first direction, the first end of the conductive step located in the middle is opposite to the first end of one of the remaining two conductive steps, and the second end is opposite to the second end of the other of the remaining two conductive steps, so that the first ends of the interlaced conductive steps form a first step, the second ends of the interlaced conductive steps form a second step, and the step surface of the first step and the step surface of the second step are staggered along the first direction, and the first step and the second step form the stepped structure.

[0019] In some possible implementations, the memory further includes a plurality of filling patterns located on a first side of the first bit line along the third direction, and along the second direction, the plurality of filling patterns are opposite to the plurality of selection transistors, and at least one of the filling patterns is arranged between two adjacent selection transistors.

[0020] The memory provided by the embodiments of the present disclosure has at least the following advantages:

[0021] The memory provided by the embodiments of the present disclosure includes multiple bitline functional groups, multiple memory cells, and a stepped structure. The multiple bitline functional groups are arranged in intervals along a first direction. Each bitline functional group includes a first bitline structure, multiple second bitline structures, and multiple select transistors. The first bitline structure includes a first isolation layer and a first bitline. The first isolation layer extends in a second direction, and the first bitline circumferentially surrounds the first isolation layer. Multiple second bitline structures are provided on a first side of the first bitline in a third direction, and the multiple second bitline structures are arranged in intervals along the second direction. Each second bitline structure is coupled to the first bitline structure via a select transistor. A stepped structure is provided on a second side of the first bitline in the third direction, and the multiple conductive steps of the stepped structure are respectively coupled to corresponding first bitlines. By arranging the stepped structure and the second bitline structures on both sides of the first bitline structure, and by adopting a structure in which the first bitline surrounds the first isolation layer, the first isolation layer can block the first bitline structure when the stepped structure is fabricated, preventing the portion of the first bitline located on the side of the first isolation layer close to the second bitline structure from being disconnected, thereby ensuring the consistency of this portion of the first bitline, thereby ensuring the connection performance with the second bitline structure and improving the performance of the memory.

[0022] According to some embodiments, the present disclosure further provides an electronic device comprising the memory as described above, and a processor coupled to the memory. The electronic device having the memory as described above has at least the advantage of good storage performance, as described above, and will not be further described here.

[0023] According to some embodiments, the present disclosure further provides a method for manufacturing a memory, comprising: forming a stacked structure on a substrate, the stacked structure comprising a first dielectric layer and a second dielectric layer alternately arranged in sequence along a first direction; removing a portion of the stacked structure to form a first trench and a plurality of second trenches, the first trench extending along a second direction, the plurality of second trenches being located on a first side of the first trench in a third direction and spaced apart along the second direction, with the second direction and the third direction intersecting the first direction in pairs; removing a portion of the first dielectric layer exposed in the first trench and the second trench to form a plurality of first receiving grooves communicating with the first trench and a plurality of second receiving grooves communicating with the second trench; forming a first bit line structure in the first trench and the first receiving groove, forming a second bit line structure in the second trench and the second receiving groove, and forming a stepped structure; the first bit line structure comprising a first isolation layer and a first bit line circumferentially surrounding the first isolation layer, the first bit line being correspondingly located in the first receiving groove, and the stepped structure being located on a second side of the first bit line in the third direction.

[0024] In some possible implementations, a first bit line structure is formed in the first trench and the first receiving groove, a second bit line structure is formed in the second trench and the second receiving groove, and the stepped structure is formed, including: depositing an initial conductive layer, the initial conductive layer fills the first receiving groove and the second receiving groove, and covers the side walls and bottom walls of the first trench, as well as the side walls and bottom walls of the second trench; retaining the initial conductive layer located in the first receiving groove and the second receiving groove, removing the remaining initial conductive layer, and the initial conductive layer located in the first receiving groove forms the first bit line; depositing an initial isolation layer, the initial isolation layer fills the remaining first trench and the remaining second trench, the initial isolation layer located in the first trench forms the first isolation layer, the initial conductive layer located in the second receiving groove and the initial isolation layer located in the second trench form the second bit line structure; forming the stepped structure, the stepped structure includes multiple conductive steps, and the multiple conductive steps are respectively coupled to the corresponding first bit lines.

[0025] In some possible implementations, the manufacturing method further includes: etching the first dielectric layer and the second dielectric layer to form a first hole, a second hole, a third hole, and a fourth hole; the first hole is located between the first bit line and the second bit line structure, the second hole is located on two opposite sides of the second bit line structure along the second direction, the third hole is located on a side of the second hole away from the second bit line structure, the fourth hole is located on a first side of the first bit line along the third direction, and along the second direction, the fourth hole is opposite to the first hole, and at least one fourth hole is provided between two adjacent first holes; forming a selection transistor, an access transistor, a capacitor, and a filling pattern, the selection transistor being located in the first hole and coupled to the second bit line structure, the access transistor being located in the second hole and coupled to both the second bit line structure and the first bit line, the capacitor being located in the third hole and coupled to the access transistor, and the filling pattern being located in the fourth hole.

[0026] In some possible implementations, the access transistor and the select transistor are formed simultaneously.

[0027] In some possible implementations, forming the stepped structure includes: etching the first dielectric layer and the second dielectric layer located on a side of the first bit line away from the second bit line structure to form a groove, wherein the groove exposes each first bit line, and two sidewalls opposite to each other along the second direction are both stepped, wherein a step surface of one sidewall includes surfaces of the odd-numbered second dielectric layers, excluding the second dielectric layer adjacent to the substrate, facing away from the substrate, and a step surface of the other sidewall includes surfaces of the even-numbered second dielectric layers facing away from the substrate; etching away a portion of the first dielectric layer exposed in the groove to form a third accommodating groove, wherein each first bit line is correspondingly exposed in the third accommodating groove; forming a conductive step, wherein the conductive step fills the third accommodating groove and contacts each first bit line, wherein each conductive step forms a stepped structure; and forming a third isolation layer in the groove, wherein the third isolation layer fills the groove.

[0028] The memory manufacturing method provided by the embodiments of the present disclosure has at least the following advantages:

[0029] In the manufacturing method of the memory provided by the embodiment of the present disclosure, a stacked structure is formed on a substrate, and part of the stacked structure is removed to form a first groove and a plurality of second grooves, wherein the plurality of second grooves are located on the first side of the first groove in the third direction and are arranged at intervals along the second direction. Part of the first dielectric layer exposed in the first groove and the second groove is removed to form a plurality of first receiving grooves connected to the first groove, and a plurality of second receiving grooves connected to the second groove. A first bit line structure is formed in the first groove and the first receiving groove, a second bit line structure is formed in the second groove and the second receiving groove, and a stepped structure is formed. The first bit line structure includes a first isolation layer and a first bit line circumferentially surrounding the first isolation layer, wherein the first bit line is correspondingly located in the first receiving groove, the stepped structure is located on the second side of the first bit line in the third direction, and includes a plurality of conductive steps, wherein the plurality of conductive steps are respectively coupled to the corresponding first bit line. By arranging the stepped structure and the second bit line structure on both sides of the first bit line structure, and the first bit line structure adopts a structure in which the first bit line surrounds the first isolation layer, when the stepped structure is manufactured, the first isolation layer can be used for blocking, thereby avoiding the disconnection of the part of the first bit line located on the side of the first isolation layer close to the second bit line structure, ensuring the consistency of the part of the first bit line, thereby ensuring the connection performance with the second bit line structure and improving the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic diagram of the structure of a memory in an embodiment of the present disclosure;

[0031] FIG2 is a schematic diagram of a first bit line structure, a second bit line structure, and a selection transistor in an embodiment of the present disclosure;

[0032] FIG3 is a simplified diagram of the architecture of a memory in one embodiment of the present disclosure;

[0033] FIG4 is a schematic diagram of a stepped structure in an embodiment of the present disclosure;

[0034] FIG5 is another schematic diagram of a stepped structure in an embodiment of the present disclosure;

[0035] FIG6 is another schematic diagram of a stepped structure in an embodiment of the present disclosure;

[0036] FIG7 is a flow chart of a method for manufacturing a memory in an embodiment of the present disclosure;

[0037] FIG8 is a perspective schematic diagram of a substrate and a laminate structure in one embodiment of the present disclosure;

[0038] FIG9 is a schematic plan view of a substrate and a laminate structure in one embodiment of the present disclosure;

[0039] FIG10 is a perspective schematic diagram after forming a first mask layer in one embodiment of the present disclosure;

[0040] FIG11 is a cross-sectional view at point A in FIG9 ;

[0041] FIG12 is a perspective schematic diagram of a first trench and a second trench formed in one embodiment of the present disclosure;

[0042] FIG13 is a diagram illustrating a process of forming a second receiving groove in one embodiment of the present disclosure;

[0043] FIG14 is a schematic diagram of forming a first receiving groove in one embodiment of the present disclosure;

[0044] FIG15 is a diagram illustrating a process of forming a second bit line and a second isolation layer in one embodiment of the present disclosure;

[0045] FIG16 is a process diagram of forming a first bit line and a first isolation layer in one embodiment of the present disclosure;

[0046] FIG17 is a perspective schematic diagram of a second mask layer formed in one embodiment of the present disclosure;

[0047] FIG18 is a perspective schematic diagram of a schematic diagram after etching a first dielectric layer in one embodiment of the present disclosure;

[0048] FIG19 is a perspective schematic diagram of a photoresist layer formed in one embodiment of the present disclosure;

[0049] FIG20 is a perspective schematic diagram of an embodiment of the present disclosure after two first dielectric layers are etched downward;

[0050] FIG21 is a perspective schematic diagram of a photoresist layer after expansion in one embodiment of the present disclosure;

[0051] FIG22 is a perspective schematic diagram of an embodiment of the present disclosure after further etching of two first dielectric layers;

[0052] FIG23 is a diagram illustrating a process of forming a third receiving groove in an embodiment of the present disclosure;

[0053] FIG24 is a diagram illustrating a process of forming a conductive step and a third isolation layer in one embodiment of the present disclosure;

[0054] FIG25 is a diagram illustrating a process of forming a third hole in one embodiment of the present disclosure;

[0055] FIG26 is a diagram illustrating a process of forming an initial electrode layer and a third dielectric layer in one embodiment of the present disclosure;

[0056] FIG27 is a diagram illustrating a process of forming a second electrode layer in one embodiment of the present disclosure;

[0057] FIG28 is a diagram illustrating a process of forming a capacitor dielectric layer in an embodiment of the present disclosure;

[0058] FIG29 is a schematic diagram after forming a first electrode in one embodiment of the present disclosure;

[0059] FIG30 is a diagram illustrating a process of forming a first hole in one embodiment of the present disclosure;

[0060] FIG31 is a diagram illustrating a process of forming an exposed initial active layer in one embodiment of the present disclosure;

[0061] FIG32 is a process diagram of forming an active layer in one embodiment of the present disclosure.

[0062] Description of reference numerals:

[0063] 10-bit line functional group; 11-first bit line structure; 12-first bit line;

[0064] 13-first isolation layer; 14-second bit line structure; 15-second bit line;

[0065] 16-second isolation layer; 17-select transistor; 18-fill pattern;

[0066] 20 - memory cell; 21 - access transistor; 22 - capacitor;

[0067] 23-capacitor plug; 30-step structure; 31-conductive step;

[0068] 32-first segment; 33-second segment; 34-bit line plug;

[0069] 35-third isolation layer; 40-base; 50-laminated structure;

[0070] 51-first dielectric layer; 52-second dielectric layer; 53-first trench;

[0071] 54 - second groove; 55 - first receiving groove; 56 - second receiving groove;

[0072] 61-gate; 62-gate dielectric layer; 63-active layer;

[0073] 71-first mask layer; 72-second mask layer; 73-photoresist layer;

[0074] 81 - third hole; 82 - initial electrode layer; 83 - third dielectric layer;

[0075] 84-second electrode; 85-capacitor dielectric layer; 86-first electrode;

[0076] 87 - first hole; 88 - initial active layer; 91 - groove;

[0077] 92-third receiving slot; 93-fourth receiving slot; 94-fifth receiving slot. DETAILED DESCRIPTION

[0078] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0079] Referring to Figures 1 to 6 , embodiments of the present disclosure provide a memory, which may be a dynamic random access memory (DRAM). The memory includes multiple bitline functional groups 10, multiple memory cells 20, and a ladder structure 30. The bitline functional groups 10 connect to corresponding memory cells 20 to read or write data from or to the corresponding memory cells 20. The multiple memory cells 20 are used to store data, and the ladder structure 30 is used to connect the multiple bitline functional groups 10 externally.

[0080] Multiple bit line functional groups 10 are arranged at intervals along a first direction, which is the Z direction as shown in Figure 1. Each bit line functional group 10 includes a first bit line structure 11, multiple second bit line structures 14, and multiple selection transistors 17. The multiple second bit line structures 14 are located on one side of the first bit line structure 11, and the first bit line structure 11 is coupled to the multiple second bit line structures 14 to serve as a common bit line, thereby aggregating the multiple second bit line structures 14. Each second bit line structure 14 is coupled to a corresponding memory cell 20, and the selection transistor 17 is used to select one of the second bit line structures 14. It can be understood that the first bit line structures 11 in the multiple bit line functional groups 10 are opposite to each other along the first direction, and the second bit line structures 14 in the multiple bit line functional groups 10 are opposite to each other along the first direction.

[0081] In some possible exemplary embodiments, the first bitline structure 11 includes a first isolation layer 13 and a first bitline 12. The first isolation layer 13 extends along a second direction, which intersects the first direction. The second direction is the X-direction shown in FIG1 . The first bitline 12 circumferentially surrounds the first isolation layer 13. For example, the first bitline 12 completely circumferentially surrounds the first isolation layer 13, i.e., the first bitline 12 is in the shape of a closed loop, completely surrounding the first isolation layer 13. A plurality of second bitline structures 14 are provided on a first side of the first bitline 12 in a third direction. The third direction intersects both the second direction and the first direction, i.e., the third direction, the second direction, and the first direction intersect in pairs, e.g., perpendicularly. The third direction is the Y-direction shown in FIG1 , and the first side of the first bitline 12 in the third direction is the upper side shown in FIG2 .

[0082] With this configuration, both sides of the first isolation layer 13 that are opposite to each other along the third direction have portions of the first bit line 12. When other structures are fabricated on one of the two sides of the first bit line 12 that are opposite to each other along the third direction, for example, when a stepped structure 30 is fabricated on the second side of the first bit line 12 in the third direction, the first isolation layer 13 can block the first bit line 12 on the other side, preventing disconnection, thereby ensuring the consistency of the first bit line 12 on the other side and its connectivity with other structures.

[0083] Along the third direction, the thickness of the first isolation layer 13 can be greater than the thickness of the first bit line 12. Exemplarily, the first isolation layer 13 includes a first sub-isolating layer extending along the second direction, and a second sub-isolating layer surrounding the first sub-isolating layer. The material of the first sub-isolating layer is different from that of the second sub-isolating layer. The thicker first sub-isolating layer can be made of an oxide, such as silicon oxide or aluminum oxide, while the thinner second sub-isolating layer can be made of a nitride, such as silicon nitride, silicon oxynitride, or silicon carbide nitride.

[0084] In some possible embodiments, the first bit line 12 in at least one bit line functional group 10 includes a first bit line portion and a second bit line portion, and the first bit line portion is in a non-closed loop shape. Exemplarily, the first bit line 12 in each bit line functional group 10 includes the first bit line portion and the second bit line portion. Alternatively, the first bit lines 12 in some bit line functional groups 10 include the first bit line portion and the second bit line portion in a non-closed loop shape (for example, such bit line functional groups are generally far from the substrate 40), while the first bit lines 12 in the remaining bit line functional groups 10 are in a closed loop shape (for example, such bit line functional groups are generally close to the substrate 40), that is, the first bit line portions in the remaining bit line functional groups 10 include the first bit line portion in a closed loop shape.

[0085] In the example where the first bit line 12 includes a first bit line portion and a second bit line portion, the first bit line portion is in a non-closed ring shape, and the opening of the non-closed ring is located on the second side of the first bit line structure 11 in the third direction. In some examples, the opening of the first bit line portion is formed during the fabrication of the stepped structure 30. The second bit line portion is located at the non-closed ring opening. Exemplarily, the second bit line portion completely fills the opening, and the first bit line portion and the second bit line portion are connected end to end to form a closed ring surrounding the first isolation layer 13.

[0086] It can be understood that an opening is formed between the two ends of the first bitline portion, the first bitline portion is continuous on the side of the first isolation layer 13 facing the second bitline structure 14, and both ends of the first bitline portion are located on the side of the first isolation layer 13 facing away from the second bitline structure 14. The first bitline portion is coupled to each second bitline structure 14, ensuring that each second bitline structure 14 is connected to a portion of the first bitline 12 having the same material composition, thereby ensuring consistency in the connection performance between each second bitline structure 14 and the first bitline 12.

[0087] Continuing with FIG1 , multiple second bitline structures 14 are located on a first side of the first bitline 12 in the third direction. Exemplarily, along the second direction, both ends of the first bitline 12 protrude beyond the two outermost second bitline structures 14, allowing multiple second bitlines 15 to pass through and couple to the first bitline 12. The multiple second bitline structures 14 extend along the third direction and are spaced apart along the second direction.

[0088] In some possible examples, the second bitline structure 14 includes a second isolation layer 16 extending along a third direction, and a second bitline 15 circumferentially surrounding the second isolation layer 16. For example, the second bitline 15 completely circumferentially surrounds the second isolation layer 16, i.e., the second bitline 15 is in the shape of a closed loop. Along the third direction, the thickness of the second isolation layer 16 can be greater than that of the second bitline 15. The second isolation layer 16 and the first isolation layer 13 have the same material composition, i.e., the second isolation layer 16 and the first isolation layer 13 have the same structure, and the corresponding film layers are made of the same material.

[0089] It is understood that the first isolation layer 13 has at least two film layers, and the second isolation layer 16 also has the same number of film layers. The arrangement direction of the film layers of the first isolation layer 13 is the same as the arrangement of the film layers of the second isolation layer 16. The film layers at corresponding positions in the first isolation layer 13 and the second isolation layer 16 are made of the same material. Exemplarily, the first isolation layer 13 includes a first sub-isolating layer and a second sub-isolating layer, with the second sub-isolating layer surrounding the first sub-isolating layer. Correspondingly, the second isolation layer 16 includes a third sub-isolating layer and a fourth sub-isolating layer, with the fourth sub-isolating layer surrounding the third sub-isolating layer. The first sub-isolating layer and the third sub-isolating layer are made of the same material, and the second sub-isolating layer and the fourth sub-isolating layer are made of the same material.

[0090] The first bit line 12 in some bit line functional groups 10 includes a first bit line portion and a second bit line portion, each having different material compositions. The first bit line 12 in the remaining bit line functional groups 10 includes only the first bit line portion. The first bit line portion in the remaining bit line functional groups 10 constitutes the entire first bit line 12, and the second bit line 15 and the first bit line portion have the same material composition. The second bit line 15 and the first bit line portion have the same structure, and the corresponding film layers are made of the same material.

[0091] In some possible examples, first isolation layers 13 opposing each other along a first direction are connected to form an integral structure, and first bit lines 12 opposing each other along the first direction are spaced apart to facilitate fabrication of the first isolation layer 13. It is understood that the first isolation layer 13 is columnar, with its axis oriented in the first direction. A cross-section of the first isolation layer 13 taken along a plane perpendicular to the axis is a long strip. Multiple first bit lines 12 are spaced apart and sleeved on the outer circumference of the first isolation layer 13 along the axis.

[0092] In some possible examples, second isolation layers 16 opposing each other along the first direction are connected to form an integrated structure, and second bit lines 15 opposing each other along the first direction are spaced apart to facilitate the fabrication of second isolation layers 16. It is understood that second isolation layer 16 is columnar, with its axis oriented in the first direction. A cross-section of second isolation layer 16 taken along a plane perpendicular to the axis is a long strip. Multiple second bit lines 15 are spaced apart and sleeved on the outer circumference of second isolation layer 16 along the axis.

[0093] Referring to Figures 1 to 3, multiple select transistors 17 are located between the first bitline structure 11 and the multiple second bitline structures 14. Each second bitline structure 14 is coupled to the first bitline structure 11 via a select transistor 17. Specifically, the multiple select transistors 17 are arranged in a spaced relationship along the second direction, with a select transistor 17 correspondingly disposed on a side of each second bitline structure 14 that faces the first bitline structure 11. The second bitline 15 in the second bitline structure 14 is coupled to a corresponding select transistor 17, and the first bitline 12 in the first bitline structure 11 is coupled to a corresponding select transistor 17.

[0094] A plurality of memory cells 20 are arranged at intervals along the first direction, at intervals along the second direction, and at intervals along the third direction. Each second bitline structure 14 is provided with a corresponding memory cell 20 on at least one of two opposing sides along the second direction, and the memory cell 20 is coupled to the corresponding second bitline structure 14. Exemplarily, each second bitline structure 14 is provided with a memory cell 20 on each of two opposing sides along the second direction to increase the storage density of the memory. The memory cells 20 on adjacent sides of two adjacent second bitline structures 14 are spaced apart.

[0095] As shown in FIG1 , each memory cell 20 includes a coupled access transistor 21 and a capacitor 22 . The access transistor 21 is coupled to a corresponding second bit line structure 14 , for example, to a corresponding second bit line 15 . The capacitor 22 is disposed on a side of the access transistor 21 away from the corresponding second bit line structure 14 .

[0096] In some possible implementations, the selection transistor 17 and the access transistor 21 each include a gate 61, a gate dielectric layer 62 surrounding the gate 61, and an active layer 63 surrounding the gate dielectric layer 62, that is, the access transistor 21 is a channel all around (CAA) transistor. The gates 61 opposite to each other along the first direction are connected to form a word line, that is, the word line extends along the first direction. The gate dielectric layers 62 opposite to each other along the first direction are connected to form an integrated structure, and the active layers 63 opposite to each other along the first direction are spaced apart from each other and coupled to the corresponding second bit line structure 14. The material of the active layer 63 can be indium gallium zinc oxide (IGZO) to improve the electron mobility and other performance of the active layer 63.

[0097] In some possible implementations, capacitor 22 includes a first electrode, a capacitor dielectric layer surrounding the first electrode, and a second electrode surrounding the capacitor dielectric layer. First electrodes opposing each other along a first direction are connected to form an integral structure, capacitor dielectric layers opposing each other along the first direction are connected to form an integral structure, and second electrodes opposing each other along the first direction are spaced apart and coupled to corresponding active layers 63. Multiple first electrodes are connected to form a first electrode column, which is further provided with a filling hole extending along the first direction, which is filled with capacitor plug 23.

[0098] Continuing with FIG. 1 , the memory device further includes a plurality of fill patterns 18 . These fill patterns 18 are located on a first side of the first bit line 12 along the third direction. That is, the fill patterns 18 and the select transistors 17 are located on the same side of the first bit line 12. Along a second direction, the fill patterns 18 face the select transistors 17. For example, the fill patterns 18 and the select transistors 17 form a row along the second direction. The presence of at least one fill pattern 18 between two adjacent select transistors 17 improves the uniformity of the overall arrangement of the select transistors 17, access transistors 21, and fill patterns 18, reducing etching loading during fabrication.

[0099] 3 , the stepped structure 30 is located on the second side of the first bit line 12 in the third direction. That is, the stepped structure 30 and the plurality of second bit line structures 14 are located on either side of the first bit line 12. The stepped structure 30 includes a plurality of conductive steps 31, each of which is coupled to the first bit line 12 in the plurality of bit line functional groups 10. That is, each first bit line 12 is connected to at least one (e.g., one) conductive step 31 to externalize the first bit line 12.

[0100] In the example where the first bit line 12 in the at least one bit line functional group 10 includes a first bit line portion and a second bit line portion, the second bit line portion and the conductive step 31 have the same material composition. The second bit line portion can be formed simultaneously with the conductive step 31, that is, when the conductive step 31 is formed, the material used to form the conductive step 31 also fills at least a portion of the opening in the first bit line portion, and this portion of material forms the second bit line portion.

[0101] In some possible implementations, referring to Figures 4 and 5 , each conductive step 31 has a groove that separates the corresponding conductive step 31 into a first segment 32 and a second segment 33 spaced apart along the second direction. The grooves are connected, and each groove has a first end and a second end opposite to each other along the second direction. The first end of each groove can be the left end as shown in Figure 4 , and the second end of each groove can be the right end as shown in Figure 4 .

[0102] Among any three adjacent grooves along the first direction, the first end of the middle groove is opposite to the first end of one of the remaining two grooves, and the second end is opposite to the second end of the other of the remaining two grooves, that is, a stepped structure 30 is formed in the middle of the conductive step 31. Specifically, as shown in FIG4 , two adjacent first segments 32 in the plurality of first segments 32 are aligned toward one end of the second segment 33, or two adjacent second segments 33 in the plurality of second segments 33 are aligned toward one end of the first segment 32, so that alternate rows of first segments 32 form a first step, and alternate rows of second segments 33 form a second step, and the step surfaces of the first step and the second step are staggered along the first direction, forming the stepped structure 30.

[0103] For example, there are five conductive steps 31. For ease of description, these five conductive steps 31 are sequentially defined as a first conductive step, a second conductive step, a third conductive step, a fourth conductive step, and a fifth conductive step. The first conductive step is located at the top, and the fifth conductive step is located at the bottom.

[0104] As shown in FIG4 , the first segment 32 of the fourth conductive step faces one end of the second segment 33 of the fourth conductive step (the right end in FIG4 ) and is aligned with one end of the first segment 32 of the third conductive step facing the second segment 33 of the third conductive step (the right end in FIG4 ). The first segment 32 of the second conductive step faces one end of the second segment 33 of the second conductive step (the right end in FIG4 ) and is aligned with one end of the first segment 32 of the first conductive step facing the second segment 33 of the first conductive step. The first segment 32 of the fifth conductive step, the first segment 32 of the third conductive step, and the first segment 32 of the first conductive step form a first step, which is used to externally connect the first bit line 12 corresponding to the fifth conductive step, the first bit line 12 corresponding to the third conductive step, and the first bit line 12 corresponding to the first conductive step (for example, via the bit line plug 34 in FIG4 ).

[0105] The second segment 33 of the fifth conductive step faces one end of the first segment 32 of the fifth conductive step (the left end as shown in FIG. 4 ) and is aligned with the second segment 33 of the fourth conductive step facing one end of the first segment 32 of the fourth conductive step (the left end as shown in FIG. 4 ). The second segment 33 of the third conductive step faces one end of the first segment 32 of the third conductive step (the left end as shown in FIG. 4 ) and is aligned with the second segment 33 of the second conductive step facing one end of the first segment 32 of the second conductive step (the left end as shown in FIG. 4 ). The second segment 33 of the fourth conductive step and the second segment 33 of the second conductive step form a second step, which is used to externally connect the first bit line 12 opposite the fourth conductive step and the first bit line 12 opposite the second conductive step (e.g., via the bit line plug 34 in FIG. 4 ).

[0106] Based on the above implementation, in some examples, referring to FIG. 5 , the non-aligned end of the topmost groove may further extend to the end of the corresponding conductive step 31 .

[0107] In other possible implementations, referring to FIG6 , each conductive step 31 has a first end and a second end that are opposite each other along the second direction. Of any three adjacent conductive steps 31 along the first direction, the first end of the middle conductive step 31 is opposite the first end of one of the remaining two conductive steps 31, and the second end is opposite the second end of the other of the remaining two conductive steps 31, thereby forming a stepped structure 30. In other words, the stepped structure 30 is formed at both ends of the conductive step 31 to reduce the difference in signal transmission resistance.

[0108] For example, there are five conductive steps 31. For ease of description, these five conductive steps 31 are sequentially defined as a first conductive step, a second conductive step, a third conductive step, a fourth conductive step, and a fifth conductive step. The first conductive step is located at the top, and the fifth conductive step is located at the bottom.

[0109] The first end of the fifth conductive step is aligned with the first end of the fourth conductive step, and the second end of the fifth conductive step protrudes from the second end of the fourth conductive step. The second end of the fourth conductive step is aligned with the second end of the third conductive step, and the first end of the fourth conductive step protrudes from the first end of the second conductive step. The first end of the third conductive step is aligned with the first end of the second conductive step, and the second end of the third conductive step protrudes from the second end of the second conductive step. The second end of the second conductive step is aligned with the second end of the first conductive step, and the first end of the second conductive step protrudes from the first end of the first conductive step.

[0110] The first end of the fourth conductive step and the first end of the second conductive step form a first step, which is used to externally connect the first bit line 12 opposite the fourth conductive step and the first bit line 12 opposite the second conductive step. The second end of the fifth conductive step, the second end of the third conductive step, and the second end of the first conductive step form a second step, which is used to externally connect the first bit line 12 opposite the fifth conductive step, the first bit line 12 opposite the third conductive step, and the first bit line 12 opposite the first conductive step.

[0111] In some other possible implementations, each conductive step 31 has a first end and a second end that are opposite each other along the second direction. Along the first direction, of two adjacent conductive steps 31, the first end of the lower conductive step 31 protrudes beyond the first end of the upper conductive step 31, and the second end of the lower conductive step 31 protrudes beyond the second end of the upper conductive step 31. The first ends of the conductive steps 31 in odd-numbered rows form a first step, and the second ends of the conductive steps 31 in even-numbered rows form a second step, thereby forming a stepped structure 30.

[0112] In summary, the memory in the embodiment of the present application includes a plurality of bitline functional groups 10, a plurality of memory cells 20, and a stepped structure 30. The plurality of bitline functional groups 10 are arranged in a first direction at intervals. Each bitline functional group 10 includes a first bitline structure 11, a plurality of second bitline structures 14, and a plurality of select transistors 17. The first bitline structure 11 includes a first isolation layer 13 and a first bitline 12. The first isolation layer 13 extends in a second direction, and the first bitline 12 circumferentially surrounds the first isolation layer 13. A plurality of second bitline structures 14 are provided on a first side of the first bitline 12 in a third direction. The plurality of second bitline structures 14 are arranged in a second direction at intervals, and each second bitline structure 14 is coupled to the first bitline structure 11 via a select transistor 17. A stepped structure 30 is provided on a second side of the first bitline 12 in the third direction. The plurality of conductive steps 31 of the stepped structure 30 are respectively coupled to corresponding first bitlines 12. By arranging the stepped structure 30 and the second bit line structure 14 on both sides of the first bit line structure 11, and the first bit line structure 11 adopts a structure in which the first bit line 12 surrounds the first isolation layer 13, when the stepped structure 30 is manufactured, the first isolation layer 13 can be used for blocking, thereby avoiding the disconnection of the part of the first bit line 12 located on the side of the first isolation layer 13 close to the second bit line structure 14, ensuring the consistency of this part of the first bit line 12, thereby ensuring the connection performance with the second bit line structure 14, and improving the performance of the memory.

[0113] The present application also provides an electronic device including a memory and a processor coupled to the memory. The memory can refer to the above, and the processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0114] The electronic device in the embodiment of the present application includes the above memory, and thus has the advantage that at least the first bit line 12 near the second bit line structure 14 is not easily disconnected and has good storage performance. Specific effects are described above and will not be repeated here.

[0115] 7 , an embodiment of the present application provides a method for manufacturing a memory, which specifically includes the following steps:

[0116] Step S100: forming a stacked structure on a substrate, the stacked structure comprising first dielectric layers and second dielectric layers alternately arranged in sequence along a first direction.

[0117] 8 and 9 , substrate 40 may be a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon germanium substrate, a germanium on insulator (GOI) substrate, or a silicon on insulator (SOI) substrate. A stacked structure 50 is formed on substrate 40 and includes first dielectric layers 51 and second dielectric layers 52 alternately arranged along a first direction. The first direction is the Z direction shown in FIG. 8 . In some examples, second dielectric layer 52 is disposed on substrate 40. The material of second dielectric layer 52 may be an oxide, such as silicon oxide, and the material of first dielectric layer 51 may be a nitride, such as silicon nitride or silicon oxynitride.

[0118] Step S200: removing part of the stacked structure to form a first groove and a plurality of second grooves, wherein the first groove extends along the second direction, and the plurality of second grooves are located on the first side of the first groove in the third direction and are arranged at intervals along the second direction, and the second direction, the third direction and the first direction intersect in pairs.

[0119] Referring to Figures 10 to 12 , a portion of the stacked structure 50 is removed to form a first trench 53 and a plurality of second trenches 54 within the stacked structure 50. The first trench 53 and the plurality of second trenches 54 expose the substrate 40. For example, the first trench 53 and the plurality of second trenches 54 penetrate the stacked structure 50, with their bottoms located within the substrate 40. The first trench 53 extends along a second direction that intersects, for example, is perpendicular to, the first direction. A plurality of second trenches 54 are formed on a first side of the first trench 53 in the third direction.

[0120] The plurality of second grooves 54 extend along a third direction and are spaced apart along the second direction. The third direction intersects both the second direction and the first direction. That is, the third direction, the second direction, and the first direction intersect with each other, for example, are perpendicular to each other. The second direction is the X direction shown in FIG12 , and the third direction is the Y direction shown in FIG12 .

[0121] The plurality of second trenches 54 and the first trenches 53 can be formed simultaneously through an etching process. As shown in FIG11 and FIG12 , a first mask layer 71 having a predetermined pattern is formed on the stacked structure 50. The first mask layer 71 is used as a mask to etch away the exposed portion of the stacked structure 50 to form the second trenches 54 and the first trenches 53. The remaining first mask layer 71 is then removed.

[0122] Step S300 : removing portions of the first dielectric layer exposed in the first trench and the second trench to form a plurality of first receiving grooves communicating with the first trench and a plurality of second receiving grooves communicating with the second trench.

[0123] Referring to Figures 13 and 14 , portions of the first dielectric layer 51 exposed within the first trench 53 are removed to form a plurality of first receiving grooves 55. The plurality of first receiving grooves 55 circumferentially surround the first trench 53 and communicate with the first trench 53. The plurality of first receiving grooves 55 are spaced apart from one another along the first direction. Portions of the second dielectric layer 52 exposed within the second trench 54 are removed to form a plurality of second receiving grooves 56. The plurality of second receiving grooves 56 circumferentially surround the second trench 54 and communicate with the second trench 54. The plurality of second receiving grooves 56 are spaced apart from one another along the first direction. The second receiving grooves 56 and the first receiving grooves 55 can be formed simultaneously.

[0124] Step S400: A first bit line structure is formed in the first groove and the first receiving groove, a second bit line structure is formed in the second groove and the second receiving groove, and a stepped structure 30 is formed; the first bit line structure includes a first isolation layer and a first bit line circumferentially surrounding the first isolation layer, the first bit line is correspondingly located in the first receiving groove, the stepped structure 30 is located on the second side of the first bit line in the third direction, and the stepped structure 30 is located on the second side of the first bit line in the third direction.

[0125] Referring to Figures 15 and 16 , as well as Figure 1 , a first bit line structure 11 is formed within the first trench 53 and the first receiving groove 55. The first bit line structure 11 includes a first isolation layer 13 and a first bit line 12. The first isolation layer 13 extends along the second direction, and the first bit line 12 circumferentially surrounds the first isolation layer 13, for example, completely surrounding the first bit line 12 circumferentially. The first isolation layer 13 is integral along the first direction, and the first bit lines 12 are correspondingly located within the first receiving groove 55. The first bit lines 12 are spaced apart from each other along the first direction.

[0126] In some possible examples, the first bit line 12 fills the entire first receiving groove 55, that is, the first bit line 12 is in a closed ring shape, with its inner surface aligned with the sidewall of the first trench 53, and the first isolation layer 13 is correspondingly filled within the first trench 53. In other possible examples, the first bit line 12 fills the portion of the first receiving groove 55 away from the first trench 53, that is, the first bit line 12 fills the bottom of the first receiving groove 55, the first isolation layer 13 fills the first trench 53 and the portion of the first receiving groove 55 adjacent to the first trench 53, and the first bit line 12 and a portion of the first isolation layer 13 fill the entire first trench 53. In yet other possible examples, the first bit line 12 fills the entire first receiving groove 55 and protrudes beyond the first receiving groove 55, that is, the first bit line 12 extends into the first trench 53, and the first isolation layer 13 fills the remaining portion of the first trench 53.

[0127] The stepped structure 30 is located on the second side of the first bit line 12 in the third direction. That is, the stepped structure 30 and the plurality of second bit line structures 14 are located on either side of the first bit line 12. The stepped structure 30 includes a plurality of conductive steps 31, which are arranged at intervals along the first direction and are respectively coupled to corresponding first bit lines 12 to externally connect the first bit lines 12. Each conductive step 31 is provided on the same layer as the second dielectric layer 52.

[0128] In summary, in the method for manufacturing a memory device according to an embodiment of the present application, a stacked structure 50 is formed on a substrate 40, and a portion of the stacked structure 50 is removed to form a first trench 53 and a plurality of second trenches 54. The plurality of second trenches 54 are located on a first side of the first trench 53 in the third direction and are spaced apart along the second direction. Portions of the first dielectric layer 51 exposed within the first trench 53 and the second trench 54 are removed to form a plurality of first receiving grooves 55 communicating with the first trench 53 and a plurality of second receiving grooves 56 communicating with the second trench 54. A first bit line structure 11 is formed within the first trench 53 and the first receiving groove 55, and a second bit line structure 14 is formed within the second trench 54 and the second receiving groove 56, thereby forming a stepped structure 30. The first bitline structure 11 includes a first isolation layer 13 and a first bitline 12 circumferentially surrounding the first isolation layer 13. The first bitline 12 is correspondingly located within the first receiving groove 55. The stepped structure 30 is located on the second side of the first bitline 12 in the third direction and includes a plurality of conductive steps 31. The plurality of conductive steps 31 are respectively coupled to corresponding first bitlines 12. By arranging the stepped structure 30 and the second bitline structure 14 on either side of the first bitline structure 11, and by adopting a structure in which the first bitline 12 surrounds the first isolation layer 13 in the first bitline structure 11, the first isolation layer 13 can provide a barrier when the stepped structure 30 is fabricated, preventing disconnection of the portion of the first bitline 12 on the side of the first isolation layer 13 near the second bitline structure 14, thereby ensuring the consistency of this portion of the first bitline 12 and thus ensuring connectivity with the second bitline structure 14, thereby improving memory performance.

[0129] In some possible examples, forming the first bit line structure 11 in the first trench 53 and the first receiving groove 55, forming the second bit line structure 14 in the second trench 54 and the second receiving groove 56, and forming the stepped structure 30 (step S400) includes:

[0130] Step S101 : depositing an initial conductive layer, which fills the first receiving groove 55 and the second receiving groove 56 and covers the sidewalls and bottom wall of the first trench 53 and the sidewalls and bottom wall of the second trench 54 .

[0131] An initial conductive layer is deposited in the first receiving groove 55, the second receiving groove 56, the first groove 53 and the second groove 54. The initial conductive layer fills the first receiving groove 55 and the second receiving groove 56, covers the side wall and bottom wall of the first groove 53, and covers the side wall and bottom wall of the second groove 54, but does not fill the first groove 53 and the second groove 54.

[0132] Exemplarily, the initial conductive layer includes an initial first conductive layer and an initial second conductive layer. The initial first conductive layer covers the sidewalls and bottom wall of the first receiving groove 55, the sidewalls and bottom wall of the second receiving groove 56, the sidewalls and bottom wall of the first trench 53, and the sidewalls and bottom wall of the second trench 54. The initial second conductive layer covers the initial first conductive layer and fills the remaining first receiving groove 55 and second receiving groove 56. The material of the initial first conductive layer can be titanium nitride, and the material of the initial second conductive layer can be tungsten.

[0133] Step S102 : retaining the initial conductive layer in the first receiving groove 55 and the second receiving groove 56 , removing the remaining initial conductive layer, and forming the first bit line 12 in the initial conductive layer in the first receiving groove 55 .

[0134] The initial conductive layer is etched to retain the initial conductive layer in the first receiving groove 55 and the second receiving groove 56, and the remaining initial conductive layer is removed to form the first bit line 12. There are multiple first bit lines 12, each located in a corresponding first receiving groove 55. The multiple first bit lines 12 are isolated from each other along the first direction.

[0135] Step S103: depositing an initial isolation layer, which fills the remaining first trench 53 and the remaining second trench 54. The initial isolation layer located in the first trench 53 forms a first isolation layer 13, and the initial conductive layer located in the second receiving groove 56 and the initial isolation layer located in the second trench 54 form a second bit line structure 14.

[0136] An initial isolation layer is deposited in the remaining first trenches 53 and second trenches 54 to fill the first trenches 53 and second trenches 54. The initial isolation layer located in the first trench 53 forms a first isolation layer 13, and the first isolation layer 13 is continuous along the first direction. The initial conductive layer located in the second receiving groove 56 forms a second bit line 15, and there are multiple second bit lines 15, and they are located in the corresponding second receiving grooves 56. The multiple second bit lines 15 are isolated from each other along the first direction. The initial isolation layer located in the second trench 54 forms a second isolation layer 16, and the second isolation layer 16 is continuous along the first direction. The second isolation layer 16 and the second bit line 15 form a second bit line structure 14, that is, the second bit line structure 14 and the first bit line structure 11 can be formed simultaneously, reducing the number of etching and deposition times and simplifying the manufacturing process.

[0137] Step S104 : forming a staircase structure 30 , the staircase structure 30 including a plurality of conductive steps 31 , each of which is coupled to a corresponding first bit line 12 .

[0138] The stepped structure 30 and the plurality of second bit line structures 14 are respectively located on both sides of the first bit line 12 . The stepped structure 30 includes a plurality of conductive steps 31 . The plurality of conductive steps 31 are arranged at intervals along the first direction and are respectively coupled to the corresponding first bit lines 12 to externally connect each first bit line 12 .

[0139] In some possible implementations, referring to FIG. 17 to FIG. 24 , forming the stepped structure 30 (step S104 ) specifically includes:

[0140] Step S1041: Etching the first dielectric layer 51 and the second dielectric layer 52 on the side of the first bit line 12 away from the second bit line structure 14 to form a groove 91. The groove 91 exposes each first bit line 12, and the two sidewalls opposite to each other along the second direction are both stepped. The step surface of one sidewall includes the surfaces of the odd-numbered second dielectric layers 52 excluding the second dielectric layer 52 adjacent to the substrate 40 facing away from the substrate 40, and the step surface of the other sidewall includes the surfaces of the even-numbered second dielectric layers 52 facing away from the substrate 40.

[0141] The groove 91 exposes a portion of each first bit line 12. The two opposing sidewalls of the groove 91 along the second direction are both stepped. Both the left and right sidewalls of the groove 91 are also stepped. The stepped surface of one of the two sidewalls of the groove 91 includes the surfaces of the odd-numbered second dielectric layers 52, excluding the second dielectric layer 52 adjacent to the substrate 40, facing away from the substrate 40. The stepped surface of the other of the two sidewalls of the groove 91 includes the surfaces of the even-numbered second dielectric layers 52 facing away from the substrate 40.

[0142] Illustratively, along the direction away from the substrate 40, the third second dielectric layer 52, ..., and the 2n+1th second dielectric layer 52 form a step surface on one side wall of the groove 91 on the surface facing away from the substrate 40, and the second second dielectric layer 52, ..., and the 2nth second dielectric layer 52 form a step surface on the other side wall of the groove 91 on the surface facing away from the substrate 40, where n is a positive integer greater than 1.

[0143] As shown in FIG. 17 to FIG. 22 , the groove 91 can be formed by the following process:

[0144] Referring to FIG17 , a second mask layer 72 is formed on the stacked structure 50. The second mask layer 72 includes the second side of the first bit line 12. Referring to FIG18 , the portion of the second dielectric layer 52 and the portion of the first dielectric layer 51 on the second side of the first bit line 12 that are furthest from the substrate 40 are removed by etching, exposing the second dielectric layer 52 beneath the first dielectric layer 51 and the first bit line 12 furthest from the substrate 40, thereby forming two step surfaces. Referring to FIG19 , a photoresist layer 73 is formed. The photoresist layer 73 has an opening that exposes portions of the two step surfaces. Referring to FIG20 , using the photoresist layer 73 as a mask, etching is performed downward to remove portions of the two second dielectric layers 52 and the corresponding two first dielectric layers 51, thereby transferring the two existing step surfaces downward and forming two new step surfaces. Referring to FIG21 , the opening in the photoresist layer 73 is enlarged. Using the enlarged photoresist layer 73 as a mask, etching is continued downward to remove portions of the two second dielectric layers 52 and the corresponding two first dielectric layers 51. The four original step surfaces are transferred downward to form two new step surfaces. This step is repeated until the second dielectric layer 52 closest to the substrate 40 is etched, or until the substrate 40 is reached, as shown in FIG22 .

[0145] Step S1042 : etching and removing the portion of the first dielectric layer 51 exposed in the groove 91 to form a third receiving groove 92 , wherein each first bit line 12 is correspondingly exposed in the third receiving groove 92 .

[0146] Referring to FIG. 23 , a portion of the sidewalls of the recess 91 is etched, removing a portion of the first dielectric layer 51 to form a plurality of third receiving grooves 92 spaced apart along the first direction. Each first bit line 12 is exposed within each of the third receiving grooves 92. In some examples, during the formation of the recess 91, the exposed first bit lines 12 may be etched, and even the exposed portions of some first bit lines 12 may be completely removed (the remaining portion being the first bit line portion), exposing the first isolation layer 13. The recess 91 and the third receiving grooves 92 are located on one side of the first isolation layer 13. The first isolation layer 13 can serve as a barrier layer to prevent disconnection of the first bit line 12 located on the other side of the first isolation layer 13, thereby ensuring that each second bit line structure 14 is connected to the same structure, ensuring the reliability and consistency of the connection.

[0147] Step S1043 : forming conductive steps 31 . The conductive steps 31 are filled in the third receiving grooves 92 and contact the first bit lines 12 . The conductive steps 31 form a stepped structure 30 .

[0148] Referring to Figures 23 and 24 , conductive steps 31 are deposited within the third receiving groove 92 . Each conductive step 31 is spaced apart along the first direction and contacts a corresponding first bit line 12 . The conductive steps 31 can be formed by deposition and etching back, and can completely fill the third receiving groove 92 . During the formation of the conductive steps 31 , the material of the conductive steps 31 also fills the removed portion of the first bit line (i.e., forming a second bit line portion). Each conductive step 31 forms a stepped structure 30, thereby enabling external connection to each first bit line 12 .

[0149] Step S1044 : forming a third isolation layer 35 in the groove 91 , wherein the third isolation layer 35 fills the groove.

[0150] 24 and 5 , the third isolation layer 35 may include a nitride layer conformally covering the stepped structure 30 and an oxide layer filling the remaining recess 91. Bitline plugs 34 are formed in the third isolation layer 35 and contact each conductive step 31 to externally connect the corresponding first bitline 12.

[0151] In some possible examples, referring to FIG. 25 to FIG. 32 , the manufacturing method further includes the following steps:

[0152] Step a: Etching the first dielectric layer 51 and the second dielectric layer 52 to form a first hole, a second hole, a third hole, and a fourth hole; the first hole is located between the first bit line 12 and the second bit line structure 14, the second hole is located on opposite sides of the second bit line structure 14 along the second direction, the third hole is located on the side of the second hole away from the second bit line structure 14, and the fourth hole is located on the first side of the first bit line 12 along the third direction. Along the second direction, the fourth hole is opposite to the first hole, and at least one fourth hole is provided between two adjacent first holes.

[0153] The first hole, the second hole, the third hole, and the fourth hole can penetrate the first dielectric layer 51 and the second dielectric layer 52. The first hole is located on the first side of the first bit line 12 in the second direction, on the same side as the second bit line structure 14, and on the side of the second bit line structure 14 adjacent to the first bit line 12. A plurality of second holes are provided on opposite sides of the second bit line structure 14 along the second direction, and the plurality of second holes are spaced apart along the third direction. The third hole is located on the side of the second bit line structure 14 away from the second bit line structure 14. The fourth hole is on the same side as the first hole and is arranged in a row with the first hole along the second direction. For example, the first hole and the fourth hole are evenly spaced apart.

[0154] In this way, the first hole, the second hole, the third hole, and the fourth hole are distributed more evenly, which reduces the loading effect when etching the first hole, the second hole, the third hole, and the fourth hole. It is understandable that this step can be performed before step S200, and the order is not limited.

[0155] Step b: Forming a selection transistor 17, an access transistor 21, a capacitor 22 and a filling pattern 18. The selection transistor 17 is located in the first hole and coupled to the second bit line structure 14. The access transistor 21 is located in the second hole and coupled to both the second bit line structure 14 and the first bit line 12. The capacitor 22 is located in the third hole and coupled to the access transistor 21. The filling pattern 18 is located in the fourth hole.

[0156] The access transistor 21 and the select transistor 17 are formed simultaneously to simplify the manufacturing process, and the material of the fill pattern 18 can be aluminum oxide. The access transistor body and the select transistor 17 can each include a gate 61, a gate dielectric layer 62 surrounding the gate 61, and an active layer 63 surrounding the gate dielectric layer 62. The gates 61 opposite to each other along the first direction are connected to form a word line, that is, the word line extends along the first direction. The gate dielectric layers 62 opposite to each other along the first direction are connected to form an integrated structure. The active layers 63 opposite to each other along the first direction are spaced apart from each other and coupled to the corresponding second bit line structure 14. The material of the active layer 63 can be indium gallium zinc oxide to improve the migration performance of the active layer 63.

[0157] Capacitor 22 includes a first electrode, a capacitor dielectric layer surrounding the first electrode, and a second electrode surrounding the capacitor dielectric layer. First electrodes facing each other along a first direction are connected to form an integrated structure. Capacitor dielectric layers facing each other along the first direction are connected to form an integrated structure. Second electrodes facing each other along the first direction are spaced apart and coupled to corresponding active layers 63. Multiple first electrodes are connected to form a first electrode column. The first electrode column also includes a filling hole extending along the first direction, which is filled with capacitor plug 23.

[0158] It is understood that the order in which the access transistor, select transistor 17, capacitor 22, and fill pattern 18 are fabricated is not limited, nor is the order in which the other structures are fabricated. For example, the fabrication process of the access transistor and select transistor 17 can be performed in conjunction with the fabrication process of the first bit line structure 11 and the second bit line structure 14.

[0159] In some possible implementations, the first hole, the second hole, the third hole, and the fourth hole are formed simultaneously. After the first hole, the second hole, the third hole, and the fourth hole are formed, filling material is formed in the first hole, the second hole, the third hole, and the fourth hole, and the filling material in the fourth hole forms a filling pattern 18.

[0160] In some possible implementations, referring to FIG. 25 to FIG. 29 , the capacitor 22 may be manufactured by the following process:

[0161] Referring to FIG. 25 , the filling material within the third hole 81 is removed, exposing the third hole 81. The first dielectric layer 51 exposed within the third hole 81 is then laterally etched to form a fourth receiving groove 93, thereby enlarging the third hole 81. Referring to FIG. 26 , an initial electrode layer 82 is formed on the sidewalls of the fourth receiving groove 93 and the sidewalls and bottom of the third hole 81. A third dielectric layer 83 is also formed to cover the initial electrode layer 82. The initial electrode layer 82 does not completely fill the fourth receiving groove 93, while the third dielectric layer 83 completely fills the fourth receiving groove 93. Referring to FIG. 26 , the third dielectric layer 83 outside the fourth receiving groove 93 is removed to expose a portion of the initial electrode layer 82. The exposed initial electrode layer 82 is removed to form a plurality of spaced-apart second electrodes 84, and the remaining third dielectric layer 83 is then removed. 28 , a capacitor dielectric layer 85 is formed in the third hole 81 and the fourth receiving groove 93 , and the capacitor dielectric layer 85 covers the second electrode 84 . Then, a first electrode 86 is formed in the remaining third hole 81 and the fourth receiving groove 93 .

[0162] In some possible implementations, referring to FIG. 30 to FIG. 32 , the selection transistor 17 may be manufactured by the following process:

[0163] Referring to FIG30 , the fill pattern within the third hole 81 is removed, exposing the first hole 87. The first dielectric layer 51 exposed within the first hole 87 is then laterally etched to form a fifth receiving groove 94. The fifth receiving groove 94 exposes the sidewalls of the first bit line 12 and the sidewalls of the second bit line 15. Referring to FIG31 , an initial active layer 88 is formed on the sidewalls of the fifth receiving groove 94 and the sidewalls and bottom of the first hole 87, filling the fifth receiving groove 94. Subsequently, referring to FIG32 , the initial active layer 88 on the sidewalls of the second dielectric layer 52 is etched away, leaving the initial active layer 88 within the fifth receiving groove 94 to form multiple active layers 63. A gate dielectric layer 62 is then formed within the first hole 87, conformally covering the active layer 63. A gate electrode 61 (i.e., a word line) is formed within the remaining first hole 87.

[0164] The fabrication of the access transistor 21 may refer to the fabrication of the selection transistor 17 . During the fabrication of the access transistor 21 , the sidewall of the corresponding second bit line 15 and the second electrode 84 of the capacitor are exposed. Other fabrication processes are similar to those of the selection transistor 17 and will not be described in detail here.

[0165] In this specification, each embodiment or implementation method is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0166] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A memory device, comprising: A plurality of bit line functional groups (10), a plurality of memory cells (20), and a stepped structure (30) arranged at intervals along a first direction (Z); Each of the bit line functional groups (10) includes: A first bit line structure (11), the first bit line structure (11) including a first isolation layer (13) extending along a second direction (X) and a first bit line (12) circumferentially surrounding the first isolation layer (13); A plurality of second bit line structures (14), the plurality of second bit line structures (14) being located on a first side of the first bit line (12) in a third direction (Y) and arranged at intervals along the second direction (X), each of the second bit line structures (14) including a second bit line (15), the second direction (X), the third direction (Y), and the first direction (Z) intersecting pairwise; A plurality of selection transistors (17), the plurality of selection transistors (17) being located between the first bit line structure and the plurality of second bit line structures, and the second bit lines in the plurality of second bit line structures being respectively coupled to the first bit line through the plurality of selection transistors; The plurality of memory cells (20) are respectively coupled to the corresponding second bit lines (15), the stepped structure (30) is located on a second side of the first bit line (12) in the third direction (Y), and includes a plurality of conductive steps (31), the plurality of conductive steps (31) being respectively coupled to the first bit lines (12) in the plurality of bit line functional groups (10).

2. The memory according to claim 1, wherein The first bit line (12) in at least one of the bit line functional groups (10) includes a first bit line portion and a second bit line portion, the first bit line portion is in a non-closed ring shape, the opening of the non-closed ring is located on a second side of the first bit line structure (11) in the third direction (Y), the second bit line portion is located at the opening of the non-closed ring, and the second bit line portion has the same material composition as the conductive step (31).

3. The memory according to claim 2, wherein, The first bit line (12) in some of the bit line functional groups (10) includes the first bit line portion and the second bit line portion, and the first bit lines (12) in the remaining bit line functional groups (10) are in a closed ring shape; Each of the second bit line structures (14) further includes a second isolation layer (16) extending along the third direction (Y), and the second bit line (15) circumferentially surrounds the second isolation layer (16).

4. The memory according to claim 3, wherein, The second isolation layer (16) has the same material composition as the first isolation layer (13), and the first bit line portion has the same material composition as the second bit line (15).

5. The memory according to claim 3 or 4, wherein The first isolation layers (13) opposite to each other along the first direction (Z) are connected to form an integral structure, and the first bit lines (12) opposite to each other along the first direction (Z) are spaced apart from each other; The second isolation layers (16) opposite to each other along the first direction (Z) are connected to form an integral structure, and the second bit lines (15) opposite to each other along the first direction (Z) are spaced apart from each other.

6. The memory according to any one of claims 1-5, wherein, The multiple memory cells (20) are arranged at intervals along the first direction (Z), at intervals along the second direction (X), and at intervals along the third direction (Y). At least one side of each of the two opposite sides of each second bit line structure (14) along the second direction (X) is correspondingly provided with a memory cell (20).

7. The memory according to claim 6, wherein, Each memory cell (20) includes a coupled access transistor (21) and a capacitor (22). The access transistor (21) is correspondingly coupled to the second bit line structure (14), and the capacitor (22) is disposed on a side of the access transistor (21) away from the corresponding second bit line structure (14).

8. The memory according to claim 7, wherein, The selection transistor (17) and the access transistor (21) include a gate (61), a gate dielectric layer (62) surrounding the gate (61), and an active layer (63) surrounding the gate dielectric layer (62). The gates (61) opposite to each other along the first direction (Z) are connected to form a word line. The gate dielectric layers (62) opposite to each other along the first direction (Z) are connected to form an integral structure. The active layers (63) opposite to each other along the first direction (Z) are spaced apart from each other and are coupled to the corresponding second bit line structure (14).

9. The memory according to claim 7 or 8, wherein, The capacitor (22) includes a first electrode (86), a capacitive dielectric layer (85) surrounding the first electrode, and a second electrode (84) surrounding the capacitive dielectric layer. The first electrodes (86) opposite to each other along the first direction (Z) are connected to form an integral structure. The capacitive dielectric layers (85) opposite to each other along the first direction (Z) are connected to form an integral structure. The second electrodes (84) opposite to each other along the first direction (Z) are spaced apart from each other and are coupled to the corresponding active layer (63).

10. The memory according to any one of claims 1-9, wherein, Each conductive step (31) has a groove (91). The groove (91) divides the corresponding conductive step (31) into a first segment (32) and a second segment (33) spaced apart along the second direction (X). The grooves (91) communicate with each other, and each groove (91) has a first end and a second end opposite to each other along the second direction (X). Among any three adjacent grooves (91) along the first direction (Z), the first end of the middle groove (91) is opposite to the first end of one of the remaining two grooves, and the second end is opposite to the second end of the other of the remaining two grooves, so that the first segments (32) in every other row form a first step, the second segments (33) in every other row form a second step, and the step surfaces of the first step and the second step are staggered along the first direction (Z). The first step and the second step form the stepped structure (30).

11. The memory according to any one of claims 1-9, wherein, Each conductive step (31) has a first end and a second end opposite to each other along the second direction (X). Among any three adjacent ones of the conductive steps (31) along the first direction (Z), the first end of the middle conductive step (31) is opposite to the first end of one of the remaining two conductive steps (31), and the second end is opposite to the second end of the other of the remaining two conductive steps (31), so that the first ends of the staggered conductive steps (31) form a first step, the second ends of the staggered conductive steps (31) form a second step, and the step surfaces of the first step and the second step are staggered along the first direction (Z), and the first step and the second step form the stepped structure (30).

12. The memory according to claims 1-11, wherein, The memory further includes a plurality of filling patterns (18) located on a first side of the first bit line (12) along the third direction (Y). Along the second direction (X), the plurality of filling patterns (18) are opposite to the plurality of selection transistors (17), and at least one of the filling patterns (18) is disposed between two adjacent selection transistors (17).

13. An electronic device, characterized in that, A memory, comprising the memory according to any one of claims 1-12, and a processor coupled to the memory.

14. A method for manufacturing a memory, comprising: forming a stacked structure (50) on a substrate (40), the stacked structure (50) including a first dielectric layer (51) and a second dielectric layer (50) alternately arranged in sequence along a first direction (Z); removing a part of the stacked structure (50) to form a first trench (53) and a plurality of second trenches (54), the first trench (53) extending along a second direction (X), the plurality of second trenches (54) being located on a first side of the first trench (53) in a third direction (Y) and being spaced apart from each other along the second direction (X), the second direction (X), the third direction (Y) and the first direction (Z) intersecting each other in pairs; removing a part of the first dielectric layer exposed in the first trench (53) and the second trenches (54) to form a plurality of first receiving grooves (55) communicating with the first trench (53) and a plurality of second receiving grooves (56) communicating with the second trenches (54); forming a first bit line structure (11) in the first trench (53) and the first receiving grooves (55), forming a second bit line structure (14) in the second trenches (54) and the second receiving grooves (56), and forming a stepped structure (30); the first bit line structure (11) includes a first isolation layer (13) and a first bit line (12) circumferentially surrounding the first isolation layer (13), the first bit line (12) being correspondingly located in the first receiving grooves (55), and the stepped structure (30) being located on a second side of the first bit line (12) in the third direction (Y).

15. The manufacturing method according to claim 14, wherein, A first bit line structure (11) is formed in the first trench (53) and the first receiving groove (55), a second bit line structure (14) is formed in the second trench (54) and the second receiving groove (56), and the stepped structure (30) is formed, including: Depositing an initial conductive layer (82), the initial conductive layer (82) filling the first receiving groove (55) and the second receiving groove (56) and covering the sidewalls and the bottom wall of the first trench (53), and the sidewalls and the bottom wall of the second trench (54); Retaining the initial conductive layer (82) located in the first receiving groove (55) and the second receiving groove (56), removing the remaining initial conductive layer (82), and the initial conductive layer (82) located in the first receiving groove (55) forms the first bit line (12); Depositing an initial isolation layer, the initial isolation layer filling the remaining first trench (53) and the remaining second trench (54), the initial isolation layer located in the first trench (53) forms the first isolation layer (13), and the initial conductive layer (82) located in the second receiving groove 56 and the initial isolation layer located in the second trench (54) form the second bit line structure (14); Forming the stepped structure (30), the stepped structure (30) including a plurality of conductive steps (31), the plurality of conductive steps (31) being respectively coupled to the corresponding first bit line (12).

16. The manufacturing method according to claim 14 or 15, wherein, The manufacturing method further includes: Etching the first dielectric layer (51) and the second dielectric layer (52) to form a first hole, a second hole, a third hole, and a fourth hole; the first hole is located between the first bit line (12) and the second bit line structure (14), and the second hole is located on opposite sides of the second bit line structure (14) along the second direction (X), the third hole is located on a side of the second hole away from the second bit line structure (14), the fourth hole is located on a first side of the first bit line (12) along the third direction (Y), along the second direction (X), the fourth hole is opposite to the first hole, and at least one fourth hole is provided between two adjacent first holes; Forming a selection transistor (17), an access transistor (21), a capacitor (22), and a filling pattern (18), the selection transistor (17) being located in the first hole and coupled to the second bit line structure (14), the access transistor (21) being located in the second hole and coupled to both the second bit line structure (14) and the first bit line (12), the capacitor (22) being located in the third hole and coupled to the access transistor (21), and the filling pattern (18) being located in the fourth hole.

17. The manufacturing method according to claim 16, wherein, The access transistor (21) and the selection transistor (17) are formed synchronously.

18. The manufacturing method according to any one of claims 14-17, wherein, Forming the stepped structure (30), including: The first dielectric layer (51) and the second dielectric layer (52) located on the side of the first bit line (12) away from the second bit line structure (14) are etched to form a groove (91), wherein the groove (91) exposes each of the first bit lines (12), and two side walls opposite to each other along the second direction (X) are both stepped, wherein the step surface of one of the side walls includes surfaces of the second dielectric layers (52) of odd numbers other than the second dielectric layer (52) adjacent to the substrate, which are away from the substrate, and the step surface of the other side wall includes surfaces of the second dielectric layers (52) of even numbers (52) which are away from the substrate; Etching and removing the portion of the first dielectric layer (51) exposed in the groove (91) to form a third receiving groove (92), wherein each of the first bit lines (12) is correspondingly exposed in the third receiving groove (92); forming a conductive step (31), wherein the conductive step (31) is filled in the third receiving groove (92) and is in corresponding contact with each of the first bit lines (12), and each of the conductive steps (31) forms a stepped structure; A third isolation layer (35) is formed in the groove, and the third isolation layer (35) fills the groove (91).

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