Semiconductor structure

Abstract

The present disclosure relates to the technical field of semiconductors. Provided is a semiconductor structure, which is used for solving the technical problems of low yield and reliability. The semiconductor structure comprises an array chip and a control chip which are bonded to each other. The array chip comprises a word line, a bit line, a first connecting pad, a second connecting pad, a first connecting structure and a second connecting structure, wherein the first connecting structure connects the bit line to the first connecting pad, and the second connecting structure connects the word line to the second connecting pad. The control chip comprises a sensing circuit, a driving circuit, a third connecting pad and a fourth connecting pad, wherein the third connecting pad is correspondingly connected to the first connecting pad and is connected to the sensing circuit, and the fourth connecting pad is correspondingly connected to the second connecting pad and is connected to the driving circuit. On the basis that the sensing circuit controls the bit line and the driving circuit controls the word line, the situation of line breakage occurring between the array chip and the control chip due to an excessive height difference therebetween can be avoided, thereby improving the yield and reliability of the semiconductor structure.

Description

semiconductor structure

[0001] This disclosure is based on the Chinese patent application with application number 202311814945.2, application date December 25, 2023, and application name “Semiconductor Structure”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this disclosure as a reference. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Art

[0003] With the continuous development of semiconductor technology and storage technology, electronic devices are constantly moving towards miniaturization and integration. Dynamic Random Access Memory (DRAM) is widely used in various electronic devices due to its high storage density and fast read and write speed.

[0004] A dynamic random access memory (DRAM) has an array area and a peripheral area. The array area is provided with multiple word lines (WL), bit lines (BL), and multiple memory cells. Each memory cell typically includes a control transistor and a capacitor. The gate of the control transistor is electrically connected to the word line, one of the source and drain is electrically connected to the bit line, and the other of the source and drain is electrically connected to the capacitor. The word line voltage on the word line can control the on and off of the control transistor, thereby enabling the data information stored in the capacitor to be read or written to the capacitor through the bit line. The peripheral area is provided with multiple word line drive circuits and multiple bit line sensing circuits.

[0005] However, as the height of memory cells in the array region continues to increase, the yield and reliability of semiconductor structures continue to decrease.

[0006] Summary of the Invention

[0007] In view of the above problems, embodiments of the present disclosure provide a semiconductor structure to improve its yield and reliability.

[0008] According to some embodiments, the present disclosure provides a semiconductor structure comprising a bonded array chip and a control chip;

[0009] The array chip comprises:

[0010] word lines and bit lines, the word lines and the bit lines intersecting and arranged on the array chip to form an array area;

[0011] a first connection pad, the first connection pad being disposed in a first region and a second region of the array region respectively close to two ends of the bit line;

[0012] second connection pads, the second connection pads being arranged in a third region and a fourth region of the array area, the third region and the fourth region being located between the first region and the second region;

[0013] a first connection structure connecting the bit line and the first connection pad;

[0014] a second connection structure connecting the word line and the second connection pad;

[0015] The control chip includes:

[0016] a sensing circuit, the sensing circuit being configured to control the bit line;

[0017] a driving circuit, the driving circuit being used to control the word line;

[0018] a third connection pad, the third connection pad being connected to the first connection pad correspondingly and connected to the sensing circuit;

[0019] A fourth connection pad is connected to the second connection pad correspondingly and is connected to the driving circuit.

[0020] In some possible implementations, the array chip and the control chip are hybrid-bonded.

[0021] In some possible implementations, the array chip further includes a first stacking structure, the word lines, the bit lines, the first connection structure, and the second connection structure are all located within the first stacking structure, and the first connection pads and the second connection pads are both exposed on a surface of the first stacking structure facing the control chip;

[0022] The control chip further includes a second stacking structure, the sensing circuit and the control circuit are both located in the second stacking structure, and the third connection pad and the fourth connection pad are both exposed on a surface of the second stacking structure facing the array chip;

[0023] And / or, the first connection structures are distributed in an axisymmetric manner, and the second connection structures are distributed in a centerymmetric manner.

[0024] In some possible implementations, the array chip includes a plurality of array areas;

[0025] The sensing circuit includes two sub-sensing circuits, and the projections of the two sub-sensing circuits on the array chip are respectively located in two adjacent array areas and are respectively close to one end of the bit line adjacent to each other;

[0026] The driving circuit includes two sub-driving circuits. The projections of the two sub-driving circuits on the array chip are respectively located in the same array area and are respectively close to two ends of the word line.

[0027] In some possible implementations, the fourth connection pads corresponding to the second connection pads in the third area and the fourth area of ​​the same array area are respectively connected to the sub-driving circuits of two different driving circuits;

[0028] And / or, the third connection pads corresponding to the first connection pads in the first area and the second area of ​​the same array area are connected to different sensing circuits respectively.

[0029] In some possible implementations, along the first direction, each of the first region and the second region of the array area has at least N first connection pads, where N is a positive integer greater than 1;

[0030] The bit lines in each array area are divided into multiple bit line groups, each bit line group includes 2N adjacent bit lines, the first ends of the N bit lines in the same group are respectively connected to the N first connection pads arranged along the first direction in the first area, and the second ends of the remaining N bit lines are respectively connected to the N first connection pads arranged along the first direction in the second area.

[0031] In some possible implementations, the bit lines arranged at odd positions are connected to the first connection pads of the first region, and the bit lines arranged at even positions are connected to the first connection pads of the second region.

[0032] In some possible implementations, the third area includes a first area, and a second area and a third area that are located in the first area away from the fourth area, and the second area is adjacent to the second area. The fourth area includes a fourth area, and a fifth area and a sixth area that are located in the fourth area away from the third area, and the fifth area is adjacent to the first area.

[0033] Along the first direction, the third region and the fourth region each have at least M second connection pads; along the second direction, the third subarea and the fifth subarea of ​​each array region each have at least P second connection pads, where M and P are positive integers greater than 1, and the second direction intersects the first direction;

[0034] The word lines located in the third and fifth subareas are divided into a plurality of first word line groups, each of the first word line groups includes 2P adjacent word lines, the first ends of the P word lines in the same group in the third subarea are respectively connected to the P second connection pads arranged along the second direction in the third subarea, and the first ends of the remaining P word lines are respectively connected to the second ends of the P word lines in the corresponding group in the adjacent array area that are connected to the second connection pads;

[0035] The second ends of the P word lines in the same group in the fifth subarea are respectively connected to the P second connection pads arranged along the second direction in the fifth subarea, and the second ends of the remaining P word lines are respectively connected to the first ends of the P word lines in the corresponding groups in the adjacent array areas that are connected to the second connection pads;

[0036] The word lines located in the first region and the second region are divided into a plurality of second word line groups, each second word line group includes 2M adjacent word lines, the second ends of the M word lines in the same group in the first region are respectively connected to the M second connection pads arranged along the first direction in the fourth subarea, and the second ends of the remaining P word lines are respectively connected to the first ends of the P word lines in the corresponding groups in the adjacent array regions that are connected to the second connection pads;

[0037] The first ends of the M word lines in the same group in the second area are respectively connected to the M second connection pads arranged along the first direction in the first partition, and the first ends of the remaining P word lines are respectively connected to the second ends of the P word lines connected to the second connection pads in the corresponding groups of adjacent array areas.

[0038] In some possible implementations, the control chip further includes first contact plugs disposed between the sensing circuit and the third connection pad, wherein the first contact plugs are arranged in a zigzag pattern on the sensing circuit.

[0039] And / or, the control chip further includes second contact plugs arranged between the driving circuit and the fourth connection pads, and the second contact plugs are arranged in a zigzag pattern on the driving circuit.

[0040] In some possible implementations, the control chip further includes a control circuit, and a wiring of the control circuit passes between the first contact plug and / or the second contact plug.

[0041] The semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0042] The semiconductor structure provided by the disclosed embodiments includes an array chip and a control chip. The array chip includes word lines, bit lines, a first connection pad, a second connection pad, a first connection structure, and a second connection structure. The first connection structure connects the bit lines to the first connection pad, and the second connection structure connects the word lines to the second connection pad. The control chip includes a sensing circuit, a driving circuit, a third connection pad, and a fourth connection pad. The third connection pad is connected to the sensing circuit, and the fourth connection pad is connected to the driving circuit. By bonding the array chip and the control chip, the third connection pad is connected to the first connection pad, and the fourth connection pad is connected to the second connection pad. On the basis of realizing that the sensing circuit controls the bit lines and the driving circuit controls the word lines, it can avoid the situation where the height difference between the array chip and the control chip is too large and causes disconnection, thereby improving the yield and reliability of the semiconductor structure. In addition, the word lines and bit lines form an array area on the array chip. The first connection pad is arranged in the first and second areas of the array area, respectively, near the ends of the bit lines. The second connection pad is arranged in the third and fourth areas of the array area. The third and fourth areas are located between the first and second areas. This allows the first and second connection pads to be arranged in separate areas within the array area, facilitating wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic diagram of a control chip and an array chip before bonding in one embodiment of the present disclosure;

[0044] FIG2 is a schematic diagram of a control chip and an array chip after bonding in one embodiment of the present disclosure;

[0045] FIG3 is a schematic diagram of an array area in one embodiment of the present disclosure;

[0046] FIG4 is a schematic diagram of the connection between the first connection structure and the first connection pad in one embodiment of the present disclosure;

[0047] FIG5 is a partial schematic diagram of a second connection structure and a second connection pad in one embodiment of the present disclosure;

[0048] FIG6 is a schematic diagram of the connection between the second connection structure and the second connection pad in one embodiment of the present disclosure;

[0049] FIG7 is a schematic diagram of a control chip in an embodiment of the present disclosure;

[0050] FIG8 is a top view of the sensing circuit and the first contact plug in one embodiment of the present disclosure;

[0051] FIG9 is a schematic cross-sectional view taken along line AA in FIG8 .

[0052] Explanation of the accompanying drawings: 10-array chip; 11-array area; 12-first area; 13-second area; 14-first partition; 15-second partition; 16-third partition; 17-fourth partition; 18-fifth partition; 19-sixth partition; 20-control chip; 21-control area; 31-first connection pad; 32-second connection pad; 33-third connection pad; 41-first connection structure; 42-second connection structure; 43-third connection structure; 44-fourth connection structure; 51-second substrate; 52-second stacking structure; 53-first contact plug; 61-first end of the bit line; 71-sensing circuit; 72-sub-sensing circuit; 73-driving circuit; 74-sub-driving circuit; 75-control circuit; 76-routing. DETAILED DESCRIPTION

[0053] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0054] 1 to 9 , an embodiment of the present disclosure provides a semiconductor structure including an array chip 10 and a control chip 20. The array chip 10 is used to store data, and the control chip 20 is used to control the writing or reading of data in the array chip 10. The array chip 10 and the control chip 20 are bonded together. Exemplarily, the array chip 10 and the control chip 20 are hybrid bonded, which can include both metal-to-metal bonding and dielectric-to-dielectric bonding.

[0055] The array chip 10 is higher in height and the control chip 20 is lower in height. By manufacturing the array chip 10 and the control chip 20 separately and connecting them face to face, compared with manufacturing the array chip 10 and the control chip 20 on the same layer, the influence of the height difference between the array chip 10 and the control chip 20 on the manufacturing can be reduced, and the connection between the array chip 10 and the control chip 20 due to the height difference can be avoided, thereby improving the yield and reliability of the semiconductor structure.

[0056] Referring to FIG3 , an array chip 10 includes word lines and bit lines. The word lines and bit lines intersect and are arranged on the array chip 10 to form an array region 11. The array region 11 may have multiple word lines and multiple bit lines. The multiple word lines and multiple bit lines intersect and are spaced apart from each other. Exemplarily, the bit lines extend along a first direction and are spaced apart along a second direction. The word lines extend along a second direction and are spaced apart along the first direction. The first direction intersects the second direction, for example, perpendicularly. The first direction is the Y direction shown in FIG1 , and the second direction is the X direction shown in FIG1 .

[0057] Array region 11 includes a first region 12, a second region 13, a third region, and a fourth region. First region 12 and second region 13 are located near the ends of the bit lines, respectively. Third region 13 and fourth region 13 are located between first region 12 and second region 13. First region 12 and second region 13 are positioned opposite each other along the direction of the bit lines (i.e., along the first direction). First region 12 is located near the first end of the bit lines, and second region 13 is located near the second end of the bit lines. As shown in FIG3 , first region 12 and second region 13 are arranged vertically, with first region 12 located at the top and second region 13 located at the bottom.

[0058] The third region is located between the first region 12 and the second region 13, and the fourth region is located between the first region 12 and the second region 13. The third region and the fourth region are arranged side by side. For example, the third region and the fourth region are arranged opposite each other along the direction in which the word lines extend (i.e., along the second direction). As shown in FIG3 , the third region and the fourth region are arranged side by side, with the third region on the left and the fourth region on the right.

[0059] In some possible examples, the third area includes a first area 14, and a second area 15 and a third area 16 arranged in the first area 14 away from the fourth area, the third area 16 is adjacent to the second area 13, that is, the second area 15 is adjacent to the first area 12. The fourth area includes a fourth area 17, and a fifth area 18 and a sixth area 19 arranged in the fourth area 17 away from the third area, the fifth area 18 is adjacent to the first area 12, that is, the sixth area 19 is adjacent to the second area 13.

[0060] The second and third sections 15 and 16 are arranged opposite each other along the first direction, and the fifth and sixth sections 18 and 19 are arranged opposite each other along the first direction. The second and fifth sections 15 and 18 are arranged opposite each other along the second direction, and the third and sixth sections 16 and 19 are arranged opposite each other along the second direction. The first, second, third, fourth, fifth, and sixth sections 14, 15, 16, 17, 18, and 19 are generally centrally symmetrically distributed.

[0061] Referring to Figures 4 to 6 , array chip 10 further includes a first connection structure 41, a second connection structure 42, a first connection pad 31, and a second connection pad 32. The first connection structure 41 connects the bit lines to the first connection pad 31, and the second connection structure 42 connects the word lines to the second connection pad 32. The first connection pad 31 is disposed in the first and second regions 12, 13 of array region 11, respectively, near the ends of the bit lines. The second connection pad 32 is disposed in the third and fourth regions of array region 11. Multiple first connection pads 31 and multiple second connection pads 32 are provided, with multiple first connection pads 31 disposed in each of the first and second regions 12, 13, and multiple second connection pads 32 disposed in each of the third and fourth regions.

[0062] The plurality of first connection pads 31 and the plurality of second connection pads 32 are distributed in an array. For example, the plurality of first connection pads 31 are arranged at intervals along a first direction and at intervals along a second direction, and the plurality of second connection pads 32 are arranged at intervals along the first direction and at intervals along the second direction. The first direction is the row direction, and the second direction is the column direction.

[0063] The sum of the number of columns of second connection pads 32 in the third and fourth regions is equal to the number of columns of first connection pads 31 in the first region 12, and equal to the number of columns of first connection pads 31 in the second region 13. A column of second connection pads 32 in the third region is aligned with a column of first connection pads 31 in the first region 12 and a column of first connection pads 31 in the second region 13. A column of second connection pads 32 in the fourth region is aligned with a column of first connection pads 31 in the first region 12 and a column of first connection pads 31 in the second region 13. The number of rows of second connection pads 32 in the third region is equal to the number of rows of fourth connection pads. A row of second connection pads 32 in the third region is aligned with a row of second connection pads 32 in the fourth region.

[0064] In the example where the third area includes the first partition 14, the second partition 15, and the third partition 16, and the fourth area includes the fourth partition 17, the fifth partition 18, and the sixth partition 19, the third partition 16 and the sixth partition 19 can be dummy areas, or the second partition 15 and the fifth partition 18 can be dummy areas, and the second connection pads 32 of the dummy areas are not connected.

[0065] In some possible embodiments, referring to Figures 4 and 5 , along the first direction, each array area 11 has at least N first connection pads 31 in the first region 12 and the second region 13, where N is a positive integer greater than 1. For example, along the first direction, each array area 11 has 10 first connection pads 31 in the first region 12, and each array area 11 has 10 first connection pads 31 in the second region 13.

[0066] The bit lines of each array area 11 are divided into multiple bit line groups, each bit line group includes 2N adjacent bit lines, the first ends 61 of the N bit lines in the same group are respectively connected to the N first connection pads 31 arranged along the first direction in the first area 12, and the second ends of the remaining N bit lines are respectively connected to the N first connection pads 31 arranged along the first direction in the second area 13.

[0067] For example, the bit lines of each array region 11 can be divided into multiple bit line groups, each of which includes 20 adjacent bit lines. Of the 20 bit lines in the same bit line group, the first ends 61 of 10 bit lines are connected to 10 first connection pads 31 arranged along the first direction in the first region 12 via portions of the first connection structures 41, while the second ends of the remaining 10 bit lines are connected to 10 first connection pads 31 arranged along the first direction in the second region 13 via another portion of the first connection structures 41. This reduces the arrangement density of the first connection structures 41 and facilitates wiring.

[0068] The bit lines arranged in odd positions are connected to the first connection pads 31 of the first region 12, and the bit lines arranged in even positions are connected to the first connection pads 31 of the second region 13. Specifically, along the first direction, the first ends 61 (e.g., upper ends) of the first, third, ..., and 2k+1 bit lines are connected to the first connection pads 31 of the first region 12 via a portion of the first connection structure 41, and the second ends (e.g., lower ends) of the second, fourth, ..., and 2k bit lines are connected to the first connection pads 31 of the second region 13 via another portion of the first connection structure 41, thereby improving the symmetry of the first connection structures 41. k is a positive integer greater than 1.

[0069] It is understood that along the second direction, the number of first connection pads 31 in each of the first region 12 and the second region 13 matches the number of bit lines. The specific number is at least greater than the number of bit lines divided by 2N, that is, at least greater than the number of bit line groups into which the bit lines are divided. When the number of bit lines is difficult to divide into multiple bit line groups, the number of bit lines in one bit line group can be less than 2N, and the number of bit lines in the remaining bit line groups is 2N. The first ends 61 of some bit lines in the bit line group with the smaller number of bit lines are connected to the corresponding I first connection pads 31 in the first region 12, and the second ends of another portion of the bit lines are connected to the corresponding L in the second region 13. I and L are both less than or equal to N, and the sum of I and L is less than 2N.

[0070] 3 and 6 , along the first direction, the third and fourth regions each have at least M second connection pads 32. Along the second direction, the third subarea 16 and the fifth subarea 18 each have at least P second connection pads 32, where M and P are both positive integers greater than 1. For example, along the first direction, the third region of each array area 11 has 9 second connection pads 32, and the fourth region has 9 second connection pads 32. Along the second direction, the third subarea 16 has 14 second connection pads 32, and the fifth subarea 18 has 14 second connection pads 32.

[0071] The word lines in the third and fifth subareas 16 and 18 are divided into multiple first word line groups. Each first word line group includes 2P adjacent word lines. The first ends of the P word lines in the same group in the third subarea 16 are respectively connected to the P second connection pads 32 arranged along the second direction in the third subarea 16. The first ends of the remaining P word lines are respectively connected to the second ends of the P word lines in the corresponding group in the adjacent array area 11 that are connected to the second connection pads 32.

[0072] The second ends of the P word lines of the first word line group in the same group in the fifth subarea 18 are respectively connected to the P second connection pads 32 arranged along the second direction in the fifth subarea 18. The second ends of the remaining P word lines in the first word line group are respectively connected to the first ends of the P word lines in the corresponding group in the adjacent array area 11, and the second ends of the P word lines in the corresponding group are connected to the opposite second connection pads 32.

[0073] In some possible examples, the word lines within the third subarea 16 of each array region 11 are divided into multiple first word line groups, each of which includes 28 adjacent word lines. Of the 28 word lines within the same first word line group within the third subarea 16, the first ends of 14 word lines are connected to 14 second connection pads 32 arranged along the second direction within the third subarea 16 via portions of the second connection structures 42. The first ends of the remaining 14 word lines are connected to the second ends of the 14 word lines connected to the second connection pads 32 within the opposite first word line group in the adjacent array region 11 (e.g., the left array region 11). The connection method between the word lines and the second connection pads 32 within the fifth subarea 18 of each array region 11 refers to the connection method between the word lines and the second connection pads 32 within the third subarea 16.

[0074] For example, in the corresponding two first word line groups in adjacent array areas 11, the first ends of the word lines arranged at odd bits in each first word line group are connected to the second connection pad 32, and the first ends of the word lines arranged at even bits in one first word line group are respectively connected to the first ends of the word lines arranged at odd bits in the other first word line group.

[0075] 3 and 6 , the word lines located in the first region 12 and the second region 13 are divided into a plurality of second word line groups. Each second word line group includes 2M adjacent word lines. The second ends of the M word lines in the same group in the first region 12 are respectively connected to the M second connection pads 32 arranged along the first direction in the fourth partition 17. The second ends of the remaining P word lines are respectively connected to the first ends of the P word lines in the corresponding group in the adjacent array region 11 that are connected to the second connection pads 32.

[0076] The word lines in the second region 13 are divided into multiple second word line groups, each of which includes 2M adjacent word lines. The first ends of the M word lines in the same second word line group in the second region 13 are respectively connected to the M second connection pads 32 arranged along the second direction in the first partition 14. The first ends of the remaining M word lines in the second word line group are respectively connected to the second ends of the M word lines in the corresponding group in the adjacent array region 11. The first ends of the M word lines in the corresponding group are connected to the corresponding second connection pads 32.

[0077] In some possible examples, the word lines within the first region 12 of each array region 11 are divided into multiple second word line groups, each of which includes 18 adjacent word lines. Of the 18 word lines within the same second word line group within the first region 12, the second ends of nine word lines are connected to nine second connection pads 32 arranged along the first direction within the fourth subregion 17 via portions of the second connection structures 42. The second ends of the remaining nine word lines are connected to the first ends of nine word lines connected to second connection pads 32 within the opposite second word line group in an adjacent array region 11 (e.g., the left array region 11). The connection method between the word lines within the second region 13 of each array region 11 and the second connection pads 32 within the first subregion 14 is similar to the connection method between the word lines within the first region 12 and the second connection pads 32 within the fourth subregion 17.

[0078] To support and fabricate the first connection structure 41, the second connection structure 42, the first connection pad 31, and the second connection pad 32, in some possible examples, the array chip 10 further includes a first substrate and a first stacked structure disposed on the first substrate. The first substrate is a semiconductor substrate, such as a single crystal silicon substrate, a single crystal germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, and can be a P-type doped semiconductor substrate or an N-type doped semiconductor substrate.

[0079] The word lines, bit lines, first connection structure 41, and second connection structure 42 are all located within the first stacked structure. The word lines and bit lines may extend partially into the first substrate or be located entirely on the first substrate. The first connection pads 31 and second connection pads 32 are both exposed on the surface of the first stacked structure facing the control chip 20. The first connection pads 31 and second connection pads 32 are arranged on the same layer to facilitate external connection.

[0080] Referring to Figures 7 to 9, the control chip 20 includes a sensing circuit 71, a driver circuit 73, a third connection pad 33, and a fourth connection pad. The sensing circuit 71 is used to control the bit lines for sensing and amplification during the data readout phase. The driver circuit 73 is used to control the word lines to drive the corresponding word lines. The third connection pad 33 is connected to the first connection pad 31 and is connected to the sensing circuit 71 to connect the sensing circuit 71 to the bit lines. The fourth connection pad is connected to the second connection pad 32 and is connected to the driver circuit 73 to connect the driver circuit 73 to the word lines.

[0081] Among them, the third connection pad 33 and the corresponding first connection pad 31 have at least a partial overlapping area. For example, the arrangement of the third connection pad 33 is the same as the arrangement of the first connection pad 31. The third connection pad 33 corresponds to the corresponding first connection pad 31 one by one and completely overlaps, so as to fully utilize the space of the array chip 10 and the control chip 20 and facilitate the production of the third connection pad 33 and the first connection pad 31.

[0082] The fourth connection pads and the second connection pads 32 have at least a partial overlapping area. For example, the arrangement of the fourth connection pads is the same as the arrangement of the second connection pads 32. The fourth connection pads correspond to the corresponding second connection pads 32 one-to-one and completely overlap, so as to fully utilize the space of the array chip 10 and the control chip 20 and facilitate the production of the fourth connection pads and the second connection pads 32.

[0083] It is understood that the control chip 20 has a control area 21, and the orthographic projection of the control area 21 on the array chip 10 coincides with the array area 11. In the example where the array chip 10 includes multiple array areas 11, the control chip 20 includes multiple control areas 21, and the control areas 21 correspond one-to-one with the array areas 11. The structure of each control area 21, as well as the position of the third connection pad 33 and the fourth connection pad therein, refer to the structure of the corresponding array area 11, as well as the position of the first connection pad 31 and the second connection pad 32 therein, and are, for example, the same.

[0084] In some possible examples, the array chip 10 includes multiple array areas 11, and the sensing circuit 71 includes two sub-sensing circuits 72. The projections of the two sub-sensing circuits 72 on the array chip 10 are located in two adjacent array areas 11, respectively, and are close to the ends of the bit lines adjacent to each other. The two sub-sensing circuits 72 are staggered along the arrangement direction of the bit lines to facilitate connection between the two sub-sensing circuits 72 and the third connection pads 33.

[0085] As shown in FIG7 , the two sub-sensing circuits 72 are arranged vertically and offset left and right. The projection of one sub-sensing circuit 72 on the array chip 10 is adjacent to the second end of the bit line in one array area 11 , and the projection of the other sub-sensing circuit 72 on the array chip 10 is adjacent to the first end 61 of the bit line in another array area 11 .

[0086] Based on the above example, in some possible implementations, the third connection pads 33 corresponding to the first connection pads 31 in the first region 12 and the second region 13 of the same array area 11 are respectively connected to different sensing circuits 71. As shown in FIG7 , the first end 61 of the bit line in the same array area 11 is correspondingly provided with a sub-sensing circuit 72 of one sensing circuit 71, and the second end of the bit line in the same array area 11 is correspondingly provided with a sub-sensing circuit 72 of another sensing circuit 71.

[0087] For ease of description, the two sensing circuits 71 corresponding to one array area 11 are defined as a first sensing circuit and a second sensing circuit, respectively. The first sensing circuit and the second sensing circuit each include two sub-sensing circuits 72. The projections of one sub-sensing circuit 72 of the first sensing circuit and one sub-sensing circuit 72 of the second sensing circuit on the array chip 10 are both located within the corresponding array area 11, and the projections of the other sub-sensing circuit 72 of the first sensing circuit and the other sub-sensing circuit 72 of the second sensing circuit on the array chip 10 are respectively located within the array areas 11 on both sides of the corresponding array area 11.

[0088] The third connection pads 33 corresponding to the first connection pads 31 in the first region 12 of an array area 11 are connected to the first sensing circuit. These third connection pads 33 are connected to the two sub-sensing circuits 72 of the first sensing circuit. The third connection pads 33 located on the left side of these third connection pads 33 are connected to the sub-sensing circuit 72 of the first sensing circuit whose projection is within the array area 11, while the third connection pads 33 located on the right side of these third connection pads 33 are connected to the sub-sensing circuit 72 of the first sensing circuit whose projection is within the adjacent array area 11. The third connection pads 33 corresponding to the first connection pads 31 in the second region 13 of this array area 11 are connected to the second sensing circuit. These third connection pads 33 are connected to the two sub-sensing circuits 72 of the second sensing circuit whose projection is within the array area 11. The third connection pads 33 located on the right side of these third connection pads 33 are connected to the sub-sensing circuit 72 of the second sensing circuit whose projection is within the array area 11, while the third connection pads 33 located on the left side of these third connection pads 33 are connected to the sub-sensing circuit 72 of the second sensing circuit whose projection is within the adjacent array area 11.

[0089] Illustratively, among the third connection pads 33 corresponding to the first connection pads 31 in the first area 12 of an array area 11, the multiple third connection pads 33 arranged along the first direction are respectively connected to one end of the adjacent multiple first lines 77 in the two sub-sensing circuits 72 of the first sensing circuit, and the other ends of these first lines 77 are respectively connected to the third connection pads 33 corresponding to the second connection pads 32 in the second area 13 of the adjacent array area 11.

[0090] Among the third connection pads 33 corresponding to the first connection pads 31 in the second area 13 of one array area 11, the multiple third connection pads 33 arranged along the first direction are respectively connected to one end of the adjacent multiple second lines in the two sub-sensing circuits 72 of the second sensing circuit, and the other ends of these second lines are respectively connected to the third connection pads 33 corresponding to the second connection pads 32 in the first area 12 of the adjacent array area 11.

[0091] With this arrangement, the bit lines in two adjacent array regions 11 are connected to both ends of the same first line 77. When reading data from one bit line, the other bit line can be used as a reference bit line. The connection between the first line 77 and the corresponding third connection pad 33, and the connection between the second line and the corresponding third connection pad 33, can refer to the connection between the bit line and the first connection pad 31.

[0092] For ease of understanding, the control area 21 includes a fifth region, a sixth region, a seventh region, and an eighth region, which are opposite the first region 12, the second region 13, the third region, and the fourth region, respectively. Along the first direction, each control area 21 has at least N third connection pads 33 within the fifth and sixth regions, where N is a positive integer greater than 1.

[0093] The two sub-sensing circuits 72 of the first sensing circuit each include multiple first lines 77. The first lines 77 of each sub-sensing circuit 72 are divided into multiple first line 77 groups, and each first line 77 group includes N adjacent first lines 77. One end of the N first lines 77 in the same group is connected to the N third connection pads 33 arranged along the first direction in the fifth region of one of the two adjacent control regions 21, and the other end is connected to the N third connection pads 33 arranged along the first direction in the sixth region of the other control region 21.

[0094] Both sub-sensing circuits 72 of the second sensing circuit include multiple second lines. The second lines of each sub-sensing circuit 72 are divided into multiple second line groups, each of which includes N adjacent second lines. One end of each of the N second lines in the same group is connected to the N third connection pads 33 arranged along the first direction within the sixth region of one of the two adjacent control regions 21, and the other end is connected to the N third connection pads 33 arranged along the first direction within the fifth region of the other control region 21.

[0095] The third connection pad 33 in the sixth region connected to the second circuit and the third connection pad 33 in the fifth region connected to the first circuit 77 are located in the same control region 21. The third connection pad 33 in the fifth region connected to the second circuit and the third connection pad 33 in the sixth region connected to the first circuit 77 are located in two control regions 21 on either side of the control region 21, respectively.

[0096] Continuing with FIG. 2 , driver circuit 73 includes two sub-driver circuits 74 . The projections of these two sub-driver circuits 74 on array chip 10 are located in the same array region 11 , respectively near the ends of the word lines. The two sub-driver circuits 74 are staggered along the word line arrangement to facilitate connection between the two sub-driver circuits 74 and the fourth connection pads.

[0097] Specifically, the projections of the two sub-driver circuits 74 on the array chip 10 are located in the same array region 11, facing each other along the second direction, and offset along the first direction. A sub-driver circuit 74 of a driver circuit 73 is correspondingly provided at the first end of a word line within the same array region 11, and a sub-driver circuit 74 of the driver circuit 73 is correspondingly provided at the second end of a word line within the same array region 11.

[0098] Based on the above example, in some possible implementations, the fourth connection pads corresponding to the second connection pads 32 in the third and fourth regions of the same array area 11 are respectively connected to sub-driver circuits 74 of the same driver circuit 73. Specifically, the fourth connection pad corresponding to the second connection pad 32 in the third region is connected to one of the sub-driver circuits 74, and the fourth connection pad corresponding to the second connection pad 32 in the fourth region is connected to the other sub-driver circuit 74. The connection method between the fourth connection pad and the corresponding sub-driver circuit 74 can refer to the connection method between the word line and the second connection pad 32.

[0099] In the example where the control area 21 includes the fifth, sixth, seventh, and eighth areas, the seventh area includes the seventh, eighth, and ninth subareas, and the fourth and eighth areas include the tenth, eleventh, and twelfth subareas. The seventh, eighth, ninth, tenth, eleventh, and twelfth subareas are opposite to the first, second, third, fourth, and sixth subareas 14, 15, 16, 17, 18, and 19, respectively.

[0100] Both sub-control circuits 75 include multiple third lines. The multiple third lines in the fifth and sixth regions are connected to the multiple fourth connection pads in the tenth and eleventh sub-regions, respectively. The multiple third lines in the ninth and eleventh sub-regions are connected to the multiple fourth connection pads in their respective sub-regions.

[0101] Exemplarily, along the first direction, the seventh and eighth regions each have at least M second connection pads 32 , and along the second direction, the ninth and eleventh subareas each have at least P second connection pads 32 , where M and P are both positive integers greater than 1.

[0102] The multiple third lines in the sub-control circuit 75 located in the fifth and sixth regions are divided into multiple third line groups, each of which includes M adjacent third lines. The M third lines in the same group in the fifth region are respectively connected to the M second connection pads 32 arranged along the first direction in the tenth sub-region. The M third lines in the same group in the sixth region are respectively connected to the M second connection pads 32 arranged along the first direction in the seventh sub-region.

[0103] The multiple third lines in the sub-control circuits 75 located in the ninth and eleventh sub-areas are divided into multiple fourth line groups, each of which includes P adjacent third lines. The P third lines in the same group in the ninth sub-area are respectively connected to the P second connection pads 32 arranged along the second direction in the ninth sub-area. The P third lines in the same group in the eleventh sub-area are respectively connected to the P second connection pads 32 arranged along the second direction in the eleventh sub-area.

[0104] In some possible examples, referring to Figures 8 and 9, the control chip 20 further includes a second substrate 51 and a second stacked structure 52 disposed on the second substrate 51. The second substrate 51 is a semiconductor substrate, such as a single crystal silicon substrate, a single crystal germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, and can be a P-type doped semiconductor substrate or an N-type doped semiconductor substrate.

[0105] The sensing circuit 71 and the control circuit 75 are both located within the first stacked structure, and may also partially extend into the second substrate 51 or be completely located on the second substrate 51. The third connection pad 33 and the fourth connection pad are both exposed on the surface of the second stacked structure 52 facing the array chip 10, and the third connection pad 33 and the fourth connection pad may be provided on the same layer for easy external connection.

[0106] To achieve corresponding connections between the sensing circuit 71 and the third connection pads 33, and / or between the control circuit 75 and the fourth connection pads, the control chip 20 further includes first contact plugs 53 and / or second contact plugs. The first contact plugs 53 are disposed between the sensing circuit 71 and the third connection pads 33, and are arranged in a zigzag pattern on the sensing circuit 71. The second contact plugs are disposed between the drive circuit 73 and the fourth connection pads, and are arranged in a zigzag pattern on the drive circuit 73. This arrangement increases the distance between the first contact plugs 53 and the distance between the second contact plugs, preventing the first contact plugs 53 and the second contact plugs from forming a barrier wall.

[0107] In the example where the control chip 20 includes the second substrate 51 and the second stacked structure 52, the control chip 20 further includes a third connection structure 43 and a fourth connection structure 44 disposed within the second stacked structure 52. The third connection structure 43 is connected to the third connection pad 33, for example, via a via, and the fourth connection structure 44 is connected to the fourth connection pad, for example, via a via. The first contact plug 53 is connected between the third connection structure 43 and the sensing circuit 71, and the second contact plug is connected between the fourth connection structure 44 and the control circuit 75.

[0108] In some possible examples, the control chip 20 further includes a control circuit 75. A trace 76 of the control circuit 75 passes between the first contact plug 53 and / or the second contact plug to connect two adjacent control areas 21, thereby achieving control of multiple array areas 11. The control circuit 75 can be disposed on the same layer as the sensing circuit 71 and the driving circuit 73. The projection of the control circuit 75 on the array chip 10 is opposite to the central area of ​​the array area 11.

[0109] In summary, the semiconductor structure in the disclosed embodiment includes an array chip 10 and a control chip 20. The array chip 10 includes word lines, bit lines, a first connection pad 31, a second connection pad 32, a first connection structure 41, and a second connection structure 42. The first connection structure 41 connects the bit lines to the first connection pad 31, and the second connection structure 42 connects the word lines to the second connection pad 32. The control chip 20 includes a sensing circuit 71, a driving circuit 73, a third connection pad 33, and a fourth connection pad. The third connection pad 33 is connected to the sensing circuit 71, and the fourth connection pad is connected to the driving circuit 73. By bonding the array chip 10 and the control chip 20, the third connection pad 33 is correspondingly connected to the first connection pad 31, and the fourth connection pad is correspondingly connected to the second connection pad 32. On the basis of realizing that the sensing circuit 71 controls the bit lines and the driving circuit 73 controls the word lines, it can avoid the situation where the array chip 10 and the control chip 20 have a large height difference and thus cause disconnection, thereby improving the yield and reliability of the semiconductor structure. In addition, the word lines and bit lines form an array area 11 on the array chip 10, and the first connection pad 31 is arranged in the first area 12 and the second area 13 of the array area 11 respectively close to the two ends of the bit line, and the second connection pad 32 is arranged in the third area and the fourth area of ​​the array area 11. The third area and the fourth area are located between the first area 12 and the second area 13, so that the first connection pad 31 and the second connection pad 32 are arranged in partitions in the array area 11 to facilitate wiring.

[0110] In this specification, each embodiment or implementation method is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, It includes a phase-bonded array chip (10) and a control chip (20); The array chip (10) includes: Word lines and bit lines, where the word lines and the bit lines intersect and are arranged on the array chip (10) to form an array region (11); First connection pads (31), which are arranged in a first region (12) and a second region (13) of the array region (11) close to both ends of the bit line respectively; Second connection pads (32), which are arranged in a third region and a fourth region of the array region (11), and the third region and the fourth region are located between the first region (12) and the second region (13); First connection structures (41), which connect the bit lines and the first connection pads (31); Second connection structures (42), which connect the word lines and the second connection pads (32); The control chip (20) includes: A sensing circuit (71), which is used to control the bit lines; A driving circuit (73), which is used to control the word lines; Third connection pads (33), which are correspondingly connected to the first connection pads (31) and are connected to the sensing circuit (71); Fourth connection pads, which are correspondingly connected to the second connection pads (32) and are connected to the driving circuit (73).

2. The semiconductor structure according to claim 1, wherein, The array chip (10) and the control chip (20) are hybrid-bonded.

3. The semiconductor structure according to claim 1, wherein The array chip (10) further includes a first stacked structure, and the word lines, the bit lines, the first connection structures (41) and the second connection structures (42) are all located within the first stacked structure, and the first connection pads (31) and the second connection pads (32) are both exposed on the surface of the first stacked structure facing the control chip (20); The control chip (20) further includes a second stacked structure (52), and the sensing circuit (71) and the control circuit are both located within the second stacked structure (52), and the third connection pads (33) and the fourth connection pads are both exposed on the surface of the second stacked structure (52) facing the array chip (10); And / or, the first connection structures (41) are axially symmetrically distributed, and the second connection structures (42) are centrosymmetrically distributed.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, The array chip (10) includes a plurality of the array regions (11); The sensing circuit (71) includes two sub-sensing circuits (72), and the projections of the two sub-sensing circuits (72) on the array chip (10) are respectively located in two adjacent array regions (11) and are respectively close to one adjacent end of the bit line; The driving circuit (73) includes two sub-driving circuits (74), and the projections of the two sub-driving circuits (74) on the array chip (10) are respectively located in the same array region (11) and are respectively close to the two ends of the word line.

5. The semiconductor structure according to claim 4, wherein The fourth connection pads corresponding to the second connection pads (32) in the third region and the fourth region of the same array region (11) are respectively connected to the sub-driving circuits (74) of two different driving circuits (73); And / or, the third connection pads (33) corresponding to the first connection pads (31) in the first region (12) and the second region (13) of the same array region (11) are respectively connected to different sensing circuits (71).

6. The semiconductor structure according to any one of claims 4, wherein Along the first direction, there are at least N first connection pads (31) in the first region (12) and the second region (13) of each array region (11), and N is a positive integer greater than 1; The bit lines of each array region (11) are divided into a plurality of bit line groups, each bit line group includes 2N adjacent bit lines, the first ends of N bit lines in the same group are respectively connected to N first connection pads (31) arranged along the first direction in the first region (12), and the second ends of the remaining N bit lines are respectively connected to N first connection pads (31) arranged along the first direction in the second region (13).

7. The semiconductor structure according to claim 6, wherein The bit lines arranged in odd positions are correspondingly connected to the first connection pads (31) in the first region (12), and the bit lines arranged in even positions are correspondingly connected to the first connection pads (31) in the second region (13).

8. The semiconductor structure according to claim 6, wherein The third region includes a first sub-region (14), and a second sub-region (15) and a third sub-region (16) provided in the first sub-region (14) away from the fourth region, the second sub-region (15) is adjacent to the second region (13), the fourth region includes a fourth sub-region (17), and a fifth sub-region (18) and a sixth sub-region (19) provided in the fourth sub-region (17) away from the third region, the fifth sub-region (18) is adjacent to the first region (12); Along the first direction, there are at least M second connection pads (32) in both the third region and the fourth region; along the second direction, there are at least P second connection pads (32) in both the third sub-region (16) and the fifth sub-region (18) of each array region (11), M and P are positive integers greater than 1, and the second direction intersects with the first direction; The word lines in the third sub-region (16) and the fifth sub-region (18) are divided into a plurality of first word line groups, each first word line group includes 2P adjacent word lines, the first ends of P word lines in the same group in the third sub-region (16) are respectively correspondingly connected to P second connection pads (32) arranged along the second direction in the third sub-region (16), and the first ends of the remaining P word lines are respectively connected to the second ends of P word lines in the corresponding group of the adjacent array region (11) connected to the second connection pads (32); The second ends of P word lines in the same group within the fifth partition (18) are respectively and correspondingly connected to P second connection pads (32) arranged along the second direction within the fifth partition (18), and the second ends of the remaining P word lines are respectively connected to the first ends of P word lines in the corresponding group of the adjacent array region (11) that are connected to the second connection pads (32). The word lines located in the first region (12) and the second region (13) are evenly divided into a plurality of second word line groups, each second word line group includes 2M adjacent word lines, the second ends of M word lines in the same group within the first region (12) are respectively and correspondingly connected to M second connection pads (32) arranged along the first direction within the fourth partition (17), and the second ends of the remaining P word lines are respectively connected to the first ends of P word lines in the corresponding group of the adjacent array region (11) that are connected to the second connection pads (32). The first ends of M word lines in the same group within the second region (13) are respectively and correspondingly connected to M second connection pads (32) arranged along the first direction within the first partition (14), and the first ends of the remaining P word lines are respectively connected to the second ends of P word lines in the corresponding group of the adjacent array region (11) that are connected to the second connection pads (32).

9. The semiconductor structure according to any one of claims 1-8, characterized in that, The control chip (20) further includes a first contact plug disposed between the sensing circuit (71) and the third connection pad (33), and the first contact plugs (53) are arranged in a zigzag pattern on the sensing circuit (71). And / or, the control chip (20) further includes a second contact plug disposed between the driving circuit (73) and the fourth connection pad, and the second contact plugs are arranged in a zigzag pattern on the driving circuit (73).

10. The semiconductor structure according to claim 5, wherein The control chip (20) further includes a control circuit, and the traces of the control circuit pass between the first contact plugs (53) and / or the second contact plugs.

11. The semiconductor structure according to any one of claims 1-10, characterized in that, The array chip includes: a first dummy region, and the first dummy region is provided with a first dummy connection pad.

12. The semiconductor structure according to claim 11, wherein, The dummy region is disposed within the third region and / or the fourth region.

13. The semiconductor structure according to claim 11, wherein The control chip includes: a second dummy region, and the second dummy region is provided with a second dummy connection pad.

14. The semiconductor structure according to claim 13, wherein The first dummy region corresponds to the second dummy region, and the first dummy connection pad is connected to the second dummy connection pad.

15. The semiconductor structure according to any one of claims 1-14, characterized in that, The array chip includes a first substrate, and the control chip includes a second substrate; wherein, the first substrate and the second substrate are oppositely disposed on the outermost side of the semiconductor structure.

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