Array substrate and display panel

Abstract

The present application relates to an array substrate and a display panel. In the present application, an array substrate is additionally provided with a first cushioning portion disposed between a photosensitive layer and a first doped portion, and / or a second cushioning portion disposed between the photosensitive layer and a photosensitive electrode, and / or an active layer, and the array substrate comprises an intrinsic portion disposed between a channel portion and the first doped portion.

Description

Array substrate and display panel

[0001] This application claims priority to Chinese patent application No. 202311826022.9 filed on December 26, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0003] Multifunctional display technology is developing rapidly. From its initial display function, screens have gradually expanded to include touchscreen, fingerprint unlocking, and light sensing. High-quality, high-value-added display technology has become a new market for major panel manufacturers. Light sensing technology converts received optical signals into electrical signals, which are then recognized by smart chips to monitor external light information (such as light intensity, wavelength, and color temperature). This technology not only records ambient light information during photography for optimal post-processing, but also effectively monitors UV light and ambient light intensity in natural environments, providing health protection recommendations and facilitating sun protection during travel. SUMMARY OF THE INVENTION

[0004] Currently, the main types of light sensing materials used in display technology include OPD, Poly-Si, IGZO, and a-Si. Among them, a-Si light sensing technology can respond to both UV and ambient light, offering the potential to monitor primary outdoor light intensity and provide accurate health protection recommendations. However, the accuracy of current a-Si light sensing technology is limited by excessively high dark-state current. Specifically, the current change step size per unit light intensity is too low, making it impossible to obtain accurate light intensity information.

[0005] In a first aspect, the present application provides an array substrate, comprising: a substrate; an active layer, arranged on the substrate, comprising a first doping portion, a second doping portion and a channel portion located between the first doping portion and the second doping portion; a photosensitive layer, arranged on a side of the first doping portion away from the substrate; a photosensitive electrode, arranged on a side of the photosensitive layer away from the substrate; and a first buffer portion, arranged between the photosensitive layer and the first doping portion; and / or a second buffer portion, arranged between the photosensitive layer and the photosensitive electrode; and / or an intrinsic portion, arranged between the channel portion and the first doping portion.

[0006] In a second aspect, the present application provides a display panel, which includes the array substrate described in the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below only disclose some embodiments. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0008] FIG1 is a schematic structural diagram of an array substrate of the present application;

[0009] FIG2 is a schematic diagram of a dark current electrode in an array substrate of the present application;

[0010] FIG3 is a schematic diagram showing the principle of the array substrate of the present application with low photocurrent influence;

[0011] FIG4 is a comparison diagram of dark state current of the array substrate of the present application and the array substrate of the prior art;

[0012] 5 to 14 are schematic diagrams corresponding to the steps of the method for manufacturing a display panel of the present application.

[0013] Description of reference numerals:

[0014] 100. Display panel.

[0015] 1. Substrate; 2. Light-shielding layer; 3. Buffer layer; 4. Active layer; 5. Gate insulating layer; 6. Gate; 7. Second interlayer insulating layer; 8. Photosensitive layer; 9. Photosensitive electrode; 10. First buffer portion; 11. Second buffer portion; 12. First interlayer insulating layer; 13. Source; 14. Flat layer; 15. Passivation layer; 16. First groove; 17. Active layer semi-finished product; 18. First via hole; 19. Second via hole; 20. Transition layer; 21. First interlayer insulating material layer; 22. Touch lead; 23. Common electrode; 24. Touch electrode.

[0016] 121. Through hole; 141. Third via hole; 41. Channel portion; 42. First doped portion; 43. Second doped portion; 44. Intrinsic portion; 45. Third doped portion; 46. Fourth doped portion; 47. Fifth doped portion; 48. Semi-finished channel portion. Modes for Carrying Out the Invention

[0017] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0018] In the description of this application, it should be understood that the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0019] The present application may repeat reference numerals and / or reference letters in different embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0020] The present application provides an array substrate, which includes: a substrate; an active layer, arranged on the substrate, including a first doping portion, a second doping portion and a channel portion located between the first doping portion and the second doping portion; a photosensitive layer, arranged on a side of the first doping portion away from the substrate; a photosensitive electrode, arranged on a side of the photosensitive layer away from the substrate; and a first buffer portion, arranged between the photosensitive layer and the first doping portion; and / or a second buffer portion, arranged between the photosensitive layer and the photosensitive electrode; and / or an intrinsic portion, arranged between the channel portion and the first doping portion.

[0021] Furthermore, the photosensitive layer is made of amorphous silicon, and the first buffer portion and the second buffer portion are both made of SiOx.

[0022] Furthermore, a surface of the first buffer portion away from the substrate is flush with a surface of the first doping portion away from the substrate, and a surface of the first buffer portion close to the substrate is located within the first doping portion.

[0023] Furthermore, a surface of the second buffer portion away from the substrate is flush with a surface of the photosensitive layer away from the substrate, and a surface of the second buffer portion close to the substrate is located within the photosensitive layer.

[0024] Furthermore, the array substrate also includes: a first interlayer insulating layer, which is arranged between the photosensitive layer and the photosensitive electrode, and the surface of the first interlayer insulating layer close to the substrate is flush with the surface of the photosensitive layer away from the substrate; wherein the first interlayer insulating layer is provided with a through hole at a position corresponding to the second buffer portion, and the photosensitive electrode is filled in the through hole and connected to the second buffer portion.

[0025] Furthermore, the intrinsic portion and the channel portion are made of the same material.

[0026] Furthermore, the active layer further includes: a third doping portion, disposed between the channel portion and the intrinsic portion; wherein the first doping portion, the second doping portion, and the third doping portion have the same doping concentration.

[0027] Furthermore, the active layer also includes: a fourth doping portion, arranged between the channel portion and the second doping portion; and a fifth doping portion, arranged between the channel portion and the third doping portion; wherein the doping concentration of the fourth doping portion is the same as that of the fifth doping portion, and the doping concentration of the fourth doping portion is less than the doping concentration of the first doping portion.

[0028] Furthermore, the array substrate also includes: a gate insulating layer, which is arranged on a side of the active layer away from the substrate and extends to cover the substrate; a gate, which is arranged on a side of the gate insulating layer away from the substrate and is arranged corresponding to the channel portion; a second interlayer insulating layer, which is arranged on a side of the gate away from the substrate and extends to cover the gate insulating layer; a source, which is arranged on a side of the second interlayer insulating layer away from the substrate and is electrically connected to the second doped portion through the second interlayer insulating layer and the gate insulating layer; wherein the surface of the source on the side close to the substrate is located in the second doped portion.

[0029] In order to solve the above problems, the present application provides a display panel, which includes the array substrate described in the present application.

[0030] The advantages of the present application are: the present application adds a first buffer portion in the array substrate, which is arranged between the photosensitive layer and the first doped portion; and / or a second buffer portion, which is arranged between the photosensitive layer and the photosensitive electrode; and / or the active layer includes an intrinsic portion arranged between the channel portion and the first doped portion. By utilizing the first buffer portion and / or the second buffer portion and / or the intrinsic portion, it is difficult for electrons in the dark state to cross the potential barrier of the first buffer portion and / or the second buffer portion and / or the intrinsic portion, thereby suppressing the upward trend of the dark state current. In the case of light illumination, the electrons can absorb sufficient energy to cross the potential barrier of the first buffer portion and / or the second buffer portion and / or the intrinsic portion, thereby significantly improving the photocurrent compared to the dark current, thereby improving the monitoring accuracy of the photosensitive layer.

[0031] As shown in FIG1 , this embodiment provides a display panel 100 including an array substrate. The array substrate includes a substrate 1, a light shielding layer 2, a buffer layer 3, an active layer 4, a gate insulating layer 5, a gate 6, a second interlayer insulating layer 7, a photosensitive layer 8, a photosensitive electrode 9, a first buffer 10, a second buffer 11, a first interlayer insulating layer 12, a source electrode 13, a planarization layer 14, and a passivation layer 15.

[0032] As shown in Figures 1, 2, and 3, the array substrate further includes: a first buffer portion 10 disposed between the photosensitive layer 8 and the first doped portion 42; and / or a second buffer portion 11 disposed between the photosensitive layer 8 and the photosensitive electrode 9; and / or an intrinsic portion 44 disposed between the channel portion 41 and the first doped portion 42. In this embodiment, the array substrate further includes: a first buffer portion 10, a second buffer portion 11, and an intrinsic portion 44. The first buffer portion 10, the second buffer portion 11, and the intrinsic portion 44 make it difficult for electrons P in the dark state to cross the potential barriers formed by the first buffer portion 10, the second buffer portion 11, and the intrinsic portion 44, thereby suppressing the upward trend of the dark state current. However, under light illumination, electrons P can absorb sufficient energy to cross the potential barriers formed by the first buffer portion 10, the second buffer portion 11, and the intrinsic portion 44, thereby significantly improving the photocurrent compared to the dark current, thereby improving the monitoring accuracy of the photosensitive layer. In other embodiments, only one or two of the first buffer portion 10 , the second buffer portion 11 , and the intrinsic portion 44 may be provided according to actual needs.

[0033] The material of the substrate 1 includes glass, polyimide, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, etc. In this embodiment, the material of the substrate 1 is glass.

[0034] The light shielding layer 2 is provided on the substrate 1 and is provided corresponding to the active layer 4. The light shielding layer 2 is mainly used to prevent light from irradiating the active layer 4 and affecting the device performance of the active layer 4.

[0035] The buffer layer 3 is disposed on the side of the light shielding layer 2 away from the substrate 1 and extends to cover the substrate 1. The buffer layer 3 mainly plays a buffering role and its material can be SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx.

[0036] The active layer 4 is disposed on a side of the buffer layer 3 away from the substrate 1 . The active layer 4 includes a channel portion 41 , a first doping portion 42 , a second doping portion 43 , an intrinsic portion 44 , a third doping portion 45 , a fourth doping portion 46 and a fifth doping portion 47 .

[0037] Among them, the channel portion 41 is located between the first doping portion 42 and the second doping portion 43, the intrinsic portion 44 is arranged between the channel portion 41 and the first doping portion 42, the third doping portion 45 is arranged between the channel portion 41 and the intrinsic portion 44, the fourth doping portion 46 is arranged between the channel portion 41 and the second doping portion 43, and the fifth doping portion 47 is arranged between the channel portion 41 and the third doping portion 45.

[0038] The channel portion 41 is made of poly-Si, which is formed by converting a-Si into poly-Si by using an excimer laser annealing (ELA) process. The intrinsic portion 44 is made of the same material as the channel portion 41 .

[0039] The first doping portion 42, the second doping portion 43, and the third doping portion 45 have the same doping concentration. The fourth doping portion 46 and the fifth doping portion 47 have the same doping concentration. The doping concentration of the fourth doping portion 46 is lower than the doping concentration of the first doping portion 42. Specifically, the first doping portion 42, the second doping portion 43, and the third doping portion 45 are all formed by heavily doping poly-Si with phosphorus ions. The fourth doping portion 46 and the fifth doping portion 47 are both formed by lightly doping poly-Si with phosphorus ions.

[0040] In this embodiment, an intrinsic portion 44 is provided in the active layer 4, so that it is difficult for electrons in the dark state to cross the potential barrier of the intrinsic portion 44, thereby suppressing the upward trend of the dark state current. In the case of light, the electrons can absorb enough energy to cross the potential barrier of the intrinsic portion 44, so that the photocurrent is significantly improved compared to the dark current, thereby improving the monitoring accuracy of the photosensitive layer 8.

[0041] The gate insulating layer 5 is disposed on a side of the active layer 4 away from the substrate 1 and extends over the buffer layer 3. The gate insulating layer 5 is primarily used to prevent a short circuit between the active layer 4 and the gate 6. The gate insulating layer 5 can be made of SiOx, SiNx, Al2O3, a combination of SiNx and SiOx, or a combination of SiOx, SiNx, and SiOx.

[0042] The gate 6 is disposed on a side of the gate insulating layer 5 away from the substrate 1 and corresponding to the channel portion 41. The material of the gate 6 can be Mo, a combination of Mo and Al, a combination of Mo and Cu, a combination of Mo, Cu, and IZO, a combination of IZO, Cu, and IZO, a combination of Mo, Cu, and ITO, a combination of Ni, Cu, and Ni, a combination of MoTiNi, Cu, and MoTiNi, a combination of NiCr, Cu, and NiCr, or CuNb, etc.

[0043] The second interlayer insulating layer 7 is disposed on a side of the gate 6 away from the substrate 1 and extends over the gate insulating layer 5. The second interlayer insulating layer 7 can be made of SiOx, SiNx, SiNOx, or the like. In this embodiment, the second interlayer insulating layer 7 is a stacked structure of SiNx and SiOx.

[0044] The photosensitive layer 8 is disposed on a side of the first doped portion 42 away from the substrate 1 . The photosensitive layer 8 is made of amorphous silicon. In this embodiment, the photosensitive layer 8 is made of amorphous silicon (a-Si).

[0045] The photosensitive electrode 9 is disposed on a side of the photosensitive layer 8 away from the substrate 1. The photosensitive electrode 9 is made of a light-transmitting material, allowing light to penetrate the photosensitive electrode 9 and illuminate the photosensitive layer 8. The photosensitive layer 8 then absorbs the light and generates a photocurrent. This photocurrent is generated between the photosensitive electrode 9 and the first doped portion 42, forming a conductive path in the photosensitive layer. In this embodiment, the photosensitive electrode 9 is made of ITO.

[0046] In this embodiment, the first buffer portion 10 is disposed between the photosensitive layer 8 and the first doped portion 42. Specifically, the surface of the first buffer portion 10 facing away from the substrate 1 is flush with the surface of the first doped portion 42 facing away from the substrate 1, and the surface of the first buffer portion 10 facing closer to the substrate 1 is located within the first doped portion 42. The material of the first buffer portion 10 includes SiOx. In this embodiment, the first buffer portion 10 is SiOx formed by plasma treatment of the surface of the first doped portion 42 facing away from the substrate 1 using oxygen.

[0047] In this embodiment, the second buffer portion 11 is disposed between the photosensitive layer 8 and the photosensitive electrode 9. Specifically, the surface of the second buffer portion 11 facing away from the substrate 1 is flush with the surface of the photosensitive layer 8 facing away from the substrate 1, and the surface of the second buffer portion 11 facing the substrate 1 is located within the photosensitive layer 8. The material of the second buffer portion 11 includes SiOx. In this embodiment, the second buffer portion 11 is SiOx formed by plasma treatment of the surface of the photosensitive layer 8 facing away from the substrate 1 with oxygen.

[0048] The first interlayer insulating layer 12 is disposed between the photosensitive layer 8 and the photosensitive electrode 9. The material of the first interlayer insulating layer 12 can be SiOx, SiNx, SiNOx, etc. The surface of the first interlayer insulating layer 12 on the side close to the substrate 1 is flush with the surface of the photosensitive layer 8 on the side away from the substrate 1. The first interlayer insulating layer 12 has a through hole 121 at a position corresponding to the second buffer portion 11. The photosensitive electrode 9 is filled in the through hole 121 and is connected to the second buffer portion 11.

[0049] The source electrode 13 is disposed on a side of the second interlayer insulating layer 7 away from the substrate 1 and is electrically connected to the second doped portion 43 through the second interlayer insulating layer 7 and the gate insulating layer 5. The surface of the source electrode 13 on the side close to the substrate 1 is located within the second doped portion 43. When oxygen is used to plasma-treat the surface of the first doped portion 42 on the side close to the substrate 1 to form SiOx, the surface of the second doped portion 43 on the side close to the substrate 1 is also plasma-treated to form SiOx. Later, before forming the source electrode 13, hydrofluoric acid is used to clean the SiOx on the second doped portion 43, and then the source electrode 13 is formed. As a result, the surface of the source electrode 13 on the side close to the substrate 1 is located within the second doped portion 43.

[0050] The planarization layer 14 is disposed on a side of the second interlayer insulating layer 7 away from the substrate 1 and covers the source electrode 13. In this embodiment, the planarization layer 14 is made of an organic photoresist material.

[0051] The passivation layer 15 is disposed on a side of the planar layer 14 away from the substrate 1 .

[0052] The array substrate includes a first groove 16 penetrating the photosensitive layer 8 and the planar layer 14 and the passivation layer 15 on the first interlayer insulating layer 12. The photosensitive electrode 9 is disposed on the passivation layer 15 on both sides of the first groove 16 and on the first groove 16.

[0053] As shown in Figure 4, when the voltages are -1V, -2V, -3V, -4V, and -5V respectively, the dark state current of the display panel of this embodiment (with a first buffer part, a second buffer part, and an intrinsic part) is smaller than the dark state current of the display panel in the prior art (without a first buffer part, a second buffer part, and an intrinsic part). It can be seen that the present application utilizes the first buffer part 10, the second buffer part 11, and the intrinsic part 44 to make it difficult for electrons P in the dark state to cross the potential barriers of the first buffer part 10, the second buffer part 11, and the intrinsic part 44, thereby suppressing the upward trend of the dark state current. In the case of light, the electrons P can absorb enough energy to cross the potential barriers of the first buffer part 10, the second buffer part 11, and the intrinsic part 44, thereby significantly improving the photocurrent compared to the dark current, thereby improving the monitoring accuracy of the photosensitive layer.

[0054] As shown in FIG. 5 to FIG. 14 , this embodiment further provides a method for preparing the display panel of this embodiment, which includes the following steps.

[0055] As shown in FIG5 , S1 , a light-shielding material layer is prepared on a substrate 1 , and then the light-shielding material layer is patterned by exposure and etching or the like to form a light-shielding layer 2 .

[0056] As shown in FIG6 , S2, a buffer layer 3 is prepared on the light-shielding layer 2 and the substrate, and an a-Si is prepared on the buffer layer 3. After excimer laser annealing, the a-Si is converted into poly-Si, and then the entire surface is doped with boron ions. The poly-Si is patterned by exposure etching and other methods to form an active layer semi-finished product 17.

[0057] 7 , in step S3 , a portion of the active layer semi-finished product 17 is heavily doped with phosphorus ions to form a first doping portion 42 , a second doping portion 43 , and a third doping portion 45 . The region not heavily doped with phosphorus ions forms a channel portion semi-finished product 48 and an intrinsic portion 44 .

[0058] As shown in FIG8 , in S4, a gate insulating layer 5 is formed on the first doping portion 42, the second doping portion 43, the third doping portion 45, the channel portion semi-finished product 48, the intrinsic portion 44, and the buffer layer 3. A gate 6 is formed on the gate insulating layer 5, and the gate 6 is arranged corresponding to the channel portion semi-finished product 48. The gate 6 is used to block a portion of the channel portion semi-finished product 48. The portion of the channel portion semi-finished product 48 not blocked by the gate 6 is lightly doped with phosphorus ions to form a fourth doping portion 46 and a fifth doping portion 47, respectively. The portion of the channel portion semi-finished product 48 blocked by the gate 6 forms the channel portion 41. The channel portion 41, the first doping portion 42, the second doping portion 43, the intrinsic portion 44, the third doping portion 45, the fourth doping portion 46, and the fifth doping portion 47 form the active layer 4.

[0059] As shown in Figure 9, in S5, a second interlayer insulating layer 7 is formed on the gate 6 and the gate insulating layer 5. A first via 18 and a second via 19 are formed through the second interlayer insulating layer 7 and the gate insulating layer 5 by exposure and etching. The first via 18 and the second via 19 are respectively provided corresponding to the first doped portion 42 and the second doped portion 43. The first buffer portion 10 is formed by plasma treating the surface of the first doped portion 42 on the side away from the substrate 1 with oxygen, and the transition layer 20 is formed by plasma treating the surface of the second doped portion 43 on the side away from the substrate 1 with oxygen.

[0060] As shown in FIG. 10 , in S6 , a photosensitive layer 8 is formed in the first via hole 18 , a first interlayer insulating material layer 21 is prepared on the photosensitive layer 8 , and then the photosensitive layer 8 and the first interlayer insulating material layer 21 are patterned by exposure and etching.

[0061] As shown in FIG11 , at S8 , a touch lead 22 and a source electrode 13 are formed on the second interlayer insulating layer 7 . The source electrode 13 is filled in the second via hole 19 and connected to the second doped portion 43 . Specifically, before forming the source electrode 13 and the touch lead 22 , the transition layer 20 is cleaned with hydrofluoric acid. As a result, the surface of the source electrode 13 on the side closest to the substrate 1 is located within the second doped portion 43 .

[0062] As shown in FIG. 12 , S9 , a planar layer 14 is prepared on the touch lead 22 , the source electrode 13 , the first interlayer insulating material layer 21 and the second interlayer insulating layer 7 , and a third via hole 141 is formed on the planar layer 14 at a position corresponding to the touch lead 22 .

[0063] As shown in FIG13 , S10 , a common electrode 23 and a touch electrode 24 are formed on the planar layer 14 . The touch electrode 24 is filled in the third via hole 141 and connected to the touch lead 22 .

[0064] As shown in FIG14 , S11, a passivation layer 15 is formed on the touch electrodes 24, the common electrodes 23, and the planar layer 14. A first groove 16 is formed in the passivation layer 15 at a position corresponding to the first interlayer insulating material layer 21. A through hole 121 is formed in the first interlayer insulating material layer 21. The remaining first interlayer insulating material layer forms the first interlayer insulating layer 12. The surface of the photosensitive layer 8 below the through hole 121 on the side away from the substrate 1 is then plasma-treated with oxygen to form a second buffer portion 11.

[0065] As shown in FIG. 1 , S12 , a photosensitive electrode 9 is prepared on the passivation layer 15 on both sides of the first groove 16 and on the first groove 16 , and the photosensitive electrode 9 is connected to the second buffer portion 11 .

[0066] In summary, although the present application is disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is based on the scope defined by the claims.

Claims

1. An array substrate, comprising: A substrate; An active layer disposed on the substrate, including a first doped portion, a second doped portion, and a channel portion located between the first doped portion and the second doped portion; A photosensitive layer disposed on a side of the first doped portion away from the substrate; A photosensitive electrode disposed on a side of the photosensitive layer away from the substrate; And A first buffer portion disposed between the photosensitive layer and the first doped portion; and / or A second buffer portion disposed between the photosensitive layer and the photosensitive electrode; and / or An intrinsic portion disposed between the channel portion and the first doped portion.

2. The array substrate according to claim 1, wherein, The material of the photosensitive layer includes amorphous silicon, and the materials of the first buffer portion and the second buffer portion both include SiOx.

3. The array substrate according to claim 1, wherein The surface of the first buffer portion away from the substrate is flush with the surface of the first doped portion away from the substrate, and the surface of the first buffer portion close to the substrate is located within the first doped portion.

4. The array substrate according to claim 1, wherein, The surface of the second buffer portion away from the substrate is flush with the surface of the photosensitive layer away from the substrate, and the surface of the second buffer portion close to the substrate is located within the photosensitive layer.

5. The array substrate according to claim 4, wherein, The array substrate further includes: A first interlayer insulating layer disposed between the photosensitive layer and the photosensitive electrode, and the surface of the first interlayer insulating layer close to the substrate is flush with the surface of the photosensitive layer away from the substrate; Wherein, the first interlayer insulating layer is provided with a through hole at a position corresponding to the second buffer portion, the photosensitive electrode is filled in the through hole, and is connected to the second buffer portion.

6. The array substrate according to claim 1, wherein, The material of the intrinsic portion is the same as that of the channel portion.

7. The array substrate according to claim 6, wherein, The active layer further includes: A third doped portion disposed between the channel portion and the intrinsic portion; Wherein, the doping concentrations of the first doped portion, the second doped portion, and the third doped portion are the same.

8. The array substrate according to claim 7, wherein, The active layer further includes: A fourth doped portion disposed between the channel portion and the second doped portion; and A fifth doped portion disposed between the channel portion and the third doped portion; Wherein, the doping concentrations of the fourth doped portion and the fifth doped portion are the same, and the doping concentration of the fourth doped portion is less than the doping concentration of the first doped portion.

9. The array substrate according to claim 1, wherein, The array substrate further includes: A gate insulating layer disposed on a side of the active layer away from the substrate, and extending to cover the substrate; A gate disposed on a side of the gate insulating layer away from the substrate, and corresponding to the channel portion; A second interlayer insulating layer disposed on a side of the gate away from the substrate, and extending to cover the gate insulating layer; A source electrode disposed on a side of the second interlayer insulating layer away from the substrate, and passing through the second interlayer insulating layer and the gate insulating layer to be electrically connected to the second doped portion; Wherein, the surface of the source electrode close to the substrate is located within the second doped portion.

10. The array substrate according to claim 9, wherein, The array substrate further includes: A planarization layer disposed on a side of the second interlayer insulating layer away from the substrate, and covering the source electrode; A passivation layer disposed on a side of the planarization layer away from the substrate; Wherein, the array substrate further includes a first groove penetrating through the photosensitive layer, the planarization layer, and the passivation layer, and the photosensitive electrode is disposed on the passivation layer on both sides of the first groove and on the first groove.

11. A display panel, including an array substrate, the array substrate includes: A substrate; An active layer disposed on the substrate, including a first doped portion, a second doped portion, and a channel portion located between the first doped portion and the second doped portion; A photosensitive layer disposed on a side of the first doped portion away from the substrate; A photosensitive electrode disposed on a side of the photosensitive layer away from the substrate; And A first buffer portion disposed between the photosensitive layer and the first doped portion; and / or A second buffer portion disposed between the photosensitive layer and the photosensitive electrode; and / or An intrinsic portion disposed between the channel portion and the first doped portion.

12. The display panel according to claim 11, wherein, The material of the photosensitive layer includes amorphous silicon, and the materials of the first buffer portion and the second buffer portion both include SiOx.

13. The display panel according to claim 11, wherein, The surface of the first buffer portion on a side away from the substrate is flush with the surface of the first doped portion on a side away from the substrate, and the surface of the first buffer portion on a side close to the substrate is located within the first doped portion.

14. The display panel according to claim 11, wherein, The surface of the second buffer portion on a side away from the substrate is flush with the surface of the photosensitive layer on a side away from the substrate, and the surface of the second buffer portion on a side close to the substrate is located within the photosensitive layer.

15. The display panel according to claim 14, wherein, The array substrate further includes: A first interlayer insulating layer disposed between the photosensitive layer and the photosensitive electrode, and the surface of the first interlayer insulating layer on a side close to the substrate is flush with the surface of the photosensitive layer on a side away from the substrate; Wherein, the first interlayer insulating layer is provided with a through hole at a position corresponding to the second buffer portion, and the photosensitive electrode is filled in the through hole and connected to the second buffer portion.

16. The display panel according to claim 11, wherein, The material of the intrinsic portion is the same as that of the channel portion.

17. The display panel according to claim 16, wherein, The active layer further includes: A third doped portion disposed between the channel portion and the intrinsic portion; Wherein, the doping concentrations of the first doped portion, the second doped portion, and the third doped portion are the same.

18. The display panel according to claim 17, wherein, The active layer further includes: A fourth doped portion disposed between the channel portion and the second doped portion; and A fifth doped portion disposed between the channel portion and the third doped portion; Wherein, the doping concentrations of the fourth doped portion and the fifth doped portion are the same, and the doping concentration of the fourth doped portion is less than the doping concentration of the first doped portion.

19. The display panel according to claim 11, wherein, The array substrate further includes: A gate insulating layer disposed on a side of the active layer away from the substrate and extending to cover the substrate; A gate disposed on a side of the gate insulating layer away from the substrate and corresponding to the channel portion; A second interlayer insulating layer disposed on a side of the gate away from the substrate and extending to cover the gate insulating layer; A source disposed on a side of the second interlayer insulating layer away from the substrate and penetrating through the second interlayer insulating layer and the gate insulating layer to be electrically connected to the second doped portion; Wherein, the surface of the source on a side close to the substrate is located within the second doped portion.

20. The display panel according to claim 19, wherein, The array substrate further includes: A planarization layer disposed on a side of the second interlayer insulating layer away from the substrate and covering the source electrode; A passivation layer disposed on a side of the planarization layer away from the substrate; Wherein, the array substrate further includes a first groove penetrating through the photosensitive layer, the planarization layer, and the passivation layer, and the photosensitive electrode is disposed on the passivation layer on both sides of the first groove and on the first groove.

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