Digital power source having adjustable power-on time interval and slew rate, and adjustment method

Abstract

The present application relates to the technical field of solid state drives (SSDs). Disclosed are a digital power source having an adjustable power-on time interval and slew rate, and an adjustment method. In the digital power source, a power supply circuit provides a working power source for the digital power source; overall control is performed by means of a main control circuit, which comprises a main control device and a first interface; and voltage outputting is performed by means of multiple power source adjustable circuits, each of which comprises a buck circuit composed of a first metal oxide semiconductor (MOS), a second MOS and a filter capacitor, and corresponds to one power source rail in an SSD. During the process, an external control parameter is received by means of the first interface in the main control circuit, the main control device is used to generate a pulse-width modulation (PWM) wave in response to the external control parameter, the PWM wave is sent to each power source adjustable circuit by means of a first pair of pins, and the turning-on / -off of the first MOS and second MOS in each power source adjustable circuit is controlled by means of the PWM wave, and by means of the buck circuit, each power source adjustable circuit is controlled to output a stable voltage at a determined power-on time interval and power-on slew rate.

Description

A digital power supply with adjustable power-on time interval and slope and a regulation method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 28, 2023, with application number 202311840203.7, entitled “A digital power supply and adjustment method with adjustable power-on time interval and slope”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the technical field of solid-state hard disks, and in particular to a digital power supply with adjustable power-on time interval and slope and a regulation method. Background Art

[0004] Solid-state drives (SSDs) are high-performance storage devices. In the cloud computing era, massive data storage and transmission requires large-capacity storage platforms. With the widespread use of SSDs in storage service systems, data computing and storage efficiency has been significantly improved.

[0005] SSDs typically have multiple power rails, and there are requirements for the power-on sequence of different power rails. Sometimes there are even certain requirements for the power-on interval and output slope between two power rails. Faced with complex timing requirements, existing test power supplies are unable to control the power-on interval and power-on slope between different channels. In other words, existing test power supplies cannot meet the testing needs of SSDs.

[0006] Summary of the Invention

[0007] In view of this, the present application provides a digital power supply and adjustment method with adjustable power-on time interval and slope to solve the technical problem of uncontrollable power-on time interval and power-on slope between different channels of SSD in the related art.

[0008] The present application provides a digital power supply with adjustable power-on time interval and slope. The digital power supply includes: a main control circuit, a power supply circuit and a multi-channel power supply adjustable circuit. The main control circuit is respectively connected to the power supply circuit and each power supply adjustable circuit, wherein the power supply circuit is configured to provide working power for the digital power supply; the main control circuit includes a main control device and a first interface, and is configured to respond to external control parameters received by the first interface and send a PWM (Pulse-Width Modulation) wave to each power supply adjustable circuit through a first pair of pins of the main control device; each power supply adjustable circuit includes a first MOS (Metal Oxide Semiconductor), a second MOS and a filter capacitor. The first MOS, the second MOS and the filter capacitor together constitute a step-down circuit, which is configured to control the on and off of the first MOS and the second MOS in response to the PWM wave of the main control circuit, and output electrical energy through the step-down circuit with a determined power-on time interval and slope.

[0009] As an optional implementation, the main control circuit is further configured to sample the voltage value of each power adjustable circuit, and calculate and output a PWM wave based on the voltage value through a digital PID (Proportion Integration Differentiation).

[0010] As an optional implementation, each adjustable power supply circuit also includes: a feedback resistor and an operational amplifier. The feedback resistor forms a low-pass filter circuit through the operational amplifier. The low-pass filter circuit is configured to respond to the voltage sampling requirements of the main control circuit and feedback the output voltage value of the corresponding adjustable power supply circuit.

[0011] As an optional implementation, the main control circuit further includes: a first frequency crystal oscillator and a second frequency crystal oscillator, and the first frequency crystal oscillator and the second frequency crystal oscillator are configured to provide a clock signal.

[0012] As an optional implementation, the main control circuit further includes: a first indicator light, which is configured to indicate a working state of the main control circuit.

[0013] As an optional embodiment, the first indicator light is configured to have a long-on state and a flashing state, wherein the long-on state is used to indicate that the working state of the main control circuit is normal, and the flashing state is used to indicate that the working state of the main control circuit is a fault state.

[0014] As an optional implementation, each power adjustable circuit further includes: a clamping diode, which is configured as an input voltage to protect subsequent circuits.

[0015] As an optional implementation, each adjustable power circuit further includes: a second indicator light, where the second indicator light is configured to indicate whether the corresponding adjustable power circuit has an input voltage.

[0016] The present application provides a method for regulating a digital power supply with an adjustable power-on time interval and slope, which is applied to the digital power supply of the first aspect described above or any corresponding embodiment thereof. The method includes: generating a PWM wave corresponding to an adjustable power supply circuit in response to an external control parameter received by a first interface; controlling the on and off of a first MOS and a second MOS corresponding to the adjustable power supply circuit based on the PWM wave; obtaining a working power supply; and outputting electrical energy at a determined power-on time interval and slope by turning on and off the first MOS and the second MOS based on the working power supply.

[0017] As an optional implementation, in response to the external control parameters received by the first interface, a PWM wave corresponding to the power adjustable circuit is generated, including: sampling the voltage value of the corresponding power adjustable circuit; and generating the corresponding PWM wave based on the voltage value through digital PID.

[0018] As an optional embodiment, the adjustable power circuit includes a low-pass filter circuit, the low-pass filter circuit includes a feedback resistor and an operational amplifier, and sampling the voltage value of the corresponding adjustable power circuit includes: the voltage value of the corresponding adjustable power circuit output by the low-pass filter circuit in the adjustable power circuit, the voltage value is obtained by the low-pass filter circuit sampling the adjustable power circuit in response to the voltage sampling requirement of the main control circuit.

[0019] As an optional implementation, based on the voltage value, a corresponding PWM wave is generated through a digital PID, including: using the digital PID to calculate the voltage value to obtain the target duty cycle of the PWM wave to be output; and generating a PWM wave with the target duty cycle through a main control device.

[0020] As an optional implementation, based on the working power supply, the first MOS and the second MOS are turned on and off to output electric energy with a determined power-on time interval and slope, including: based on the working power supply, the first MOS and the second MOS are turned on and off to control the corresponding power adjustable circuit to power on at a determined time interval; based on the working power supply, the first MOS and the second MOS are turned on and off to control the corresponding power adjustable circuit to reach the set electric energy at a determined time.

[0021] As an optional implementation, based on the working power supply, the corresponding power adjustable circuit is controlled to be powered on at a determined time interval by turning on and off the first MOS and the second MOS, including: controlling the power-on timing of the corresponding power adjustable circuit by turning on and off the first MOS and the second MOS, wherein the power-on timing is used to adjust the power-on time interval of the power adjustable circuit.

[0022] As an optional implementation, based on the working power supply, the corresponding power adjustable circuit is controlled to reach the set power within a determined time by turning on and off the first MOS and the second MOS, including: controlling the voltage of the corresponding power adjustable circuit to reach the target time required for the output voltage value from 0V by turning on and off the first MOS and the second MOS, wherein the target time is used to adjust the power-on slope of the power adjustable circuit.

[0023] The present application provides a parallel digital power supply with adjustable power-on time interval and slope, comprising at least two digital power supplies according to the first aspect or any corresponding embodiment thereof, wherein the main control circuit further comprises a second interface, a third interface, and a conversion switch, the conversion switch being configured to identify the execution priority of each digital power supply, the second interface being configured to transmit external control parameters between the at least two digital power supplies, and the third interface being configured to transmit trigger signals between the at least two digital power supplies.

[0024] As an optional embodiment, the third interface is a second pair of pins of the device, the at least two digital power supplies include a first digital power supply and a second digital power supply, the first digital power supply has a higher execution priority than the second digital power supply, and the main control circuit of the first digital power supply is configured to send a trigger signal to the second digital power supply through the second pair of pins of the first digital power supply; the main control circuit of the second digital power supply is configured to receive external control parameters through the second interface of the second digital power supply in response to the trigger signal, and send PWM waves to each power adjustable circuit corresponding to the second digital power supply through the first pair of pins of the main control device of the second digital power supply.

[0025] The present application provides a method for adjusting the parallel use of a digital power supply with an adjustable power-on time interval and slope, which is applied to the first digital power supply in the parallel use of the digital power supply of the third aspect or any corresponding embodiment thereof, wherein the execution priority of the first digital power supply is higher than that of the second digital power supply. The method includes: obtaining a first state of a first conversion switch; based on the first state, generating a first PWM wave corresponding to the adjustable power supply circuit in response to an external control parameter received by a first interface; controlling the on and off of a first MOS and a second MOS corresponding to the adjustable power supply circuit based on the first PWM wave; obtaining a first working power supply; based on the first working power supply, outputting electrical energy with a determined power-on time interval and slope by turning the first MOS and the second MOS on and off; sending the external control parameter to the second digital power supply via the second interface; and sending a trigger signal to the second digital power supply via the third interface.

[0026] The present application provides a method for adjusting the parallel use of a digital power supply with adjustable power-on time interval and slope, which is applied to the second digital power supply in the parallel use of the digital power supply according to the third aspect or any corresponding embodiment thereof, wherein the execution priority of the first digital power supply is higher than that of the second digital power supply. The method includes: obtaining a second state of a second conversion switch; based on the second state, in response to a trigger signal received by a third interface, generating a second PWM wave corresponding to the adjustable power supply circuit through an external control parameter received by the second interface; based on the second PWM wave, controlling the on and off of a third MOS transistor and a fourth MOS transistor corresponding to the adjustable power supply circuit; obtaining a second working power supply; and based on the second working power supply, outputting electrical energy with a determined power-on time interval and slope by turning on and off the third MOS transistor and the fourth MOS transistor.

[0027] The present application provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to thereby execute the adjustment method of the above-mentioned first aspect, fourth aspect, fifth aspect or any corresponding embodiment thereof.

[0028] The technical solution of a digital power supply with adjustable power-on time interval and slope and a regulation method provided in this application has the following advantages:

[0029] This digital power supply provides operating power to the digital power supply through a power supply circuit. A main control circuit, including a main control device and a first interface, performs overall control. Multiple adjustable power circuits, including a step-down circuit composed of a first MOS transistor, a second MOS transistor, and a filter capacitor, provide voltage output. Each adjustable power circuit corresponds to a power rail in an SSD. During this process, external control parameters are received through the first interface in the main control circuit. The main control device generates a PWM wave responsive to the external control parameters. This PWM wave is transmitted to each adjustable power circuit via a first pair of pins. The PWM wave controls the on / off switching of the first and second MOS transistors in each adjustable power circuit. The step-down circuit controls each adjustable power circuit to output a stable voltage at a predetermined power-on interval and power-on slope. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0031] FIG1 is an application diagram of a digital power supply with adjustable power-on time interval and slope according to an embodiment of the present application;

[0032] 2 is a schematic diagram of a main control circuit of a digital power supply with adjustable power-on time interval and slope according to an embodiment of the present application;

[0033] 3 is a schematic diagram of an adjustable power supply circuit of a digital power supply with adjustable power-on time interval and slope according to an embodiment of the present application;

[0034] 4 is a schematic diagram of a power supply circuit of a digital power supply with adjustable power-on time interval and slope according to an embodiment of the present application;

[0035] 5 is a flow chart of a method for regulating a digital power supply with adjustable power-on time interval and slope according to an embodiment of the present application;

[0036] FIG6 is a schematic diagram of an application of a digital power supply with an adjustable power-on time interval and slope in parallel according to an embodiment of the present application;

[0037] 7 is a schematic diagram of an interactive flow of a method for adjusting parallel use of a digital power supply with adjustable power-on time interval and slope according to an embodiment of the present application;

[0038] FIG8 is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present application;

[0039] Reference numerals:

[0040] U1-operational amplifier; U2-power supply circuit; U3-main control device; J1-first interface;

[0041] J2-second interface; J3-third interface; SW1-conversion switch; Y1-first frequency crystal oscillator;

[0042] Y2-second frequency crystal oscillator; R5, R6-feedback resistors; D1-feedforward diode;

[0043] C9-filter capacitor; Q1, Q3-first MOS; Q2, Q4-second MOS;

[0044] LED1-second indicator light; LED2-first indicator light. DETAILED DESCRIPTION

[0045] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0046] An embodiment of the present application provides an application schematic diagram of a digital power supply with adjustable power-on time interval and slope, as shown in Figure 1, including: a host computer 10, a host computer 20, a load 301, and a load 302, wherein the host computer 20 includes an interface 201, a channel 204, and a channel 205. The host computer 201 is equivalent to a digital power supply with adjustable power-on time interval and slope, the interface 201 is equivalent to the first interface of the main control circuit, and the channel 204 and the channel 205 are respectively equivalent to a power adjustable circuit. The host computer 10 transmits external control parameters through the first interface 201. The external control parameters refer to the set parameters issued, such as the output voltage value and the power-on time interval value. In response to the external control parameters, the host computer 20 uses the main control circuit to generate a PWM (Pulse-Width Modulation) wave to respectively control the channel 204 and the channel 205 to output electrical energy to the load 301 and the load 302 at a determined power-on time interval and slope.

[0047] The embodiment of the present application provides a digital power supply with adjustable power-on time interval and slope, the digital power supply comprising: a main control circuit, a power supply circuit and a multi-way power supply adjustable circuit, the main control circuit being connected to the power supply circuit and each power supply adjustable circuit respectively, wherein:

[0048] The power supply circuit is configured to provide working power for the digital power supply.

[0049] An embodiment of the present application provides a schematic diagram of a power supply circuit, as shown in Figure 4. Figure 4 schematically shows the circuit connection structure of the power supply circuit U2. It should be understood that the power supply circuit includes but is not limited to the connection method shown in Figure 4. As long as the power supply circuit can be configured to provide working power for the digital power supply, the power supply circuit is usually configured to convert 12V to 3.3V to provide a stable 3.3V working power supply for the digital power supply.

[0050] The main control circuit includes a main control device and a first interface, and is configured to send a PWM wave to each power adjustable circuit through a first pair of pins of the main control device in response to an external control parameter received by the first interface.

[0051] An embodiment of the present application provides a schematic diagram of a main control circuit, as shown in FIG2 , in which the main control circuit includes a main control device U3 and a first interface J1. The first interface J1 is used to receive external control parameters. The main control device U3 responds to the external control parameters and outputs a PWM wave with an adjustable duty cycle through a first pair of pins to control each power adjustable circuit respectively, thereby stabilizing the output voltage on the POWER1_OUT network or the POWER2_OUT network at a certain set value. In which, the first pair of pins in FIG2 refers to a pair of pins formed by pins 41 and 42 or a pair of pins formed by pins 22 and 23, and the first pair of pins refers to a pair of pins connected to each power adjustable circuit. It should be understood that, for ease of understanding, only two channels, i.e., two power adjustable circuits, are shown in the figure, and the main control circuit includes but is not limited to the connection method shown in FIG2 .

[0052] Each adjustable power supply circuit includes a first MOS (Metal Oxide Semiconductor), a second MOS and a filter capacitor. The first MOS, the second MOS and the filter capacitor together constitute a step-down circuit, which is configured to respond to the PWM wave of the main control circuit, control the on and off of the first MOS and the second MOS, and output electrical energy through the step-down circuit with a determined power-on time interval and slope.

[0053] Optionally, an embodiment of the present application provides a schematic diagram of an adjustable power supply circuit, as shown in Figure 3. Taking one adjustable power supply circuit as an example, each adjustable power supply circuit includes a first MOS, Q1, a second MOS, Q2 and a filter capacitor C9. The first MOS, the second MOS and the filter capacitor together constitute a step-down circuit, which receives the PWM wave transmitted by the main control circuit through pins 41 and 42, controls the on and off of the first MOS and the second MOS, controls the power-on time interval of the power supply by controlling the power-on timing of the POWER1_OUT network, and controls the power-on slope of the POWER1_OUT network by controlling the time required for the voltage on the POWER1_OUT network to reach the set voltage value from 0V.

[0054] FIG3 schematically illustrates the circuit connection structure of an adjustable power supply circuit. It should be understood that the adjustable power supply circuit includes, but is not limited to, the connection method shown in FIG3 . The two adjustable power supply circuits shown in FIG3 are constructed using a basic BUCK topology. The connection structure of each adjustable power supply circuit is the same and will not be further described.

[0055] Embodiments of the present application provide a digital power supply with adjustable power-on time interval and slope. The digital power supply provides operating power to the digital power supply via a power supply circuit. A main control circuit comprising a main control device and a first interface performs overall control. Multiple adjustable power supply circuits comprising a step-down circuit consisting of a first MOS transistor, a second MOS transistor, and a filter capacitor provide voltage output. Each adjustable power supply circuit corresponds to a power rail in an SSD. During this process, external control parameters are received via the first interface in the main control circuit, a PWM wave responsive to the external control parameters is generated by the main control device, and the PWM wave is transmitted to each adjustable power supply circuit via a first pair of pins. The PWM wave controls the on / off switching of the first and second MOS transistors in each adjustable power supply circuit. The step-down circuit controls each adjustable power supply circuit to output a stable voltage at a predetermined power-on time interval and power-on slope.

[0056] In an optional implementation, the main control circuit is further configured to sample the voltage value of each power adjustable circuit, and calculate and output a PWM wave based on the voltage value through a digital PID (Proportion Integration Differentiation).

[0057] In an optional embodiment, each adjustable power supply circuit further includes: a feedback resistor and an operational amplifier, the feedback resistor forms a low-pass filter circuit through the operational amplifier, and the low-pass filter circuit is configured to respond to the voltage sampling requirements of the main control circuit and feedback the output voltage value of the corresponding adjustable power supply circuit.

[0058] Optionally, as shown in FIG3 , each adjustable power supply circuit further includes feedback resistors R5 and R6 and an operational amplifier U1 . The voltage divider circuit formed by the feedback resistors R5 and R6 forms a low-pass filter circuit through the operational amplifier U1 . The low-pass filter circuit feeds back the output voltage to the main control device U3 .

[0059] Optionally, the main control device U3 of the main control circuit samples the voltage value of each power adjustable circuit and changes the duty cycle of the output PWM wave through digital PID calculation, so that the power supply stably outputs the set voltage value.

[0060] In an optional implementation, the main control circuit further includes: a first frequency crystal oscillator and a second frequency crystal oscillator, and the first frequency crystal oscillator and the second frequency crystal oscillator are configured to provide a clock signal.

[0061] Optionally, as shown in Figure 2, the main control circuit also includes a first frequency crystal oscillator Y1 and a second frequency crystal oscillator Y2. The first frequency crystal oscillator Y1 usually uses an 8MHz crystal oscillator, and the second frequency crystal oscillator Y2 usually uses a 32.768KHz crystal oscillator. The first frequency crystal oscillator Y1 and the second frequency crystal oscillator Y2 provide the necessary clock signal for the main control device U3.

[0062] In an optional implementation, the main control circuit further includes: a first indicator light, and the first indicator light is configured to indicate the working status of the main control circuit.

[0063] Optionally, as shown in Figure 2, the main control circuit also includes: a first indicator light LED2, which is configured to indicate the working status of the main control circuit. Usually, when the digital power supply is working normally, LED2 is in a long-on state, and when the digital power supply fails and enters protection, LED2 is in a flashing state.

[0064] In an optional implementation, each power adjustable circuit further includes: a clamping diode, which is configured to input voltage to protect subsequent circuits.

[0065] Optionally, as shown in FIG3 , each adjustable power supply circuit further includes: a clamping diode D1 , which is configured to suppress the input voltage, thereby protecting the subsequent circuit when the input voltage is too high.

[0066] In an optional implementation, each adjustable power circuit further includes: a second indicator light, where the second indicator light is configured to indicate whether the corresponding adjustable power circuit has an input voltage.

[0067] Optionally, as shown in FIG3 , each power adjustable circuit further includes: a second indicator light LED 1 , which is normally always on when there is input voltage.

[0068] According to an embodiment of the present application, an embodiment of a method for regulating a digital power supply with an adjustable power-on time interval and slope is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0069] In an optional embodiment, the present application provides a method for regulating a digital power supply with an adjustable power-on time interval and slope, as shown in FIG5 . The method includes the following steps:

[0070] S101 : Generate a PWM wave corresponding to an adjustable power circuit in response to an external control parameter received by a first interface.

[0071] Optionally, the external control parameters include: an output voltage value and a power-on time interval value.

[0072] In an optional embodiment, generating a PWM wave corresponding to the power adjustable circuit in response to the external control parameter received by the first interface includes:

[0073] Sample the voltage value of the corresponding power adjustable circuit.

[0074] Optionally, the voltage value of the sampling corresponding to the adjustable power supply circuit refers to the output voltage value fed back by the sampling adjustable power supply circuit, wherein the output voltage value fed back by the adjustable power supply circuit refers to the feedback resistor and the operational amplifier of the adjustable power supply circuit, and a low-pass filter circuit is formed by the feedback resistor through the operational amplifier. The low-pass filter circuit is configured to respond to the voltage sampling requirement of the main control circuit and feed back the output voltage value of the corresponding adjustable power supply circuit.

[0075] Based on the voltage value, the corresponding PWM wave is generated through digital PID.

[0076] Optionally, based on the voltage value, generating the corresponding PWM wave through digital PID means sampling the output voltage value of the power supply adjustable circuit and changing the duty cycle of the output PWM wave through digital PID calculation, so that the power supply can stably output the output voltage value that meets the external control parameters.

[0077] S102 : Based on the PWM wave, controlling the on and off of the first MOS and the second MOS corresponding to the power adjustable circuit.

[0078] S103: Obtain working power.

[0079] Optionally, obtaining working power refers to obtaining power supply provided by a power supply circuit.

[0080] S104 : Based on the working power supply, the first MOS and the second MOS are turned on and off to output electric energy with a determined power-on time interval and slope.

[0081] In an optional embodiment, based on the working power supply, the first MOS and the second MOS are turned on and off to output electric energy with a determined power-on time interval and slope, including:

[0082] Based on the working power supply, the corresponding power adjustable circuit is controlled to be powered on at a determined time interval by turning on and off the first MOS and the second MOS.

[0083] Optionally, based on the working power supply, controlling the power-on of the corresponding power adjustable circuit at a determined time interval by turning on and off the first MOS and the second MOS means controlling the power-on timing of the corresponding power regulating circuit by turning on and off the first MOS and the second MOS, thereby controlling the power-on time interval of the power supply.

[0084] Based on the working power supply, the first MOS and the second MOS are turned on and off to control the corresponding power adjustable circuit to reach the set power within a certain time.

[0085] Optionally, based on the working power supply, by turning on and off the first MOS and the second MOS, controlling the corresponding power adjustable circuit to reach the set power within a determined time means controlling the time required for the voltage of the corresponding power regulation circuit to reach the output voltage value from 0V by turning on and off the first MOS and the second MOS, thereby controlling the power-on slope of the power supply.

[0086] The present application provides an application diagram of a parallel digital power supply with adjustable power-on time interval and slope, as shown in FIG6 , including: a host computer 10, a host 20, a slave 40, a load 301, a load 3032, a load 303, and a load 304. The corresponding parts of FIG1 in the above embodiment will not be repeated here, and for details, please refer to the above embodiment. Among them, interface 401 corresponds to the first interface of slave 40, interface 202 and interface 402 correspond to the third interface of host 20 and slave 40, respectively, and channel 404 and channel 405 correspond to one adjustable power circuit of slave 40. Interface 203 and interface 403 correspond to the second interfaces of the host 20 and the slave 40, respectively. The host 20 transmits external control parameters to the slave 40 through the second interface, and the host 20 sends a trigger signal to the slave 40 through the third interface. In response to the external control parameters, the slave 40 uses the main control circuit to generate a PWM wave to regulate the channel 404 and the channel 405 to output electrical energy to the load 303 and the load 304 respectively at a determined power-on time interval and slope.

[0087] The embodiment of the present application provides a parallel digital power supply with adjustable power-on time interval and slope, comprising at least two digital power supplies with adjustable power-on time interval and slope in the above embodiments, wherein:

[0088] The main control circuit also includes a second interface, a third interface and a conversion switch. The conversion switch is configured to identify the execution priority of each digital power supply. The second interface is configured to transmit external control parameters between at least two digital power supplies. The third interface is configured to transmit trigger signals between at least two digital power supplies.

[0089] Optionally, an embodiment of the present application provides a schematic diagram of a main control circuit, as shown in FIG2 , in which the main control circuit device includes a second interface J2 , a third interface J3 and a conversion switch SW1 .

[0090] Optionally, SW1 is configured to identify the execution priority of each digital power supply. For example, with two digital power supplies with adjustable power-on intervals and slopes, the first digital power supply is the master and the second digital power supply is the slave. In this case, the master's transfer switch SW1 may be open, while the slave's transfer switch SW1 is closed. In this case, the corresponding load is first powered by the master's channel, i.e., the master's adjustable power circuit, followed by the slave's channel, i.e., the slave's adjustable power circuit. Similarly, with three digital power supplies with adjustable power-on intervals and slopes, the first digital power supply is the master, the second digital power supply is a slave relative to the first digital power supply, and the third digital power supply is a slave relative to the second digital power supply. The execution priority is indicated by the transfer switches of the corresponding digital power supplies. In this case, the corresponding load is first powered by the channel of the first digital power supply, followed by the channel of the second digital power supply, and finally by the channel of the third digital power supply. It should be understood that the same analogy applies to more digital power supplies with adjustable power-on intervals and slopes, and this description is omitted.

[0091] Optionally, after the master obtains operating power from the power supply, the master sends external control parameters to the second interface of the slave via the second interface. After the master completes outputting voltage to the corresponding load via the path included in the master, the master sends a trigger signal to the third interface of the slave via the third interface. Upon receiving the trigger signal, the slave begins coordinated operation with the master parallel machine, i.e., the parallel machine begins outputting voltage to the corresponding load via the path included in the parallel machine.

[0092] In an optional embodiment, the third interface is a second pair of pins of the device, the at least two digital power supplies include a first digital power supply and a second digital power supply, and the execution priority of the first digital power supply is higher than that of the second digital power supply.

[0093] The main control circuit of the first digital power supply is configured to send a trigger signal to the second digital power supply through the second pair of pins of the first digital power supply.

[0094] The main control circuit of the second digital power supply is configured to respond to the trigger signal and the external control parameters received through the second interface of the second digital power supply, and send a PWM wave to each power adjustable circuit corresponding to the second digital power supply through the first pair of pins of the main control device of the second digital power supply.

[0095] Optionally, an embodiment of the present application provides a schematic diagram of a master control circuit, as shown in FIG2 . The second pair of pins in FIG2 refers to pins 11, and the second pair of pins refers to pins connecting the master control device of the host and the master control device of the slave. The master control circuit of the second digital power supply is configured to respond to a trigger signal and receive external control parameters via the second interface of the second digital power supply, and transmit a PWM wave to each power adjustable circuit corresponding to the second digital power supply via the first pair of pins of the master control device of the second digital power supply via the first pair of pins. For the specific process, refer to the description of the master control circuit in the above embodiment, and will not be repeated here.

[0096] By implementing the embodiments of the present application, the parallel use of multiple digital power supplies with adjustable power-on time intervals and slopes is achieved through the parallel use of the digital power supply with adjustable power-on time intervals and slopes, including the second interface, the third interface, and the conversion switch. In this process, the external control parameters of the host are transmitted to the slave through the second interface, and after the host completes the voltage output of the corresponding power adjustable circuit, a trigger signal is sent to the slave through the third interface, so that the slave outputs the voltage of the corresponding power regulation circuit, thereby realizing the parallel use of the host and the slave, and realizing the control and adjustment of the power-on time interval and power-on slope of each power regulation circuit, that is, achieving multi-channel output stable voltage with a determined power-on time interval and power-on slope.

[0097] In an optional embodiment, an embodiment of the present application provides a method for regulating a digital power supply with an adjustable power-on time interval and slope, which is applied to a first digital power supply, wherein the execution priority of the first digital power supply is higher than that of the second digital power supply. As shown in FIG7 , the method includes the following steps:

[0098] S201: Acquire a first state of a first conversion switch.

[0099] Optionally, the first conversion switch refers to the conversion switch of the first digital power supply, and obtaining the first state of the first conversion switch refers to determining the execution priority of the first digital power supply relative to the second digital power supply. In the embodiment of the present application, since the execution priority of the first digital power supply is higher than that of the second digital power supply, the first digital power supply is the host and the second digital power supply is the slave.

[0100] S202: Based on the first state, in response to the external control parameters received by the first interface, generate a first PWM wave corresponding to the power adjustable circuit. This process is described in detail in the above embodiment regarding the main control circuit, and will not be repeated here.

[0101] S203: Based on the first PWM wave, the first MOS and the second MOS corresponding to the power adjustable circuit are controlled to be on and off. This process is described in detail in the above embodiment regarding the main control circuit and the power adjustable circuit, and will not be repeated here.

[0102] S204: Obtain a first working power source.

[0103] Optionally, the first working power supply refers to the working power supply provided by the power supply circuit in the first digital power supply.

[0104] S205: Based on the first working power supply, the first MOS and the second MOS are turned on and off to output electric energy with a determined power-on time interval and slope. This process is described in detail in the above embodiment regarding the power adjustable circuit, and will not be described in detail here.

[0105] S206: Send external control parameters to the second digital power supply via the second interface, and send a trigger signal to the second digital power supply via the third interface. This process is described in detail in the above embodiment regarding the second interface and the third interface, and will not be repeated here.

[0106] In an optional implementation, an embodiment of the present application provides a method for regulating a digital power supply with an adjustable power-on time interval and slope, which is applied to a second digital power supply, wherein the execution priority of the first digital power supply is higher than that of the second digital power supply. As shown in FIG7 , the method includes the following steps:

[0107] S207: Acquire a second state of the second conversion switch.

[0108] Optionally, the second conversion switch refers to a conversion switch of a second digital power supply, and obtaining the second state of the second conversion switch refers to determining the execution priority of the second digital power supply relative to the first digital power supply. In an embodiment of the present application, since the execution priority of the first digital power supply is higher than that of the second digital power supply, the first digital power supply is the host and the second digital power supply is the slave.

[0109] S208: Based on the second state, in response to the trigger signal received by the third interface, a second PWM wave corresponding to the adjustable power circuit is generated using the external control parameters received by the second interface. This process is described in detail in the above embodiment regarding the main control circuit and will not be further elaborated here.

[0110] S209: Based on the second PWM wave, the third MOS and the fourth MOS corresponding to the power adjustable circuit are controlled to be on and off. This process is described in detail in the above embodiment regarding the main control circuit and the power adjustable circuit, and will not be described in detail here.

[0111] S210: Obtain a second working power source.

[0112] Optionally, the second working power supply refers to the working power supply provided by the power supply circuit in the second digital power supply.

[0113] S211: Based on the second working power supply, the third MOS and the fourth MOS are turned on and off to output electric energy with a determined power-on time interval and slope. This process is described in detail in the above embodiment regarding the power adjustable circuit, and will not be described in detail here.

[0114] An embodiment of the present application also provides a computer device. Please refer to Figure 8, which is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present application. As shown in Figure 8, the computer device includes: one or more processors 501, a memory 502, and interfaces configured to connect various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in or on the memory to display graphical information of a GUI (Graphical User Interface) on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, with each device providing some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 8 takes a processor 501 as an example.

[0115] Processor 501 may be a central processing unit, a network processor, or a combination thereof. Processor 501 may also include hardware devices. The hardware devices may be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or a combination thereof. The programmable logic devices may be complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), general purpose array logic (GAL), or any combination thereof.

[0116] The memory 502 stores instructions that can be executed by at least one processor 501, so as to enable the at least one processor 501 to execute the method shown in the above embodiment.

[0117] The memory 502 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 502 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 502 may optionally include a memory remotely located relative to the processor 501, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0118] The memory 502 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, a hard disk, or a solid-state drive; the memory 502 may also include a combination of the aforementioned types of memory. The computer device also includes a communication interface 503 configured to enable the computer device to communicate with other devices or a communication network.

[0119] The embodiments of the present application also provide a computer non-volatile readable storage medium. The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a non-volatile readable storage medium, or implemented as a computer code that is originally stored in a remote non-volatile readable storage medium or a non-transitory machine non-volatile readable storage medium and is downloaded through a network and will be stored in a local non-volatile readable storage medium, so that the method described herein can be stored in such software processing on a non-volatile readable storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the non-volatile readable storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; optionally, the non-volatile readable storage medium can also include a combination of the above-mentioned types of memory. It can be understood that the computer, processor, microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by the computer, processor or hardware, the method shown in the above embodiment is implemented.

[0120] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A digital power supply with adjustable power-on time interval and slope, characterized in that The digital power supply includes: a main control circuit, a power supply circuit, and a multi-channel adjustable power supply circuit. The main control circuit is respectively connected to the power supply circuit and each channel of the adjustable power supply circuit. Among them, The power supply circuit is configured to provide a working power supply for the digital power supply; The main control circuit includes a main control device and a first interface, and is configured to respond to external control parameters received by the first interface, and send a pulse width modulation (PWM) wave to each channel of the adjustable power supply circuit through a first pair of pins of the main control device; Each channel of the adjustable power supply circuit includes a first metal-oxide semiconductor (MOS), a second MOS, and a filter capacitor. The first MOS, the second MOS, and the filter capacitor together form a buck circuit, which is configured to respond to the PWM wave of the main control circuit, control the on / off of the first MOS and the second MOS, and output electric energy at a determined power-on time interval and slope through the buck circuit.

2. The digital power supply according to claim 1, wherein The main control circuit is further configured to sample the voltage value of each channel of the adjustable power supply circuit, and calculate and output a PWM wave based on the voltage value through digital proportional integral derivative (PID).

3. The digital power supply according to claim 2, wherein Each channel of the adjustable power supply circuit further includes: a feedback resistor and an operational amplifier. The feedback resistor and the operational amplifier form a low-pass filter circuit, and the low-pass filter circuit is configured to respond to the voltage sampling requirement of the main control circuit and feedback the output voltage value of the corresponding adjustable power supply circuit.

4. The digital power supply according to claim 1, characterized in that, The main control circuit further includes: a first frequency crystal oscillator and a second frequency crystal oscillator, and the first frequency crystal oscillator and the second frequency crystal oscillator are configured to provide clock signals.

5. The digital power supply according to claim 1, wherein The main control circuit further includes: a first indicator light, and the first indicator light is configured to indicate the working state of the main control circuit.

6. The digital power supply according to claim 5, characterized in that, The first indicator light is configured to have a long-on state and a flashing state. Among them, the long-on state is used to indicate that the working state of the main control circuit is normal, and the flashing state is used to indicate that the working state of the main control circuit is a fault state.

7. The digital power supply according to claim 1, characterized in that Each channel of the adjustable power supply circuit further includes: a clamping diode, and the clamping diode is configured to input voltage to protect the subsequent circuit.

8. The digital power supply according to claim 1, wherein Each channel of the adjustable power supply circuit further includes: a second indicator light, and the second indicator light is configured to indicate whether the corresponding adjustable power supply circuit has an input voltage.

9. A regulation method for a digital power supply with adjustable power-on time interval and slope, characterized in that, Applied to the digital power supply according to any one of claims 1 to 8, the method includes: Responding to external control parameters received by the first interface, generating a PWM wave corresponding to the adjustable power supply circuit; Based on the PWM wave, controlling the on / off of the first MOS and the second MOS corresponding to the adjustable power supply circuit off; Obtaining a working power supply; Based on the working power supply, outputting electric energy at a determined power-on time interval and slope through the on / off of the first MOS and the second MOS.

10. The method according to claim 9, wherein The step of responding to external control parameters received by the first interface and generating a PWM wave corresponding to the adjustable power supply circuit includes: Sampling the voltage value of the corresponding adjustable power supply circuit; Based on the voltage value, generating a corresponding PWM wave through digital PID.

11. According to the method of claim 10, wherein The power adjustable circuit includes a low-pass filter circuit, and the low-pass filter circuit includes a feedback resistor and an operational amplifier. Sampling the voltage value corresponding to the power adjustable circuit includes: The voltage value corresponding to the power adjustable circuit output through the low-pass filter circuit in the power adjustable circuit, where the voltage value is obtained by sampling the power adjustable circuit by the low-pass filter circuit in response to the voltage sampling requirement of the main control circuit.

12. The method according to claim 10, wherein Generating a corresponding PWM wave based on the voltage value through a digital PID includes: Calculating the voltage value using the digital PID to obtain the target duty cycle of the PWM wave to be output; Generating the PWM wave with the target duty cycle through the main control device.

13. The method according to claim 9, characterized in that, Based on the working power supply, outputting electric energy at a determined power-on time interval and slope by turning on and off the first MOS and the second MOS includes: Based on the working power supply, controlling the power-on of the corresponding power adjustable circuit at a determined time interval by turning on and off the first MOS and the second MOS; Based on the working power supply, controlling the corresponding power adjustable circuit to reach the set electric energy at a determined time by turning on and off the first MOS and the second MOS.

14. The method according to claim 13, wherein Based on the working power supply, controlling the power-on of the corresponding power adjustable circuit at a determined time interval by turning on and off the first MOS and the second MOS includes: Controlling the power-on timing of the corresponding power adjustable circuit by turning on and off the first MOS and the second MOS, where the power-on timing is used to adjust the power-on time interval of the power adjustable circuit.

15. The method according to claim 13, wherein Based on the working power supply, controlling the corresponding power adjustable circuit to reach the set electric energy at a determined time by turning on and off the first MOS and the second MOS includes: Controlling the target time required for the voltage of the corresponding power adjustable circuit to reach the output voltage value from 0V by turning on and off the first MOS and the second MOS, where the target time is used to adjust the power-on slope of the power adjustable circuit.

16. A parallel-connected digital power supply with adjustable power-on time interval and slope, characterized in that Including at least two digital power supplies as described in any one of claims 1 to 8, wherein The main control circuit further includes a second interface, a third interface, and a switch. The switch is configured to identify the execution priority of each digital power supply. The second interface is configured to transmit external control parameters between at least two digital power supplies. The third interface is configured to transmit trigger signals between at least two digital power supplies.

17. The parallel-operated digital power supply according to claim 16, wherein The third interface is the second pair of pins of the device. At least two digital power supplies include a first digital power supply and a second digital power supply. The execution priority of the first digital power supply is higher than that of the second digital power supply. The main control circuit of the first digital power supply is configured to send a trigger signal to the second digital power supply through the second pair of pins of the first digital power supply. The main control circuit of the second digital power supply is configured to receive external control parameters through the second interface of the second digital power supply in response to the trigger signal, and send a PWM wave to each power adjustable circuit corresponding to the second digital power supply through a first pair of pins of the main control device of the second digital power supply.

18. A method for adjusting the parallel operation of a digital power supply with adjustable power-on time interval and slope, characterized in that, Applied to the first digital power supply in the parallel digital power supplies described in any one of claims 16 to 17, wherein the execution priority of the first digital power supply is higher than that of the second digital power supply, the method includes: Obtain the first state of the first switch. Based on the first state, in response to the external control parameters received by the first interface, generate a first PWM wave corresponding to the power adjustable circuit. Based on the first PWM wave, control the on / off of the first MOS and the second MOS corresponding to the power adjustable circuit. Obtain the first working power supply. Based on the first working power supply, output electric energy at a determined power-on time interval and slope through the on / off of the first MOS and the second MOS. Send the external control parameters to the second digital power supply through the second interface, and send a trigger signal to the second digital power supply through the third interface.

19. A method for adjusting the parallel operation of a digital power supply with adjustable power-on time interval and slope, characterized in that, Applied to the second digital power supply in the parallel digital power supplies described in any one of claims 16 to 17, wherein the execution priority of the first digital power supply is higher than that of the second digital power supply, the method includes: Obtain the second state of the second switch. Based on the second state, in response to the trigger signal received by the third interface and the external control parameters received by the second interface, generate a second PWM wave corresponding to the power adjustable circuit. Based on the second PWM wave, control the on / off of the third MOS and the fourth MOS corresponding to the power adjustable circuit. Obtain the second working power supply. Based on the second working power supply, output electric energy at a determined power-on time interval and slope through the on / off of the third MOS and the fourth MOS.

20. A computer device, characterized in that, Includes: A memory and a processor, which are communicatively connected to each other. Computer instructions are stored in the memory, and the processor executes the computer instructions to execute the method described in any one of claims 9 to 15 or 18, 19.

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