Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, which comprises: providing a substrate; forming a trench within the substrate, where a lattice damage layer is present on a bottom surface of the trench; and using an ion beam etching process to remove the lattice damage layer on the bottom of the trench by means of a neutral particle beam. In the method for forming a semiconductor structure provided in the present invention, the lattice damage layer on the bottom surface of the trench is removed by means of an ion beam etching process, which facilitates the subsequent growth of a high quality epitaxial layer within the trench; and the neutral particles do not cause an additional loading effect, which facilitates improving the performance of the semiconductor device ultimately formed.

Description

Method for forming semiconductor structure

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 27, 2023, with application number 202311831141.3 and invention name “Method for Forming a Semiconductor Structure”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art

[0003] As semiconductor device integration continues to increase, process linewidths are shrinking, posing significant challenges to the etching process in order to maintain stable and reliable device performance. Currently, when using inductively coupled plasma (ICP) etching to form trenches in semiconductor substrates, the inherent characteristics of ICP etching, characterized by anisotropic etching dominated by charged particles and reactive free radicals, inevitably lead to plasma-induced damage during the trench etching process. This damage layer forms a lattice damage layer on the substrate's bottom surface, which can cause epitaxy and misalignment in the subsequent silicon germanium epitaxial layer growth, severely impacting device performance.

[0004] Current methods for improving trench lattice damage usually include further lowering the electron temperature to reduce damage, or using ashing processes, atomic-like etching processes, high-temperature annealing and other processes to repair etching damage, but they cannot achieve the effect of clearing lattice damage.

[0005] Therefore, there is an urgent need to provide a method for forming a semiconductor structure that can effectively improve and remove the lattice damage caused during the trench etching process.

[0006] Summary of the Invention

[0007] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which effectively removes the lattice damage layer formed during the trench etching process, is conducive to the subsequent growth of high-quality epitaxial layers, and improves the performance of semiconductor devices.

[0008] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a trench in the substrate, wherein the bottom surface of the trench has a lattice damage layer; and using an ion beam etching process to remove the lattice damage layer at the bottom of the trench with a neutral particle beam.

[0009] Optionally, the aspect ratio of the groove is less than 10:1.

[0010] Optionally, before forming the grooves in the substrate, the method further includes forming a mask layer on the surface of the substrate, and etching the substrate using the mask layer as a mask.

[0011] Optionally, the mask layer includes a bottom anti-reflective coating layer on the substrate, and a photoresist layer on a surface of the bottom anti-reflective coating layer.

[0012] Optionally, the mask layer includes an oxynitride oxide dielectric layer on the substrate, a bottom anti-reflective coating layer on the oxynitride oxide dielectric layer, and a photoresist layer on the bottom anti-reflective coating layer.

[0013] Optionally, when the lattice damaged layer is removed by an ion beam etching process, the angle between the incident direction of the ion beam and the normal to the substrate is 0° to 40°.

[0014] Optionally, the screen grid voltage of the ion beam etching process is 50V to 200V, the screen grid current is 0.05A to 0.5A, and the ion acceleration bias is 100ACV to 800ACV.

[0015] Optionally, in the ion beam etching process, the etching chamber pressure is 0.05 mT to 5 mT, the total gas flow rate is 10 sccm to 100 sccm, and the etching time is 30 s to 300 s.

[0016] Optionally, the etching gas of the ion beam etching process adopts one or more inert gases.

[0017] Optionally, the etching gas of the ion beam etching process is a mixed gas of an inert gas and a reactive gas, and the reactive gas is one or more of a fluorine-based gas and a chlorine-based gas.

[0018] Optionally, the inert gas includes one or more of Ar, Kr, Xe, Ne, and He.

[0019] Optionally, the fluorine-based gas includes C x F y , one or more of NF3, SF6, WF6, CHF3, CH2F2, wherein x and y are positive integers; the chlorine-based gas includes one or more of Cl2, BCl3, CCl4, SiCl4.

[0020] Optionally, after forming the trench, the method further includes forming an epitaxial layer in the trench.

[0021] Optionally, after forming the epitaxial layer, the method further includes etching the epitaxial layer to form a plurality of discretely arranged fins.

[0022] Optionally, the material of the epitaxial layer includes silicon germanium or silicon.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] After forming a groove in the substrate, this technical solution uses an ion beam etching process to remove the lattice damage layer on the bottom surface of the groove with neutral particles. While removing the lattice damage layer, the neutral particles will not cause additional loading effects, which is conducive to the subsequent growth of high-quality epitaxial layers, greatly reducing lattice defects, achieving high electrical performance of semiconductor devices, and helping to improve the stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] 1 to 7 are schematic structural diagrams of various steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0026] 8 to 13 are schematic structural diagrams of various steps of a method for forming a semiconductor structure in accordance with a second embodiment of the present invention. DETAILED DESCRIPTION

[0027] As described in the background technology, etching damage is inevitably formed in the process of forming grooves, and a lattice damage layer is formed on the bottom surface of the groove. The lattice damage layer will affect the growth of the epitaxial layer. However, the current method of reducing etching damage is not effective, and the lattice damage layer cannot be effectively removed, which affects the performance of the semiconductor structure finally formed.

[0028] To address the aforementioned issues, the present invention provides a method for forming a semiconductor structure, comprising providing a substrate; forming a trench within the substrate, wherein the bottom surface of the trench has a lattice damage layer; and then employing an ion beam etching process to remove the lattice damage layer from the bottom surface of the trench using neutral particles, thereby repairing the lattice damage at the bottom of the trench. The ion beam etching process utilizes the directional etching of ions and the etching of neutral particles in the ion beam etching process to remove the lattice damage layer at the bottom of the trench without causing additional loading effects, thereby facilitating the subsequent growth of high-quality epitaxial layers and improving the performance of the resulting semiconductor device.

[0029] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] First embodiment

[0031] 1 to 7 are schematic structural diagrams of various steps of a method for forming a semiconductor structure in a first embodiment of the present invention.

[0032] 1 , a substrate 100 is provided.

[0033] In this embodiment, the optional semiconductor substrate 100 includes materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0034] After the substrate 100 is formed, a trench is formed in the substrate 100 , and a lattice damage layer is formed on the bottom surface of the trench.

[0035] The aspect ratio of the trench formed in the substrate 100 is less than 10:1.

[0036] Before forming the grooves in the substrate 100 , a mask layer is formed on the surface of the substrate 100 , and the substrate 100 is etched using the mask layer as a mask.

[0037] Alternatively, the mask layer may be a multi-layer structure or a hard mask structure.

[0038] When the mask layer is a multi-layer structure, it mainly includes a bottom anti-reflective coating located on the substrate 100 and a photoresist layer located on the surface of the bottom anti-reflective coating; when the mask layer is a hard mask structure, it mainly includes an oxygen-nitrogen-oxygen dielectric layer located on the substrate, a bottom anti-reflective coating located on the oxygen-nitrogen-oxygen dielectric layer, and a photoresist layer located on the bottom anti-reflective coating.

[0039] Referring to Figure 2, in this embodiment, the mask layer is a hard mask structure, and the mask layer includes an oxide layer 101 located on the surface of the substrate 100, a silicon nitride layer 102 located on the surface of the oxide layer 101, an organic dielectric layer 103 located on the surface of the silicon nitride layer 102, a bottom anti-reflective coating layer 104 located on the surface of the organic dielectric layer 103, and a photoresist layer 105 located on the surface of the bottom anti-reflective coating layer 104.

[0040] In this embodiment, the photoresist layer 105 has a pattern thereon, and the pattern is used to define the size and position of the trench to be formed.

[0041] In other embodiments, when the mask layer is a hard mask structure, the mask layer may also be an oxide layer located on the surface of the substrate 100, a silicon nitride layer located on the surface of the oxide layer, an ethyl silicate layer located on the surface of the silicon nitride, a spin-on carbon layer located on the surface of the ethyl silicate layer, a bottom anti-reflective coating layer located on the surface of the spin-on carbon layer, and a photoresist layer located on the surface of the bottom anti-reflective coating layer; or the mask layer includes a silicon nitride layer located on the surface of the substrate 100, an oxide layer located on the surface of the silicon nitride, a spin-on carbon layer located on the surface of the oxide layer, a dielectric anti-reflective coating layer located on the surface of the spin-on carbon layer, and a photoresist layer located on the surface of the dielectric anti-reflective coating layer.

[0042] In other embodiments, when the mask layer has a multi-layer structure, the mask layer includes an oxide layer located on the surface of the substrate 100, an organic dielectric layer located on the surface of the oxide layer, a bottom anti-reflective coating layer located on the surface of the organic dielectric layer, and a photoresist layer located on the surface of the bottom anti-reflective coating layer; or the mask layer includes an oxide layer located on the surface of the substrate 100, a spin-on carbon layer located on the surface of the oxide layer, a dielectric anti-reflective coating layer located on the surface of the spin-on carbon layer, and a photoresist layer located on the surface of the dielectric anti-reflective coating layer.

[0043] 3 , using the photoresist layer 105 as a mask, the bottom anti-reflective coating 104, the organic dielectric layer 103, the silicon nitride layer 102, the oxide layer 101 and the substrate 100 are sequentially etched to form a groove 106 in the substrate 100, and the photoresist layer 105, the bottom anti-reflective layer 104 and the organic dielectric layer 103 are removed.

[0044] In this embodiment, an inductively coupled plasma (ICP) etching process is used to etch the substrate 100 to form a trench 106 in the substrate 100 .

[0045] Inductively coupled plasma etching (ICP) is a commonly used dry etching technology in the semiconductor field. Due to the inherent characteristics of ICP etching technology, anisotropic etching dominated by charged particles and active free radicals, plasma-induced damage is inevitable during the trench etching process, including plasma damage and plasma-induced damage. The lattice damage layer formed on the bottom surface of the trench by ICP etching will have an adverse effect on the growth of the subsequent epitaxial layer and affect the performance of the semiconductor device. Therefore, the lattice damage layer caused by the ICP etching process needs to be removed later.

[0046] Optionally, during the ICP etching process to etch the substrate 100 to form the groove 106, the source power range is 100W to 800W, and the bias electrode power is 50W to 500W; the etching gas adopts a mixture of fluorine-based gas and auxiliary gas, wherein the fluorine-based gas includes one or more of CF4, CHF3, CH2F2, SF6, NF3, C2F6, C3F8, C2HF5, and the auxiliary gas includes one or more of Ar, N2, O2, He, and CH4.

[0047] Optionally, the etching chamber pressure of the ICP etching process is 2 mT to 20 mT, the total gas flow rate is 100 sccm to 1000 sccm, and the etching temperature is 20° C. to 80° C.

[0048] In this embodiment, the source power used in the ICP etching process is 300W, and the bias electrode power is 200W; the etching gas is a combination of fluorine-based gases such as CHF3, SF6, NF3 and auxiliary gases such as Ar and N2; the etching chamber pressure is 5mT, the gas flow rate is 500sccm, and the reaction temperature is 40°C.

[0049] In this embodiment, the aspect ratio of the trench 106 formed in the substrate 100 is less than 5:1.

[0050] As shown in FIG. 3 , after the trench 106 is formed by ICP etching, a lattice damage layer 107 is formed on the bottom surface of the trench 106 .

[0051] 4 and 5 , in order to remove the lattice damage layer 107 , an ion beam etching process is used to remove the lattice damage layer 107 at the bottom of the trench 106 using a neutral particle beam.

[0052] The arrows in FIG4 represent the incident direction of the neutral particle beam.

[0053] Optionally, when an ion beam etching process is used to remove the lattice damage layer 107, the angle between the incident direction of the ion beam and the normal of the substrate 100 is 0° to 40°. The ion beam has a certain incident angle to achieve angled directional etching of the lattice damage layer 107, thereby improving process flexibility. The incident angle of the ion beam can be adjusted according to the structure and size of the device. The range of the incident angle is between 0° and 40°. A smaller incident angle can ensure a steeper etching morphology of the ion beam and avoid the existence of etching dead corners.

[0054] In this embodiment, the incident angle of the ion beam is 10°, which is more conducive to the ion beam directly hitting the lattice damage layer 107 at the bottom of the trench 106, thereby removing the lattice damage layer 107.

[0055] Optionally, the screen grid voltage of the ion beam etching process is 50V to 200V, the screen grid current is 0.05A to 0.5A, and the ion acceleration bias is 100ACV to 800ACV. The larger the screen grid voltage, the greater the impact energy of the ion beam on the etching target and the higher the etching efficiency. However, if the screen grid voltage is too large, new lattice damage will be introduced during the etching process. Therefore, the screen grid voltage is controlled within the range of 50V to 200V. The larger the screen grid current, the more ions there are and the higher the etching efficiency. However, the larger the screen grid current, the more ions there are, which will increase the mutual collision and scattering between the ion beams, thereby affecting the etching efficiency. Therefore, the screen grid current is controlled within the range of 0.05A to 0.5A. The ion acceleration bias also affects the ion energy. If the ion energy is too high, new lattice damage is likely to be introduced during the removal of the lattice damage layer 107. If the ion energy is too low, the lattice damage layer may not be removed well. Therefore, the ion acceleration bias is controlled within the range of 100ACV to 800ACV. The above parameter settings are appropriately conducive to the removal of the lattice damage layer 107 without introducing new lattice damage.

[0056] In this embodiment, the screen grid voltage used is 200V, the screen grid current is 0.2A, and the ion acceleration bias voltage is 400ACV.

[0057] Optionally, the ion beam etching process has an etching chamber pressure range of 0.05mT to 5mT, a total gas flow rate of 10sccm to 100sccm, and an etching time of 30s to 300s. The etching chamber pressure is related to the free path of the particles. Low chamber pressure is beneficial for increasing the molecular free path, improving directionality, and improving ion alignment. Gas pressure also has a significant impact on uniformity. Higher chamber pressure results in better uniformity, enabling more uniform process modifications. In addition, during the etching process, there is an obvious relationship between the ion beam etching rate and the total flow rate of the etching gas. As the total gas flow rate range increases, the etching rate first increases. After reaching the maximum value, the etching rate decreases slightly at a larger flow rate. This is because, under low flow conditions, the etching rate is limited by the supply of active substances, while under high flow conditions, it is limited by the extraction of active substances. Therefore, the total flow rate of the etching gas cannot be too large or too small. At the same time, the etching time cannot be too short. If it is too short, the etching effect will be poor, and the surface quality of the subsequently formed grooves will be poor. The etching time cannot be too long either. If it is too long, over-etching will occur, and the quality of the formed grooves will also be poor.

[0058] In this embodiment, the chamber pressure used in the etching process is 0.5 mT, the total gas flow rate is 40 sccm, and the etching time is controlled at about 100 s.

[0059] Optionally, when the lattice damage layer 107 is removed by an ion beam etching process, it can be performed based on two etching technologies: IBE (ion beam etching) or RIBE (reactive ion beam etching). IBE etching is a physical etching with strong directional plasma, and the etching gas uses one or more of inert gases; RIBE etching is an etching technology with chemical reaction functions and physical bombardment functions, and the etching gas uses a mixture of inert gas and reactive gas, and the reactive gas uses one or more of fluorine-based gas and / or chlorine-based gas.

[0060] Optionally, the inert gas includes one or more of Ar, Kr, Xe, Ne, and He; the fluorine-based gas includes C x F y , one or more of NF3, SF6, WF6, CHF3, CH2F2, wherein x and y are positive integers; chlorine-based gases include one or more of Cl2, BCl3, CCl4, SiCl4.

[0061] In this embodiment, the ion beam etching process is performed based on the IBE etching technology, and inert gas Ar is used as the etching gas.

[0062] An ion beam etching process is adopted to bombard the lattice damage layer 107 with a neutral ion beam with a certain energy. By adjusting parameters such as the energy, angle and etching gas of the ion beam, the motion trajectory of the colliding particles can be controlled, which can directly act on the lattice damage layer 107 at the bottom of the groove 106. Combined with interaction mechanisms such as sputtering, scattering and chemical reaction, the lattice damage layer 107 can be removed. At the same time, because a neutral particle beam is used for etching and repair, no additional load effect will be caused, and the lattice damage layer 107 can be effectively removed, which is beneficial to improving the quality of the epitaxial layer formed subsequently, achieving a high electrical surface of the semiconductor device, and improving the stability of the device.

[0063] 6 , after the lattice damaged layer 107 is removed, an epitaxial layer 108 is formed in the trench 106 .

[0064] Optionally, the epitaxial layer 108 is made of silicon germanium or silicon.

[0065] In this embodiment, the epitaxial layer 108 is made of silicon germanium.

[0066] In this embodiment, the epitaxial layer 108 is formed in the trench 106 by epitaxial growth.

[0067] 7 , after forming the epitaxial layer 108 , the epitaxial layer 108 is further etched to form a plurality of discretely arranged fins 109 .

[0068] In this embodiment, the epitaxial layer 108 is etched using an ICP etching process.

[0069] Second embodiment

[0070] 8 to 13 are schematic structural diagrams of various steps of a method for forming a semiconductor structure in accordance with a second embodiment of the present invention.

[0071] The difference between this embodiment and the first embodiment lies in the different structure of the mask layer formed on the substrate 100 . Therefore, different process parameters are used when etching the mask layer to form the trench and removing the lattice damage layer on the bottom surface of the trench.

[0072] 8 , in this embodiment, the mask layer includes an oxide layer 201 located on the surface of the substrate 100, a silicon nitride layer 202 located on the surface of the oxide layer 201, an ethyl silicate layer 203 located on the surface of the silicon nitride layer 202, a spin-on carbon layer 204 located on the surface of the ethyl silicate layer 203, a bottom anti-reflective coating layer 205 located on the surface of the spin-on carbon layer 204, and a photoresist layer 206 located on the surface of the bottom anti-reflective coating layer 205.

[0073] 9 , using the photoresist layer 206 as a mask, the bottom anti-reflective coating 205, the spin-on carbon layer 204, the ethyl silicate layer 203, the silicon nitride layer 202, the oxide layer 201 and the substrate 100 are sequentially etched to form a groove 207 in the substrate 100, and the bottom anti-reflective coating 205, the spin-on carbon layer 204 and the ethyl silicate layer 203 are removed.

[0074] In this embodiment, an inductively coupled plasma (ICP) etching process is used to etch the substrate 100 to form a trench 207 in the substrate 100 .

[0075] In this embodiment, the aspect ratio of the formed trench 207 is less than 5:1.

[0076] In this embodiment, the source power used in the ICP etching process is 600W, and the bias electrode power is 200W; the etching gas is a combination of fluorine-based gases such as CF4, CHF3, SF6 and auxiliary gases such as Ar and He; the etching chamber pressure is 10mT, the gas flow rate is 300sccm, and the reaction temperature is 60°C.

[0077] As shown in FIG. 9 , after the trench 207 is formed by ICP etching, a lattice damage layer 208 is formed on the bottom surface of the trench 207 .

[0078] 10 and 11 , an ion beam etching process is used to remove the lattice damaged layer 208 at the bottom of the trench 207 using a neutral particle beam.

[0079] The arrows in FIG10 represent the incident direction of the neutral particle beam.

[0080] In this embodiment, the incident angle of the ion beam is 5°, which is more conducive to the ion beam directly hitting the lattice damage layer 208 at the bottom of the groove 207, thereby removing the lattice damage layer 208.

[0081] In this embodiment, the screen grid voltage used is 100 V, the screen grid current is 0.1 A, and the ion acceleration bias voltage is 200 ACV.

[0082] In this embodiment, the chamber pressure used in the etching process is 2 mT, and the total gas flow rate is 60 sccm. The low chamber pressure is beneficial to improving the collimation of the incident ions, and can accurately strike the lattice damage layer 208.

[0083] In this embodiment, the ion beam etching process is performed based on RIBE etching technology, using a mixture of inert gas Ar and reactive gas CF4 as etching gas, and the etching time is controlled at about 50s, which can achieve complete removal of the lattice damage layer 208 and avoid excessive etching amount.

[0084] 12 , after the lattice damaged layer 208 is removed, an epitaxial layer 209 is formed in the trench 207 .

[0085] Optionally, the epitaxial layer 209 is made of silicon germanium or silicon.

[0086] In this embodiment, the epitaxial layer 209 is made of silicon germanium.

[0087] In this embodiment, the epitaxial layer 209 is formed in the trench 207 by epitaxial growth.

[0088] 13 , after forming the epitaxial layer 209 , the epitaxial layer 209 is further etched to form a plurality of discretely arranged fins 210 .

[0089] In this embodiment, the epitaxial layer 209 is etched using an ICP etching process.

[0090] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a trench in the substrate, the bottom surface of the trench having a lattice damage layer; Adopting an ion beam etching process to remove the lattice damage layer at the bottom of the trench with a neutral particle beam.

2. The method for forming a semiconductor structure as claimed in claim 1, wherein The aspect ratio of the trench is less than 10:

1.

3. The method for forming a semiconductor structure according to claim 1, wherein, Before forming the trench in the substrate, it further includes forming a mask layer on the surface of the substrate and etching the substrate using the mask layer as a mask.

4. The method for forming a semiconductor structure according to claim 3, wherein The mask layer includes a bottom anti-reflection coating on the substrate and a photoresist layer on the bottom anti-reflection coating.

5. The method for forming a semiconductor structure according to claim 3, wherein The mask layer includes an oxynitride oxide dielectric layer on the substrate, a bottom anti-reflection coating on the oxynitride oxide dielectric layer, and a photoresist layer on the bottom anti-reflection coating.

6. The method for forming a semiconductor structure according to claim 1, wherein, When using the ion beam etching process to remove the lattice damage layer, the angle between the incident direction of the ion beam and the normal of the substrate is 0° to 40°.

7. The method for forming a semiconductor structure according to claim 1, wherein The screen grid voltage of the ion beam etching process is 50V to 200V, the screen grid current is 0.05A to 0.5A, and the ion acceleration bias voltage is 100ACV to 800ACV.

8. The method for forming a semiconductor structure according to claim 1, wherein, The pressure in the etching chamber of the ion beam etching process is 0.05mT to 5mT, the total gas flow rate is 10sccm to 100sccm, and the etching time is 30s to 300s.

9. The method for forming a semiconductor structure according to claim 1, wherein, The etching gas of the ion beam etching process uses one or more of inert gases.

10. The method for forming a semiconductor structure according to claim 1, wherein, The etching gas of the ion beam etching process uses a mixed gas of an inert gas and a reactive gas, and the reactive gas uses one or more of fluorine-based gases and chlorine-based gases.

11. The method for forming a semiconductor structure as described in claim 10, wherein, The fluorine-based gas includes C x F y , one or more of NF3, SF6, WF6, CHF3, CH2F2, where x and y are positive integers; the chlorine-based gas includes one or more of Cl2, BCl3, CCl4, SiCl4.

12. The method for forming a semiconductor structure according to claim 1, wherein, After forming the trench, it further includes forming an epitaxial layer in the trench.

13. The method for forming a semiconductor structure according to claim 12, wherein After forming the epitaxial layer, it further includes etching the epitaxial layer to form a plurality of fin portions arranged discretely.

14. The method for forming a semiconductor structure according to claim 12, wherein, The material of the epitaxial layer includes germanium silicon, silicon.

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