Semiconductor structure and manufacturing method therefor

Abstract

The present application relates to a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises a substrate (1), a buried dielectric layer (2), a lateral power device (3), a longitudinal power device (4), and an isolation structure (5). The buried dielectric layer (2) is provided in the substrate, and comprises a first portion having a gradient thickness, and an opening (21) is formed in the buried dielectric layer (2). The lateral power device is provided above the first portion (22) of the buried dielectric layer, and comprises a source region (31) and a drain region (32) spaced apart in a direction parallel to the substrate (1). The longitudinal power device (4) comprises a well region (41), a drift region (42), a source region (43), and a drain region (44); the well region (41) is located in the substrate (1) above the opening (21) of the buried dielectric layer (2); the source region (43) is located in the well region (41), the drift region (42) passes through the opening (21) of the buried dielectric layer (2) and the well region (41), and comprises a region of the substrate (1) located below the buried dielectric layer (2); and the drain region (44) is located at the bottom of the drift region (42). The isolation structure (5) is located in the substrate (1) between the lateral power device (3) and the longitudinal power device (4), and has the bottom connected to the buried dielectric layer (2). The present application can expand the application of SOI high voltage integrated circuits.

Description

Semiconductor structure and method for manufacturing the same

[0001] Related applications

[0002] This application claims priority to Chinese patent application number 202311834914.3, filed on December 27, 2023, entitled “Semiconductor Structure and Method for Manufacturing the Same,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure, and also to a method for manufacturing a semiconductor structure. Background Art

[0004] Bipolar-CMOS-DMOS (BCD) technology is a monolithic integration process that enables the fabrication of bipolar transistors (bipolar), metal-oxide semiconductor field-effect transistors (CMOS), and double-diffused metal-oxide semiconductor field-effect transistors (DMOS) on the same chip. Devices fabricated using this process combine the advantages of bipolar devices, such as high transconductance and strong load-driving capability, with the high integration density and low power consumption of CMOS devices. Furthermore, as power devices, DMOS devices can handle higher voltages and consume very low power when operating in switching mode, enabling them to deliver high power to the load without the need for expensive packaging and cooling systems. This technology has been widely used in automotive electronics, power management, lighting, and radio frequency communications. The DMOS device, responsible for the power supply, is the core of these circuits. Because it must carry relatively high currents and voltages, it often occupies 30%-90% of the total integrated circuit area, making it crucial for the entire integrated circuit. However, related technologies only allow the integration of power devices for one voltage range on a single chip, which can significantly limit the application of SOI high-voltage integrated circuits.

[0005] Summary of the Invention

[0006] Based on this, it is necessary to provide a semiconductor structure and a manufacturing method thereof.

[0007] In some embodiments of the present application, a semiconductor structure includes: a substrate, a buried dielectric layer, a lateral power device, a vertical power device, and an isolation structure. The buried dielectric layer is disposed in the substrate, includes a first portion having a gradient thickness, and has an opening. The lateral power device is disposed above the first portion of the buried dielectric layer, includes a source region and a drain region spaced apart in a direction parallel to the substrate. The vertical power device includes: a well region, a drift region, a source region, and a drain region; wherein the well region is located in the substrate above the opening of the buried dielectric layer; the source region is located in the well region; the drift region passes through the opening and the well region of the buried dielectric layer, and includes a region where the substrate is located below the buried dielectric layer; and the drain region is located at the bottom of the drift region. The isolation structure is located in the substrate between the lateral power device and the vertical power device, and the bottom of the isolation structure is connected to the buried dielectric layer.

[0008] In one embodiment, the isolation structure includes an isolation barrier wall having a bottom portion connected to the buried dielectric layer.

[0009] In another embodiment, the isolation structure includes: a first isolation barrier wall and a second isolation barrier wall connected to the buried dielectric layer at the bottom and spaced apart in a direction parallel to the substrate, and a depletion region located between the first isolation barrier wall and the second isolation barrier wall.

[0010] In one embodiment, the first portion includes: a first sub-portion directly opposite to the drain region of the lateral power device, and a second sub-portion directly opposite to the source region of the lateral power device; the minimum thickness of the first sub-portion is greater than the maximum thickness of the second sub-portion.

[0011] In one embodiment, the upper surface of the buried dielectric layer is parallel to the surface of the substrate. The lower surface of the first portion is an inclined surface, which includes an inclined plane or an inclined curved surface.

[0012] In one embodiment, the buried dielectric layer further includes a second portion, the thickness of the second portion being less than or equal to the minimum thickness of the first portion; and the semiconductor structure further includes a non-power device disposed above the second portion of the buried dielectric layer.

[0013] In one embodiment, the non-power device is located on a side of the lateral power device away from the vertical power device. The isolation structure includes: a first isolation structure located between the lateral power device and the vertical power device, and a second isolation structure located between the lateral power device and the non-power device.

[0014] In another embodiment, the non-power device is located between the lateral power device and the vertical power device. The isolation structure includes: a third isolation structure located between the non-power device and the vertical power device, and a fourth isolation structure located between the non-power device and the lateral power device.

[0015] In some embodiments of the present application, a method for manufacturing a semiconductor structure includes:

[0016] Providing a substrate, and forming a hard mask layer on the substrate; the hard mask layer includes a first thickness film layer and a second thickness film layer arranged in the same layer, wherein the first thickness film layer has a gradient thickness, and the thickness of the second thickness film layer is greater than the maximum thickness of the first thickness film layer;

[0017] Ion implantation is performed on the substrate based on the hard mask layer to form a buried dielectric layer in the substrate. The buried dielectric layer includes a first portion having a gradient thickness and an opening; wherein the first portion is formed based on a film layer of a first thickness and the opening is formed based on a film layer of a second thickness;

[0018] removing the hard mask layer;

[0019] forming an isolation structure, wherein the bottom of the isolation structure is connected to the buried dielectric layer and separates a plurality of active areas;

[0020] forming a lateral power device, the lateral power device being located in the active area and above the first portion of the buried dielectric layer, and including a source region and a drain region spaced apart in a direction parallel to the substrate;

[0021] A vertical power device is formed, which includes: a well region, a drift region, a source region and a drain region; wherein the well region is located in the active region above the opening of the buried dielectric layer; the source region is located in the well region; the drift region passes through the opening of the buried dielectric layer and the well region, and includes an area where the substrate is located below the buried dielectric layer; and the drain region is located at the bottom of the drift region.

[0022] In one embodiment, forming the isolation structure includes: forming a trench in the substrate above the buried dielectric layer, wherein the trench separates the substrate into a plurality of active areas; and forming an isolation barrier in the trench to obtain the isolation structure.

[0023] In another embodiment, the formation of the isolation structure includes: forming a trench in the substrate above the buried dielectric layer, the trench separating the substrate into multiple active regions and at least one depletion region; forming an isolation barrier in the trench; wherein the lateral power device and the vertical power device are respectively located on both sides of the depletion region along a direction parallel to the substrate; the depletion region and the isolation barriers on both sides thereof constitute an isolation structure.

[0024] In one embodiment, forming a hard mask layer on the substrate includes:

[0025] forming a hard mask material layer on the substrate;

[0026] forming a first photoresist layer having a first opening pattern on the hard mask material layer;

[0027] Based on the first opening pattern, the hard mask material layer is etched to obtain an initial hard mask layer; the initial hard mask layer has a second thickness film layer and an initial third thickness film layer, wherein the thickness of the initial third thickness film layer is less than the thickness of the second thickness film layer and is greater than or equal to the maximum thickness of the first thickness film layer;

[0028] removing the first photoresist layer;

[0029] forming a second photoresist layer having a second opening pattern on the initial hard mask layer; the second opening pattern exposing a portion of the initial third thickness film layer;

[0030] Based on the second opening pattern, wet etching is performed on the initial hard mask layer to obtain a hard mask layer; the hard mask layer includes: a first thickness film layer, a second thickness film layer and a third thickness film layer;

[0031] The second photoresist layer is removed.

[0032] In one embodiment, the substrate is a silicon wafer. Ion implantation is performed on the substrate based on a hard mask layer to form a buried dielectric layer in the substrate, including: implanting oxygen ions into the substrate based on the hard mask layer; and performing a high temperature treatment on the substrate after oxygen ion implantation to form the buried dielectric layer.

[0033] In one embodiment, the buried dielectric layer further includes a second portion, and a thickness of the second portion is less than or equal to a minimum thickness of the first portion.

[0034] In one embodiment, the method for manufacturing a semiconductor structure further includes: forming a non-power device in an active area of ​​the lateral power device away from the vertical power device, or forming a non-power device in an active area between the lateral power device and the vertical power device; wherein the non-power device is located above the second portion of the buried dielectric layer.

[0035] In the above-mentioned semiconductor structure and its manufacturing method, by providing a buried dielectric layer in the substrate and making the buried dielectric layer include a first portion with a gradient thickness and an opening, a lateral power device can be formed above the first portion of the buried dielectric layer, and a vertical power device can be formed based on the opening of the buried dielectric layer, thereby enabling the integration of different power devices in the same semiconductor structure. Moreover, the embodiment of the present application can utilize the substrate above and below the buried dielectric layer to jointly constitute the drift region of the vertical power device through the opening of the buried dielectric layer, so as to further improve the voltage resistance characteristics of the vertical power device. The embodiment of the present application can also take into account the requirements of the lateral power device for voltage resistance characteristics and heat dissipation characteristics by providing the first portion with a gradient thickness in the buried dielectric layer, so as to further improve the reliability of the lateral power device. The embodiment of the present application can also effectively achieve complete isolation between the lateral power device and the vertical power device based on the SOI process by providing an isolation structure provided in the substrate between the lateral power device and the vertical power device and connected to the buried dielectric layer at the bottom, so as to further improve the reliability of the semiconductor structure.

[0036] As described above, the semiconductor structure and its manufacturing method can effectively improve the device performance and reliability of the semiconductor structure, thereby expanding the application of SOI high-voltage integrated circuits. In addition, the manufacturing method provided in this application is simple and easy to implement, which is conducive to improving production efficiency and yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings described below are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be derived from these drawings without inventive effort.

[0038] FIG1 is a schematic cross-sectional view of a semiconductor structure in some embodiments of the present application.

[0039] FIG2 is a schematic cross-sectional view of a semiconductor structure in some other embodiments of the present application.

[0040] FIG3 is a schematic cross-sectional view of an inclined surface in a buried dielectric layer in some embodiments of the present application.

[0041] FIG4 is a schematic cross-sectional view of the structure obtained at each step in the epitaxial layer formation process in some embodiments of the present application.

[0042] FIG5 is a flow chart of a method for manufacturing a semiconductor structure in some embodiments of the present application.

[0043] FIG6 is a flowchart of step S100 in some embodiments of the present application.

[0044] FIG7 is a flowchart of step S200 in some embodiments of the present application.

[0045] FIG8 is a flowchart of step S400 in some embodiments of the present application.

[0046] FIG9 is a flowchart of step S400 in some other embodiments of the present application.

[0047] FIG10 is a schematic cross-sectional view of a structure obtained after forming a first photoresist layer in some embodiments of the present application.

[0048] FIG11 is a schematic cross-sectional view of a structure obtained after forming a second photoresist layer in some embodiments of the present application.

[0049] FIG12 is a schematic cross-sectional view of a structure obtained after forming a hard mask layer in some embodiments of the present application.

[0050] FIG13 is a schematic cross-sectional view of a structure obtained after forming a buried dielectric layer in some embodiments of the present application.

[0051] FIG14 is a schematic cross-sectional view of a structure obtained after removing the hard mask layer in some embodiments of the present application.

[0052] FIG15 is a schematic cross-sectional view of a structure obtained after forming an isolation structure in some embodiments of the present application. DETAILED DESCRIPTION

[0053] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide some embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0055] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. In this specification, "connected" should be understood as "electrically connected," "communicatively connected," etc., if the connected circuits, modules, units, etc. have electrical signals or data transmission with each other. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0056] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0057] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an" and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" means one or more, and "a plurality" means two or more. "At least a portion of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0058] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the present application.

[0059] The semiconductor field terms used in this article are technical terms commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0060] The embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which can realize the integration of different power devices in the same semiconductor structure to expand the application of SOI high-voltage integrated circuits.

[0061] Referring to Figures 1 and 2, in some embodiments of the present application, a semiconductor structure includes: a substrate 1, a buried dielectric layer 2, a lateral power device 3, a vertical power device 4, and an isolation structure 5. The buried dielectric layer 2 is disposed within the substrate 1 and includes: a first portion 22 having a gradient thickness and an opening 21. The lateral power device 3 is disposed above the first portion 22 of the buried dielectric layer 2 and includes a source region 31 and a drain region 32 spaced apart in a direction parallel to the substrate 1. The vertical power device 4 includes: a well region 41, a drift region 42, a source region 43, and a drain region 44. The well region 41 is located within the substrate 1 above the opening 21 of the buried dielectric layer 2; the source region 43 is located within the well region 41; the drift region 42 extends through the opening 21 and the well region 41 of the buried dielectric layer 2 and includes the region of the substrate 1 below the buried dielectric layer 2; and the drain region 44 is located at the bottom of the drift region 42. The isolation structure 5 is located in the substrate 1 between the lateral power device 3 and the vertical power device 4 , and its bottom is connected to the buried dielectric layer 2 .

[0062] For example, substrate 1 has a first conductivity type, such as a P-type silicon substrate or an N-type silicon substrate. Buried dielectric layer 2 is a buried oxide layer, and its material may be silicon oxide, such as silicon dioxide. In one embodiment of the present application, the minimum thickness of buried dielectric layer 2 may range from 1 micron to 8 microns.

[0063] In some embodiments, the first portion 22 of the buried dielectric layer 2 has a gradient thickness, which means that the thickness of each longitudinal section of the first portion 22 along a direction perpendicular to the substrate 1 can gradually change along a direction parallel to the substrate 1, for example, it can present an equal incremental change or an equal proportional change.

[0064] In some embodiments, please continue to refer to Figures 1 and 2. The first portion 22 of the buried dielectric layer 2 includes: a first sub-portion 221 facing the drain region 32 of the lateral power device 3, and a second sub-portion 222 facing the source region 31 of the lateral power device 3; the minimum thickness of the first sub-portion 221 is greater than the maximum thickness of the second sub-portion 222.

[0065] In some embodiments, as shown in Figures 1 and 2, the upper surface of the buried dielectric layer 2 is parallel to the surface of the substrate 1. The lower surface of the first portion 22 is an inclined surface, which may include an inclined plane or an inclined curved surface. The inclined curved surface may include, for example, a convex inclined surface or a concave inclined surface. Figure 3 shows the inclined plane S1 in (a), the convex inclined surface S2 in (b), and the concave inclined surface S3 in (c).

[0066] For example, the lateral power device 3 includes, but is not limited to, a lateral double-diffused MOSFET (LDMOS) device. FIG. 1 and FIG. 2 illustrate the lateral power device 3 as an LDMOS device.

[0067] Continuing to refer to FIG. 1 and FIG. 2 , for example, in an LDMOS device, a drift region 33 and a well region 34 are formed in the substrate 1 above the first portion 22 of the buried dielectric layer 2. The drain region 32 can be formed in the drift region 33, and the source region 31 can be formed in the well region 34. Furthermore, the drift region 33 and the well region 34 have different conductivity types, and the conductivity types of the drain region 32 and the source region 31 are different from the conductivity type of the well region 34.

[0068] In some examples, as shown in FIG1 and FIG2 , in an LDMOS device, the drift region 33, the drain region 32, and the source region 31 are all N-type doped regions, and the well region 34 is a P-type doped region. The ion doping concentrations of the drain region 32 and the source region 31 are greater than the ion doping concentration of the drift region 33.

[0069] Continuing to refer to Figures 1 and 2, by way of example, the LDMOS device further includes a gate structure 35. The gate structure 35 may be formed above the substrate 1. The orthographic projection of the gate structure 35 on the substrate 1 may be located within the space between the source region 31 and the drain region 32. Alternatively, the gate structure 35 may not only be located within the space between the source region 31 and the drain region 32, but may also partially overlap with at least one of the source region 31 and the drain region 32.

[0070] For example, the vertical power device 4 includes, but is not limited to, a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS) device. For example, the vertical power device 4 may also be an insulated gate bipolar transistor (IGBT) device or a shielded gate trench (SGT) device. FIG. 1 and FIG. 2 illustrate the vertical power device 4 as a VDMOS device.

[0071] Continuing with Figures 1 and 2 , for example, in a VDMOS device, the drain region 44 and source region 43 are spaced apart in a direction perpendicular to the substrate 1 , and the two source regions 43 can be spaced apart in a direction parallel to the substrate 1 and located on either side of the portion of the drift region 42 that penetrates the well region 41 . The VDMOS device also includes a gate structure 45 formed above the substrate 1 . The gate structure 45 can cover the drift region 42, a portion of the well region 41, and a portion of the source region 43 . In some embodiments, the gate structure 45 of the VDMOS device can also be configured as a trench gate structure.

[0072] In the embodiment of the present application, by providing a buried dielectric layer 2 in the substrate 1, and making the buried dielectric layer 2 include a first portion 22 with a gradient thickness and an opening 21, a lateral power device 3 can be formed above the first portion 22 of the buried dielectric layer 2, and a vertical power device 4 can be formed based on the opening 21 of the buried dielectric layer 2, thereby enabling the integration of different power devices in the same semiconductor structure (for example, the same chip). In addition, in the embodiment of the present application, through the opening 21 of the buried dielectric layer 2, the substrate 1 above and below the buried dielectric layer 2 can be used to jointly form the drift region 42 of the vertical power device 4, so as to further improve the withstand voltage characteristics of the vertical power device 4. In the embodiment of the present application, by having the first portion 22 with a gradient thickness in the buried dielectric layer 2, the requirements of the lateral power device 3 for withstand voltage characteristics and heat dissipation characteristics can also be taken into account at the same time, so as to further improve the reliability of the lateral power device 3. In the embodiment of the present application, an isolation structure 5 is arranged in the substrate 1 between the lateral power device 3 and the vertical power device 4 and is connected to the buried dielectric layer 2 at the bottom. It is also possible to effectively achieve complete isolation between the lateral power device 3 and the vertical power device 4 based on the SOI process, so as to further improve the reliability of the semiconductor structure.

[0073] As described above, the embodiments of the present application can effectively improve the device performance and reliability of the semiconductor structure, so as to expand the application of SOI high-voltage integrated circuits.

[0074] 1 and 2 , in some embodiments, the buried dielectric layer 2 further includes a second portion 23 having a thickness less than or equal to the minimum thickness of the first portion 22 . The semiconductor structure further includes a non-power device 6 . The non-power device 6 is disposed above the second portion 23 of the buried dielectric layer 2 .

[0075] For example, the non-power device 6 includes, but is not limited to, a complementary metal oxide semiconductor field effect transistor (CMOS) device. FIG1 and FIG2 illustrate the non-power device 6 as a CMOS device as an example.

[0076] For example, as shown in Figures 1 and 2, in a CMOS device, a well region 61 can be formed on top of the substrate 1 above the second portion 23 of the buried dielectric layer 2, and a source region 62 and a drain region 63 are located in the same well region 61 and spaced apart in a direction parallel to the substrate 1. The CMOS device also includes a gate structure 64 formed above the substrate 1.

[0077] In some embodiments, as shown in FIG. 1 , the non-power device 6 is located on a side of the lateral power device 3 away from the vertical power device 4 .

[0078] In other embodiments, as shown in FIG. 2 , the non-power device 6 is located between the lateral power device 3 and the vertical power device 4 .

[0079] In some embodiments, as shown in FIG. 1 , the isolation structure 5 includes a first isolation structure 51 located between the lateral power device 3 and the vertical power device 4 , and a second isolation structure 52 located between the lateral power device 3 and the non-power device 6 .

[0080] In other embodiments, as shown in FIG. 2 , the isolation structure 5 includes: a third isolation structure 53 located between the non-power device 6 and the vertical power device 4 , and a fourth isolation structure 54 located between the non-power device 6 and the lateral power device 3 .

[0081] For example, the first isolation structure 51 includes a first isolation barrier 511 and a second isolation barrier 512, each connected to the buried dielectric layer 2 and spaced apart in a direction parallel to the substrate 1, and a depletion region 513 located between the first isolation barrier 511 and the second isolation barrier 512. The depletion region 513 has a different conductivity type than the substrate 1. The depletion region 513 can prevent the electric field lines of the lateral power device 3 and the vertical power device 4 from interfering with each other.

[0082] Illustratively, the second isolation structure 52 includes an isolation barrier wall whose bottom is connected to the buried dielectric layer 2 .

[0083] For example, the third isolation structure 53 and the fourth isolation structure 54 both include an isolation barrier wall whose bottom is connected to the buried dielectric layer 2 .

[0084] Optionally, in some of the above embodiments, the isolation retaining wall for the isolation structure 5 may also be obtained by coating a filler with an insulating dielectric layer, and the material of the filler may be, for example, polysilicon.

[0085] In summary, CMOS devices are low-voltage devices, and VDMOS devices and LDMOS devices are different types of high-voltage devices. The embodiment of the present application can simultaneously integrate different power devices such as VDMOS devices and LDMOS devices and CMOS devices on the same substrate 1 based on SOI technology, so as to effectively achieve high-density integration and miniaturization of devices on the basis of meeting the voltage resistance requirements and heat dissipation characteristics of devices at different voltage levels. In addition, the embodiment of the present application can avoid voltage coupling between the LDMOS device and adjacent devices by increasing the thickness of the buried dielectric layer 2 under the drain region 32 of the LDMOS device. The embodiment of the present application can ensure heat dissipation to the greatest extent by reducing the thickness of the buried dielectric layer 2 under the source region 31 of the LDMOS device, thereby taking into account the requirements of the LDMOS device for voltage resistance and heat dissipation characteristics, and is also conducive to the integration of more complex circuits and the miniaturization of chips.

[0086] It should be noted that in some embodiments, the substrate 1 above the buried dielectric layer 2 can be obtained by forming an epitaxial layer on an initial substrate, either before or after forming the buried dielectric layer 2 within the initial substrate. In this way, the thickness of the substrate 1 above the buried dielectric layer 2 can be tailored to meet specific requirements by forming epitaxial layers of varying thicknesses, effectively expanding the application of various high- and low-voltage transistor devices on this substrate 1.

[0087] In addition, it is worth mentioning that the epitaxial layer formed on the initial substrate before or after the buried dielectric layer 2 is formed in the initial substrate can be formed by a selective epitaxial process.

[0088] 1 , the initial substrate 10 has a first conductivity type. Optionally, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0089] Please understand in conjunction with FIG1 that before or after forming the buried dielectric region 2, a first epitaxial layer 1-1 may be formed above the region outside the opening 21 in the buried dielectric region 2 (including but not limited to at least one of the first portion 22, the second portion 23, and the region below the depletion region 513), and a second epitaxial layer 1-2 may be formed above the opening 21 in the buried dielectric region 2. The conductivity type of the second epitaxial layer 1-2 may be the same as that of the initial substrate 10, but different from that of the first epitaxial layer 1-1.

[0090] For example, the first conductivity type of the initial substrate 10 is N-type, the conductivity type of the first epitaxial layer 1 - 1 is P-type, and the conductivity type of the second epitaxial layer 1 - 2 is N-type.

[0091] Furthermore, the thickness of the first epitaxial layer 1-1 and the second epitaxial layer 1-2 can be determined based on the withstand voltage of the device to be formed (e.g., the withstand voltage of a trench-gate vertical device). This makes it easier to adjust the thickness of the first epitaxial layer 1-1 and the second epitaxial layer 1-2 during manufacturing, and the upper limit of the thickness that can be formed is relatively large, facilitating the design of the withstand voltage of the device and enabling the production of devices with higher withstand voltages, thereby expanding the richness of the entire process.

[0092] For example, referring to Figure 4 (a), after a buried dielectric layer 2 is formed on the initial substrate 10, the upper surface of the buried dielectric layer 2 and the initial substrate 10 in the opening 21 of the buried dielectric layer 2 can be exposed, and a first epitaxial material layer 1-10, a protective dielectric layer 30 and a photoresist layer 40 are sequentially formed on the exposed surfaces of the buried dielectric layer 2 and the initial substrate 10.

[0093] Referring to FIG. 4( b ), the protective dielectric layer 30 and the first epitaxial material layer 1-10 are patterned based on the opening pattern in the photoresist layer 40 to form the protective layer 3 and the first epitaxial layer 1-1, respectively. The etched and removed regions of the protective dielectric layer 30 and the first epitaxial material layer 1-10 expose the initial substrate 10 in the opening 21 of the buried dielectric layer 2. After forming the protective layer 3 and the first epitaxial layer 1-1, the photoresist layer 40 is removed.

[0094] Illustratively, the initial substrate 10 has a first conductivity type, and the first epitaxial layer 1 - 1 has a second conductivity type.

[0095] Illustratively, the thickness of the first epitaxial material layer 1 - 10 is 1 to 5 micrometers.

[0096] Referring to FIG. 4( c ), an isolation material layer 50 is formed covering the sidewalls of the first epitaxial layer 1 - 1 and extending into the initial substrate 10 and connected to the sidewalls of the buried dielectric layer 2 .

[0097] Please refer to FIG. 4 ( d ), a second epitaxial material layer 1 - 20 is formed on the exposed upper surface of the initial substrate 10 .

[0098] Illustratively, the second epitaxial material layer 1 - 20 has a first conductivity type.

[0099] 4 (e), the protective layer 3 is removed by grinding to expose the upper surface of the first epitaxial layer 1-1, and the isolation structure 5 and the second epitaxial layer 1-2 are simultaneously formed to obtain the substrate 1.

[0100] In some embodiments of the present application, the initial substrate 10 may be a silicon substrate with a higher doping concentration to facilitate the formation of a narrower depletion region, thereby reducing the distance between two adjacent devices and further reducing the area of ​​the semiconductor structure.

[0101] In some embodiments of the present application, the doping concentration of the initial substrate 10 is controlled so that its resistivity reaches a range of 8Ω×cm to 45Ω×cm.

[0102] In some embodiments of the present application, the material of the protective dielectric layer 30 may be silicon oxide, such as silicon dioxide.

[0103] It is understood that the epitaxial layer formed on the initial substrate 10 may also be formed by other processes different from those described in the above embodiment, which is not limited in the present embodiment.

[0104] Some embodiments of the present application also provide a method for manufacturing a semiconductor structure, for manufacturing the semiconductor structure described in some of the above embodiments. This manufacturing method also possesses the technical advantages of the aforementioned semiconductor structure, for example, effectively improving the device performance and reliability of the semiconductor structure, thereby expanding the application of SOI high-voltage integrated circuits. Furthermore, the manufacturing method provided by this application is simple and easy to implement, and is also conducive to improving production efficiency and yield.

[0105] Please refer to FIG. 5 , the manufacturing method includes the following steps S100 - S600 .

[0106] S100: providing a substrate and forming a hard mask layer on the substrate; the hard mask layer includes a first thickness film layer and a second thickness film layer arranged in the same layer, wherein the first thickness film layer has a gradient thickness, and the thickness of the second thickness film layer is greater than the maximum thickness of the first thickness film layer.

[0107] S200 ion implants are performed on the substrate based on the hard mask layer to form a buried dielectric layer in the substrate. The buried dielectric layer includes a first portion having a gradient thickness and an opening; wherein the first portion is formed based on a film layer of a first thickness, and the opening is formed based on a film layer of a second thickness.

[0108] S300: removing the hard mask layer.

[0109] S400: forming an isolation structure, wherein the bottom of the isolation structure is connected to the buried dielectric layer and separates a plurality of active regions.

[0110] S500: forming a lateral power device. The lateral power device is located in the active area and above the first portion of the buried dielectric layer, and includes a source region and a drain region spaced apart in a direction parallel to the substrate.

[0111] S600: Forming a vertical power device. The vertical power device includes a well region, a drift region, a source region, and a drain region. The well region is located within the active region above the opening of the buried dielectric layer. The source region is located within the well region. The drift region extends through the opening of the buried dielectric layer and the well region and includes an area where the substrate is located below the buried dielectric layer. The drain region is located at the bottom of the drift region.

[0112] In some embodiments, referring to FIG. 6 , step S100 of forming a hard mask layer on a substrate may include the following steps S110 - S170 .

[0113] S110: forming a hard mask material layer on the substrate.

[0114] S120 : forming a first photoresist layer having a first opening pattern on the hard mask material layer.

[0115] S130: Based on the first opening pattern, the hard mask material layer is etched to obtain an initial hard mask layer; the initial hard mask layer has a second thickness film layer and an initial third thickness film layer, and the thickness of the initial third thickness film layer is less than the thickness of the second thickness film layer and is greater than or equal to the maximum thickness of the first thickness film layer.

[0116] S140: removing the first photoresist layer.

[0117] S150: forming a second photoresist layer having a second opening pattern on the initial hard mask layer; the second opening pattern exposes a portion of the initial third thickness film layer.

[0118] S160: Based on the second opening pattern, wet-etching the initial hard mask layer to obtain a hard mask layer. The hard mask layer includes: a first thickness film layer, a second thickness film layer, and a third thickness film layer.

[0119] S170: removing the second photoresist layer.

[0120] In some embodiments, the substrate is a silicon wafer. Referring to FIG7 , step S200 of performing ion implantation on the substrate based on the hard mask layer to form a buried dielectric layer in the substrate may include the following steps S210 and S220 .

[0121] S210: performing oxygen ion implantation on the substrate based on the hard mask layer.

[0122] S220: performing high-temperature treatment on the substrate after the oxygen ions are implanted to form a buried dielectric layer.

[0123] In some embodiments, referring to FIG. 8 , step S400 of forming an isolation structure may include the following steps S410 and S420 .

[0124] S410: forming trenches in the substrate above the buried dielectric layer, wherein the trenches separate the substrate into a plurality of active regions.

[0125] S420: forming an isolation retaining wall in the trench to obtain an isolation structure.

[0126] In some other embodiments, referring to FIG. 9 , step S400 of forming an isolation structure may include the following steps S410 ′ and S420 ′.

[0127] S410 ′: forming a trench in the substrate above the buried dielectric layer, wherein the trench separates the substrate into a plurality of active regions and at least one depletion region.

[0128] S420': forming an isolation barrier in the trench; wherein the lateral power device and the vertical power device are respectively located on both sides of the depletion region in a direction parallel to the substrate; the depletion region and the isolation barrier on both sides constitute an isolation structure.

[0129] It is worth mentioning that in some embodiments, the hard mask layer includes: a first thickness layer, a second thickness layer, and a third thickness layer. The buried dielectric layer formed based on the hard mask layer also includes a second portion, the thickness of which is less than or equal to the minimum thickness of the first portion.

[0130] Accordingly, in some embodiments, the method for manufacturing a semiconductor structure further includes step S700.

[0131] S700: forming a non-power device in an active region of the lateral power device on a side away from the vertical power device, wherein the non-power device is located above the second portion of the buried dielectric layer.

[0132] Accordingly, in some other embodiments, the method for manufacturing a semiconductor structure further includes step S700 ′.

[0133] S700 ′: forming a non-power device in the active area between the lateral power device and the vertical power device, wherein the non-power device is located above the second portion of the buried dielectric layer.

[0134] It should be understood that although the steps in the various flowcharts of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowcharts of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0135] In order to more clearly illustrate the manufacturing methods of the semiconductor structures in some of the above embodiments, please refer to FIG. 10 to FIG. 15 for understanding.

[0136] In step S100, referring to Figures 10 to 12, a substrate 1 is provided, and a hard mask layer 11 is formed on the substrate 1; the hard mask layer 11 includes a first thickness film layer R1 and a second thickness film layer R2, wherein the thickness of the first thickness film layer R1 has a gradient, and the thickness of the second thickness film layer R2 is greater than the maximum thickness of the first thickness film layer R1.

[0137] For example, step S100 may include steps S110 to S170.

[0138] In steps S110 and S120, as shown in FIG10 , a hard mask material layer 110 is formed on a substrate 1. A first photoresist layer 12 having a first opening pattern K1 is formed on the hard mask material layer 110.

[0139] Illustratively, the substrate 1 includes but is not limited to a silicon wafer.

[0140] By way of example, the hard mask material layer 110 includes but is not limited to an oxide layer, such as a silicon oxide layer.

[0141] In steps S130-S150, as shown in conjunction with FIG11 , the hard mask material layer 110 is etched based on the first opening pattern K1 to obtain an initial hard mask layer 11A. The initial hard mask layer 11A comprises a second-thickness layer R2 and an initial third-thickness layer R3'. The thickness of the initial third-thickness layer R3' is less than that of the second-thickness layer R2 and greater than or equal to the maximum thickness of the first-thickness layer R1. The first photoresist layer 12 is removed. A second photoresist layer 13 having a second opening pattern K2 is formed on the initial hard mask layer 11A. The second opening pattern K2 exposes a portion of the initial third-thickness layer R3'.

[0142] 11 and 12 , in step S160 , the initial hard mask layer 11A is wet-etched based on the second opening pattern K2 to obtain a hard mask layer 11. The hard mask layer 11 includes a first thickness layer R1, a second thickness layer R2, and a third thickness layer R3.

[0143] It is understood that when the initial hard mask layer 11A is wet-etched based on the second opening pattern K2, an inclined surface can be formed on the upper surface of the first-thickness film layer R1. The area, morphology, and angle between the inclined surface and the substrate 1 can all be matched to the thickness of the buried dielectric layer 2 to be formed by setting relevant wet etching process parameters. This is not described in detail in the present embodiment.

[0144] In step S170 , referring to FIG. 13 , the second photoresist layer 13 is removed.

[0145] In step S200, referring to FIG. 13 , ion implantation is performed on substrate 1 based on hard mask layer 11 to form a buried dielectric layer 2 within substrate 1. Buried dielectric layer 2 includes a first portion 22 having a gradient thickness and an opening 21. The first portion 22 is formed based on a film layer of first thickness R1, and the opening 21 is formed based on a film layer of second thickness R2.

[0146] Specifically, the hard mask layer 11 is an injection barrier layer. The first portion 22 has a gradient thickness, which means that the thickness D1 of each longitudinal section of the first portion 22 along a direction perpendicular to the substrate 1 gradually changes along a direction parallel to the substrate 1, for example, by equal increments or in equal proportions.

[0147] 13 , the hard mask layer 11 includes a third thickness layer R3. The buried dielectric layer 2 also includes a second portion 23 having a thickness less than or equal to the minimum thickness of the first portion 22. The second portion 23 is formed based on the third thickness layer R3.

[0148] It should be noted that FIG13 illustrates the buried dielectric layer 2 by taking the first portion 22 as being located on the side of the second portion 23 away from the opening 21 as an example. However, it is understood that the first portion 22, the second portion 23, and the opening 21 may be distributed in any position to meet the distribution requirements of different types of power devices and other transistor devices, and this is not specifically limited in the present embodiment.

[0149] For example, the substrate 1 may be a silicon wafer. Step S200 may include the following steps S210 to S220.

[0150] In step S210 , oxygen ions are implanted into the substrate 1 based on the hard mask layer 11 .

[0151] Specifically, the implantation depth of oxygen ions is related to the ion implantation concentration and the ion implantation energy, and the implantation of oxygen ions can be achieved by controlling relevant process parameters.

[0152] In step S220 , the substrate 1 after the oxygen ion implantation is subjected to a heat treatment (high temperature treatment) to form a buried dielectric layer 2 .

[0153] Specifically, the high temperature treatment may be, for example, an annealing treatment. The treatment temperature of the high temperature treatment may be selected and set to match the requirements. This embodiment of the present application does not limit this.

[0154] For example, the buried dielectric layer 2 is a buried oxide layer, and its material may be silicon oxide, such as silicon dioxide.

[0155] In the embodiment of the present application, the substrate 1 after oxygen ion implantation is subjected to high temperature treatment, which can also effectively eliminate internal defects of the buried dielectric layer 2 and the substrate 1 .

[0156] As described above, the present application utilizes the opening 21 in the buried dielectric layer 2, the gradient thickness D1 of the first portion 22, and the second portion 23 to effectively optimize the electric field lines of the semiconductor structure, thereby easily improving the heat dissipation performance of the semiconductor structure while meeting the requirements of high-voltage device characteristics, thereby effectively improving the device performance and reliability of the semiconductor structure. Furthermore, the manufacturing method provided by the present application is simple and easy to implement, which is conducive to improving production efficiency and yield.

[0157] In step S300 , referring to FIG. 14 , the hard mask layer 11 is removed.

[0158] In some examples, after removing the hard mask layer 11 , the aforementioned substrate can be used as an initial substrate to grow an epitaxial layer on the initial substrate, thereby ensuring that the substrate thickness above the buried dielectric layer 2 can meet requirements.

[0159] In step S400, referring to FIG15, an isolation structure 5 is formed. The bottom of the isolation structure 5 is connected to the buried dielectric layer 2 and separates a plurality of active areas AA.

[0160] For example, in step S410, trenches can be formed in the substrate 1 above the buried dielectric layer 2 to separate the substrate 1 into multiple active areas AA. Here, each active area AA can be used to fabricate different power devices or other transistor devices, matching different regions of the buried dielectric layer 2. In step S420, isolation barriers can be formed in the trenches to obtain an isolation structure 5. Subsequently, LDMOS devices, VDMOS devices, CMOS devices, etc. can be fabricated based on each active area AA, thereby obtaining the semiconductor structure described in FIG2 .

[0161] For example, in step S410', a trench may be formed in the substrate 1 above the buried dielectric layer 2 first, so as to separate the substrate 1 into a plurality of active areas AA and at least one depletion area 513 through the trench. Here, different regions of the buried dielectric layer 2 are matched, and each active area AA can be used to prepare different power devices or other transistor devices. In step S420', an isolation barrier may be formed in the trench. Afterwards, LDMOS devices, VDMOS devices, CMOS devices, etc. may be prepared based on each active area AA, thereby obtaining the semiconductor structure described in Figure 1. Among them, the lateral power device 3 and the vertical power device 4 may be respectively located on both sides of the depletion area 513 along a direction parallel to the substrate 1. The depletion area 513 and the isolation barrier walls (511 and 512) on both sides thereof together constitute an isolation structure 5.

[0162] It is understood that different types of power devices or other transistor devices may have different internal structures. Thus, to match the internal structures of different devices, the manufacturing process of each device can have multiple possible implementations, and the embodiments of this application do not limit the manufacturing process of each device. For example, the aforementioned LDMOS device, VDMOS device, and CMOS device can be manufactured independently, or there can be some overlapping or interleaving of the manufacturing steps, as long as the respective devices can be manufactured.

[0163] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0164] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0165] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, comprising: A substrate; A buried dielectric layer disposed within the substrate, including a first portion having a gradient thickness and having an opening; A lateral power device disposed above the first portion of the buried dielectric layer, including a source region and a drain region spaced apart in a direction parallel to the substrate; A vertical power device, including: a well region, a drift region, a source region, and a drain region; wherein, the well region is within the substrate above the opening; the source region is within the well region; the drift region penetrates through the opening and the well region and includes a region of the substrate below the buried dielectric layer; the drain region is at the bottom of the drift region; An isolation structure within the substrate between the lateral power device and the vertical power device, and a bottom of the isolation structure is connected to the buried dielectric layer.

2. The semiconductor structure according to claim 1, wherein The isolation structure includes: An isolation barrier wall with a bottom connected to the buried dielectric layer.

3. The semiconductor structure according to claim 1, wherein The isolation structure includes: A first isolation barrier wall and a second isolation barrier wall with bottoms connected to the buried dielectric layer and spaced apart in a direction parallel to the substrate, and a depletion region between the first isolation barrier wall and the second isolation barrier wall.

4. The semiconductor structure according to claim 1, wherein the first portion comprises: A first sub - portion facing the drain region of the lateral power device, and a second sub - portion facing the source region of the lateral power device; Wherein, a minimum thickness of the first sub - portion is greater than a maximum thickness of the second sub - portion.

5. The semiconductor structure according to claim 4, wherein an upper surface of the buried dielectric layer is parallel to a surface of the substrate; a lower surface of the first portion is an inclined surface, and the inclined surface includes an inclined plane or an inclined curved surface.

6. The semiconductor structure according to any one of claims 1 to 5, wherein the buried dielectric layer further includes a second portion, and a thickness of the second portion is less than or equal to a minimum thickness of the first portion; the semiconductor structure further includes: A non - power device disposed above the second portion of the buried dielectric layer.

7. The semiconductor structure according to claim 6, wherein, The non - power device is on a side of the lateral power device away from the vertical power device; the isolation structure includes: a first isolation structure between the lateral power device and the vertical power device, and a second isolation structure between the lateral power device and the non - power device.

8. The semiconductor structure according to claim 6, wherein, The non - power device is between the lateral power device and the vertical power device; the isolation structure includes: a third isolation structure between the non - power device and the vertical power device, and a fourth isolation structure between the non - power device and the lateral power device.

9. A manufacturing method of a semiconductor structure, comprising: Providing a substrate and forming a hard mask layer on the substrate; The hard mask layer includes a first - thickness film layer and a second - thickness film layer disposed in the same layer, wherein, the first - thickness film layer has a gradient thickness, and a thickness of the second - thickness film layer is greater than a maximum thickness of the first - thickness film layer; Ion implant the substrate based on the hard mask layer to form a buried dielectric layer in the substrate; the buried dielectric layer includes a first portion with a gradient in thickness, and the buried dielectric layer has an opening; wherein, the first portion is formed based on the first thickness film layer, and the opening is formed based on the second thickness film layer; Remove the hard mask layer; Form an isolation structure, the bottom of the isolation structure is connected to the buried dielectric layer, and separates a plurality of active regions; Form a lateral power device, the lateral power device is located in the active region and above the first portion of the buried dielectric layer, the lateral power device includes a source region and a drain region arranged at intervals in a direction parallel to the substrate; Form a vertical power device, the vertical power device includes: a well region, a drift region, a source region and a drain region; wherein, The well region is located in the active region above the opening; the source region is located in the well region; the drift region penetrates through the opening and the well region, and includes the region of the substrate below the buried dielectric layer; the drain region is located at the bottom of the drift region.

10. The manufacturing method of the semiconductor structure according to claim 9, wherein the forming of the isolation structure includes: Form a trench in the substrate above the buried dielectric layer, the trench separates the substrate into a plurality of the active regions; Form an isolation barrier in the trench to obtain the isolation structure.

11. The manufacturing method of the semiconductor structure according to claim 9, wherein the forming of the isolation structure includes: Form a trench in the substrate above the buried dielectric layer, the trench separates the substrate into a plurality of the active regions and at least one depletion region; Form an isolation barrier in the trench; wherein, the lateral power device and the vertical power device are respectively located on two sides of the depletion region in a direction parallel to the substrate; the depletion region and the isolation barriers on both sides thereof constitute the isolation structure.

12. The manufacturing method of the semiconductor structure according to claim 9, wherein the forming of the hard mask layer on the substrate includes: Form a hard mask material layer on the substrate; Form a first photoresist layer with a first opening pattern on the hard mask material layer; Etch the hard mask material layer based on the first opening pattern to obtain an initial hard mask layer; The initial hard mask layer has the second thickness film layer and an initial third thickness film layer; The thickness of the initial third thickness film layer is less than the thickness of the second thickness film layer, and is greater than or equal to the maximum thickness of the first thickness film layer; Remove the first photoresist layer; Form a second photoresist layer with a second opening pattern on the initial hard mask layer; the second opening pattern exposes part of the initial third thickness film layer; Wet-etch the initial hard mask layer based on the second opening pattern to obtain the hard mask layer; the hard mask layer includes: the first thickness film layer, the second thickness film layer and a third thickness film layer; Remove the second photoresist layer.

13. The manufacturing method of the semiconductor structure according to claim 9, wherein the substrate is a silicon wafer; Performing ion implantation on the substrate based on the hard mask layer to form a buried dielectric layer in the substrate, including: Performing oxygen ion implantation on the substrate based on the hard mask layer; Performing a high-temperature treatment on the substrate after the oxygen ion implantation to form the buried dielectric layer.

14. The method for manufacturing a semiconductor structure according to any one of claims 9 to 13, wherein the buried dielectric layer further includes a second part, and the thickness of the second part is less than or equal to the minimum thickness of the first part.

15. The method for manufacturing a semiconductor structure according to claim 14, further including: Forming a non-power device in the active region on a side of the lateral power device away from the vertical power device, or forming a non-power device in the active region between the lateral power device and the vertical power device; wherein the non-power device is located above the second part of the buried dielectric layer.

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