Display panel, manufacturing method therefor and display apparatus

Abstract

The present disclosure relates to a display panel. The display panel comprises a first insulating layer, the first insulating layer being provided with a driving area, and the driving area being provided with a micropore array. The micropore array comprises a plurality of micropores, a protrusion being formed between any two adjacent micropores, and the surfaces of the plurality of micropores and the surfaces of the plurality of protrusions being connected to form a smooth wavy curved surface. When the slope angles of the side surfaces of the micropores are between 4.5 degrees and 65 degrees, pixel electrodes formed in the driving area form an uneven continuous morphology, thus well improving the brightness of the display panel. Further provided in the present disclosure is a manufacturing method for the display panel, and further provided in the present disclosure is a display apparatus comprising the display panel. (FIG. 10)

Description

Display panel and manufacturing method thereof, and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202311867210.6 filed on December 28, 2023, entitled “Display panel, manufacturing method thereof, and display device”, and the entire contents of the Chinese patent application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0004] In order to improve the light extraction effect of the light emitting device, it is necessary to form a microhole array in the driving area of ​​the first insulating layer below the pixel electrode to achieve the purpose of increasing the light extraction effect.

[0005] During the preparation of the light-emitting device, the microhole array formed in the driving region has an uneven topography, which causes a risk of breakage of the pixel electrode formed on the driving region.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0007] The purpose of the present disclosure is to overcome the problem that the morphology of the microhole array formed in the driving area is uneven, which makes the pixel electrode formed on the driving area have the risk of breakage, and to provide a display panel and its manufacturing method and display device.

[0008] According to one aspect of the present disclosure, a display panel is provided, comprising a base substrate, a driving circuit layer and a light-emitting layer, the driving circuit layer comprising a pixel circuit and a first insulating layer, the pixel circuit being arranged on one side of the base substrate, the first insulating layer being arranged on a side of the pixel circuit away from the base substrate, the first insulating layer having a connection area and a driving area, the connection area being provided with a first via hole, the driving area being provided with a micropore array, the micropore array comprising a plurality of micropores; the light-emitting layer comprising a pixel electrode, the pixel electrode being attached to a side of the first insulating layer away from the base substrate, the pixel electrode being connected to the pixel circuit through the first via hole; a protrusion being formed between any two adjacent micropores, the surfaces of the plurality of micropores and the surfaces of the plurality of protrusions being connected to form a smooth wavy surface, the slope angle of the side of the micropore being between 4.5 degrees and 65 degrees.

[0009] In one embodiment of the present disclosure, the width of the micropore gradually increases in a direction away from the substrate, and the increase amplitude of the micropore width gradually increases in the direction away from the substrate.

[0010] In one embodiment of the present disclosure, the light-emitting layer further includes a light-emitting material layer group and a common electrode. The light-emitting material layer group is arranged on a side of the pixel electrode away from the base substrate, and the common electrode is arranged on a side of the light-emitting material layer group away from the base substrate.

[0011] In one embodiment of the present disclosure, the display panel further includes a pixel defining layer having a pixel opening, and the orthographic projection of the microhole array on the base substrate at least partially overlaps with the orthographic projection of the pixel opening on the base substrate.

[0012] In one embodiment of the present disclosure, the first insulating layer includes a plurality of microlens units, each of the microlens units is respectively provided with a group of microhole arrays, the orthographic projection of the microlens unit on the pixel defining layer covers the pixel opening, and the distance between the edge of the orthographic projection of the microlens unit on the pixel defining layer and the edge of the pixel opening is between 2um and 5um.

[0013] In one embodiment of the present disclosure, the microlens unit includes a plurality of sub-microlenses, and each of the sub-microlenses includes the microhole.

[0014] In one embodiment of the present disclosure, the orthographic projection shape of the side of the sub-microlens away from the base substrate on the base substrate includes a hexagon, and a deflection angle is provided between the straight line where the side of each sub-microlens of the microlens unit lies and the pixel opening, and the deflection angle is less than or equal to 60 degrees.

[0015] In one embodiment of the present disclosure, the plurality of sub-microlenses of the microlens unit have a plurality of different arrangements, the deflection angles of the different arrangements increase successively, and the difference between the deflection angles of two adjacent arrangements is greater than or equal to 5 degrees.

[0016] In one embodiment of the present disclosure, the pixel electrode is a transparent conductive film, the common electrode is a metal reflective layer, and the display panel further includes a color filter layer, which is disposed on a side of the first insulating layer close to the base substrate.

[0017] In one embodiment of the present disclosure, the pixel electrode is a metal reflective layer, the common electrode is a transparent conductive film, and the display panel further includes a color filter layer, which is disposed on a side of the common electrode away from the base substrate.

[0018] In one embodiment of the present disclosure, the color filter layer includes a black matrix, the black matrix is ​​provided with a plurality of color resist openings, and the color resist openings are respectively provided with a first color resist block, a second color resist block, a third color resist block and a fourth color resist block. The first color resist block is red, the second color resist block is green, the third color resist block is blue, and the fourth color resist block is transparent.

[0019] In one embodiment of the present disclosure, the driving circuit layer includes a thin film transistor, which includes an active layer, a second insulating layer, a gate, a source and a drain. The active layer is arranged on one side of the base substrate, the second insulating layer is arranged on the side of the active layer away from the base substrate, the second insulating layer covers the active layer, the gate, the source and the drain are arranged on the side of the second insulating layer away from the base substrate, the source and the drain are respectively connected to the active layer through a second via hole, the gate is located between the source and the drain, the orthographic projection of the gate on the base substrate is located within the orthographic projection of the active layer on the base substrate, and the pixel electrode is connected to the source or the drain through a first via hole.

[0020] In one embodiment of the present disclosure, the display panel also includes a third insulating layer and a light-shielding layer. The light-shielding layer is located on one side of the base substrate. The third insulating layer is arranged on the side of the light-shielding layer away from the base substrate. The third insulating layer covers the light-shielding layer. The orthographic projection of the active layer on the base substrate is located within the orthographic projection of the light-shielding layer on the base substrate.

[0021] According to another aspect of the present disclosure, a method for manufacturing the display panel provided in one aspect of the present disclosure is provided, the method comprising:

[0022] forming a pixel circuit on the base substrate, and forming a first insulating layer on a side of the pixel circuit away from the base substrate;

[0023] exposing the connection area of ​​the first insulating layer using all the energy, exposing the driving area of ​​the first insulating layer using part of the energy, and not exposing other areas of the first insulating layer;

[0024] Developing the exposed first insulating layer to form a first via hole in the connection area and a microhole array in the driving area;

[0025] A pixel electrode is formed on a side of the first insulating layer away from the base substrate, and the pixel electrode is connected to the pixel circuit through a first via hole.

[0026] According to yet another aspect of the present disclosure, a display device is provided, comprising the display panel provided according to any one aspect of the present disclosure.

[0027] The display panel disclosed herein includes a first insulating layer, the first insulating layer has a driving area, a micropore array is provided on the driving area, the micropore array includes a plurality of micropores, a protrusion is formed between any two adjacent micropores, the surfaces of the plurality of micropores and the surfaces of the plurality of protrusions are connected to form a smooth wavy surface, and when the slope angle of the side of the micropore is between 4.5 degrees and 65 degrees, the pixel electrode formed on the driving area forms an uneven continuous morphology, which can greatly improve the brightness of the display panel.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0030] FIG1 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure before a microhole array is formed in a first insulating layer.

[0031] FIG. 2 is a schematic diagram of stacking the display panel according to an embodiment of the present disclosure before a microhole array is formed in the first insulating layer.

[0032] FIG3 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when a microhole array is formed in the first insulating layer.

[0033] FIG. 4 is a schematic diagram of stacking the display panel according to an embodiment of the present disclosure when the first insulating layer does not form a microhole array.

[0034] FIG5 is a schematic diagram showing a state of exposing the photoresist layer on the first insulating layer according to an embodiment of the present disclosure.

[0035] FIG. 6 is a schematic diagram illustrating a state in which the photoresist layer on the first insulating layer is developed according to an embodiment of the present disclosure.

[0036] FIG7 is a planar topography diagram showing that the micropores of the micropore array formed by dry etching according to an embodiment of the present disclosure are uneven and have attachments.

[0037] FIG8 is a cross-sectional morphology diagram of a micropore array formed by dry etching according to an embodiment of the present disclosure, in which the micropores have uneven morphology and have attachments.

[0038] FIG9 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when the surface unevenness of the micropores causes the surface of each sub-microlens away from the base substrate to be relatively rough, resulting in disconnection of the pixel electrode.

[0039] FIG10 is a plan view of a display panel according to an embodiment of the present disclosure, in which the surfaces of multiple micropores and the surfaces of multiple protrusions are connected to form a smooth wavy curved surface, and the display panel emits light from a side close to the base substrate.

[0040] FIG11 is a plan view of a display panel according to an embodiment of the present disclosure, in which the surfaces of multiple micropores and the surfaces of multiple protrusions are connected to form a smooth wavy curved surface, and the display panel emits light from a side away from the base substrate.

[0041] FIG12 is a cross-sectional morphology diagram showing a smooth wavy surface formed by connecting the surfaces of multiple micropores and multiple protrusions according to an embodiment of the present disclosure.

[0042] FIG13 is a cross-sectional morphology diagram of the microhole array of the first insulating layer according to an embodiment of the present disclosure when the slope angle of the side surface of the microhole is 4.5 degrees.

[0043] FIG14 is a cross-sectional morphology diagram of the microhole array of the first insulating layer according to an embodiment of the present disclosure when the slope angle of the side surface of the microhole is 15.8 degrees.

[0044] FIG15 is a cross-sectional morphology diagram of the microhole array of the first insulating layer according to an embodiment of the present disclosure when the slope angle of the side surface of the microhole is 26.7 degrees.

[0045] FIG16 is a cross-sectional morphology diagram of the micropore array of the first insulating layer involved in an embodiment of the present disclosure, showing a microscopic manifestation of the micropore array, in which the brightness increases significantly at the slope angle of the morphology.

[0046] FIG17 is a schematic diagram of a microlens unit of a display panel and a corresponding relationship between the microlens unit and sub-pixels according to an embodiment of the present disclosure.

[0047] FIG18 is a schematic plan view of the fourth microlens unit before removal according to an embodiment of the present disclosure.

[0048] FIG19 is a plan view of the fourth microlens unit after removal according to an embodiment of the present disclosure.

[0049] FIG20 is a partial enlarged view of a portion A of the fourth microlens unit before removal according to an embodiment of the present disclosure.

[0050] FIG. 21 is a schematic diagram showing the arrangement of the sub-microlenses in position A before the fourth microlens unit in FIG. 20 is removed.

[0051] FIG. 22 is a schematic diagram showing the arrangement of sub-microlenses at position A after the fourth microlens unit in FIG. 20 is removed.

[0052] FIG. 23 is a schematic diagram showing the arrangement of sub-microlenses at position A after the fourth microlens unit in FIG. 20 is removed when the deflection angle between the straight line where the edge of the sub-microlens lies and the pixel opening is 5 degrees.

[0053] FIG. 24 is a schematic diagram showing the arrangement of sub-microlenses at position A after the fourth microlens unit in FIG. 20 is removed when the deflection angle between the straight line where the edge of the sub-microlens lies and the pixel opening is 10 degrees.

[0054] FIG. 25 is a schematic diagram showing the arrangement of sub-microlenses at position A after the fourth microlens unit in FIG. 20 is removed when the deflection angle between the straight line where the edge of the sub-microlens lies and the pixel opening is 25 degrees.

[0055] FIG. 26 is a schematic diagram showing the arrangement of sub-microlenses at position A after the fourth microlens unit in FIG. 20 is removed when the deflection angle between the straight line where the edge of the sub-microlens lies and the pixel opening is 45 degrees.

[0056] FIG. 27 is a plan view of a corner portion of a fourth microlens unit according to an embodiment of the present disclosure before being cut off when no patterning is performed.

[0057] FIG28 is a partial enlarged view of a portion A before the fourth microlens unit is removed in FIG27 for explanation.

[0058] FIG. 29 is a schematic diagram showing the arrangement of the sub-microlenses in portion A after the fourth microlens unit in FIG. 27 is removed.

[0059] FIG30 is a schematic diagram showing the arrangement of sub-microlenses at position A after the fourth microlens unit in FIG27 is removed when the deflection angle between the straight line where the edge of the sub-microlens lies and the pixel opening is 5 degrees.

[0060] FIG31 is a schematic diagram showing the arrangement of sub-microlenses at position A after the fourth microlens unit in FIG27 is removed when the deflection angle between the straight line where the edge of the sub-microlens is located and the pixel opening is 10 degrees.

[0061] FIG32 is a schematic diagram showing the arrangement of sub-microlenses at position A after the fourth microlens unit in FIG27 is removed when the deflection angle between the straight line where the edge of the sub-microlens is located and the pixel opening is 25 degrees.

[0062] FIG33 is a schematic diagram showing the arrangement of sub-microlenses at position A after the fourth microlens unit in FIG27 is removed when the deflection angle between the straight line where the edge of the sub-microlens is located and the pixel opening is 45 degrees.

[0063] FIG34 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure.

[0064] 35 is a schematic diagram showing a state where the connection area of ​​the first insulating layer is exposed with full energy, the driving area of ​​the first insulating layer is exposed with partial energy, and the other areas of the first insulating layer are not exposed.

[0065] In the figure: 1-substrate, 2-driving circuit layer, 21-active layer, 22-second insulating layer, 221-second via, 23-first metal layer, 231-gate, 232-source, 233-drain, 24-first insulating layer, 241-first via, 25-light shielding layer, 26-third insulating layer, 3-pixel layer, 31-pixel defining layer, 311-pixel opening, 32-light-emitting layer, 321-pixel electrode, 3211-first concave-convex morphology, 322-light-emitting material layer group, 3221-second concave-convex morphology, 323-common electrode, 3231-third concave-convex topography, 33-color filter layer, 331-black matrix, 332-first color block, 333-second color block, 334-third color block, 335-fourth color block, 4-encapsulation layer, 5-microlens unit, 51-sub-microlens, 511-microwell, 501-first microlens unit, 502-second microlens unit, 503-third microlens unit, 504-fourth microlens unit, 52-microwell array, 6-mask, 7-photoresist layer, 71-microwell area. DETAILED DESCRIPTION

[0066] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0067] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0068] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0069] Figure 1 is a schematic cross-sectional view of a display panel. The display panel may include a base substrate 1, a drive circuit layer 2, and a pixel layer 3, which are stacked in sequence. The drive circuit layer 2 is disposed on one side of the base substrate 1. The pixel layer 3 includes a pixel defining layer 31 and a light-emitting layer 32. The light-emitting layer 32 is disposed on the side of the first insulating layer 24 away from the array substrate. The light-emitting layer 32 may include a pixel electrode 321, which is located on the surface of the first insulating layer 24 away from the base substrate 1. The pixel defining layer 31 is disposed between the pixel electrode 321 and the surface of the first insulating layer 24 away from the base substrate 1. The pixel defining layer 31 has a plurality of pixel openings 311, through which the pixel electrodes 321 are exposed.

[0070] Figure 2 is a schematic diagram of the stacking of the display panel. As shown in Figure 2, the first insulating layer 24 has a connection area and a driving area. The connection area is overlapped with the source 232 or drain 233 of the thin film transistor through the first via 241, and the driving area is used to drive the light-emitting layer 32 to emit light. As shown in Figures 3 and 4, in order to improve the light-emitting effect, a microhole array 52 is formed in the driving area of ​​the pixel electrode 321 to achieve the purpose of increasing the light-emitting effect. The first via 241 and the microhole array 52 are both located in the pixel opening 311. It should be noted that the depth of the multiple microholes 511 arranged in the microhole array 52 is less than the thickness of the first insulating layer 24. In this embodiment, the first via 241 and the microhole 511 are formed using two different mask processes.

[0071] As shown in Figures 5 and 6, the first insulating layer 24 is a photosensitive material, and the connection can be directly patterned using an exposure and development process. Forming the first via 241 in the connection area of ​​the first insulating layer 24 may include: exposing the connection area, developing the exposed area of ​​the first insulating layer 24, forming the first via 241 connected to the source electrode 232 or the drain electrode 233. The depth of the first via 241 is equal to the thickness of the first insulating layer 24, and the pixel electrode 321 is directly overlapped with the source electrode 232 or the drain electrode 233.

[0072] Forming the micropore array 52 in the driving region of the first insulating layer 24 may include: first forming a photoresist layer 7 on the driving region, exposing the photoresist layer 7, developing the exposed regions of the photoresist layer 7 to form a plurality of micropore regions 71, dry etching the patterned photoresist layer 7 to form a plurality of micropores 511, and removing the photoresist remaining between the micropores 511 on the first insulating layer 24. As shown in Figures 7 and 8, the micropores 511 formed by dry etching have uneven morphologies and are covered with deposits, resulting in a relatively rough surface on the side of the micropores 511 that forms the micropore array 52 and is away from the substrate 1. This surface may puncture the pixel electrode 321, causing a risk of disconnection of the pixel electrode 321, as shown in Figure 9.

[0073] The driving area can be directly patterned using an exposure and development process, with the depth of the micropores 511 being less than the thickness of the first insulating layer 24. A photoresist layer 7 is first formed on the connection area, exposed, and developed to form a via area. The via area is then dry-etched to form a first via 241, and the photoresist remaining on the first insulating layer 24 around the first via 241 is removed. The depth of the first via 241 formed by dry etching is less than the thickness of the first insulating layer 24. If the depth of the first via 241 reaches the thickness of the first insulating layer 24, the dry etching process will damage the first insulating layer 24 in the connection area around the first via 241, potentially affecting the morphology of the pixel electrode 321 in the driving area and, consequently, the luminous effect of the light-emitting device.

[0074] Based on this, embodiments of the present disclosure provide a display panel. As shown in Figures 10 to 33, the display panel includes a base substrate 1, a driving circuit layer 2, a first insulating layer 24, and a light-emitting layer 32. The driving circuit layer 2 includes a pixel circuit and a first insulating layer 24. The pixel circuit is provided on one side of the base substrate 1, and the first insulating layer 24 is provided on a side of the pixel circuit away from the base substrate 1. The first insulating layer 24 has a connection area and a driving area. The connection area is provided with a first via 241. The driving area is provided with a micropore array 52. ​​The micropore array 52 includes a plurality of micropores 511. The light-emitting layer 32 includes a pixel electrode 321. The pixel electrode 321 is attached to a side of the first insulating layer 24 away from the base substrate 1 and connected to the pixel circuit via the first via 241. A protrusion is formed between any two adjacent micropores 511. The surfaces of the multiple micropores 511 and the surfaces of the multiple protrusions are connected to form a smooth wavy surface. The slope angle α of the side of the micropore 511 is between 4.5 degrees and 65 degrees.

[0075] The first insulating layer 24 has a driving area, and a micropore array 52 is provided on the driving area. The micropore array 52 includes a plurality of micropores 511. A protrusion is formed between any two adjacent micropores 511. The surfaces of the plurality of micropores 511 and the surfaces of the plurality of protrusions are connected to form a smooth wavy surface. When the slope angle α of the side of the micropore 511 is between 4.5 degrees and 65 degrees, the pixel electrode 321 formed on the driving area forms an uneven continuous morphology, which can greatly improve the brightness of the display panel.

[0076] It should be noted that the slope angle α of the side surface of the microhole 511 refers to the angle between the side surface of the microhole 511 and the horizontal plane.

[0077] The display panel involved in the embodiments of the present disclosure will be described in detail below with reference to specific embodiments.

[0078] As shown in Figures 10 and 11, the display panel may include a base substrate 1, a driving circuit layer 2 and a pixel layer 3 stacked in sequence, the driving circuit layer 2 is arranged on one side of the base substrate 1, and the pixel layer 3 is arranged on the side of the driving circuit layer 2 away from the base substrate 1.

[0079] The base substrate 1 may be an inorganic material or an organic material. For example, in one embodiment of the present disclosure, the base substrate 1 may be made of a glass material such as soda-lime glass, quartz glass, or sapphire glass, or may be made of a metal material such as stainless steel, aluminum, or nickel.

[0080] In another embodiment of the present disclosure, the material of the base substrate 1 can be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyethersulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PEmm), polyethylene naphthalate (PEN), or a combination thereof.

[0081] In another embodiment of the present disclosure, the substrate 1 may be a flexible substrate 1. For example, the substrate 1 may be made of polyimide (PI). The substrate 1 may also be a composite of multiple layers. For example, in one embodiment of the present disclosure, the substrate 1 may include a base film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0082] The driving circuit layer 2 includes a pixel circuit, which may include a thin film transistor. The thin film transistor may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor. The thin film transistor may have a first terminal, a second terminal, and a control terminal. One of the first terminal and the second terminal may be a source electrode 232 of the thin film transistor, and the other may be a drain electrode 233 of the thin film transistor. The control terminal may be a gate electrode 231 of the thin film transistor. It is understood that the source electrode 232 and the drain electrode 233 of the thin film transistor are two relative and interchangeable concepts; when the operating state of the thin film transistor changes, for example, when the current direction changes, the source electrode 232 and the drain electrode 233 of the thin film transistor may be interchangeable.

[0083] In the present disclosure, the driving circuit layer 2 may include an active layer 21, a second insulating layer 22, a first metal layer 23, and a first insulating layer 24. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. In the present disclosure, the active layer 21 is provided on one side of the base substrate 1, the second insulating layer 22 is provided on the side of the active layer 21 away from the base substrate 1, the second insulating layer 22 covers the active layer 21, the first metal layer 23 is provided on the side of the second insulating layer 22 away from the base substrate 1, and the first insulating layer 24 is provided on the side of the first metal layer 23 away from the base substrate 1. The thin film transistor formed in this way is a top-gate thin film transistor.

[0084] The active layer 21 can be used to form the active portion of a thin-film transistor. The active portion includes a channel region and source and drain electrodes 232 and 233 located on either side of the channel region. The channel region can maintain semiconductor properties, while the semiconductor material in the source and drain electrodes 232 and 233 regions is partially or fully conductive. The first metal layer 23 can be used to form the gate electrode 231, source electrode 232, and drain electrode 233 of the thin-film transistor.

[0085] The orthographic projection of the gate 231 on the base substrate 1 covers the orthographic projection of the channel region of the active portion on the base substrate 1. The source 232 and the drain 233 are respectively provided on either side of the gate 231. The source 232 is connected to the source 232 region of the active portion through the second via 221 of the second insulating layer 22. The drain 233 is connected to the drain 233 region of the active portion through the second via 221 of the second insulating layer 22. The first insulating layer 24 covers the gate 231, the source 232, and the drain 233.

[0086] In some embodiments, the material of the active layer 21 can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material or other types of semiconductor materials; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0087] The driving circuit layer 2 may further include a third insulating layer 26 and a light-shielding layer 25. The light-shielding layer 25 is located on one side of the base substrate 1. The third insulating layer 26 is provided on the side of the light-shielding layer 25 away from the base substrate 1. The third insulating layer 26 covers the light-shielding layer 25. The orthographic projection of the active layer 21 on the base substrate 1 is located within the orthographic projection of the light-shielding layer 25 on the base substrate 1. The light-shielding layer 25 can shield light from the thin-film transistor, thereby stabilizing the electrical characteristics of the thin-film transistor.

[0088] The pixel layer 3 includes a pixel defining layer 31 and a light-emitting layer 32. The light-emitting layer 32 is disposed on a side of the first insulating layer 24 away from the array substrate. The light-emitting layer 32 may include a pixel electrode 321. The pixel electrode 321 is located on a surface of the first insulating layer 24 away from the base substrate 1. The pixel defining layer 31 is disposed between the pixel electrode 321 and the surface of the first insulating layer 24 away from the base substrate 1. The pixel defining layer 31 has a plurality of pixel openings 311, with the pixel electrode 321 exposed through the pixel openings 311. The light-emitting layer 32 may also include a light-emitting material layer group 322 and a common electrode 323. The light-emitting material layer group 322 is disposed on a surface of the pixel electrode 321 away from the base substrate 1, and the common electrode 323 is disposed on a surface of the light-emitting material layer group 322 away from the base substrate 1.

[0089] The first insulating layer 24 has a connection area, and a first via 241 is provided on the connection area. The first via 241 of the first insulating layer 24 is located in the pixel opening 311. The pixel electrode 321 is connected to the source electrode 232 through the first via 241. The pixel electrode 321 and the common electrode 323 can drive the light-emitting material layer group 322 to emit light to display an image. The specific light-emitting principle is not described in detail here. The light-emitting material layer group 322 may include an electroluminescent organic light-emitting material and may be formed by a process such as evaporation. For example, the light-emitting material layer group 322 may include a hole injection layer, a hole transport layer, a light generating layer, an electron transport layer, and an electron injection layer stacked sequentially on the pixel electrode 121 layer.

[0090] As shown in Figures 12 to 16, the first insulating layer 24 has a driving region, on which a micropore array 52 is disposed. The micropore array 52 is located within the pixel opening 311. The micropore array 52 includes a plurality of micropores 511, with a protrusion formed between any two adjacent micropores 511. The surfaces of the plurality of micropores 511 and the surfaces of the plurality of protrusions are connected to form a smooth wavy surface. The slope angle α of the side of the micropore 511 ranges from 4.5 degrees to 65 degrees. It can be seen that the width of the micropore 511 gradually increases as it moves away from the substrate 1, and the increase in the width of the micropore 511 gradually increases as it moves away from the substrate 1.

[0091] The slope angle α of the side of the micropore 511 can be 4.5 degrees as shown in FIG13 , 15.8 degrees as shown in FIG14 , and 26.7 degrees as shown in FIG15 . The resulting micropore array 52 has a brightening effect. As shown in FIG16 , the microscopic appearance of the micropore array 52 shows a significant increase in brightness due to the slope angle of the topography.

[0092] As shown in Figures 10 and 11, the first insulating layer 24 also includes a plurality of microlens units 5, each of which is provided with a micropore array 52. ​​The orthographic projection of the microlens unit 5 on the pixel defining layer 31 covers the pixel opening 311. The surfaces of the plurality of micropores 511 and the surfaces of the plurality of protrusions of the micropore array 52 are connected to form a smooth wavy curved surface. The pixel electrode 321 covers the micropore array 52, so that the side of the pixel electrode 321 on the micropore array 52 away from the substrate 1 can form a continuous first concave-convex topography 3211. The luminescent material layer group 322 is superimposed on the continuous first concave-convex topography, so that the side of the luminescent material layer group 322 away from the substrate 1 can form a continuous second concave-convex topography 3221. The common electrode 323 is superimposed on the second concave-convex topography, so that the side of the common electrode 323 away from the substrate 1 can form a continuous third concave-convex topography 3231.

[0093] The microlens unit 5 includes multiple sub-microlenses 51, each of which includes multiple micropores 511. Each sub-microlens 51 may include one micropore 511, so the number of sub-microlenses 51 is equal to the number of micropores 511. The sub-microlenses 51 have the same refractive index as the base substrate 1. Through multiple reflections, the emitted light from the light-emitting unit can be propagated at an angle smaller than the critical angle of total reflection, allowing light trapped in the base substrate 1 and the light-emitting material layer group 322 to be extracted, thereby improving the brightness of the display panel. When the portion of the pixel electrode 321 located in the driving area can form a continuous uneven topography, the brightness of the display panel can be increased by 4% to 22%.

[0094] It should be noted that the sub-microlenses 51 are located between the dotted lines or between the dotted lines and the longitudinal edges in FIG. 10 to FIG. 16 .

[0095] As shown in Figure 17, the microlens unit 5 includes a first microlens unit 501, a second microlens unit 502, a third microlens unit 503 and a fourth microlens unit 504, the pixel layer 3 includes multiple groups of pixel units, each group of pixel units includes red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels, the orthographic projection of the first microlens unit 501 on the pixel defining layer 31 covers the pixel opening 311 of the red sub-pixel, the orthographic projection of the second microlens unit 502 on the pixel defining layer 31 covers the pixel opening 311 of the green sub-pixel, the orthographic projection of the third microlens unit 503 on the pixel defining layer 31 covers the pixel opening 311 of the blue sub-pixel, and the orthographic projection of the fourth microlens unit 504 on the pixel defining layer 31 covers the pixel opening 311 of the white sub-pixel.

[0096] As shown in FIG18 , the edges of the microlens units 5 are irregular in shape and have significant differences. The microlens units 5 corresponding to adjacent sub-pixels interfere with each other, and the size of a single microlens unit 5 does not perfectly match the pixel opening 311. Parts of the microlens units 5 are patterned outside the pixel opening 311. Therefore, the portions of the microlens units 5 outside the pixel opening 311 are cut away so that the distance between the edge of the orthographic projection of the microlens unit 5 on the pixel defining layer 31 and the edge of the pixel opening 311 is between 2 μm and 5 μm, to prevent interference between the microlens units 5 corresponding to adjacent sub-pixels, as shown in FIG19 .

[0097] The substrate 1 undergoes a high-temperature hardening treatment. During this high-temperature treatment, the uneven molecular structure of the substrate 1 surface causes scattering. The higher the intensity of the hardening treatment, the more difficult it is to control rainbow patterns. The presence of rainbow patterns can affect the display panel's light transmittance and visual quality. Setting a deflection angle θ between the line along which the edges of each sub-microlens 51 of the microlens unit 5 lie and the pixel opening 311 can reduce this unevenness and improve the rainbow pattern phenomenon.

[0098] As shown in Figure 20, a partial enlarged view of portion A of the fourth microlens unit is used for illustration. The arrangement of the sub-microlenses 51 in portion A of the fourth microlens unit 504 in Figure 20 before removal is shown in Figure 21. The sub-microlenses 51 at the edge of the microlens unit 5 are removed, and the arrangement of the sub-microlenses 51 in portion A after removal of the fourth microlens unit 504 in Figure 22 is shown in Figure 21. Each sub-microlens 51 of the microlens unit 5 has a deflection angle θ between the straight line on which the edge lies and the pixel opening 311. The sub-microlenses 51 are hexagonal in shape, and the deflection angle θ is less than or equal to 60 degrees. The multiple sub-microlenses 51 of the microlens unit 5 have various arrangements, with the deflection angle θ increasing in each arrangement. The difference in deflection angle θ between two adjacent arrangements is 5 degrees. Taking a hexagon as an example, with each 60-degree period forming one arrangement of the microlens units 5, one arrangement is rotated 5 degrees to form another arrangement. Each microlens unit 5 has 12 different arrangements. The deflection angle θ is related to the arrangement of the microlens units 5. In FIG. 23 to FIG. 26 , the deflection angle θ between the straight line on which the edge of the sub-microlens 51 lies and the pixel opening 311 is 5 degrees, 10 degrees, 25 degrees, and 45 degrees, respectively.

[0099] To more clearly understand the aforementioned deflection angle θ, the following description will be made using the unpatterned corner portion of the microlens unit 5 shown in FIG27 . The arrangement of the sub-microlenses 51 before portion A of FIG27 is shown in FIG28 . The sub-microlenses 51 at the edge of the microlens unit 5 are removed, and the arrangement of the sub-microlenses 51 after portion A of FIG29 is shown. The deflection angle θ between the straight line along the edge of the sub-microlens 51 and the pixel opening 311 in FIG29 is 0 degrees. The deflection angle θ between the straight line along the edge of the sub-microlens 51 and the pixel opening 311 in FIG30 is 5 degrees. The deflection angle θ between the straight line along the edge of the sub-microlens 51 and the pixel opening 311 in FIG31 is 10 degrees. The deflection angle θ between the straight line along the edge of the sub-microlens 51 and the pixel opening 311 in FIG32 is 25 degrees. The deflection angle θ between the straight line along the edge of the sub-microlens 51 and the pixel opening 311 in FIG33 is 45 degrees.

[0100] As shown in Figures 9 and 10, the display panel may further include a color filter layer 33. The color filter layer 33 includes a black matrix 331. The black matrix 331 is provided with a plurality of color-resistance openings. The color-resistance openings are provided with a first color-resistance block 332, a second color-resistance block 333, and a third color-resistance block 334, respectively. The first color-resistance block 332 is red, the second color-resistance block 333 is green, the third color-resistance block 334 is blue, and the fourth color-resistance block 335 is transparent. The light-emitting layer 32 can emit white light. After passing through the first color-resistance block 332, the white light becomes red light, forming a red sub-pixel. After passing through the second color-resistance block 333, the white light becomes green light, forming a green sub-pixel. After passing through the third color-resistance block 334, the white light becomes blue light, forming a blue sub-pixel. After passing through the fourth color-resistance block 335, the white light remains white light, forming a white sub-pixel.

[0101] When the display panel emits light from the side closest to the base substrate 1, the color filter layer 33 is disposed between the first insulating layer 24 and the second insulating layer 22, that is, the color filter layer 33 is disposed on the same layer as the first metal layer 23. The pixel electrode 321 is a transparent conductive film, the common electrode 323 is a metal reflective layer, and the color filter layer 33 is disposed between the third insulating layer 26 and the second insulating layer 22. The orthographic projection of each color resist block on the base substrate 1 overlaps the orthographic projection of the pixel opening 311 on the base substrate 1. White light emitted by the light-emitting layer 32 is reflected by the common electrode 323 and enters the transparent pixel electrode 321. After exiting the transparent pixel electrode 321, it enters the color filter layer 33, forming sub-pixels of various colors.

[0102] When the display panel emits light from the side away from the base substrate 1, the display panel also includes an encapsulation layer 4, which is disposed on the side of the common electrode 323 away from the base substrate 1. The color filter layer 35 is disposed on the side of the encapsulation layer 4 away from the base substrate 1. The pixel electrode 321 is a metal reflective layer, the common electrode 323 is a transparent conductive film, and the color filter layer 33 is disposed on the side of the common electrode 323 away from the base substrate 1. White light emitted by the light-emitting layer 32 directly enters the transparent common electrode 323, exits the transparent common electrode 323, and then enters the color filter layer 33, forming sub-pixels of various colors.

[0103] The present disclosure also provides a method for manufacturing a display panel as provided in any of the above embodiments. As shown in FIG. 10 to FIG. 35 , the method may include:

[0104] In step S10 , a pixel circuit is formed on the base substrate 1 , and a first insulating layer 24 is formed on a side of the pixel circuit away from the base substrate 1 .

[0105] In step S20 , the connection area of ​​the first insulating layer 24 is exposed using full energy, the driving area of ​​the first insulating layer 24 is exposed using partial energy, and other areas of the first insulating layer 24 are not exposed, as shown in FIG. 35 .

[0106] In step S30 , the exposed first insulating layer 24 is developed to form a first via hole 241 in the connection area and a microhole array 52 in the driving area.

[0107] In step S40 , a pixel electrode 321 is formed on a side of the first insulating layer 24 away from the base substrate 1 . The pixel electrode 321 is connected to the pixel circuit through the first via hole 241 .

[0108] This method uses a single mask process. After the connection area is exposed and developed using full energy, the depth of the first via hole 241 formed can reach the thickness of the first insulating layer 24. Therefore, the pixel electrode 321 can pass through the first via hole 241 and directly overlap the source electrode 232 of the thin-film transistor. After the drive area is exposed and developed using partial energy, the microhole array 52 formed has a smooth, wavy surface. This display panel manufacturing method not only reduces costs and simplifies the process flow, but also increases the luminous intensity of the display panel.

[0109] Step S10 of forming a pixel circuit on the base substrate 1 and forming a first insulating layer 24 on a side of the pixel circuit away from the base substrate 1 may include:

[0110] A light shielding layer 25 is formed on the base substrate 1;

[0111] A third insulating layer 26 is formed on one side of the base substrate 1;

[0112] An active layer 21 is formed on a side of the third insulating layer 26 away from the substrate 1 , and a source 232 region and a drain 233 region of the active layer 21 are conductively connected;

[0113] forming a second insulating layer 22 on a side of the active layer 21 away from the base substrate 1 , and forming a second via hole 221 on the second insulating layer 22 ;

[0114] A first metal layer 23 is formed on a side of the second insulating layer 22 away from the base substrate 1 , and the first metal layer 23 is patterned to form a gate 231 , a source 232 , and a drain 233 .

[0115] A first insulating layer 24 is formed on a side of the gate 231 , the source 232 , and the drain 233 away from the base substrate 1 .

[0116] In step S40, a pixel electrode 321 is formed on a side of the first insulating layer 24 away from the base substrate 1 , and the pixel electrode 321 is connected to the pixel circuit through the first via hole 241 , including:

[0117] A pixel electrode 321 is formed on a side of the first insulating layer 24 away from the base substrate 1 . The pixel electrode 321 is connected to the source electrode 232 through a first via hole 241 .

[0118] The present disclosure also provides a display device. The display device may include any of the display panels described above. The specific structure and beneficial effects of the display panel have been described in detail above and are therefore not further elaborated here.

[0119] It should be noted that, in addition to the display panel, the display device also includes other necessary components and components, such as circuit boards, power cords, etc. Those skilled in the art can make corresponding supplements based on the specific usage requirements of the display device, which will not be repeated here.

[0120] The display device can be a traditional electronic device, such as a mobile phone, a computer, a television, a projector, and a camcorder, or it can be an emerging wearable device, such as VR glasses, which are not listed here one by one.

[0121] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, characterized in that, Comprising: A substrate; A driving circuit layer, including a pixel circuit and a first insulating layer. The pixel circuit is disposed on one side of the substrate, and the first insulating layer is disposed on the side of the pixel circuit away from the substrate. The first insulating layer has a connection region and a driving region. A first via hole is provided on the connection region, and a micropore array is provided on the driving region. The micropore array includes a plurality of micropores; A light-emitting layer, including a pixel electrode. The pixel electrode is attached to the surface of the first insulating layer away from the substrate, and the pixel electrode is connected to the pixel circuit through the first via hole; A protrusion is formed between any two adjacent micropores, and the surfaces of the plurality of micropores and the surfaces of the plurality of protrusions are connected into a smooth wavy surface. The slope angle of the side surface of the micropore is between 4.5 degrees and 65 degrees.

2. The display panel according to claim 1, wherein The width of the micropore gradually increases in the direction away from the substrate, and the increasing amplitude of the micropore width gradually increases in the direction away from the substrate.

3. The display panel according to claim 1, wherein The light-emitting layer further includes a light-emitting material layer group and a common electrode. The light-emitting material layer group is disposed on the side of the pixel electrode away from the substrate, and the common electrode is disposed on the side of the light-emitting material layer group away from the substrate.

4. The display panel according to claim 3, wherein, The display panel further includes a pixel defining layer, and the pixel defining layer is provided with a pixel opening. The orthographic projection of the micropore array on the substrate at least partially overlaps with the orthographic projection of the pixel opening on the substrate.

5. The display panel according to claim 1, wherein The first insulating layer includes a plurality of microlens units, and each microlens unit is respectively provided with a group of micropore arrays. The orthographic projection of the microlens unit on the pixel defining layer covers the pixel opening, and the distance between the edge of the orthographic projection of the microlens unit on the pixel defining layer and the edge of the pixel opening is between 2 μm and 5 μm.

6. The display panel according to claim 5, wherein The microlens unit includes a plurality of sub-microlenses, and each sub-microlens includes the micropore.

7. The display panel according to claim 6, wherein The orthographic projection shape of the side of the sub-microlens away from the substrate on the substrate includes a hexagon. There is a deflection angle between the straight line where the side of each sub-microlens of the microlens unit is located and the pixel opening, and the deflection angle is less than or equal to 60 degrees.

8. The display panel according to claim 7, wherein The plurality of sub-microlenses of the microlens unit have a variety of different arrangement modes, and the deflection angles of different arrangement modes increase in sequence, and the difference between the deflection angles of two adjacent arrangement modes is greater than or equal to 5 degrees.

9. The display panel according to claim 3, wherein The pixel electrode is a transparent conductive film, the common electrode is a metal reflection layer, and the display panel further includes a color filter layer, and the color filter layer is disposed on the side of the first insulating layer close to the substrate.

10. The display panel according to claim 3, wherein The pixel electrode is a metal reflection layer, the common electrode is a transparent conductive film, and the display panel further includes a color filter layer, and the color filter layer is disposed on the side of the common electrode away from the substrate.

11. The display panel according to claim 9 or 10, characterized in that, The color filter layer includes a black matrix, and the black matrix is provided with a plurality of color-resist openings. A first color-resist block, a second color-resist block, a third color-resist block, and a fourth color-resist block are respectively provided in the color-resist openings. The first color-resist block is red, the second color-resist block is green, the third color-resist block is blue, and the fourth color-resist block is transparent.

12. The display panel according to claim 1, wherein The driving circuit layer includes thin film transistors, and each thin film transistor includes an active layer, a second insulating layer, a gate electrode, a source electrode, and a drain electrode. The active layer is disposed on one side of the substrate. The second insulating layer is disposed on a surface of the active layer away from the substrate, and the second insulating layer covers the active layer. The gate electrode, the source electrode, and the drain electrode are disposed on a surface of the second insulating layer away from the substrate. The source electrode and the drain electrode are respectively connected to the active layer through second vias. The gate electrode is located between the source electrode and the drain electrode, and a positive projection of the gate electrode on the substrate is located within a positive projection of the active layer on the substrate. The pixel electrode is connected to the source electrode or the drain electrode through the first via.

13. The display panel according to claim 12, wherein The display panel further includes a third insulating layer and a light-shielding layer. The light-shielding layer is disposed on one side of the substrate. The third insulating layer is disposed on a surface of the light-shielding layer away from the substrate, and the third insulating layer covers the light-shielding layer. A positive projection of the active layer on the substrate is located within a positive projection of the light-shielding layer on the substrate.

14. A method for manufacturing a display panel according to any one of claims 1 to 13, characterized in that, The method includes: forming the pixel circuit on the substrate, and forming a first insulating layer on a side of the pixel circuit away from the substrate; exposing a connection area of the first insulating layer with all energy, exposing a driving area of the first insulating layer with partial energy, and not exposing other areas of the first insulating layer; developing the exposed first insulating layer to form a first via in the connection area and form a micropore array in the driving area; forming a pixel electrode on a surface of the first insulating layer away from the substrate, and connecting the pixel electrode to the pixel circuit through the first via.

15. A display device, characterized in that, including the display panel according to any one of claims 1 to 13.

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