Low-noise amplifier circuit, radio frequency chip, and radio frequency front-end module

Abstract

The present application discloses a low-noise amplifier circuit, a radio frequency chip and a radio frequency front-end module. The low-noise amplifier circuit comprises an amplification transistor and a bias transistor. The amplification transistor comprises a first amplification unit and a second amplification unit arranged in a first direction. The first amplification unit is an always-on unit, and the second amplification unit is configured to be turned on in accordance with a corresponding gain stage control signal. The bias transistor is connected to the amplification transistor, and the bias transistor comprises a first bias unit and a second bias unit. The first bias unit and the second bias unit are arranged on two sides of the first amplification unit in the first direction, and the first bias unit or the second bias unit is disposed between the first amplification unit and the second amplification unit. The bias transistor is split into at least two bias units, so that the effects of process deviations on gain from the bias transistor and the amplification transistor offset each other, thereby improving the gain accuracy of the low-noise amplifier circuit.

Description

Low-noise amplifier circuits, RF chips, and RF front-end modules

[0001] This application is based on the Chinese patent application with application number 202311853154.0 filed on December 29, 2023 and entitled “Low-noise amplifier circuit, RF chip and RF front-end module”, and claims priority. Technical Field

[0002] The present application relates to the field of radio frequency technology, and in particular to a low-noise amplifier circuit, a radio frequency chip, and a radio frequency front-end module. Background Art

[0003] A low-noise amplifier (LNA) is an amplifier with a very low noise figure. In the RF field, it is usually used as a preamplifier in the receiving channel. It can obtain extremely weak and uncertain signals from the antenna and then amplify the signal to a more useful level.

[0004] Generally, a low noise amplifier includes a bias transistor and an amplifying transistor. The bias transistor provides a bias signal to the amplifying transistor. The sizes of the bias transistor and the amplifying transistor affect the gain of the low noise amplifier.

[0005] However, process variations often occur during the manufacturing process, which can affect the gain of low-noise amplifiers. Therefore, minimizing the impact of process variations on the gain accuracy of low-noise amplifiers is a pressing issue.

[0006] Application Contents

[0007] This application proposes a low-noise amplifier circuit, a radio frequency chip, and a radio frequency front-end module, which can reduce the impact of process errors on the gain of the low-noise amplifier circuit and improve the gain accuracy of the low-noise amplifier circuit.

[0008] In a first aspect, an embodiment of the present application provides a low-noise amplifier circuit, comprising:

[0009] an amplifying transistor, wherein the amplifying transistor includes a first amplifying unit;

[0010] The bias transistor is connected to the amplifying transistor, and the bias transistor includes a first bias unit and a second bias unit. The first bias unit is arranged adjacent to one side of the first amplifying unit; the second bias unit is arranged spaced apart from the first bias unit.

[0011] In a second aspect, an embodiment of the present application provides a low-noise amplifier circuit, comprising:

[0012] an amplifying transistor, disposed in the second layout area;

[0013] The ninth dummy unit and the tenth dummy unit are distributed on both sides of the second layout area along the first direction or the second direction.

[0014] In a third aspect, an embodiment of the present application provides a radio frequency chip, comprising a low-noise amplifier circuit as described in the first or second aspect above.

[0015] In a fourth aspect, an embodiment of the present application provides a radio frequency front-end module, comprising the radio frequency chip of the third aspect.

[0016] The low-noise amplifier circuit, RF chip and RF front-end module of the present application avoid process deviations of the amplifier module by setting dummy units on both sides of the amplifier module, or splitting the bias transistor into at least two bias units and setting them on both sides of the normally-on amplifier unit, so that the effects of the process deviation of the normally-on amplifier unit and the process deviation of the bias transistor on the gain can offset each other, thereby improving the gain accuracy of the low-noise amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] FIG1 shows a circuit schematic diagram of a low-noise amplifier circuit provided in an embodiment of the present application.

[0019] FIG2 shows a schematic diagram of a circuit layout of a low-noise amplifier circuit provided in an embodiment of the present application.

[0020] FIG3 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0021] FIG4 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0022] FIG5 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0023] FIG6 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0024] FIG7 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0025] FIG8 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0026] FIG9 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0027] FIG10 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0028] FIG11 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0029] FIG12 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0030] FIG13 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0031] FIG14 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0032] FIG15 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0033] FIG16 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0034] FIG17 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0035] FIG18 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0036] FIG19 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0037] FIG20 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0038] FIG21 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0039] FIG22 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0040] FIG23 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0041] FIG24 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0042] FIG25 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0043] FIG26 shows another circuit layout diagram of the low-noise amplifier circuit provided in an embodiment of the present application.

[0044] FIG27 shows a circuit schematic diagram of an amplifier transistor in a low-noise amplifier circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the present invention, the following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0046] The terms "first," "second," and so on, used in this application to distinguish between different items, not to describe a specific order. The term "plurality" refers to two or more items. The term "and / or" refers to at least one of the listed items. For example, "A and / or B" can mean any of the following: including A but not B, including B but not A, or including both A and B.

[0047] Furthermore, the terms "include," "comprise," and "have," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0048] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0049] With the advancement of communications technology and the increasing popularity of 5G (5th Generation Mobile Communication Technology), stringent requirements are being placed on various performance specifications of radio frequency front-ends. The low-noise amplifier (LNA), a core component in the RF front-end receive channel, must acquire and amplify extremely weak signals from the antenna. Therefore, its gain factor is a crucial parameter.

[0050] Generally, a low-noise amplifier includes a bias transistor and an amplifier transistor. The bias transistor provides a bias signal to the amplifier transistor. The size ratio of the bias transistor to the amplifier transistor affects the gain accuracy and consistency of the low-noise amplifier. In related technologies, for the convenience of routing, the bias transistor and the amplifier transistor are usually laid out separately during layout design. This leads to inconsistent process deviations between the two, which in turn leads to inaccurate gain coefficients and unsatisfactory gain consistency of the low-noise amplifier. In particular, when the low-noise amplifier is designed with multiple gain gears, the gain difference between different gain gears is inaccurate, which is a very serious problem for the low-noise amplifier.

[0051] In order to solve the above problems, the embodiments of the present application provide a low-noise amplifier circuit, an RF chip and an RF front-end module, which can reduce the impact of process deviations on the gain accuracy of the low-noise amplifier circuit and improve the gain accuracy of the low-noise amplifier circuit. The following will be explained in conjunction with the accompanying drawings.

[0052] In a first aspect, the present application provides a low-noise amplifier circuit 10. As shown in FIG1 , the low-noise amplifier circuit 10 includes an amplifier transistor Ma and a bias transistor Mb, wherein a first end of the amplifier transistor Ma is connected to the bias transistor Mb to receive a bias signal provided by the bias transistor Mb. Furthermore, a first end of the amplifier transistor Ma is also connected to an input end of the low-noise amplifier circuit 10 for receiving a radio frequency input signal RF-in. A first end of the amplifier transistor Ma is connected to an output end of the low-noise amplifier circuit 10 for outputting an amplified radio frequency output signal RF-out. A third end of the amplifier transistor Ma is grounded.

[0053] Optionally, the amplifying transistor Ma and the biasing transistor Mb may be bipolar junction transistors or field-effect transistors. When the amplifying transistor Ma and the biasing transistor Mb are bipolar junction transistors, the first terminal is the base, the second terminal is the collector, and the third terminal is the emitter. When the amplifying transistor Ma and the biasing transistor Mb are field-effect transistors, the first terminal is the gate, the second terminal is the source / drain, and the third terminal is the drain / source. Taking field-effect transistors as an example, illustratively, the amplifying transistor Ma and the biasing transistor Mb may be MOS (metal oxide semiconductor) transistors fabricated on a silicon substrate; or MOS transistors fabricated on an SOI (Silicon-On-Insulator) substrate. The amplifying transistor Ma may be composed of a plurality of amplifying units connected in series and parallel, and the biasing transistor Mb may also be composed of a plurality of biasing units connected in series and parallel.

[0054] As shown in Figure 1, the amplifier transistor Ma and the bias transistor Mb are connected to form a current mirror structure. Taking a MOS transistor as an example, the output current Idd of the amplifier transistor Ma is the product of the reference current Iref of the bias transistor Mb and the mirror ratio. Since the gain accuracy of the amplifier transistor is related to the accuracy of the output current Idd, that is, the accuracy of the mirror ratio, and the mirror ratio depends on the size ratio between the amplifier transistor Ma and the bias transistor Mb, when the process deviations of the amplifier transistor Ma and the bias transistor Mb are inconsistent, the gain accuracy of the low-noise amplifier circuit will be affected. For a low-noise amplifier with multiple gain levels, to ensure gain consistency, it is necessary to have good gain accuracy at each gain level, or to have consistent gain deviations at different gain levels.

[0055] Exemplarily, when the amplifying transistor Ma and the biasing transistor Mb are MOS transistors, the size of the transistor may refer to the width-to-length ratio of the MOS transistor.

[0056] As an embodiment, as shown in FIG1 , the amplifier transistor Ma and the bias transistor Mb can be connected via a bias resistor R. The bias resistor R has a high impedance characteristic for the RF signal, which can prevent the RF signal from leaking to the bias transistor. Optionally, the bias resistor R may include one or more resistance units, and the resistance of the bias resistor R may be fixed or variable. For example, the resistance of the bias resistor R may be adjusted by controlling the number of resistance units that are turned on. Exemplarily, a DC blocking capacitor C may also be provided at the input end of the low-noise amplifier circuit to prevent the DC bias signal from leaking to the input port of the low-noise amplifier circuit.

[0057] It should be understood that in the low-noise amplifier circuit of the present application, in addition to the amplifier transistor Ma, bias transistor Mb, resistor R and DC blocking capacitor C shown in Figure 1, other circuit elements can also be set as needed. For example, the low-noise amplifier circuit can also include one or more capacitors, inductors, resistors, transistors and other elements. These elements can be composed of one or more circuits including but not limited to input matching circuits, output matching circuits, filtering circuits, bypasses, switches, etc. according to circuit design requirements. This application does not impose any restrictions on this.

[0058] Please also refer to FIG2 , which is a schematic diagram of a circuit layout of the low-noise amplifier circuit 10. As shown in FIG2 , the amplifier transistor includes a first amplifier unit Ma1, and the bias transistor Mb includes a first bias unit Mb1 and a second bias unit Mb2. The first bias unit Mb1 and the second bias unit Mb2 are spaced apart, and the first bias unit Mb1 is disposed adjacent to one side of the first amplifier unit Ma1.

[0059] In the embodiment of the present application, the first bias unit Mb1 and the second bias unit Mb2 are spaced apart, which means that the first bias unit Mb1 and the second bias unit Mb2 are not arranged as a continuous whole, but rather as different units that are relatively independent in position. Optionally, the first bias unit Mb1 and the second bias unit Mb2 can be separated by a certain distance or at least one circuit unit. For example, the first bias unit Mb1 and the second bias unit Mb2 can be separated by the first amplifier unit Ma1 or other circuit units.

[0060] Taking the MOS transistor as an example, the amplifying transistor and the biasing transistor respectively include a gate, a source, and a drain, and the gate, source, and drain are respectively designed in a finger-like shape, where the arrangement direction of the fingers is the width direction of the transistor. In the related art, all the fingers of the same pole are arranged continuously in a row along the same direction. However, the embodiment of the present application splits the biasing transistor Mb into a first biasing unit Mb1 and a second biasing unit Mb2. For example, the gate, source, and drain of the biasing transistor Mb can be split into multiple sections, each section including a certain number of fingers, and the fingers of the same pole are connected to each other so that the first biasing unit Mb1 and the second biasing unit Mb2 are connected in parallel. Optionally, the number of gate fingers of the first biasing unit Mb1 and the number of gate fingers of the second biasing unit Mb2 can be the same or different. Exemplarily, the gate of the first biasing unit Mb1 and the gate of the second biasing unit Mb2 can respectively include 2-5 fingers, and the size of each gate finger is approximately equal. As an illustration, FIG2 splits the bias transistor having six gate fingers into a first bias unit Mb1 and a second bias unit Mb2 each having three gate fingers.

[0061] Optionally, in order to make the layout density of the bias transistor uniform, the gate fingers of different bias units can be arranged in the same direction. The gate fingers of different bias units can be arranged in the same row or in multiple rows. For example, the first bias unit Mb1 and the second bias unit Mb2 each include at least two gate fingers, wherein at least two gate fingers in the first bias unit Mb1 are arranged along the first direction, and at least two gate fingers in the second bias unit Mb2 are also arranged along the first direction. When the second bias unit Mb2 is located on one side of the first bias unit Mb1 in the first direction, the gate fingers in the first bias unit Mb1 and the second bias unit Mb2 are arranged in a row. When the second bias unit Mb2 is located on one side of the first bias unit Mb1 in the second direction, the gate fingers in the first bias unit Mb1 and the gate fingers in the second bias unit Mb2 are arranged in different rows.

[0062] As an implementation manner, the gate fingers in the first amplifying unit are arranged in the same direction as the gate fingers in the bias transistor, so that the layout of the low-noise amplifier circuit is more orderly and the density is more uniform.

[0063] During the manufacturing process, process deviations usually occur where the circuit density changes significantly. Therefore, the closer to the edge of the layout area, the greater the process deviations tend to be. In related technologies, the bias transistors are continuously laid out as a whole along a fixed direction, and the amplifier transistors are also laid out as a whole along the same direction as the bias transistors. Therefore, process deviations are often concentrated on the bias transistors or the amplifier transistors. The process deviations of the two differ greatly, resulting in changes in the size ratio of the two, which in turn affects the gain of the low-noise amplifier. In particular, the size of the bias transistor Mb is usually smaller than that of the amplifier transistor Ma. When the process deviation on the bias transistor Mb is greater than the process deviation on the amplifier transistor Ma, the error in the size ratio of the two will be further exacerbated, which will have a particularly serious impact on the gain accuracy and consistency.

[0064] In the embodiment of the present application, the smaller bias transistor Mb is split into at least two bias units, and the at least two bias units are spaced apart, thereby avoiding the concentration of process deviations on the bias transistor Mb. Moreover, the first bias unit Mb1 and the first amplification unit Ma1 are located close to each other, and the process deviations of the two are also relatively close, which has little impact on the size ratio. Therefore, the effects of the process deviations of the two on the gain of the low-noise amplifier circuit can offset each other to a certain extent, thereby improving the gain accuracy of the low-noise amplifier circuit.

[0065] In some embodiments, as shown in Figure 2, the first bias unit Mb1 is disposed on one side of the first amplifying unit Ma1 in the first direction, and the second bias unit Mb2 is disposed on the other side of the first amplifying unit Ma1 in the first direction. In other words, the first bias unit Mb1 and the second bias unit Mb2 are distributed on both sides of the first amplifying unit Ma1 along the first direction. Exemplarily, the first direction is the width direction of the bias transistor Mb. For example, in the case of a MOS transistor, the width direction is the arrangement direction of the gate fingers.

[0066] In the embodiment of the present application, the first bias unit Mb1 and the second bias unit Mb2 are arranged on both sides of the first amplifying unit Ma1. Due to their close positions, the process deviations of the two bias units Mb1 and Mb2 are basically the same as the process deviation of the first amplifying unit Ma1. The effects of the process deviations of the bias units and the amplifying units on the gain can be basically completely offset, which can effectively improve the gain accuracy of the low-noise amplifier circuit.

[0067] Optionally, when the low-noise amplifier circuit includes multiple gain gears, the amplifier transistor may also include one or more other amplifier units other than the first amplifier unit, such as a second amplifier unit or a third amplifier unit. At this time, the first amplifier unit Ma1 can be configured as a normally-on unit, and the other amplifier units can be configured as units that are not normally-on. For example, the first amplifier unit Ma1 is turned on at all gain gears, while the second amplifier unit and the third amplifier unit are turned on only at the corresponding gain gears. Each second amplifier unit / third amplifier unit may correspond to one or more gain gears. When there are multiple second amplifier units / third amplifier units, the low-noise amplifier circuit can turn on a corresponding number of second amplifier units / third amplifier units according to the received gain gear control signal to adjust the gain gear of the low-noise amplifier circuit 10. For example, when the low-noise amplifier circuit 10 is configured to the lowest gain gear, only the first amplifier unit Ma1 can be turned on, and all second amplifier units Ma2 can be turned off; when the low-noise amplifier circuit 10 is configured to the second lowest gain gear, the first amplifier unit Ma1 and one second amplifier unit Ma2 can be turned on; when the low-noise amplifier circuit 10 is configured to the highest gain gear, the first amplifier unit Ma1 and all second amplifier units Ma2 can be turned on. The bias current can be the same or different at different gain gears, and this application does not impose any restrictions on this.

[0068] By arranging the first bias unit Mb1 and the second bias unit Mb2 on both sides of the normally-on first amplifying unit Ma1, no matter how the gain gear of the low-noise amplifier circuit is switched, the influence of the process deviation of the first bias unit Mb1 and the second bias unit Mb2 can be offset by the first amplifying unit Ma1, thereby greatly improving the gain accuracy and consistency of the low-noise amplifier.

[0069] As an embodiment, as shown in FIG3 , the low-noise amplifier circuit further includes a second amplifier unit Ma2. When there are one or more second amplifier units Ma2, the first bias unit Mb1, the first amplifier unit Ma1, and the second bias unit Mb2 are sequentially arranged on one side of the second amplifier unit Ma2 in the first direction. When there are multiple second amplifier units Ma2, the multiple second amplifier units Ma2 can be arranged on the same side of the first amplifier unit Ma1, thereby facilitating the wiring arrangement between the amplifier transistor and the bias transistor.

[0070] For example, as shown in Figure 4, the first bias unit Mb1 is disposed on a side of the first amplifying unit Ma1 away from the second amplifying unit Ma2, and the second bias unit Mb2 is disposed between the first amplifying unit Ma1 and the second amplifying unit Ma2. By interspersing at least one bias unit between different amplifying units, process variations during the manufacturing process can be more evenly distributed across the amplifying transistors and the bias transistors, bringing their process variations closer together and thereby offsetting the effects of process variations on gain.

[0071] Since the first bias unit Mb1 is relatively close to the edge of the layout area, in order to reduce the process deviation of the first bias unit Mb1, the low-noise amplifier circuit is further provided with a first dummy unit Dummy1. The first dummy unit Dummy1 is arranged on the side of the first bias unit Mb1 away from the first amplifier unit Ma1, and is closer to the edge of the layout area than the first bias unit Mb1, so that most of the process deviation can occur in the first dummy unit Dummy1, reducing the process deviation of the first bias unit Mb1 and other units, further reducing the impact of the process deviation on the gain of the low-noise amplifier circuit, and improving the gain accuracy and consistency of the low-noise amplifier circuit.

[0072] Optionally, the size of the first dummy unit Dummy1 is greater than or equal to the size of the first bias unit Mb1. For example, the width of the first dummy unit Dummy1 is greater than or equal to the width of the first bias unit Mb1. This allows process deviations to be more concentrated on the first dummy unit Dummy1, allowing the first bias unit Mb1 and other units to maintain relatively accurate sizes. The width refers to the size in the first direction X.

[0073] As an embodiment, as shown in Figures 5 and 6, the low-noise amplifier circuit further includes a second dummy unit Dummy2, and the second dummy unit Dummy2 is arranged on a side of the second amplifier unit Ma2 away from the second bias circuit Mb2. When the low-noise amplifier circuit includes multiple second amplifier units Ma2, the second dummy unit Dummy2 can be arranged on a side of all second amplifier units Ma2 away from the second bias circuit Mb2, or in other words, all second amplifier units Ma2 are located on the same side of the second dummy unit Dummy2. By arranging the second dummy unit Dummy2 outside the second amplifier unit Ma2, the embodiment of the present application can significantly reduce or even avoid process deviations on the second amplifier unit Ma2, thereby further improving the gain accuracy and consistency of the low-noise amplifier circuit. When the low-noise amplifier circuit is provided with both the first dummy unit Dummy1 and the second dummy unit Dummy2, the amplifier transistor Ma and the bias transistor Mb are sandwiched between the first dummy unit Dummy1 and the second dummy unit Dummy2. The probability of process deviation in each unit of the amplifier transistor Ma and the bias transistor Mb is greatly reduced, thereby effectively avoiding gain errors caused by process deviations and further improving the gain accuracy of the low-noise amplifier circuit. When the low-noise amplifier circuit has multiple gain levels, the consistency of the output current Idd of the amplifier transistor Ma at different gain levels can also be optimized, thereby improving the gain consistency of the low-noise amplifier circuit.

[0074] It can be understood that in some embodiments, if the size of the bias transistor allows, the bias transistor can be split into more bias units, for example, split into 3 or more bias units, and more bias units are staggered with different amplification units, which can further offset the impact of process errors on gain. For example, when the overall size of the bias transistor is large, the number of bias units can be the same as the number of amplification units, and a bias unit is provided between every two amplification units. When the overall size of the bias transistor is small, illustratively, the number of bias units can be less than the number of amplification units. For example, the bias transistor can be split into each bias unit with a width of 2-3 gate fingers. For example, when the overall size of the bias transistor is designed to have 10 gate fingers, the bias transistor can be split into 3-5 bias units and staggered with multiple amplification units.

[0075] As an embodiment, as shown in FIG7 , when there are at least two second amplifying units Ma2, the bias transistor Mb further includes a third biasing unit Mb3, which is disposed between two adjacent second amplifying units. Due to their proximity, the process variations of the two second amplifying units Ma2 and the process variations of the third biasing unit Mb3 are substantially the same, and the effects of these process variations on gain can be substantially completely offset. Therefore, when the low-noise amplifier circuit is configured to require switching on the gain levels of at least some of the second amplifying units Ma2, this embodiment can further offset the effects of these process variations on gain, making the gain difference between different gain levels more accurate.

[0076] As an embodiment, the low-noise amplifier has multiple gain gears, wherein the first amplifying unit Ma1 is a normally-on amplifying unit that is turned on at all gain gears; the second amplifying unit Ma2 is an amplifying unit that is not normally-on and is used to be turned on according to the corresponding gain gear control signal. Each second amplifying unit can correspond to one or more gain gears and can be turned on at one or more gain gears. When the number of third biasing units Mb3 is at least 2 less than the number of second amplifying units Ma1, the third biasing unit Mb3 is arranged between the two second amplifying units with a larger number of corresponding gain gears, so that the influence of the process deviation of the bias transistor and the amplifying transistor can be offset at as many gain gears as possible.

[0077] In some embodiments, when there are multiple second amplifying units Ma2, as shown in FIG8 , the first amplifying unit Ma1 can be disposed between two of the second amplifying units Ma2, or in other words, the multiple second amplifying units Ma2 can be distributed on both sides of the first amplifying unit Ma1 along the first direction X. Specifically, some of the second amplifying units Ma2 are disposed on the side of the first bias unit Mb1 away from the first amplifying unit Ma1, while other parts of the second amplifying units Ma2 are disposed on the side of the second bias unit Mb2 away from the first amplifying unit Ma1. In this embodiment, the first amplifying unit Ma1 is located away from the edge of the layout area, and the bias transistor is split into two bias units and disposed on both sides of the first amplifying unit Ma1. This allows the bias units to be away from the edge of the low-noise amplifier circuit layout area, thereby significantly reducing the probability of process variation in the bias transistor. Even if there is still a small amount of process variation in the two bias units, its impact on gain can be offset by the process variation of the first amplifying unit Ma1, thereby effectively reducing the mismatch between the bias transistor and the amplifying transistor and improving the gain consistency of the low-noise amplifier circuit.

[0078] As an embodiment, the first amplifier unit Ma1 is a normally-on amplifier unit, that is, the first amplifier unit Ma1 is turned on at all gain levels. Placing the normally-on first amplifier unit Ma1 between multiple second amplifier units and placing the normally-on first amplifier unit Ma1 near the center of the layout area not only offsets the effects of process deviations of the bias transistor at most gain levels, but also significantly reduces the probability of process deviations occurring in the normally-on amplifier unit. This improves gain accuracy and consistency better than placing the normally-on first amplifier unit Ma1 at the edge of the layout area.

[0079] As an embodiment, when there are multiple second amplifying units Ma2, the second amplifying units Ma2 with more corresponding gain levels can be set closer to the center of the low-noise amplifier circuit layout area to optimize the Idd current consistency under as many gain levels as possible, thereby optimizing the gain consistency.

[0080] As an embodiment, as shown in FIG9 , the bias transistor Mb further includes at least one fourth bias unit Mb4, which is disposed on a side of the second amplifying unit away from the first bias unit and / or the second bias unit. Optionally, the number of the fourth bias units Mb4 may be equal to or less than the number of the second amplifying units Ma2. When the number of the fourth bias units Mb4 is equal to the number of the second amplifying units Ma2, a fourth bias unit Mb4 may be disposed on a side of each second amplifying unit Ma2 away from the first amplifying unit Ma1, that is, the bias units are arranged in an alternating pattern with the amplifying units so that both sides of each amplifying unit are biased. In this way, the effect of process deviation on the gain of each amplifying unit can be offset by the effect of the bias units on both sides, thereby maximizing the Idd current consistency and optimizing the gain consistency.

[0081] Optionally, when the number of fourth bias units Mb4 is less than the number of second amplifying units Ma2, the fourth bias unit Mb4 is positioned next to the second amplifying unit Ma2 corresponding to a greater number of gain levels. For example, when there is only one fourth bias unit Mb4, it is positioned on one side of the second amplifying unit Ma2 corresponding to the greatest number of gain levels. In this way, at most gain levels, the effects of process variations of the second amplifying unit Ma2 and the fourth bias unit Mb4 can offset each other.

[0082] In some embodiments, some dummy units may be provided to make the layout density inside the low-noise amplifier circuit more uniform.

[0083] In some embodiments, at least one dummy unit, such as a fourth dummy unit and / or a fifth dummy unit, may be further provided on at least one side of the fourth bias unit Mb4.

[0084] As an embodiment, as shown in FIG10 , the low-noise amplifier circuit further includes a third dummy unit Dummy3, and the third dummy unit Dummy3 is arranged on a side of the fourth bias unit Mb4 away from the second amplifying unit Ma2. Optionally, the number of the third dummy unit Dummy3 can be one or more. The number of the third dummy units Dummy3 can be the same as the number of the fourth bias units Mb4, for example, the third dummy unit Dummy3 is arranged on one side of each fourth bias unit Mb4. The number of the third dummy units Dummy3 can also be less than the number of the fourth bias units Mb4, for example, the third dummy unit Dummy3 is only arranged on one side of some of the fourth bias units Mb4. For example, as shown in FIG10 , when the number of third dummy units Dummy3 is two, the two third dummy units Dummy3 can be respectively arranged on both sides farthest from the first amplifying unit Ma1, that is, at the edge of the transistor layout area. This can keep each unit in the amplifying transistor Ma and the biasing transistor Mb away from the edge position, greatly reducing the probability of process deviation of the amplifying transistor Ma and the biasing transistor Mb, and reducing the mismatch between the amplifying transistor Ma and the biasing transistor Mb, thereby optimizing the gain consistency of the low-noise amplifier circuit. Optionally, the size of the third dummy unit Dummy3 can be greater than or equal to the size of the fourth biasing unit Mb4.

[0085] As an optional embodiment, as shown in Figure 11, the low-noise amplifier circuit further includes a fourth dummy unit Dummy4, which is arranged on the side of the fourth bias unit Mb4 close to the second amplifying unit Ma2. Optionally, the number of the fourth dummy unit Dummy4 can be one or more. The number of the fourth dummy units Dummy4 can be the same as the number of the fourth bias units Mb4, for example, a fourth dummy unit Dummy4 is arranged on the side of each fourth bias unit Mb4 close to the second amplifying unit Ma2. The number of the fourth dummy units Dummy4 can also be less than the number of the fourth bias units Mb4, for example, the fourth dummy unit Dummy4 is only arranged on the side of some of the fourth bias units Mb4 close to the second amplifying unit. By adding the fourth dummy unit Dummy4, at least some of the fourth bias units Mb4 are arranged between the two dummy units, so that the layout density of the area where the fourth bias unit Mb4 is located is more uniform, thereby reducing the probability of process deviation of the fourth bias unit Mb4.

[0086] Further optionally, the size of the fourth dummy unit Dummy4 is the same as the size of the third dummy unit Dummy3 , and both sizes are greater than or equal to the size of the fourth bias unit Mb4 .

[0087] In some embodiments, a pair of dummy units, such as a fifth dummy unit Dummy5 and / or a sixth dummy unit Dummy6 , may be further provided on both sides of the first bias unit Mb1 and / or the second bias unit Mb2 .

[0088] Exemplarily, as shown in Figures 12 and 13, the low-noise amplifier circuit further includes at least two fifth dummy units Dummy5 and at least two sixth dummy units Dummy6, wherein at least two fifth dummy units Dummy5 are arranged on both sides of the first bias unit Mb1; and at least two sixth dummy units Dummy6 are arranged on both sides of the second bias unit. Optionally, the size of each fifth dummy unit Dummy5 is the same as the size of the first bias unit Mb1, and the size of each sixth dummy unit Dummy6 is the same as the size of the second bias unit Mb2. By respectively arranging corresponding dummy units on both sides of the first bias unit Mb1 and the second bias unit Mb2, the layout density of the area where the first bias unit Mb1 and the second bias unit Mb2 are located can be made more uniform, and the finger morphology of the bias transistor can be made more consistent, thereby reducing the probability of process deviation of the first bias unit Mb1 and the second bias unit Mb2, and further optimizing the gain consistency of the low-noise amplifier circuit.

[0089] In some embodiments, in addition to the first amplifying unit Ma1 , the amplifying transistor further includes a third amplifying unit Ma3 , wherein the third amplifying unit Ma3 is located on one side or both sides of the first amplifying unit Ma1 in the second direction Y.

[0090] Optionally, the number of the third amplifying units Ma3 may be one or more. When the number of the third amplifying unit Ma3 is one, the third amplifying unit Ma3 is located on one side of the first amplifying unit Ma1 in the second direction Y. When the number of the third amplifying unit Ma3 is multiple, the multiple third amplifying units Ma3 may be located on the same side of the first amplifying unit Ma1 in the second direction Y, or may be distributed on both sides of the first amplifying unit Ma1 along the second direction Y. The first direction X is the width direction of the transistor. Taking the MOS transistor as an example, the first direction is the arrangement direction of the gate fingers. The second direction Y is a direction substantially perpendicular to the first direction X, such as the length direction of the gate fingers.

[0091] When the amplifying transistor Ma further includes a third amplifying unit Ma3, one bias unit is disposed on one side of the first amplifying unit Ma1, and the other bias unit is disposed on one side of the third amplifying unit Ma1. For example, as shown in FIG14 , the first bias unit Mb1 is disposed on one side of the first amplifying unit Ma1 in the first direction X, and the second bias unit Mb2 is disposed on one side of the third amplifying unit Ma3 in the first direction X. Because the first bias unit Mb1 and the first amplifying unit Ma1 are positioned close together, the effects of their process variations on gain can be offset; and because the second bias unit Mb2 and the third amplifying unit Ma3 are positioned close together, the effects of their process variations on gain can be offset, thereby improving the gain accuracy and consistency of the low-noise amplifier circuit.

[0092] Optionally, the first bias unit Mb1 and the second bias unit Mb2 may be arranged relative to each other in the second direction, as shown in (a) of FIG. 14 , so as to facilitate the connection between the first bias unit Mb1 and the second bias unit Mb2 .

[0093] Optionally, the first bias unit Mb1 and the second bias unit Mb2 can be staggered in the second direction, as shown in (b) in Figure 14. This can make the process deviation of the amplifying transistor closer to the process deviation of the bias transistor, better offset the impact on the gain, and further optimize the gain consistency.

[0094] As an embodiment, as shown in Figures 15 and 16, the number of second bias units Mb2 can be at least two, wherein each second bias unit Mb2 is disposed on one side of a third amplifying unit Ma3 in the first direction. Optionally, the number of second bias units Mb2 is less than or equal to the number of third amplifying units Ma3.

[0095] When the number of second bias units Mb2 is equal to the number of third amplifying units Ma3, as shown in FIG15 , a second bias unit Mb2 is provided next to each third amplifying unit Ma3. In this way, the effects of the process errors of each amplifying unit and its adjacent bias units can offset each other, thereby greatly improving the gain accuracy and consistency of the low-noise amplifier circuit.

[0096] When the bias transistor is small and the number of split bias units is less than the number of gain levels of the low-noise amplifier, the number of second bias units Mb2 is less than the number of third amplifying units Ma3. In this case, a second bias unit Mb2 can be positioned adjacent to some of the third amplifying units Ma3. Alternatively, each third amplifying unit Ma3 corresponds to one or more gain levels. When the number of second bias units Mb2 is less than the number of third amplifying units Ma3, the second bias unit Mb2 is positioned adjacent to the third amplifying unit Ma3 corresponding to a greater number of gain levels, thereby offsetting the effects of process errors on gain at as many gain levels as possible.

[0097] As an embodiment, as shown in FIG16 , the low-noise amplifier circuit further includes at least one seventh dummy unit Dummy7; the number of the third amplifier units is at least two, at least two of the third amplifier units are arranged along the second direction, and at least one of the third amplifier units is provided with the seventh dummy unit Dummy7 on one side of the first direction. For example, when the number of second bias units Mb2 is less than the number of third amplifier units Ma3, some of the third bias units Mb2 are not provided with a second bias unit Mb2 in the first direction, then a seventh dummy unit can be provided in the first direction of the third bias unit Mb2, so that the layout area of ​​the low-noise amplifier circuit is roughly rectangular, making the density of the transistors in the layout more uniform and the consistency of the finger stripe morphology better, thereby reducing process deviation and further improving the consistency of the Idd current and the gain consistency.

[0098] As an embodiment, when there are multiple third amplifying units Ma3 and each third amplifying unit Ma3 corresponds to one or more gain levels, the third amplifying units Ma3 with more corresponding gain levels can be arranged at a position closer to the center of the layout area of ​​the low-noise amplifier circuit, so as to avoid or reduce the occurrence of process deviations at as many gain levels as possible.

[0099] As an embodiment, as shown in Figures 17 and 18, the low-noise amplifier circuit includes a first amplifier unit Ma1, at least one second amplifier unit Ma2, and at least two third amplifier units Ma3, wherein the second amplifier unit Ma2 is arranged in the first direction X of the first amplifier unit Ma1, and the third amplifier unit Ma3 is arranged in the second direction Y of the first amplifier unit Ma1. The number of third amplifier units Ma3 can be greater than the number of second amplifier units Ma2, and at least two third amplifier units Ma3 can be arranged along the first direction X and arranged in an array with the first amplifier unit Ma1 and the second amplifier unit Ma2. In this way, the layout area of ​​the low-noise amplifier circuit can be roughly rectangular, the density of the transistors in the layout can be more uniform, the consistency of the finger morphology can be better, thereby reducing process deviations and further improving the consistency of Idd current and gain consistency.

[0100] Optionally, as shown in FIG17 , the first bias unit Mb1 can be disposed between the first amplifying unit Ma1 and one of the second amplifying units Ma2 to keep the first bias unit Mb1 away from the edge of the layout area, thereby avoiding or reducing process deviations on the first bias unit Mb1. Since the bias unit is relatively small in size, its process deviation has a relatively large impact on the gain. Therefore, by reducing the process deviations on the bias unit, the mismatch between the bias transistor and the amplifying transistor can be effectively reduced, thereby improving the accuracy and consistency of the gain. Similar to the first bias unit Mb1, the second bias unit Mb2 can also be disposed between the two third amplifying units Ma4 to reduce the mismatch between the bias transistor and the amplifying transistor, thereby improving the accuracy and consistency of the gain.

[0101] Optionally, as shown in FIG18 , the first bias unit Mb1 may also be disposed on a side of the first amplifying unit Ma1 close to an edge of the layout area to facilitate layout of circuit traces; similarly, the second bias unit Mb2 may also be disposed on a side of the third amplifying unit Ma3 close to an edge of the layout area.

[0102] Optionally, in this embodiment, the first bias unit Mb1 and any second bias unit Mb2 may be opposite or offset in the second direction Y. When the first bias unit Mb1 and the second bias unit Mb2 are opposite in the second direction Y, they can be connected in parallel. When the first bias unit Mb1 and the second bias unit Mb2 are offset in the second direction Y, gain errors caused by process variations can be better offset, further optimizing gain consistency.

[0103] In one embodiment, the first amplifying unit Ma1 is a normally-on amplifying unit, and the other amplifying units, such as the second amplifying unit Ma2 and the third amplifying unit Ma3, are not normally-on amplifying units and are only turned on at certain gain levels. To avoid process deviations at as many gain levels as possible, the second amplifying unit Ma2 and the third amplifying unit Ma3 corresponding to more gain levels are optionally arranged closer to the center of the low-noise amplifier circuit layout area.

[0104] In some embodiments, in order to avoid or reduce process deviations of the amplifying transistor and the biasing transistor, some dummy units may be provided around the amplifying transistor and the biasing transistor.

[0105] As an embodiment, as shown in Figures 19 and 20, the low-noise amplifier circuit further includes two eighth dummy units Dummy8, which are arranged relative to each other in a first direction and / or relative to each other in a second direction, wherein the bias transistor Mb and the amplifier transistor Ma are sandwiched between the two relative eighth dummy units Dummy8. By adding the eighth dummy unit Dummy8 to the periphery, the amplifier transistor Ma and the bias transistor Mb can be located in an area with uniform layout density in at least one direction, so that the finger morphology consistency of the area where the amplifier transistor Ma and the bias transistor Mb are located is better, thereby effectively avoiding or reducing process deviations, and improving the gain accuracy and consistency of the low-noise amplifier circuit.

[0106] As an embodiment, the bias transistor and the amplifier transistor are located in the first layout area. As shown in FIG20 , there are four eighth dummy units Dummy8, which are arranged around the first layout area. This makes the layout density of the area where the amplifier transistor Ma and the bias transistor Mb are located more uniform and the finger morphology more consistent, thereby further avoiding or reducing process deviations and improving the gain accuracy and consistency of the low-noise amplifier circuit.

[0107] Optionally, the size of the eighth dummy unit Dummy8 in the second direction Y may be equal to the size of the first layout area in the second direction, so that the layout density of the first layout area is more uniform and the finger morphology is more consistent.

[0108] Optionally, the two eighth dummy units Dummy8 disposed opposite each other in the first direction of the first layout area may have a size in the first direction greater than or equal to the size of the first layout area, so as to cover the projection of the first amplifying unit Ma1 in the width direction. This can significantly reduce or even avoid process variations in the amplifying transistor Ma and the biasing transistor Mb. When some dummy units are further disposed in the first layout area, the eighth dummy unit Dummy8 also covers the projection of these dummy units in the width direction, thereby making the layout density of the entire low-noise amplifier circuit more uniform and the finger profile more consistent, thereby reducing the probability of process variations occurring in the amplifying transistor and the biasing transistor.

[0109] Optionally, each eighth dummy unit Dummy8 may be an independent unit, wherein some or all of the eighth dummy units Dummy8 may also be interconnected to form a whole as shown in FIG. 21 , and the present application does not impose any limitation on this.

[0110] Similarly, any dummy unit Dummy8 can be a continuous whole or divided into multiple sub-units. Taking the MOS tube as an example, if the gate fingers / source fingers / drain fingers of the eighth dummy unit Dummy8 are continuously arranged in one direction, the eighth dummy unit Dummy8 can be considered as a whole. If the gate fingers / source fingers / drain fingers of the eighth dummy unit Dummy8 are divided into multiple discontinuous segments, the corresponding part of each segment can be regarded as a sub-unit. For example, as shown in Figure 22, the eighth dummy unit Dummy8 includes multiple sub-units, and different sub-units are respectively opposite to different amplification units or bias units or dummy units sandwiched between the amplification units and the bias units, so that the layout density around the amplification units and the bias units can be more uniform and the finger strip morphology can be more consistent.

[0111] In some embodiments, as shown in Figures 23 and 24, the low-noise amplifier circuit 10 includes an amplifier transistor Ma, a ninth dummy unit Dummy9, and a tenth dummy unit Dummy10. The amplifier transistor Ma is disposed in the second layout area 101. The ninth dummy unit Dummy9 and the tenth dummy unit Dummy10 are distributed on both sides of the second layout area 101 along the first direction X or the second direction Y. By adding dummy units on both sides of the second layout area 101, the process deviation of the amplifier transistor Ma can be avoided or reduced, thereby improving the gain accuracy of the low-noise amplifier circuit. When the amplifier transistor Ma includes multiple amplifier units, that is, when the low-noise amplifier circuit has multiple gain gears, the consistency of the gain under different gain gears can also be improved.

[0112] Optionally, the amplifying transistor Ma may adopt a current biasing method or a voltage biasing method.

[0113] When the amplifier transistor Ma adopts a voltage biasing method, a bias transistor may not be provided in the low-noise amplifier circuit 10. In this case, the amplifier transistor Ma can directly receive a bias voltage, which can be provided by other bias circuits, or can be a power supply voltage Vdd or a voltage obtained by dividing the power supply voltage Vdd. This application does not limit this. When the voltage biasing method is adopted, the accuracy of the output current Idd of the amplifier transistor Ma is related to its own dimensional accuracy. Therefore, reducing the process deviation on the amplifier transistor Ma can also improve the gain accuracy of the low-noise amplifier circuit. When the low-noise amplifier circuit has multiple gain gears, it can also improve the consistency of the output current Idd and the gain consistency under different gain gears.

[0114] As an embodiment, the amplifier transistor Ma adopts a current biasing method. The low-noise amplifier circuit 10 also includes a bias transistor Mb, which is arranged in the second layout area 101 and connected to the amplifier transistor Ma. Arranging the bias transistor Mb and the amplifier transistor Ma together in the second layout area 101 can reduce the mismatch between the bias transistor Mb and the amplifier transistor Ma, improve the accuracy of the output current Idd of the amplifier transistor Ma, and thus optimize the gain accuracy of the low-noise amplifier circuit. When the amplifier transistor Ma has multiple gain levels, it can also improve the accuracy of the output current Idd at different gain levels, thereby optimizing the gain consistency of the low-noise amplifier circuit 10.

[0115] For example, as shown in FIG23 , when the ninth dummy unit Dummy9 and the tenth dummy unit Dummy10 are distributed on both sides of the second layout area 101 along the second direction Y, the width of the ninth dummy unit Dummy9 and the width of the tenth dummy unit Dummy10 are greater than or equal to the width of the second layout area 101 and cover the projection of the second layout area 101 in the width direction. Here, the width refers to the dimension along the first direction X, and the width direction is the first direction X. Optionally, the dimensions of the ninth dummy unit Dummy9 and the tenth dummy unit Dummy10 in the second direction Y may be the same or different.

[0116] For example, as shown in FIG24 , when the ninth dummy unit Dummy9 and the tenth dummy unit Dummy10 are distributed on both sides of the amplifying module along the first direction X, the length of the ninth dummy unit Dummy9 and the length of the tenth dummy unit Dummy10 are greater than or equal to the length of the amplifying module and cover the projection of the amplifying module 101 in the length direction. Here, the length refers to the dimension along the second direction Y, and the length direction is the second direction Y.

[0117] Optionally, similar to the eighth dummy unit Dummy8 , any one of the ninth dummy unit Dummy9 and the tenth dummy unit Dummy10 in this embodiment may be a continuous whole, or may be divided into a plurality of discontinuous sub-units.

[0118] As an embodiment, as shown in FIG25 , the dummy module further includes an eleventh dummy unit and a twelfth dummy unit; wherein the eleventh dummy unit Dummy11, the twelfth dummy unit Dummy12, and the ninth dummy unit Dummy9 and the tenth dummy unit Dummy10 are arranged along the periphery of the second layout area 101. For example, if the ninth dummy unit Dummy9 and the tenth dummy unit Dummy10 are arranged on both sides of the second layout area 101 along the first direction X, then the eleventh dummy unit Dummy11 and the twelfth dummy unit Dummy12 are arranged on both sides of the second layout area 101 along the second direction Y. If the ninth dummy unit Dummy9 and the tenth dummy unit Dummy10 are arranged on both sides of the second layout area 101 along the second direction Y, then the eleventh dummy unit Dummy11 and the twelfth dummy unit Dummy12 are arranged on both sides of the second layout area 101 along the first direction X.

[0119] Alternatively, similar to the plurality of eighth dummy cells Dummy8, the ninth dummy cell Dummy9, the tenth dummy cell Dummy10, the eleventh dummy cell Dummy11, and the twelfth dummy cell Dummy12 can be spaced apart and discontinuous dummy cells. Alternatively, at least some of the dummy cells can be arranged continuously. For example, the four dummy cells can be arranged continuously to form a whole in a zigzag shape surrounding the second layout area 101.

[0120] In the embodiment of the present application, the amplifying transistor Ma may include at least one amplifying unit, for example, at least a first amplifying unit Ma1, and may further include at least one of a second amplifying unit Ma2 and a third amplifying unit Ma3. The biasing transistor Mb may include at least two biasing units, for example, at least one of a second biasing unit Mb2, a third biasing unit Mb3, and a fourth biasing unit Mb4, and the first biasing unit Mb1.

[0121] Among them, regarding the specific implementation of each bias unit and each amplification unit, please refer to Figures 2 to 22 and the relevant description above, which will not be repeated here.

[0122] It is understood that in the low-noise amplifier circuit of the embodiment of the present application, the number of amplifier transistors can be one or more, and similarly, the number of bias transistors can be one or more. The present application does not limit the number of amplifier transistors or bias transistors, as long as at least one amplifier transistor and its corresponding bias transistor adopt the layout of any of the above embodiments.

[0123] As an embodiment, when the low-noise amplifier circuit includes at least two amplifier transistors, if the two amplifier transistors have different sizes in the second direction, the two amplifier transistors can be arranged along the second direction, where the second direction is the length direction of the transistor. Taking a MOS tube as an example, when the gate lengths of the two amplifier units are different, if they are arranged along the gate width direction, the layout area will be irregular in shape and the layout density will be uneven. However, if they are arranged along the gate length direction, even if the gate widths are different, the layout area can be roughly rectangular by splitting or adding dummy units, and the density inside the layout area is more uniform, the finger stripe morphology is more consistent, and process deviation is less likely to occur. For example, two amplifier transistors are connected to form a common source and common gate structure. The gate lengths of the two amplifier transistors are different, and one of the amplifier transistors can be arranged in the second direction (i.e., the gate length direction) of the other amplifier transistor. In this way, the voltage gain of the low-noise amplifier circuit can be improved, and the gain effect caused by process errors can be avoided or reduced.

[0124] As an embodiment, when a plurality of amplifying transistors are arranged along the second direction, the second layout area can be divided into a plurality of sub-areas arranged along the second direction, such as the first sub-area and the second sub-area shown in FIG26 . Each sub-area corresponds to at least one amplifying transistor, and the amplifying transistor is arranged in the corresponding sub-area. If the amplifying transistor adopts a current biasing method, its corresponding biasing transistor is also arranged in the same sub-area. Furthermore, when the sizes of different sub-areas along the second direction are different, one or more dummy units can be set between two adjacent sub-areas so that the layout density around each sub-area is similar to or consistent with the layout density of the sub-area, thereby avoiding process deviations of the amplifying transistors and their biasing transistors inside the sub-area. For example, the low-noise amplifier circuit further includes at least one thirteenth dummy unit Dummy13, which is arranged in the second layout area and located between two adjacent sub-areas. For example, as shown in FIG26 , a fourteenth dummy unit Dummy14 is provided between the first sub-region and the second sub-region, wherein the thirteenth dummy unit Dummy14 is adjacent to the fourteenth dummy unit Dummy14. The size of the thirteenth dummy unit Dummy13 can be the same as that of the adjacent sub-region, such as the first sub-region, so that the layout density of the first sub-region is closer to that of the surrounding area; the size of the fourteenth dummy unit Dummy14 can be the same as that of the adjacent sub-region, such as the second sub-region, so that the layout density of the second sub-region is closer to that of the surrounding area. This can further improve the gain accuracy of the low-noise amplifier.

[0125] As an implementation method, more dummy units can be set in the second layout area. For example, in some sub-areas, at least one of the second dummy unit Dummy2, the third dummy unit Dummy3, the fourth dummy unit Dummy4, the fifth dummy unit Dummy5, ​​the sixth dummy unit Dummy6, and the seventh dummy unit Dummy7 mentioned in the above embodiments can be set. The specific matters and methods can be referred to the previous text and will not be repeated here.

[0126] It can be understood that each of the above-mentioned dummy units can have the same structure as the amplifying unit or the biasing unit, for example, they all include a gate, a source, and a drain. Unlike the amplifying unit and the biasing unit, the dummy unit is not connected to the circuit and does not participate in the working process of the low-noise amplifier circuit. It can be understood that since the dummy unit does not participate in the work of the low-noise amplifier circuit, the present application does not limit the electrical connection relationship between the source, drain, and gate of the dummy unit, as long as it does not affect the work of the low-noise amplifier circuit. For example, the source, drain, and gate of each dummy unit can be set to a floating state and not connected to other transistors or wiring in the low-noise amplifier circuit. For another example, the source, drain, and gate of each dummy unit can be short-circuited to each other or grounded, etc.

[0127] Optionally, the biasing methods used by different amplifier transistors may be the same or different. At least some of the amplifier transistors may be current biased and connected to corresponding bias transistors, and at least some of the amplifier transistors that use current biasing and their bias transistors may be arranged in a layout as shown in any of the above embodiments in FIG. 2-25 .

[0128] Optionally, some amplifier transistors in the low-noise amplifier circuit can be voltage-biased. These amplifier transistors can directly receive a bias voltage without being connected to a bias transistor. This bias voltage can be provided by another bias circuit, or it can be the supply voltage Vdd, or a voltage obtained by dividing the supply voltage Vdd. This application does not limit this.

[0129] For example, when two amplifier transistors are connected to form a cascode structure, one amplifier transistor Ma in the cascode structure is connected to the bias transistor Mb, and the other amplifier transistor in the cascode structure receives a bias voltage.

[0130] Alternatively, the low-noise amplifier circuit includes at least two bias transistors, and the two amplifier transistors Ma in a common-source common-gate structure are respectively connected to corresponding bias transistors Mb.

[0131] As an example, as shown in FIG26 , the low-noise amplifier circuit includes an amplifier transistor Ma, an amplifier transistor Mc, and a bias transistor Mb, wherein the amplifier transistor Ma is connected to the bias transistor Mb, and the bias transistor Mb provides a bias for the amplifier transistor Ma. The amplifier transistor Ma and the bias transistor Mb can adopt the layout described in any of the above embodiments. The amplifier transistor Mc is connected to the amplifier transistor Ma to form a common source and common gate structure. In this example, the amplifier transistor Mc adopts a voltage bias, and its gate directly receives the bias power supply Vbias without being connected to the bias transistor.

[0132] In other implementations, the amplifier transistor Mc may also be current biased, and its gate may be connected to another bias transistor. The layout between the bias transistor and the amplifier transistor Mc may refer to the layout between the bias transistor Mb and the amplifier transistor Ma, or may be different therefrom.

[0133] It should be noted that the embodiments of the present application do not limit the circuit architecture of the low-noise amplifier circuit. For example, using MOS transistors as an example, the low-noise amplifier circuit of the embodiments of the present application can adopt architectures including but not limited to the following: common-gate architecture, conventional cascode architecture, folded cascode architecture, negative feedback architecture, distributed architecture, architecture with source degeneration inductor, architecture based on GM boost technology, etc.

[0134] The third aspect of the present application further provides a radio frequency chip, which may include a low-noise amplifier circuit as in any of the above embodiments. The low-noise amplifier circuit in the chip avoids process deviations by setting dummy units on both sides of the amplifier transistor layout area, or splitting the bias transistor into at least two bias units so that the at least two bias units are spaced apart, thereby avoiding process deviations from being concentrated on the bias transistor. Moreover, the bias unit is set adjacent to the amplifier unit, and the effects of the process deviations of the two on the gain of the low-noise amplifier circuit can offset each other to a certain extent, thereby improving the gain accuracy of the low-noise amplifier circuit. When the low-noise amplifier circuit has multiple gain gears, it can also optimize the consistency of the output current Idd of the amplifier transistor Ma under different gain gears, thereby improving the gain consistency of the low-noise amplifier circuit.

[0135] A fourth aspect of the present application further provides a radio frequency front-end module, which is a component that integrates two or more discrete components, such as a radio frequency switch, a low-noise amplifier, a filter, a duplexer, and a power amplifier, into a single module, thereby improving integration and hardware performance while miniaturizing the module. Specifically, the radio frequency front-end module can be applied to 4G and 5G communication devices such as smartphones, tablets, and smart watches.

[0136] The RF front-end module of the embodiment of the present application may include the aforementioned chip, or include a low-noise amplifier circuit as in any of the above embodiments. The low-noise amplifier circuit in the RF front-end module avoids process deviations by setting dummy units on both sides of the amplifier transistor layout area, or splitting the bias transistor into at least two bias units so that the at least two bias units are spaced apart, thereby avoiding process deviations from being concentrated on the bias transistor. Moreover, the bias unit is arranged adjacent to the amplifier unit, and the effects of the process deviations of the two on the gain of the low-noise amplifier circuit can offset each other to a certain extent, thereby improving the gain accuracy of the low-noise amplifier circuit. When the low-noise amplifier circuit has multiple gain gears, it can also optimize the consistency of the output current Idd of the amplifier transistor Ma under different gain gears, thereby improving the gain consistency of the low-noise amplifier circuit.

[0137] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A low-noise amplifier circuit, characterized in that Including: An amplifying transistor, the amplifying transistor including a first amplifying unit; A bias transistor, connected to the amplifying transistor, and the bias transistor including a first bias unit and a second bias unit, the first bias unit being disposed on one side adjacent to the first amplifying unit; the second bias unit being spaced apart from the first bias unit.

2. The low-noise amplifying circuit according to claim 1, wherein The first bias unit is disposed on one side of the first amplifying unit in a first direction, and the second bias unit is disposed on the other side of the first amplifying unit in the first direction.

3. The low-noise amplifier circuit according to claim 2, wherein The amplifying transistor further includes a second amplifying unit; The first bias unit, the first amplifying unit, and the second bias unit are sequentially disposed on one side of the second amplifying unit in a first direction, and the first bias unit is located on a side of the first amplifying unit away from the second amplifying unit; The low-noise amplifying circuit further includes a first dummy unit, the first dummy unit being disposed on a side of the first bias unit away from the first amplifying unit.

4. The low-noise amplifying circuit according to claim 3, wherein The low-noise amplifying circuit further includes a second dummy unit, the second dummy unit being disposed on a side of the second amplifying unit away from the second bias circuit.

5. The low-noise amplifier circuit according to claim 3, characterized in that, The number of the second amplifying units is at least two; The bias transistor further includes a third bias unit, the third bias unit being disposed between two adjacent second amplifying units.

6. The low-noise amplifier circuit according to claim 2, characterized in that, The number of the second amplifying units is at least two, and the first bias unit, the first amplifying unit, and the second bias unit are sequentially disposed between the two second amplifying units.

7. The low-noise amplifier circuit according to any one of claims 3-6, characterized in that, The first amplifying unit is a normally-conducting amplifying unit, and the second amplifying unit is configured to conduct according to a corresponding gain gear control signal.

8. The low-noise amplifier circuit according to claim 1, wherein, The amplifying transistor further includes at least one third amplifying unit, the third amplifying unit being located on one side or both sides of the first amplifying unit in a second direction; The first bias unit is disposed on one side of the first amplifying unit in a first direction; The second bias unit is disposed on one side of one of the third amplifying units in a first direction.

9. The low-noise amplifier circuit according to claim 8, characterized in that, The number of the second bias units is at least two, and each of the second bias units is disposed on one side of one of the third amplifying units in a first direction.

10. The low-noise amplifier circuit according to claim 8, wherein The low-noise amplifying circuit further includes at least one seventh dummy unit; The number of the third amplifying units is at least two, at least two of the third amplifying units are arranged along the second direction, and at least one of the third amplifying units is provided with the seventh dummy unit on one side in the first direction.

11. The low-noise amplifier circuit according to claim 8, wherein, The low-noise amplifying circuit further includes a second amplifying unit, the second amplifying unit being located on one side of the first amplifying unit in a first direction; At least two of the third amplifying units are arranged along the first direction, and the first amplifying unit, the second amplifying unit, and at least two of the third amplifying units are distributed in an array.

12. The low-noise amplifier circuit according to any one of claims 8-11, characterized in that, The first amplification unit is a normally-conducting amplification unit; the other amplification units except the first amplification unit are used to conduct according to corresponding gain gear control signals.

13. The low-noise amplification circuit according to any one of claims 1-11, wherein the low-noise amplification circuit further includes at least two eighth dummy units, and the two eighth dummy units are oppositely arranged in a first direction and / or in a second direction; the bias transistor and the amplification transistor are clamped between the two oppositely arranged eighth dummy units.

14. The low-noise amplifier circuit according to claim 13, wherein The bias transistor and the amplification transistor are located in a first layout region; The number of the eighth dummy units is four, and the four eighth dummy units are arranged around the periphery of the first layout region.

15. The low-noise amplifier circuit according to claim 1, wherein The low-noise amplification circuit includes at least two of the amplification transistors, and two of the amplification transistors are connected to form a cascode structure.

16. The low-noise amplifier circuit according to claim 15, wherein One of the amplification transistors in the cascode structure is connected to the bias transistor, and the other amplification transistor in the cascode structure receives a bias voltage.

17. The low-noise amplifier circuit according to claim 15, characterized in that, The low-noise amplification circuit includes at least two of the bias transistors, and the two amplification transistors in the cascode structure are respectively connected to the corresponding bias transistors.

18. A low-noise amplifier circuit, characterized in that, Comprising: an amplification transistor, disposed in a second layout region; a ninth dummy unit and a tenth dummy unit, the ninth dummy unit and the tenth dummy unit are distributed on both sides of the second layout region along the first direction or the second direction.

19. The low-noise amplifier circuit according to claim 18, wherein The dummy module further includes an eleventh dummy unit and a twelfth dummy unit; the eleventh dummy unit, the twelfth dummy unit, the ninth dummy unit and the tenth dummy unit are arranged around the periphery of the second layout region.

20. The low-noise amplification circuit according to claim 18, characterized in that, The second layout region includes at least two sub-regions arranged along the second direction, and each sub-region corresponds to at least one of the amplification transistors, and the amplification transistor is disposed in the corresponding sub-region.

21. The low-noise amplifier circuit according to claim 20, wherein The low-noise amplification circuit further includes at least one thirteenth dummy unit, and the thirteenth dummy unit is disposed in the second layout region and is located between two adjacent sub-regions.

22. The low-noise amplifier circuit according to claim 18, characterized in that, The low-noise amplification circuit further includes a bias transistor, and the bias transistor is disposed in the second layout region and is connected to the amplification transistor.

23. A radio frequency chip, characterized in that, Comprising the low-noise amplification circuit according to any one of claims 1-22.

24. A radio frequency front-end module, characterized in that, Comprising the radio frequency chip according to claim 23.

Images