Memory and storage apparatus

Abstract

Provided in the embodiments of the present disclosure are a memory and a storage apparatus. The memory comprises a base substrate, a first inverter and a third transistor. The first inverter is arranged on the base substrate and comprises a first transistor and a second transistor stacked in the direction perpendicular to the base substrate. The first transistor and the second transistor comprise a common first gate. The first transistor further comprises a first source and a first drain arranged on the side of the first gate close to the base substrate. The second transistor further comprises a second source and a second drain arranged on the side of the first gate away from the base substrate. The first drain and the second drain are electrically connected by means of a first via hole. The first source is configured to receive a first power supply signal, and the second source is configured to receive a second power supply signal. The third transistor comprises a second gate, a third source and a third drain, the second gate being electrically connected to a first word line, the third source being electrically connected to a first bit line, and the third drain being electrically connected to the first gate. The memory occupies a small area, and can be easily manufactured by means of a back-end-of-line process.

Description

Memory and storage devices

[0001] This application claims priority to Chinese Patent Application No. 202311841264.5 filed on December 28, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a memory and a storage device. Background Art

[0003] Complementary Metal Oxide Semiconductor (CMOS) technology combines N-type MOS and P-type MOS on the same chip to form a circuit. CMOS circuits have almost zero static power consumption and good noise tolerance. They are the main semiconductor technology for memories such as microprocessors, microcontroller chips, RAM, ROM, EEPROM, and application-specific integrated circuits (ASICs).

[0004] As semiconductor process nodes continue to decrease, MOS device size is proportionally shrinking, and the distance between the transistor source and drain is becoming increasingly closer. This leads to short-channel effects in transistors, reducing the device's threshold voltage, degrading gate control capabilities, increasing leakage current, and subsequently increasing power consumption, seriously impacting transistor performance. Traditional silicon-based semiconductors use the type and spatial distribution of dopant atoms to manufacture the required transistors. Due to the statistical distribution of dopant atoms and the ease of diffusion of dopant atoms at certain temperatures, traditional planar CMOS requires spatial isolation of PMOS field-effect transistors from NMOS. The lateral isolation region occupies necessary space on the limited chip, resulting in wasted chip area. Summary of the Invention

[0005] At least one embodiment of the present disclosure provides a memory, which includes a substrate, a first inverter and a third transistor, wherein the first inverter is arranged on the substrate, and includes a first transistor and a second transistor stacked in a direction perpendicular to the substrate, wherein the first transistor and the second transistor include a common first gate, the first transistor also includes a first source and a first drain arranged on a side of the first gate close to the substrate, the second transistor also includes a second source and a second drain arranged on a side of the first gate away from the substrate, the first drain and the second drain are electrically connected through a first via, the first source is configured to receive a first power supply signal, and the second source is configured to receive a second power supply signal, and the third transistor is arranged on the substrate, and includes a second gate, a third source and a third drain, wherein the second gate is electrically connected to a first word line, the third source is electrically connected to a first bit line, and the third drain is electrically connected to the first gate.

[0006] For example, in the memory provided by at least one embodiment of the present disclosure, the third transistor is arranged on the same layer as the first transistor, and is of the same type as the first transistor, both are N-type transistors, and the second transistor is a P-type transistor; or the third transistor is arranged on the same layer as the second transistor, and is of the same type as the second transistor, both are N-type transistors, and the first transistor is a P-type transistor.

[0007] For example, the memory provided by at least one embodiment of the present disclosure also includes: a second inverter, including a fourth transistor and a fifth transistor stacked in a direction perpendicular to the substrate, wherein the fourth transistor and the fifth transistor include a common third gate, the fourth transistor also includes a fourth source and a fourth drain arranged on a side of the third gate close to the substrate, the fifth transistor also includes a fifth source and a fifth drain arranged on a side of the third gate away from the substrate, the fourth drain and the fifth drain are electrically connected through a second via, the fourth source is configured to receive the first power supply signal, and the fifth source is configured to receive the second power supply signal; and a sixth transistor, including a fourth gate, a sixth source and a sixth drain, wherein the fourth gate is electrically connected to the second word line, the sixth source is electrically connected to the second bit line, and the sixth drain is electrically connected to the third gate; wherein the first gate is also electrically connected to the fourth drain and the fifth drain, and the third gate is also electrically connected to the first drain and the second drain.

[0008] For example, in the memory provided by at least one embodiment of the present disclosure, the sixth transistor is provided in the same layer as the third transistor and is of the same type as the third transistor, both being N-type transistors.

[0009] For example, in the memory provided by at least one embodiment of the present disclosure, in a planar structure of the memory, the first inverter and the second inverter are symmetrically arranged, and the third transistor and the sixth transistor are symmetrically arranged.

[0010] For example, in the memory provided by at least one embodiment of the present disclosure, the first source and the fourth source are electrically connected to a first power signal line, the second source and the fifth source are electrically connected to a second power signal line, the first power signal line extends along a first direction, and the second power signal line extends along a second direction, and the second direction is different from the first direction.

[0011] For example, in the memory provided by at least one embodiment of the present disclosure, the first word line is multiplexed as the second word line, the first word line extends along the first direction, and the first inverter and the second inverter are arranged between the first word line and the first power signal line.

[0012] For example, in the memory provided in at least one embodiment of the present disclosure, the second power signal line includes a first sub-power line and a second sub-power line extending along the second direction, and the first bit line and the second bit line extend along the second direction and are located between the first sub-power line and the second sub-power line.

[0013] For example, in the memory provided by at least one embodiment of the present disclosure, the third transistor and the sixth transistor are located between the first sub-power line and the second sub-power line.

[0014] For example, in the memory provided by at least one embodiment of the present disclosure, the first source, the first drain, the fourth source and the fourth drain are arranged on a first straight line, the second source, the second drain, the fifth source and the fifth drain are arranged on a second straight line, and the first straight line is parallel to the second straight line and parallel to the first direction.

[0015] For example, in the memory provided by at least one embodiment of the present disclosure, the third source and the third drain are arranged on a third straight line, the sixth source and the sixth drain are arranged on a fourth straight line, and the third straight line is parallel to the fourth straight line and parallel to the second direction.

[0016] For example, in the memory provided by at least one embodiment of the present disclosure, the first source and the fourth source are electrically connected to a first power signal line, the second source and the fifth source are electrically connected to a second power signal line, the first word line is multiplexed as the second word line, the first power signal line, the second power signal line and the first word line extend along a first direction, the first bit line and the second bit line extend along a second direction, and the first direction is different from the second direction.

[0017] For example, in the memory provided by at least one embodiment of the present disclosure, the first inverter and the second inverter are located between the first word line and the second power signal line.

[0018] For example, in the memory provided by at least one embodiment of the present disclosure, the first source and the first drain are arranged on a fifth straight line, the fourth source and the fourth drain are arranged on a sixth straight line, the fifth straight line is parallel to the second direction, and the sixth straight line is parallel to the first direction.

[0019] At least one embodiment of the present disclosure also provides a storage device, which includes a memory array and a peripheral circuit; the memory array includes a plurality of memories arranged in an array, and the peripheral circuit is arranged on at least one side of the memory array, including a driving transistor, wherein the driving transistor includes a first driving transistor and a second driving transistor stacked in a direction perpendicular to the substrate, and the first driving transistor and the second driving transistor share a first driving gate.

[0020] For example, in the storage device provided by at least one embodiment of the present disclosure, the peripheral circuit includes a first encoder and a second encoder; the first encoder is arranged on the first side of the memory array, electrically connected to the first word line, and configured to provide a first electrical signal to the first word line, and the second encoder is arranged on the second side of the memory array, electrically connected to the first bit line, and configured to provide a second electrical signal to the first bit line; at least one of the first encoder and the second encoder includes the driving transistor.

[0021] At least one embodiment of the present disclosure also provides a method for preparing a memory, comprising: providing a substrate, forming a first inverter on the substrate, wherein the first inverter includes a first transistor and a second transistor stacked in a direction perpendicular to the substrate, the first transistor and the second transistor include a common first gate, the first transistor also includes a first source and a first drain arranged on a side of the first gate close to the substrate, the second transistor also includes a second source and a second drain arranged on a side of the first gate away from the substrate, the first drain and the second drain are electrically connected through a first via, the first source is configured to receive a first power signal, the second source is configured to receive a second power signal, and forming a third transistor on the substrate, wherein the third transistor includes a second gate, a third source, and a third drain, the second gate is electrically connected to a first word line, the third source is electrically connected to a first bit line, and the third drain is electrically connected to the first gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0023] FIG1 is a circuit diagram of a memory provided by at least one embodiment of the present disclosure;

[0024] FIG2 is a schematic diagram of a planar structure of a memory provided by at least one embodiment of the present disclosure;

[0025] FIG3 is a schematic diagram of the stacked structure of the memory in FIG2 along the direction of arrow 1;

[0026] FIG4 is a schematic diagram of the stacked structure of the memory in FIG2 along the direction of arrow 2;

[0027] FIG5 is a schematic diagram of the stacked structure of the memory in FIG2 along the direction of arrow 3;

[0028] FIG6 is a schematic diagram of a horizontal arrangement of memories according to at least one embodiment of the present disclosure;

[0029] FIG7 is a schematic diagram of a planar structure of another memory provided by at least one embodiment of the present disclosure;

[0030] FIG8 is a schematic diagram of another horizontal arrangement of memories provided by at least one embodiment of the present disclosure;

[0031] FIG9 is a circuit diagram of a memory device according to at least one embodiment of the present disclosure;

[0032] FIG10 is a schematic diagram of a partial planar structure of a peripheral circuit provided by at least one embodiment of the present disclosure;

[0033] FIG11 is a partial circuit diagram of a peripheral circuit provided by at least one embodiment of the present disclosure; and

[0034] FIG12 is a scanning electron microscope image of a memory device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0036] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0037] Static random-access memory (SRAM) is a type of random-access memory. The term "static" refers to the fact that as long as the memory remains powered, the stored data remains permanently, without requiring a refresh circuit to lock the data. In contrast, dynamic random-access memory (DRAM) requires periodic refreshes and recharging, otherwise the stored data will be lost.

[0038] An SRAM cell is usually composed of 4-6 transistors. In some cases, SRAM also has an 8-10 transistor structure. Taking the most commonly used 6-transistor SRAM (6T SRAM, T is the abbreviation of transistor) cell as an example, each storage cell in the SRAM can store a one-bit number. The storage structure consists of a trigger. The input and output of the two inverters are cross-connected, that is, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter, realizing the latching of the output states of the two inverters. When the SRAM cell is assigned a state of 0 or 1, it will maintain this state until it is assigned a new state next time or the power is cut off.

[0039] In addition to its static storage properties, SRAM has very fast storage and read speeds, making it often used as a cache. Cache is a temporary storage device used to improve data access efficiency. Located between the central processing unit (CPU) and main memory, it temporarily stores frequently accessed data and instructions to quickly respond to the processor's read requests. SRAM is a common cache device in current general-purpose computer architectures. The main advantages of SRAM as a cache are its fast read and write speeds and high reliability, typically operating at speeds of 10ns or faster. Furthermore, the bistable flip-flop structure in SRAM allows for persistent data storage, which makes SRAM highly stable and reliable.

[0040] The disadvantage of SRAM is its relatively small storage capacity, usually expressed in bytes or smaller units. This is because compared to the single-transistor, single-capacitor structure of DRAM, a single SRAM memory cell has more transistors and occupies a larger area, making large-capacity storage difficult and expensive, and reducing the integration of chip memory.

[0041] Monolithic 3D integration is an advanced semiconductor manufacturing technology that allows for the vertical stacking of multiple layers of new logic, storage, and computational devices that can be integrated in later processes on a single chip, significantly reducing chip area. Currently, monolithic 3D integration technology explores homogeneous materials, meaning that multiple layers of silicon transistors are stacked vertically. Traditional silicon-based semiconductor processes require high-temperature processes such as active layer growth, ion implantation, and annealing. Metal interconnects and other temperature-sensitive steps are placed after the high-temperature process. Therefore, after using traditional silicon-based processes to produce one layer of transistors, it is impossible to continue using the same high-temperature process to produce the second layer of devices on the same chip. The use of processes such as epitaxy and bonding is also limited by factors such as temperature and yield.

[0042] At least one embodiment of the present disclosure provides a memory, which includes a substrate, a first inverter and a third transistor. The first inverter is arranged on the substrate, and includes a first transistor and a second transistor stacked in a direction perpendicular to the substrate, wherein the first transistor and the second transistor include a common first gate, the first transistor also includes a first source and a first drain arranged on a side of the first gate close to the substrate, the second transistor also includes a second source and a second drain arranged on a side of the first gate away from the substrate, the first drain and the second drain are electrically connected through a first via, the first source is configured to receive a first power signal, and the second source is configured to receive a second power signal. The third transistor is arranged on the substrate, and includes a second gate, a third source and a third drain, wherein the second gate is electrically connected to the first word line, the third source is electrically connected to the first bit line, and the third drain is electrically connected to the first gate.

[0043] The above-mentioned memory provided by the embodiment of the present disclosure uses a vertically stacked first transistor and a second transistor to form an inverter, which reduces the area occupied by the memory. In addition, the memory can be stacked on top of a silicon-based chip as a back-end process through monolithic three-dimensional integration technology, and high-density interconnection between the back-end memory and the storage or computing module below is achieved through interlayer dielectric through-holes, thereby realizing a multifunctional and highly integrated new storage and computing chip.

[0044] The memory and storage device provided by the embodiments of the present disclosure are described below through several specific embodiments.

[0045] At least one embodiment of the present disclosure provides a memory. Figure 1 shows a circuit diagram of the memory, Figure 2 shows a layout of the memory, Figure 3 shows a schematic diagram of the stacked structure of the memory along the direction of arrow 1 in Figure 2, Figure 4 shows a schematic diagram of the stacked structure of the memory along the direction of arrow 2 in Figure 2, and Figure 5 shows a schematic diagram of the stacked structure of the memory along the direction of arrow 3 in Figure 2. As shown in Figures 1-5, the memory includes a substrate BS, a first inverter 10, and a third transistor 30.

[0046] The first inverter 10 is disposed on a substrate BS and includes a first transistor 101 and a second transistor 102 stacked in a direction perpendicular to the substrate BS. The first transistor 101 and the second transistor 102 share a first gate G1. The first transistor 101 also includes a first source S1 and a first drain D1 disposed on a side of the first gate G1 that is close to the substrate BS. The second transistor 102 also includes a second source S2 and a second drain D2 disposed on a side of the first gate G1 that is away from the substrate BS. The first drain D1 and the second drain D2 are electrically connected via a first via. The first source S1 is configured to receive a first power signal, such as a first power signal line VDD, to receive the first power signal, e.g., a high-level power signal. The second source S2 is configured to receive a second power signal, such as a second point source signal line GND, to receive the second power signal, e.g., a low-level power signal or a ground signal.

[0047] The third transistor 30 is disposed on the substrate BS and includes a second gate G2, a third source S3, and a third drain D3. The second gate G2 is electrically connected to the first word line WL1, the third source S3 is electrically connected to the first bit line BL, and the third drain D3 is electrically connected to the first gate G1. The third transistor 30 can serve as a gate transistor for the first inverter 10.

[0048] For example, in some embodiments, the third transistor 30 is arranged on the same layer as the first transistor 101 and is of the same type as the first transistor 101, for example, both are N-type transistors. In this case, the second transistor 102 is a P-type transistor; or, in other embodiments, the third transistor 30 is arranged on the same layer as the second transistor 102 and is of the same type as the second transistor 102, for example, both are N-type transistors. In this case, the first transistor 101 is a P-type transistor.

[0049] For example, in some embodiments, as shown in FIG1-3 , the memory may further include a second inverter 20 . The second inverter 20 includes a fourth transistor 201 and a fifth transistor 202 stacked in a direction perpendicular to the substrate BS. The fourth transistor 201 and the fifth transistor 202 share a third gate G3 . The fourth transistor 201 further includes a fourth source S4 and a fourth drain D4 disposed on a side of the third gate G3 closer to the substrate BS. The fifth transistor 202 further includes a fifth source S5 and a fifth drain D5 disposed on a side of the third gate G3 farther from the substrate BS. The fourth drain D4 and the fifth drain D5 are electrically connected via a second via. The fourth source S4 is configured to receive a first power signal, for example, connected to a first power signal line VDD to receive the first power signal, for example, a high-level power signal. The fifth source S5 is configured to receive a second power signal, for example, connected to a second point source signal line GND to receive the second power signal, for example, a low-level power signal or a ground signal.

[0050] The sixth transistor 40 includes a fourth gate G4, a sixth source S6, and a sixth drain D6. The fourth gate G4 is electrically connected to the second word line WL2, the sixth source S6 is electrically connected to the second bit line BLB, and the sixth drain D6 is electrically connected to the third gate G3. For example, in some embodiments, the sixth transistor 40 is provided in the same layer as the third transistor 30 and is of the same type as the third transistor 30. The sixth transistor 40 can serve as a gate transistor for the second inverter 20.

[0051] For example, as shown in FIG3 , the first transistor 101 may further include a semiconductor layer 11, a passivation layer 12, and an insulating layer 13, and the second transistor 102 may further include a semiconductor layer 15 and an insulating layer 14. Correspondingly, the fourth transistor 201 may further include a semiconductor layer 21, a passivation layer 22, and an insulating layer 23, and the fifth transistor 202 may further include a semiconductor layer 25 and an insulating layer 24.

[0052] For example, in one embodiment, the first transistor 101 and the fourth transistor 201 are P-type transistors, and the materials of the semiconductor layers 11 and 21 include P-type nanomaterials or P-type oxides. The second transistor 102 and the fifth transistor 202 are N-type transistors, and the materials of the semiconductor layers 15 and 25 include N-type nanomaterials or N-type oxides. Thus, the semiconductor layers 11 and 12 and the semiconductor layers 21 and 22 are all made of materials such as nanomaterials and oxide materials that can be prepared and patterned in a low-temperature environment (e.g., an environment below 300 degrees Celsius). Therefore, the two can be formed sequentially on the same substrate, which can avoid the impact of high-temperature processes on circuits already formed in the previous process.

[0053] Alternatively, in other examples, the first transistor 101 and the fourth transistor 201 are N-type transistors. In this case, the materials of the semiconductor layers 11 and 21 include N-type nanomaterials or N-type oxides. The second transistor 102 and the fifth transistor 202 are P-type transistors, and the materials of the semiconductor layers 15 and 25 include P-type nanomaterials or P-type oxides. In this case, the semiconductor layers 11 and 12 and the semiconductor layers 21 and 22 also use materials such as nanomaterials and oxide materials that can be prepared and patterned in a low-temperature environment (e.g., an environment below 300 degrees Celsius). Therefore, the two can be formed sequentially on the same substrate, thereby avoiding the impact of high-temperature processes on circuits already formed in the previous process.

[0054] For example, in some embodiments, P-type nanomaterials may include CNTs, WSe2, or black phosphorus, and P-type oxides may include SnO, etc.; N-type nanomaterials may include MoS2 or WS2, and N-type oxides may include IGZO, ITO, IWO, or IZO, etc. These materials can be formed / prepared and patterned in a low-temperature environment (e.g., an environment below 300 degrees Celsius), and their preparation process is simple.

[0055] For example, both the passivation layer 12 / 22 and the insulating layer 13 / 14 / 23 / 24 can be made of a metal oxide insulating material. By providing a double oxide layer structure (i.e., an insulating layer and a passivation layer), the passivation layer can achieve a good interface with the semiconductor material, and the insulating layer can realize a high-k dielectric. The high-k dielectric can enhance gate control capabilities. Because different semiconductor materials have different oxide materials that match them to form a good interface, adding a passivation layer can achieve a better interface with the semiconductor layer.

[0056] For example, in some embodiments, the material of the passivation layer 12 / 22 may include Y2O3, and the material of the insulating layer 13 / 14 / 23 / 24 may include HfO2. HfO2 is a high-k dielectric that helps enhance the gate control capability of the transistor, while Y2O3 can form a good interface with nano-semiconductor materials (such as carbon nanotubes).

[0057] For example, in the embodiment of the present disclosure, the substrate BS can be a silicon substrate or a functional substrate that has undergone front-end processing to form some devices and connections, and each source and drain can be made of metal materials or alloy materials such as palladium, titanium, aluminum, copper, and molybdenum, and each gate can also be made of metal materials or alloy materials such as palladium, titanium, aluminum, copper, and molybdenum.

[0058] For example, in some examples, the first word line WL1 is multiplexed as the second word line WL2 , that is, the second word line WL2 and the first word line WL1 may be the same line, which is labeled as word line WL in FIG. 2 to FIG. 5 .

[0059] For example, the first gate G1 and the third drain D3 of the third transistor 30 are connected to the node Q. The first gate G1 is also electrically connected to the fourth drain D4 and the fifth drain D5. The third gate G3 and the sixth drain D6 of the sixth transistor 40 are connected to the node QB. The third gate G3 is also electrically connected to the first drain D1 and the second drain D2. Thus, the input of the first inverter 10 is connected to the output of the second inverter 20, and the input of the second inverter 20 is connected to the output of the first inverter 10.

[0060] Therefore, the memory in the above embodiment is composed of 4 NMOS (for example, the second transistor, the third transistor, the fifth transistor and the sixth transistor) and 2 PMOS (for example, the first transistor and the fourth transistor). The first inverter 10 including the first transistor 101 and the second transistor 102 and the second inverter 20 including the fourth transistor 201 and the fifth transistor 202 are connected end to end to realize positive feedback latching of the storage potential, that is, the potential stored at point Q is opposite to the potential stored at point QB. When the first power supply signal VDD and the second power supply signal GND are kept powered on, the potential stored at point Q outputs the opposite potential QB through the first inverter 10, and the QB potential outputs the opposite potential through the second inverter 20 and is connected to Q, forming a positive feedback loop. The third and sixth transistors serve as memory gate transistors, with their gates connected to word line WL. Opening word line WL enables writing and reading from the memory. The drains of the third and sixth transistors are connected to nodes Q and QB, respectively, and their sources are connected to the first and second bit lines BL and BLB, respectively. When a write operation is required, the first and second bit lines BL and BLB are preset to a write voltage. For example, for writing a "1," the first bit line BL is preset to "1" and the second bit line BLB is preset to "0." Opening word line WL turns on the third and sixth transistors to initiate writing. At this point, the first and second bit lines BL and BLB are connected to nodes Q / QB, increasing the voltage at node Q and decreasing the voltage at node QB. The latch structure accelerates voltage changes through positive feedback, allowing data to be written. Closing word line WL completes the write operation. During a read operation, opening word line WL turns on the third and sixth transistors, causing nodes Q and QB to discharge to the first and second bit lines BL and BLB, and the node voltages are read through the first and second bit lines BL and BLB.

[0061] For example, in some embodiments, as shown in FIG2 , in the planar structure of the memory, the first inverter 10 and the second inverter 20 may be symmetrically arranged, and the third transistor 30 and the sixth transistor 40 may be symmetrically arranged. Thus, the entire memory has a symmetrical structure.

[0062] For example, with reference to FIG1 and FIG2 , the first source S1 and the fourth source S4 are electrically connected to a first power signal line VDD, the second source S2 and the fifth source S5 are electrically connected to a second power signal line GND, the first power signal line VDD extends along a first direction R1, and the second power signal line GND extends along a second direction R2, where the second direction R2 is different from the first direction R1. For example, the second direction R2 is perpendicular to the first direction R1.

[0063] For example, in conjunction with FIG1 and FIG2, the first word line WL1 is multiplexed into the second word line WL2, which is labeled as the word line WL in FIG2, and the word line WL extends along the first direction R1. The first inverter 10 and the second inverter 20 are arranged between the word line WL and the first power signal line VDD.

[0064] For example, the second power signal line GND includes a first sub-power line GND1 and a second sub-power line GND2 extending along a second direction R2. The first bit line BL and the second bit line BLB extend along the second direction R2 and are located between the first sub-power line GND1 and the second sub-power line GND2. For example, the third transistor 30 and the sixth transistor 40 are also located between the first sub-power line GND1 and the second sub-power line GND2.

[0065] For example, in combination with Figures 2 and 3, the first source S1, the first drain D1, the fourth source S4 and the fourth drain D4 are arranged on a first straight line L1, the second source S2, the second drain D2, the fifth source S5 and the fifth drain D5 are arranged on a second straight line L2, and the first straight line L1 is parallel to the second straight line L2 and parallel to the first direction R1.

[0066] For example, the third source S3 and the third drain D3 are arranged on a third straight line L3, and the sixth source S6 and the sixth drain D6 are arranged on a fourth straight line L4. The third straight line L3 is parallel to the fourth straight line L4 and parallel to the second direction R2. For example, the first bit line BL is also arranged on the third straight line L3, and the second bit line BLB is arranged on the fourth straight line L4.

[0067] This layout design makes the memory more compact, occupies a smaller area, and its symmetrical structure improves manufacturing uniformity. Testing, as shown in Figure 2, shows that the memory can be fabricated within a range of 8.3F in length (H) and 8.4F in width (W), where F represents the minimum process standard.

[0068] For example, Figure 6 shows a layout in which the structure of Figure 2 is arranged horizontally, that is, the first transistor 101 and the second transistor 102 included in the first inverter 10 are arranged horizontally, and the fourth transistor 201 and the fifth transistor 202 included in the second inverter 20 are arranged horizontally. As shown in Figure 6, in this case, the memory needs to be manufactured within a range of a length H of 10.6F and a width W of 10.8F, where F represents the minimum process standard.

[0069] As can be seen from FIG2 , in the embodiment of the present disclosure, the first inverter 10 and the second inverter 20 can be vertically stacked on the size of a transistor using the back-end process, and a memory including, for example, six transistors can be implemented within the range of four transistors in the back-end (4T-area). Without changing the number of transistors, it only occupies the area of ​​four transistors. In conjunction with FIG2 and FIG6 , in the layout design, the minimum size determined by the photolithography technology in the back-end process is defined as F. As shown in FIG2 , the area of ​​the memory including the vertically stacked inverters is about 70F. 2 As shown in Figure 6, the area of ​​the planar memory is about 115F2 , that is, the layout design based on Figure 2 can reduce the back-end memory area by about 39%.

[0070] For example, FIG7 is a schematic diagram of the planar structure of another memory device provided by at least one embodiment of the present disclosure. As shown in FIG7 , in other embodiments, the first inverter 10 and the second inverter 20 may also adopt other layout designs. For example, in the embodiment of FIG7 , the first source S1 and the fourth source S4 are electrically connected to the first power signal line VDD, the second source S2 and the fifth source S5 are electrically connected to the second power signal line GND, the first word line WL1 is multiplexed as the second word line WL2, and is labeled as word line WL in the figure. The first power signal line VDD, the second power signal line GND, and the first word line WL1 extend along a first direction R1, and the first bit line BL and the second bit line BLB extend along a second direction R2. The first direction R1 is different from the second direction R2. For example, the first direction R1 is perpendicular to the second direction R2.

[0071] For example, as shown in FIG. 7 , the first inverter 10 and the second inverter 20 are located between the first word line WL1 and the second power signal line GND.

[0072] For example, as shown in FIG7 , the first source S1 and the first drain D1 are arranged on a fifth straight line L5, which is parallel to the second direction R2, and the fourth source S4 and the fourth drain D4 are arranged on a sixth straight line L6, which is parallel to the first direction R1. That is, the first inverter 10 and the second inverter 20 are arranged in different directions.

[0073] For example, the third source S3 and the third drain S3 of the third transistor 30 are arranged in a direction parallel to the second direction R2, and the sixth source S3 and the sixth drain S6 of the sixth transistor 40 are arranged in a direction parallel to the second direction R2. For example, the structures of the third transistor 30 and the sixth transistor 40 are arranged substantially symmetrically.

[0074] Through the layout design shown in Figure 7, the structure of the memory is also very compact. Through testing, as shown in Figure 7, the above-mentioned memory can be manufactured within the range of a length H of 63F and a width W of 67F, where F represents the minimum process standard.

[0075] For example, Figure 8 shows a layout in which the structure of Figure 7 is arranged horizontally, that is, the first transistor 101 and the second transistor 102 included in the first inverter 10 are arranged horizontally, and the fourth transistor 201 and the fifth transistor 202 included in the second inverter 20 are arranged horizontally. As shown in Figure 8, in this case, the memory needs to be manufactured within a range of a length H of 83F and a width W of 87F, where F represents the minimum process standard.

[0076] It can be seen that by using the back-end process, the first inverter 10 and the second inverter 20 in Figure 7 can be vertically stacked on the size of a transistor respectively. Without changing the number of transistors, they only occupy the area of ​​4 transistors. Combined with Figures 7 and 8, the layout design based on Figure 7 can reduce the area of ​​the back-end memory by about 41.5%.

[0077] At least one embodiment of the present disclosure further provides a storage device, which includes a memory array 100 and a peripheral circuit 200; the memory array 100 includes a plurality of memories arranged in an array, and the plurality of memories are the above-mentioned memories provided in the embodiment of the present disclosure; the peripheral circuit 200 is arranged on at least one side of the memory array 100, and includes a first encoder, a second encoder, a transmission gate / buffer circuit, a sense amplifier, a control circuit, and other circuit structures.

[0078] For example, the peripheral circuit 200 includes a driving transistor, which includes a first driving transistor and a second driving transistor stacked in a direction perpendicular to the substrate BS, and the first driving transistor and the second driving transistor share a first driving gate. Therefore, the vertical stacking structure of the driving transistors can also reduce the area occupied by the peripheral circuit 200.

[0079] For example, as shown in FIG9 , a first encoder is provided on a first side (left side in the figure) of the memory array 100, electrically connected to the first word line WL1, and configured to provide a first electrical signal, such as a row scan signal, to the first word line WL1. A second encoder is provided on a second side (lower side in the figure) of the memory array 100, electrically connected to the first bit line BL, and configured to provide a second electrical signal, such as a data signal, to the first bit line BL. For example, at least one of the first encoder and the second encoder includes (e.g., both include) a drive transistor having a vertically stacked structure as described above.

[0080] For example, the transmission gate / buffer circuit can be composed of a series of inverters, such as inverters with a vertical stacking structure (the structure can be seen in the first inverter 10 and the second inverter 20), thereby reducing the area occupied by the transmission gate / buffer circuit.

[0081] For example, in some embodiments, both the first encoder and the second encoder can be composed of multi-input logic gates. Taking a 3-8 decoder composed of a three-input NAND gate (NAND) as an example, FIG10 shows an exemplary layout of the first encoder (or second encoder), and FIG11 shows a circuit diagram of a three-input NAND gate. As shown in FIG10 , the first encoder (or second encoder) includes a plurality of three-input NAND gates 201 and a plurality of inverters 202 having a vertically stacked structure. The inverters 202 can be implemented as the aforementioned drive transistors, or each inverter in the three-input NAND gates 201 can be implemented as the aforementioned drive transistors. For example, the first encoder also includes a plurality of input terminals In1-In3 and a plurality of output terminals O1-O8. The plurality of output terminals O1-O8 can be used to connect to different word lines WL.

[0082] As shown in FIG11 , a three-input NAND gate 201 includes three inverters 211 / 212 / 213, each having input terminals A1 / B1 / C1 and a common output terminal OUT1. For example, each inverter can be a vertically stacked inverter, reducing the occupied area by half. In the embodiments of FIG10 and FIG11 , a 3-8 decoder can be implemented using three inverters for controlling input signals and eight three-input NAND gates to implement basic binary digital logic. All transistors can be stacked using a back-end process, reducing the occupied area by 50%.

[0083] For example, the circuit structure of a sense amplifier also includes a latch structure similar to that in a memory, which can also be implemented using a common-gate vertical stacking structure.

[0084] For example, FIG12 shows a scanning electron microscope image of a memory device provided by an embodiment of the present disclosure. As shown in FIG12 , the memory device as a whole can be formed within a relatively small area. That is, a full-function memory array can be prepared based on the back-end process. For example, a back-end full-function SRAM array based on the back-end process is composed of a 6T (including six transistors) SRAM memory array and peripheral circuits. The SRAM memory can be prepared in the SRAM array using the CFET process to perform digital storage functions. The peripheral circuit structure of the SRAM array can also be implemented in the back-end using the CFET structure. A specific SRAM cell is selected for operation by inputting the row / column address, the write signal is controlled by the control circuit, and the data stored in the SRAM cell is read out by the sense amplifier.

[0085] In the embodiments of the present disclosure, in addition to using a CFET structure to vertically stack common-gate CMOS transistors within the SRAM array structure, a full-function SRAM array prepared using a back-end process can be fully stacked on a silicon-based chip with an existing lower-layer circuit (a CFET back-end full-function SRAM array prepared with a 2μm lithography accuracy). Because the back-end CFET uses a low-temperature process (generally not exceeding 300°C, which is a low-temperature process compared to the silicon-based transistor process), it will not damage the underlying silicon-based transistors and other back-end process structures. The cache can be directly stacked on top of the computing unit, saving a lot of chip area. Using monolithic three-dimensional integration technology, high-density interlayer dielectric vias can be opened in the insulating medium between different layers, and metal connections can be filled to achieve monolithic three-dimensional integrated ultra-high-density interconnection, which not only saves the overall area of ​​the back-end full-function SRAM array, but also enables on-chip ultra-high-density bandwidth data transmission.

[0086] At least one embodiment of the present disclosure further provides a method for manufacturing a memory, comprising: providing a substrate BS, forming a first inverter 10 on the substrate BS, wherein the first inverter 10 includes a first transistor 101 and a second transistor 102 stacked in a direction perpendicular to the substrate BS, the first transistor 101 and the second transistor 102 including a common first gate G1, the first transistor 101 further including a first source S1 and a first drain D1 disposed on a side of the first gate G1 close to the substrate BS, the second transistor 102 further including a first source S1 and a first drain D1 disposed on the first gate G1, The second source S2 and the second drain D2 of the gate G1 are away from the substrate BS, the first drain D1 and the second drain D2 are electrically connected through a first via, the first source S1 is configured to receive a first power supply signal, the second source S2 is configured to receive a second power supply signal, and a third transistor 30 is formed on the substrate BS, wherein the third transistor 30 includes a second gate G2, a third source S3 and a third drain D3, the second gate G2 is electrically connected to the first word line WL1, the third source S3 is electrically connected to the first bit line BL, and the third drain D3 is electrically connected to the first gate G1.

[0087] For example, a second inverter 20 is also formed on the substrate BS. The second inverter 20 includes a fourth transistor 201 and a fifth transistor 202 stacked in a direction perpendicular to the substrate BS. The fourth transistor 201 and the fifth transistor 202 include a common third gate G3. The fourth transistor 201 also includes a fourth source S4 and a fourth drain D4 arranged on a side of the third gate G3 close to the substrate BS. The fifth transistor 202 also includes a fifth source S5 and a fifth drain D5 arranged on a side of the third gate G3 away from the substrate BS. The fourth drain D4 and the fifth drain D5 are electrically connected through a second via.

[0088] For example, a third transistor 30 and a fourth transistor 40 are further formed on the base substrate BS. For example, the third transistor 30 and the fourth transistor 40 are formed in the same layer as the second transistor 102 and the fifth transistor 202 .

[0089] For example, referring to Figure 3, in a specific preparation process, a substrate BS is first provided, and under process conditions of less than 300 degrees Celsius, a first metal layer is formed on the substrate BS using a composition process. The first metal layer may include signal lines such as a first bit line BL, a second bit line BLB, and a second power signal line GND. The composition process may include forming a signal line material layer (such as a copper, tungsten metal layer, etc.), forming a photoresist on the material layer, exposing and developing the photoresist to form a photoresist pattern, and etching the material layer using the photoresist pattern as a mask to form signal lines such as a first bit line BL, a second bit line BLB, and a second power signal line GND.

[0090] Then, an insulating layer (not shown) is formed on the first metal layer, and then a second metal layer (e.g., a copper or tungsten metal layer) is formed using a patterning process. The second metal layer may include signal lines such as word lines WL and first power signal lines VDD. An insulating layer (not shown) is formed on the second metal layer. For example, each of the above insulating layers may be an inorganic insulating layer (e.g., silicon oxide, silicon nitride, or silicon oxynitride) or an organic insulating layer (e.g., a resin). The embodiments of the present disclosure do not limit the specific form of the insulating layer.

[0091] Semiconductor layers 11 and 21 are formed on the insulating layer. In this embodiment, semiconductor layers 11 and 21 may include carbon nanotubes (CNTs). In this case, a wet transfer method can be used to form the CNT material layer. For example, a first photoresist pattern is formed on the side of semiconductor layers 11 and 21 away from the substrate BS. The first photoresist pattern includes hollowed-out regions corresponding to the source electrodes S1 and S4 and the drain electrodes D1 and D4, respectively. Then, a first source-drain electrode material layer is formed on the side of the first photoresist pattern away from the substrate BS. For example, the first source-drain electrode material layer can be formed by electron beam evaporation. For example, in this embodiment, the first source-drain electrode material layer can be made of 30 nm thick metal palladium (Pd). Then, the first photoresist pattern is stripped, and the first source-drain electrode material formed above the first photoresist pattern is also stripped, thereby forming the source electrodes S1 and S4 and the drain electrodes D1 and D4.

[0092] For example, after forming each source electrode S1 and S4 and each drain electrode D1 and D4, a second photoresist pattern is formed on the side of the semiconductor layer 11 and 12 and each source electrode S1 and S4 and each drain electrode D1 and D4 away from the substrate BS, and the second photoresist pattern covers the formation area of ​​the semiconductor layers 11 and 12, and for example, may also cover the area of ​​each source electrode S1 and S4 and each drain electrode D1 and D4. Thereafter, the second photoresist pattern is used as a mask to etch the semiconductor layers 11 and 12, for example, by using plasma etching, such as oxygen plasma etching, to etch away the portions of the semiconductor layers 11 and 12 outside the area covered by the second photoresist pattern, and then the second photoresist pattern is stripped off to form a pattern of the patterned semiconductor layers 11 and 12.

[0093] For example, in some embodiments, after the semiconductor layers 11 and 12, the source electrodes S1 and S4, and the drain electrodes D1 and D4 are formed, passivation layers 12 and 22 can be formed thereon. For example, the passivation layer 12 can be formed by deposition. For example, in this embodiment, the passivation layers 12 and 22 can be made of yttrium oxide (Y2O3) with a thickness of 10 nm. After the passivation layers 12 and 22 are formed, insulating layers 13 and 23 can be formed on the passivation layers 12 and 22. For example, the insulating layers 13 and 23 can be formed by deposition using an atomic layer deposition device. For example, in this embodiment, the insulating layers 13 and 23 can be made of hafnium oxide (HfO2) with a thickness of 10 nm as the gate oxide layers of the first transistor and the fourth transistor.

[0094] For example, after the passivation layers 12 and 22 and the insulating layers 13 and 23 are formed, a patterning process can be used to simultaneously form vias (first vias and second vias) in the passivation layers 12 and 22 and the insulating layers 13 and 23 for connecting the drains between vertically stacked transistors.

[0095] For example, forming gates G1 and G3 on the side of the insulating layers 13 and 23 away from the substrate BS includes: forming a third photoresist pattern on the side of the insulating layers 13 and 23 away from the substrate BS, the third photoresist pattern including hollow areas corresponding to the gates G1 and G3, and then forming a gate material layer on the side of the third photoresist pattern away from the substrate BS, for example, by using an evaporation method to form the gate material layer. In this embodiment, the gate material layer can use 45nm thick metal palladium (Pd), and then the third photoresist pattern is stripped off, and the gate material located above the third photoresist pattern is also stripped off, thereby forming each gate G1 and G3.

[0096] For example, after each gate G1 and G3 is formed, insulating layers 14 and 24 are formed on the side of each gate G1 and G3 away from the substrate BS. For example, the insulating layers 14 and 24 can be formed by deposition, and then the insulating layers 14 and 24 are patterned, for example, to form vias. In this embodiment, the insulating layers 14 and 24 include 15 nm thick hafnium oxide (HfO2) to serve as the gate oxide layer of the second transistor and the fifth transistor.

[0097] For example, in some embodiments, forming the semiconductor layers 15 and 25 and the source electrodes S2 and S5 and the drain electrodes D2 and D5 on the side of the insulating layers 14 and 24 away from the substrate BS includes: forming a semiconductor material layer on the side of the insulating layers 14 and 24 away from the substrate BS under process conditions of less than 300 degrees Celsius, for example, forming the semiconductor material layer by a deposition method. For example, in this embodiment, the semiconductor material layer uses 15nm IGZO, and the semiconductor material layer is patterned.

[0098] For example, a fourth photoresist pattern is formed on the side of the semiconductor material layer away from the substrate BS, and the fourth photoresist pattern includes hollow areas corresponding to the source electrodes S2 and S5 and the drain electrodes D2 and D5, respectively. A second source-drain electrode material layer is formed on the side of the fourth photoresist pattern away from the substrate BS, for example, by using an evaporation method to form the second source-drain electrode material layer. In this embodiment, the second source-drain electrode material layer may include 20 nm thick titanium and 45 nm thick palladium (Ti / Pd). Then, the fourth photoresist pattern is stripped off, and the source-drain electrode material on the fourth photoresist pattern is also stripped off to form the source electrodes S2 and S5 and the drain electrodes D2 and D5.

[0099] For example, after the source electrodes S2 and S5 and the drain electrodes D2 and D5 are formed, patterns of the semiconductor layers 15 and 25 are formed using a patterning process.

[0100] Thus, the memory provided by the embodiment of the present disclosure is formed by using the back-end process. For example, a similar method can also be used to form the memory device shown in Figures 9-12.

[0101] Therefore, the embodiments of the present disclosure propose a back-end full-function memory array based on vertically stacked transistors, which uses stacked common-gate inverters to reduce the area of ​​the memory cell. Similarly, using the back-end vertical stacking technology, the common-gate inverter structures in the peripheral circuits of the memory array are vertically stacked to reduce the overall area of ​​the memory array. On this basis, the full-function memory array is stacked as a back-end cache as a whole on top of the silicon-based chip through monolithic three-dimensional integration technology, and high-density interconnection between the back-end memory array and the storage or computing module below is achieved through interlayer dielectric through-holes, realizing a new multifunctional and highly integrated memory and computing chip.

[0102] For example, the memory can be implemented as a static random access memory (SRAM). The embodiments of the present disclosure utilize back-end vertical stacking preparation technology to propose a back-end full-function SRAM array, thereby improving the transistor integration of the complete SRAM array. Furthermore, through monolithic three-dimensional heterogeneous integration technology, the full-function SRAM array is stacked as a back-end cache as a whole on top of a silicon-based chip, and high-density interconnection between the back-end SRAM array and the storage or computing module below is achieved through interlayer dielectric vias, thereby realizing a new multifunctional and highly integrated storage and computing chip.

[0103] There are a few points to note:

[0104] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0105] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated or reduced, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or intervening elements may be present.

[0106] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0107] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory device, comprising: A substrate, A first inverter disposed on the substrate, including a first transistor and a second transistor stacked in a direction perpendicular to the substrate, wherein the first transistor and the second transistor include a common first gate, the first transistor further includes a first source and a first drain disposed on a side of the first gate close to the substrate, the second transistor further includes a second source and a second drain disposed on a side of the first gate away from the substrate, the first drain and the second drain are electrically connected through a first via, the first source is configured to receive a first power signal, the second source is configured to receive a second power signal, and A third transistor disposed on the substrate, including a second gate, a third source, and a third drain, wherein the second gate is electrically connected to a first word line, the third source is electrically connected to a first bit line, and the third drain is electrically connected to the first gate.

2. The memory according to claim 1, wherein, The third transistor is disposed on the same layer as the first transistor and has the same type as the first transistor, both being N-type transistors, and the second transistor is a P-type transistor; Or The third transistor is disposed on the same layer as the second transistor and has the same type as the second transistor, both being N-type transistors, and the first transistor is a P-type transistor.

3. The memory device according to claim 1 or 2, further comprising: A second inverter, including a fourth transistor and a fifth transistor stacked in a direction perpendicular to the substrate, wherein the fourth transistor and the fifth transistor include a common third gate, the fourth transistor further includes a fourth source and a fourth drain disposed on a side of the third gate close to the substrate, the fifth transistor further includes a fifth source and a fifth drain disposed on a side of the third gate away from the substrate, the fourth drain and the fifth drain are electrically connected through a second via, the fourth source is configured to receive the first power signal, the fifth source is configured to receive the second power signal, and A sixth transistor, including a fourth gate, a sixth source, and a sixth drain, wherein the fourth gate is electrically connected to a second word line, the sixth source is electrically connected to the first bit line, and the sixth drain is electrically connected to the third gate; Wherein the first gate is further electrically connected to the fourth drain and the fifth drain, and the third gate is further electrically connected to the first drain and the second drain.

4. The memory according to claim 3, wherein, The sixth transistor is disposed on the same layer as the third transistor and has the same type as the third transistor, both being N-type transistors.

5. The memory according to claim 3 or 4, wherein, In the planar structure of the memory device, the first inverter and the second inverter are symmetrically disposed, and the third transistor and the sixth transistor are symmetrically disposed.

6. The memory according to any one of claims 3-5, wherein, The first source and the fourth source are electrically connected to a first power signal line, and the second source and the fifth source are electrically connected to a second power signal line, The first power signal line extends in a first direction, the second power signal line extends in a second direction, and the second direction is different from the first direction.

7. The memory according to claim 6, wherein The first word line is multiplexed as the second word line, and the first word line extends along the first direction. The first inverter and the second inverter are disposed between the first word line and the first power supply signal line.

8. The memory according to claim 6 or 7, wherein, The second power supply signal line includes a first sub-power supply line and a second sub-power supply line extending along the second direction. The first bit line and the second bit line extend along the second direction and are located between the first sub-power supply line and the second sub-power supply line.

9. The memory according to claim 8, wherein, The third transistor and the sixth transistor are located between the first sub-power supply line and the second sub-power supply line.

10. The memory according to any one of claims 6-9, wherein, The first source, the first drain, the fourth source, and the fourth drain are arranged on a first straight line. The second source, the second drain, the fifth source, and the fifth drain are arranged on a second straight line. The first straight line is parallel to the second straight line and parallel to the first direction.

11. The memory according to claim 10, wherein, The third source and the third drain are arranged on a third straight line. The sixth source and the sixth drain are arranged on a fourth straight line. The third straight line is parallel to the fourth straight line and parallel to the second direction.

12. The memory according to claim 3, wherein, The first source and the fourth source are electrically connected to the first power supply signal line, the second source and the fifth source are electrically connected to the second power supply signal line, and the first word line is multiplexed as the second word line. The first power supply signal line, the second power supply signal line, and the first word line extend along the first direction. The first bit line and the second bit line extend along the second direction. The first direction is different from the second direction.

13. The memory according to claim 12, wherein, The first inverter and the second inverter are located between the first word line and the second power supply signal line.

14. The memory according to claim 12 or 13, wherein, The first source and the first drain are arranged on a fifth straight line. The fourth source and the fourth drain are arranged on a sixth straight line. The fifth straight line is parallel to the second direction, and the sixth straight line is parallel to the first direction.

15. A storage device, comprising: A memory array including a plurality of memories arranged in an array as described in any one of claims 1-14, and A peripheral circuit disposed on at least one side of the memory array, including a driving transistor. Wherein the driving transistor includes a first driving transistor and a second driving transistor stacked in a direction perpendicular to the substrate, and the first driving transistor and the second driving transistor share a first driving gate.

16. The storage device according to claim 15, wherein, The peripheral circuit includes: A first encoder disposed on a first side of the memory array, electrically connected to the first word line, and configured to provide a first electrical signal to the first word line, and A second encoder disposed on a second side of the memory array, electrically connected to the first bit line, and configured to provide a second electrical signal to the first bit line; At least one of the first encoder and the second encoder includes the driving transistor.

17. A method for manufacturing a memory, comprising: Providing a substrate. A first inverter is formed on the substrate, wherein the first inverter includes a first transistor and a second transistor stacked in a direction perpendicular to the substrate, the first transistor and the second transistor include a shared first gate, the first transistor further includes a first source and a first drain disposed on a side of the first gate close to the substrate, the second transistor further includes a second source and a second drain disposed on a side of the first gate far from the substrate, the first drain and the second drain are electrically connected through a first via, the first source is configured to receive a first power signal, the second source is configured to receive a second power signal, and A third transistor is formed on the substrate, wherein the third transistor includes a second gate, a third source, and a third drain, the second gate is electrically connected to a first word line, the third source is electrically connected to a first bit line, and the third drain is electrically connected to the first gate.

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