RFID tag, RFID analog conditioner circuit and RFID tag digital core

Abstract

An RFID tag having an antenna input (RF1) connected to a carrier frequency divider (FD16), to a demodulator (Dmd) and to a harvester with modulator (HM), whose output is connected to the carrier frequency divider (FD16), the demodulator (Dmd), a reference voltage circuit (Vref), a voltage hold circuit (VH) and an initialization circuit (Int). The output of the reference voltage circuit (Vref) is connected to the demodulator (Dmd), whose output is connected to a demodulation interpreter (DI). The frequency divider (FD16) output is connected to the demodulation interpreter (DI), a response preparation and shaping circuit (RPS) and a subcarrier frequency divider (FD64), whose output is connected to the demodulation interpreter (DI) and to the response preparation and shaping circuit (RPS), whose output is connected to a modulation input of the harvester with modulator (HM). At least one output of the demodulation interpreter (DI) is connected to the response preparation and shaping circuit (RPS). The inputs of the voltage hold circuit (VH) and an initialization circuit (Int) are connected to the power output of the harvester with modulator (HM). The output of the voltage hold circuit (VH) is connected to a holding input of the demodulation interpreter (DI), and an output of the initialization circuit (Int) is connected to initialization inputs of the demodulation interpreter (DI) and the response preparation and shaping circuit (RPS). The RFID tag also comprises a protocol handler (ProtH), whose inputs are connected to an initialization circuit (Int), the demodulation interpreter (DI) and the subcarrier frequency divider (FD64), while an output of protocol handler (ProtH) is connected to the response preparation and shaping circuit (RPS).

Description

[0001] RFID tag, RFID analog conditioner circuit and RFID tag digital core

[0002] The invention concerns an RFID tag, an RFID analog conditioner circuit and an RFID tag digital core, intended especially for flexible integrated circuits for near-field communication (NFC).

[0003] There is known from publication titled „A Thin Elastic NFC Forum Type 1 Compatible RFID Tag” in IEEE Journal of Solid-State Circuits (Early Access), DOI: 10.1109 / JSSC.2023.3300256, an NFC RFID tag, whose architecture has been divided into an analog part and a digital part. The analog part consists of the following circuits: harvester with modulator, frequency divider, AM demodulator, reference voltage circuit, and symbol detector. The digital part consists of the following circuits: symbol decoder, NFC core, and NFC response circuit. In this tag, the antenna is connected to the harvester with modulator, the frequency divider, and the AM demodulator. The supply voltage from the harvester with modulator is connected to each analog and digital tag circuit. The output of the frequency divider is connected to the symbol decoder, the NFC core, the NFC response circuit, and the symbol detector. The output of the reference voltage circuit is connected to the AM demodulator and the symbol detector. The output of the AM demodulator is connected to the symbol detector and the frequency divider. Two other outputs of the AM demodulator are connected to the symbol detector. The output of the symbol detector is connected to the symbol decoder. The outputs of the symbol decoder are connected to the NFC core. The outputs of the NFC core are connected to the NFC response circuit. At least one output of the NFC response circuit is connected to the frequency divider, while the modulation output of the NFC response circuit is connected to the harvester with modulator. The symbol detector consists of a pulse counter made of a cascade of four flip-flops, a synchronizer of two flip-flops, and a delay circuit of five inverters. The NFC response circuit contains a 73 -bit shift register made of flip-flops. The digital part of the tag uses two clock signals with frequencies resulting from dividing the antenna signal frequency by 16 and 64.

[0004] There is known from the Korean patent description KR101839081B1, an NFC integrated circuit, which includes a rectifier for rectifying an ASK-modulated RF input signal and outputting a rectified signal; an offset calibrator for tracking the rectified signal outputted from the rectifier in response to control signals and generating a first input signal in accordance with a result of tracking; and a comparator for receiving and comparing the first input signal and a reference signal, and outputting a comparison signal. It is possible to automatically calibrate the offset of the comparator. In particular, an architecture is known from this invention in which part of the RF interface contains the following circuits: a rectifier, a modulator / demodulator, and a clock signal extractor. Moreover, the entire circuit contains a power management circuit, an internal oscillator, and a control circuit.

[0005] There are known from the European patent application EP2680458A2 an apparatus and method to provide improved NFC communications. A first NFC device antenna transmits information to a second NFC device by driving an antenna module with a current to generate a magnetic field. The magnetic field is modulated and the information is transmitted according to a first set of operating parameters. A second NFC device harvests power from the magnetic field and communicates information to the first NFC device by modulating the magnetic field according to a second set of operating parameters, which is received by the first NFC device. The first NFC device recovers a signal metric from the modulated magnetic field. The first NFC device uses the signal metric to provide feedback regarding the second set of operating parameters. Various systems are presented to utilize the signal metric feedback and provide efficient and reliable communications between the first and second NFC devices.

[0006] In particular, a system is known for this solution: an antenna module, an antenna driver, a modulator, a demodulator, a detection module, and an NFC controller module.

[0007] There is known from American invention description US2002167405A1 a radio frequency identification (RFID) architecture, in which RFID tags are interrogated by a reader, which may be located in a network of readers. The reader transmits symbols to the tags. Tags respond to the interrogations with symbols that each represent one or more bits of data. An RFID tag includes an antenna pad, a receiver, a state machine, and a modulator. The receiver is coupled to the antenna pad. The receiver receives a symbol from the antenna pad and outputs a received signal. The state machine is configured to determine a response symbol from the received signal and an operating state of the tag. The modulator is coupled to the antenna pad. The modulator is configured to backscatter modulate the received symbol with the response symbol. The modulator is configured to output the backscatter modulated symbol to the antenna pad.

[0008] In particular, an RFID tag digital core solution is known from this invention, comprising two frequency dividers connected to an oscillator, a counter connected to one frequency divider, and a state machine to which an interface part comprising a rectifier, a charge pump, and a modulator is connected.

[0009] There are known from international patent description W02008013418A1 apparatus and method for integrated reader and tag. Provided are a reader-tag integrated RFID apparatus and a method for controlling the same. The apparatus includes a tag unit for communicating with an external reader, and transmitting a response signal and data corresponding to a signal transmitted from the external reader to the external reader, a reader unit for selecting a channel between other reader and the reader- tag integrated RFID apparatus with a different delay time, and communicating with an external tag using a random value to minimize collision; and a controller for selectively activating one of the tag unit and the reader unit if it necessary.

[0010] In particular, a functionally similar solution to an RFID response preparation and shaping circuit is known from this invention, comprising a tag memory connected to a tag controller, to which a message generator is connected, which is connected to a checksum calculator, which is connected to a coding system, which is connected to a digital modulator. In addition, the message generator is connected to a tag controller and an anti -collision state machine, to which a message buffer is connected, and a digital decoder and a demodulator are connected via a system for calculating and confirming the checksum. There is known from patent description of Japanese invention JP2006157593A an RFID communication system and wireless communication device comprising interpreter. A wireless communication device is connected to a host device for outputting instruction information of RFID recording media in an RFID communication system. A plurality of antenna mechanisms for transmitting / receiving transmitting signals to the RFID recording media and received signals from the RFID recording media are provided to the wireless communication device for each of communication specifications of the RFID recording media. The wireless communication device is provided with a control mechanism having a signal processing means which generates a transmitting signal and analyzes a received signal on the basis of the communication specifications shown by the instruction information, and antenna switching means for selecting an antenna mechanism to transmit a transmitting signal and an antenna mechanism to receive a received signal.

[0011] In particular, a solution is known from this invention in which the controller encodes an instruction command as instruction information from the host computer using the encoder by the command interpreter unit and passes it to the tag driver. When the instruction is data writing, a value to be written is temporarily stored in the memory. The tag driver converts an instruction from the host computer into a radio wave format and passes it to the antenna module. The antenna module transmits the radio wave to the RFID tag as a transmission signal. The tag driver analyzes an analog signal as a radio wave received from the RFID tag via the antenna module, converts the content into a digital signal, and passes the digital signal to the command interpreter unit. The command interpreter unit decodes the received digital signal by the decoder and supplies it to the host computer as data read from the tag.

[0012] In state-of-the-art electronics engineering, there are known (remote) radio-frequency identification (RFID) systems, and in particular near-field communication (NFC). There are known in the art field-effect transistors (FETs) with an insulated gate, thin-film transistors (TFTs), as well as transistors based on indium-gallium zinc oxide (IGZO or InGaZnO - from indium (In), gallium (Ga), zinc (Zn), oxygen (O)). It is also known that the designation of the drain and source of these transistors is conventional because, due to the symmetrical structure of the transistor, changing these designations does not affect the functionality of the transistor or the circuit in which it is located; however, this nomenclature is of an ordering nature.

[0013] The aim of the invention is to create a small, in terms of area occupied, and fast circuit for NFC RFID in a-IGZO technology, which is characterized by large TFT transistors with a relatively low cut-off frequency. There is therefore a need to solve the problem of implementation with too large an area, meeting critical time parameters and providing sufficient power, which are necessary for the correct operation of the entire NFC RFID tag circuit.

[0014] The essence of the solution is that an RFID tag having an antenna input connected to an antenna input of a carrier frequency divider, to an antenna input of a demodulator and to a first antenna input of a harvester with modulator, whose power output is connected to a power input of the carrier frequency divider, to a power input of the demodulator and to a reference voltage circuit, whose output is connected to a reference input of the demodulator, whose output is connected to a demodulated signal input of a demodulation interpreter, and having the frequency divider output connected to a subcarrier frequency divider, to the demodulation interpreter and to a response preparation and shaping circuit, while the output of the subcarrier frequency divider is connected to the demodulation interpreter and to the response preparation and shaping circuit, whose output is connected to a modulation input of the harvester with modulator, and having at least one output of the demodulation interpreter connected to the response preparation and shaping circuit, according to the invention, it comprises a voltage hold circuit and an initialization circuit, whose inputs are connected to the power output of the harvester with modulator, an output of the voltage hold circuit is connected to a holding input of the demodulation interpreter, and an output of the initialization circuit is connected to initialization inputs of the demodulation interpreter and the response preparation and shaping circuit. Moreover, RFID tag comprises a protocol handler, whose inputs are connected to an initialization circuit, the demodulation interpreter and the subcarrier frequency divider, while an output of protocol handler is connected to the response preparation and shaping circuit. The technical advantage of using the voltage hold circuit is to maintain a constant voltage at the holding output of the conditioner circuit, even in the event of a short-term lack of a high-frequency signal at the antenna input. However, as a result of the initialization circuit, it is possible to reset several digital circuits connected to this circuit through the initialization output and synchronously trigger their operation at the correct time and their implementation does not require the use of a supply voltage maintaining the states of the registers.

[0015] Advantageously, the reference voltage circuit is connected to the demodulator via a ripple rejection circuit, which has a power input connected to the power output of the harvester with modulator. This makes the demodulator less susceptible to errors caused by momentary fluctuations in the DC voltage coming from the harvester with modulator.

[0016] Advantageously, the RFID tag comprises a shunt regulator circuit connected to the power output of the harvester with modulator. For that reason, the voltage at the harvester's output with modulator and the entire power supply line cannot exceed the maximum voltage value, which protects the other circuits from destruction or incorrect operation, even with high signal amplitudes at the antenna input.

[0017] Advantageously, the protocol handler comprises a clock phase synchronization circuit, whose output is connected to the carrier frequency divider and to the subcarrier frequency divider, the first input is connected to at least one of the outputs of the demodulation interpreter, while the second input is connected to the response end-of-frame signal output of the response preparation and shaping circuit. Moreover, the protocol handler comprises a protocol state machine and a checksum calculator, where both circuits are connected to the output of the subcarrier frequency divider, both circuits are connected to at least one output of the demodulation interpreter, the output of the protocol state machine is connected to the checksum calculator, while the output of the checksum calculator is connected to the protocol state machine, the output of the protocol state machine, which is also the output of the protocol handler, is connected to the response preparation and shaping circuit, and the initialization input of the protocol state machine is connected to the output of the initialization circuit. As the result of use of the clock phase synchronization circuit, the clock can be adjusted precisely to the signal phase, and thus the response time parameters. However, the protocol state machine and the checksum calculator makes it possible to manage the content of transmitted data, including calculating checksums confirming the consistency of received commands.

[0018] Advantageously, the RFID tag comprises a second antenna input connected to a second antenna input of the harvester with modulator. By using the second complementary antenna signal input, it is possible to provide a much attenuated high-frequency signal than in the case without this input, which is beneficial to the efficiency of the harvester with modulator and reduces the risk of overloading the demodulator and carrier frequency divider.

[0019] Advantageously, the second antenna input is connected to a ground of the RFID tag. For that reason, the entire tag has asymmetric inputs and outputs, significantly reducing the number of nodes and the level of complexity of the construction of particular tag components.

[0020] Advantageously, a power supply bus, supplying digital core circuits, is connected to the power output of the harvester with modulator. This allows for autonomous power supply of the entire tag only with energy obtained from the antenna inputs. Advantageously, the RFID tag operates substantially at a frequency of 13.56 MHz of the input signal. For that reason, it is possible to use the circuit to implement the NFC standard.

[0021] Advantageously, the voltage hold circuit contains a diode and a capacitor connected in series between the input and ground of this circuit, and the output is connected to the connection point of the diode and the capacitor. For that reason, temporary drops in signal amplitude at the antenna input or inputs caused by modulation during communication or spikes caused by supply voltage surges are eliminated.

[0022] Advantageously, the diode used in the voltage hold circuit is made of a transistor with its gate connected to its source and connected to the input of the circuit, and the drain of the transistor connected to the capacitor and the output of the circuit. For that reason, it is possible to implement the circuit in a technological process that does not allow the creation of a P-N or M-S semi conductor j uncti on .

[0023] Advantageously, the capacitance of the capacitor used in the voltage hold circuit ranges from 5 pF to 20 pF. For that reason, a sufficient electric charge is provided to momentarily maintain the voltage in the case of signal decays at the antenna input or inputs.

[0024] Advantageously, the ripple rejection circuit has its input and output connected inside the circuit and connected to the power input of the circuit via a resistor, and to the ground of the circuit via a capacitor or capacitors connected in parallel. This allows the capacitor charging current to be limited by the resistor, and the parallelly connected capacitors increase the stored charge.

[0025] Advantageously, the resistance of the resistor used in the ripple rejection circuit ranges from 2 MQ to 5 MO. This allows the discharge time constant of the charge-holding capacitor to initialize the demodulator on subsequent input signal frames properly.

[0026] Advantageously, the cumulative capacitance of capacitors used in the ripple rejection circuit ranges from 3 pF to 50 pF. Therefore, the level of interference at the demodulator supply voltage does not cause errors during signal demodulation.

[0027] Furthermore, the essence of the solution is that an RFID analog conditioner circuit having an antenna input connected to an antenna input of a carrier frequency divider, to an antenna input of a demodulator and to a first antenna input of a harvester with modulator, whose power output is connected to a power input of the carrier frequency divider, to a power input of the demodulator and to a reference voltage circuit, whose output is connected to a reference input of the demodulator, whose output is connected to a demodulation output of the RFID analog conditioner circuit, as well as having a modulation input connected to a modulation input of the harvester with modulator, according to the invention, it comprises a voltage hold circuit and an initialization circuit, whose inputs are connected to the power output of the harvester with modulator. Furthermore, an output of the voltage hold circuit is connected to a holding output of the RFID analog conditioner circuit, and an output of the initialization circuit is connected to an initialization output of the RFID analog conditioner circuit. The technical advantage of using the voltage hold circuit is to maintain a constant voltage at the holding output of the conditioner circuit, even in the event of a short-term lack of a high-frequency signal at the antenna input. However, as a result of the initialization circuit, it is possible to reset several digital circuits connected to this circuit through the initialization output and synchronously trigger their operation at the correct time.

[0028] Advantageously, the reference voltage circuit is connected to the demodulator via a ripple rejection circuit, which has a power input connected to the power output of the harvester with modulator. This makes the demodulator less susceptible to errors caused by momentary fluctuations in the DC voltage coming from the harvester with modulator.

[0029] Advantageously, the RFID analog conditioner circuit comprises a shunt regulator circuit connected to the power output of the harvester with modulator. For that reason, the voltage at the harvester's output with modulator and the entire power supply line cannot exceed the maximum voltage value, which protects the other circuits from destruction or incorrect operation, even with high signal amplitudes at the antenna input.

[0030] Advantageously, the RFID analog conditioner circuit comprises a second antenna input connected to a second antenna input of the harvester with modulator. By using the second complementary antenna signal input, it is possible to provide a much attenuated high-frequency signal than in the case without this input, which is beneficial to the efficiency of the harvester with modulator and reduces the risk of overloading the demodulator and carrier frequency divider.

[0031] Advantageously, the second antenna input is connected to a ground of the RFID analog conditioner circuit. For that reason, the entire conditioner has asymmetric inputs and outputs, significantly reducing the number of nodes and the level of complexity of the construction of particular conditioner components.

[0032] Advantageously, the RFID analog conditioner circuit operates substantially at a frequency of 13.56 MHz of the input signal. For that reason, it is possible to use the circuit to implement the NFC standard.

[0033] Advantageously, all transistors in the circuit are the FETs of "n" type. The use of one type of FETs with insulated gates simplifies the technological process of implementing a circuit.

[0034] Advantageously, all transistors in the circuit are TFT-type transistors. TFTs allow to manufacture cheap and / or flexible integrated circuits.

[0035] Advantageously, the transistor channels are made of amorphous semiconductor material. The use of amorphous semiconductor material ensures low cost of manufacturing transistors (at relatively low temperatures).

[0036] Advantageously, the transistors contain indium-gallium zinc oxide. The use of indium gallium zinc oxide (IGZO) provides a relatively high carrier mobility parameter.

[0037] Advantageously, the voltage hold circuit contains a diode and a capacitor connected in series between the input and ground of this circuit, and the output is connected to the connection point of the diode and the capacitor. For that reason, temporary drops in signal amplitude at the antenna input or inputs caused by modulation during communication or spikes caused by supply voltage surges are eliminated.

[0038] Advantageously, the diode used in the voltage hold circuit is made of a transistor with its gate connected to its source and connected to the input of the circuit, and the drain of the transistor connected to the capacitor and the output of the circuit. For that reason, it is possible to implement the circuit in a technological process that does not allow the creation of a P-N or M-S semi conductor j uncti on .

[0039] Advantageously, the width-to-length ratio of the transistor channel used to construct the diode in the voltage hold circuit ranges from 5 to 20. For that reason, a proper current efficiency of the transistor is provided, ensuring a suitably short charging time of the capacitance connected to the transistor.

[0040] Advantageously, the capacitance of the capacitor used in the voltage hold circuit ranges from 5 pF to 20 pF. For that reason, a sufficient electric charge is provided to momentarily maintain the voltage in the case of signal decays at the antenna input or inputs.

[0041] Advantageously, the ripple rejection circuit has its input and output connected inside the circuit and connected to the power input of the circuit via a resistor, and to the ground of the circuit via a capacitor or capacitors connected in parallel. This allows the capacitor charging current to be limited by the resistor, and the parallelly connected capacitors increase the stored charge.

[0042] Advantageously, the resistance of the resistor used in the ripple rejection circuit ranges from 2 MQ to 5 MO. This allows the discharge time constant of the charge-holding capacitor to initialize the demodulator on subsequent input signal frames properly. Advantageously, the cumulative capacitance of capacitors used in the ripple rejection circuit ranges from 3 pF to 50 pF. Therefore, the level of interference at the demodulator supply voltage does not cause errors during signal demodulation.

[0043] Furthermore, the essence of the solution is that, an RFID tag digital core comprising a carrier frequency divider, whose output is connected to a demodulation interpreter, to a response preparation and shaping circuit and to a subcarrier frequency divider, whose output is connected to the demodulation interpreter and to the response preparation and shaping circuit, whose output is connected to a modulation output of the RFID tag digital core, whose demodulation input is connected to the demodulated signal input of the demodulation interpreter, of which at least one output is connected to the response preparation and shaping circuit, according to the invention, it comprises a protocol handler and has a holding input and an initialization input, where the holding input is connected to the holding input of the demodulation interpreter, the initialization input is connected to the initialization inputs of the demodulation interpreter, the response preparation and shaping circuit and the protocol handler. Moreover, two further inputs of the protocol handler are connected to the subcarrier frequency divider and the demodulation interpreter, while the output of the protocol handler is connected to the response preparation and shaping circuit. The technical advantage of such a circuit design is the management of the transmission protocol by the protocol handler, starting with the content of the transmitted data, down to the time parameters of the frames. Due to the use of holding input, the circuit can work uninterruptedly during short-term decays of the high-frequency signal. Due to the connection of subcircuits to the initialization input, their implementation does not require the use of a supply voltage maintaining the states of the registers.

[0044] Advantageously, the protocol handler comprises a clock phase synchronization circuit, whose output is connected to the carrier frequency divider and to the subcarrier frequency divider, the first input is connected to at least one of the outputs of the demodulation interpreter, while the second input is connected to the response end-of-frame signal output of the response preparation and shaping circuit. Therefore, the clock can be adjusted precisely to the signal phase, and thus the response time parameters.

[0045] Advantageously, the subcarrier frequency divider comprises two sequentially connected "D" type flip-flops equipped with "R" and "S" inputs, where the input of the first flip-flop is connected to the input of the divider, the output of the second flip-flop is connected to the output of the divider, and the "R" and "S" inputs are connected to the outputs of the clock phase synchronization circuit accordingly to the expected initial state of the divider. This makes it possible to choose a proper phase adjustment of the divider output signal.

[0046] Advantageously, the protocol handler comprises a protocol state machine and a checksum calculator, where both circuits are connected to the output of the subcarrier frequency divider, both circuits are connected to at least one output of the demodulation interpreter, the output of the protocol state machine is connected to the checksum calculator, while the output of the checksum calculator is connected to the protocol state machine, whose initialization input is connected to the initialization input of the RFID tag digital core, and further output of the protocol state machine is connected to further input of the response preparation and shaping circuit. This makes it possible to manage the content of transmitted data, including calculating checksums confirming the consistency of received commands.

[0047] Advantageously, the protocol state machine comprises a counter. It allows some states encoded by the protocol state machine to require fewer registers for implementation.

[0048] The invention has been described below in detail, with reference to the attached figures. Fig. 1 presents a schematic diagram of a basic RFID tag, fig. 2 presents a schematic diagram of a RFID tag with supporting circuits, fig. 3 presents a schematic diagram of a basic RFID analog conditioner circuit, fig. 4 presents a schematic diagram of an RFID analog conditioner circuit with supporting circuits, fig. 5 presents a schematic diagram of an RFID tag digital core with a general form of protocol handler, and fig. 6 - a schematic diagram of an RFID tag digital core comprising a detailed construction of protocol handler.

[0049] The RFID tag in the embodiment shown in fig. 1 consists essentially of two parts marked with a dashed line: an RFID analog conditioner circuit ANL and an RFID tag digital core DIG. The carrier frequency divider FD16 has been classified as both of these parts, because of its mixed circuits - i.e., it has both a purely analog and a digital part. The RFID analog conditioner circuit ANL contains a harvester with modulator HM, an initialization circuit Int, a reference voltage circuit Vref, a voltage hold circuit VH, a demodulator Dmd, an antenna input RF1 and the analog subcircuit of the carrier frequency divider FD16. The RFID tag digital core DIG contains the digital part of the carrier frequency divider FD16, a subcarrier frequency divider FD64, a demodulation interpreter DI, a response preparation and shaping circuit RPS and a protocol handler ProtH.

[0050] The antenna input RF1 is connected to: the first antenna input harvester with modulator HM, the antenna input of the carrier frequency divider FD16, and the antenna input of the demodulator Dmd. The power output of the harvester with modulator HM is connected to: the power input of the carrier frequency divider FD16, the reference voltage circuit Vref, the power input of the demodulator Dmd, the input of the voltage hold circuit VH, and the input of the initialization circuit Int. The output of the reference voltage circuit Vref is connected to the reference input of the demodulator Dmd. The output of the demodulator Dmd is connected to the demodulation interpreter DI. The voltage hold circuit VH output is connected to the holding input of the demodulation interpreter DI. The output of the initialization circuit Int is connected to the initialization inputs of the following circuits: the demodulation interpreter DI, the response preparation and shaping circuit RPS, and the protocol handler ProtH. The output of the carrier frequency divider FD16 is connected to the subcarrier frequency divider FD64, the demodulation interpreter DI, and the response preparation and shaping circuit RPS. The subcarrier frequency divider FD64 output is connected to the demodulation interpreter DI, the response preparation and shaping circuit RPS, and the protocol state machine PSM. The first output of the demodulation interpreter DI is connected to the response preparation and shaping circuit RPS, and the second output of the demodulation interpreter DI is connected to the protocol handler ProtH. The output response preparation and shaping circuit RPS is connected to the modulation input of the harvester with modulator HM. The protocol handler ProtH output is connected to the response preparation and shaping circuit RPS.

[0051] The RFID tag in the embodiment shown in fig. 2 consists essentially of two parts marked with a dashed line: an RFID analog conditioner circuit ANL and an RFID tag digital core DIG. The carrier frequency divider FD16 has been classified as both of these parts, because of its mixed circuits - i.e., it has both a purely analog and a digital part. The RFID analog conditioner circuit ANL contains a harvester with modulator HM, a shunt regulator circuit SR, an initialization circuit Int, a reference voltage circuit Vref, a ripple rejection circuit RR, a voltage hold circuit VH, a demodulator Dmd, and the analog subcircuit of the carrier frequency divider FD16. The RFID tag digital core DIG contains the digital part of the carrier frequency divider FD16, a subcarrier frequency divider FD64, a demodulation interpreter DI, a response preparation and shaping circuit RPS and a protocol handler ProtH, which contains a protocol state machine PSM, a checksum calculator CRC and a clock phase synchronization circuit ClkS.

[0052] The antenna input RF1 is connected to: the first antenna input harvester with modulator HM, the antenna input of the carrier frequency divider FD16, and the antenna input of the demodulator Dmd. The second antenna input RF1 is connected to the second antenna input of the harvester with modulator HM and the ground gnd. The power output of the harvester with modulator HM is connected to: the power input of the carrier frequency divider FD16, the reference voltage circuit Vref, the shunt regulator circuit SR, the power input of the ripple rejection circuit RR, the power input of the demodulator Dmd, the input of the voltage hold circuit VH, and the input of the initialization circuit Int. The output of the reference voltage circuit Vref is connected to the input of the ripple rejection circuit RR, and the output of the ripple rejection circuit RR is connected to the reference input of the demodulator Dmd. The output of the demodulator Dmd is connected to the demodulation interpreter DI. The voltage hold circuit VH output is connected to the holding input of the demodulation interpreter DI. The output of the initialization circuit Int is connected to the initialization inputs of the following circuits: the demodulation interpreter DI, the response preparation and shaping circuit RPS, and the protocol state machine PSM. The output of the carrier frequency divider FD16 is connected to the subcarrier frequency divider FD64, to the demodulation interpreter DI, and to the response preparation and shaping circuit RPS. The subcarrier frequency divider FD64 output is connected to the demodulation interpreter DI, to the response preparation and shaping circuit RPS, and to the protocol state machine PSM. The output of the demodulation interpreter DI is connected to the response preparation and shaping circuit RPS and to the clock phase synchronization circuit ClkS. The first output of the response preparation and shaping circuit RPS is connected to the modulation input of the harvester with modulator HM. The second output of the response preparation and shaping circuit RPS is connected to the clock phase synchronization circuit ClkS. The first output of the protocol state machine PSM is connected to the response preparation and shaping circuit RPS. The second output of the protocol state machine PSM is connected to the checksum calculator CRC. The output of the checksum calculator CRC is connected to the protocol state machine PSM. The clock phase synchronization circuit ClkS output is connected to the carrier frequency divider FD16 and to the subcarrier frequency divider FD64.

[0053] The harvester with modulator HM circuit converts the high-frequency voltage signal from the antenna input RF1 or the antenna inputs RF1 and RF2 to a constant voltage that supplies a number of components of the ANL conditioner circuit that are connected to the power output of the harvester with modulator HM. The maximum value of this voltage is limited by the shunt regulator circuit SR (to about 6 V), which ensures the correct operation of the ANL conditioner components at a high level of the high-frequency signal amplitude at the antenna input RF1 or the antenna inputs RF1 and RF2 while reducing the risk of damage caused by a too high voltage level. In addition to the power-delivering function, the harvester with modulator HM loads or unloads the antenna inputs RF1 and RF2, depending on the voltage level on the modulation input of the harvester with modulator HM supplied from the response preparation and shaping circuit RPS, thus affecting the total impedance at the antenna inputs RF1 and RF2, which performs the return communication of the NFC tag. The high-frequency alternating voltage from the antenna input RF1, after being provided to the carrier frequency divider FD16, is converted into a signal with a sixteen-time lower frequency with preserved phase synchronism, which can additionally be regulated from the digital side of the circuit.

[0054] Due to the use of the reference voltage circuit Vref, it is possible to obtain a reference voltage independent of the temporary amplitude of the high-frequency signal at the input or inputs of the ANL conditioner and, consequently, at the power output of the harvester with modulator HM. Moreover, the voltage from the antenna input RF1 is fed to the input of the demodulator Dmd, which, by comparing the temporary values of the amplitude from the antenna input RF1 with the voltage from the reference voltage circuit Vref, converts the temporary values of this amplitude into a binary sequence assigning respectively high and low amplitude values to low and high logical levels for the demodulation interpreter DI. The ripple rejection circuit RR has an additional beneficial effect on the operation of the demodulator Dmd by reducing its vulnerability to errors caused by unusual voltage interferences at the output of the reference voltage circuit Vref. The high-frequency alternating voltage from the antenna input RF1, after conversion to a constant voltage in the harvester with modulator HM, is also used to accumulate electrical energy in the voltage hold circuit VH, whose goal is to maintain a constant voltage during short-term decays of the high-frequency signal, and for that reason, the circuits connected to the demodulation interpreter DI, sensitive to the supply voltage declining, can operate correctly.

[0055] The use of the second, symmetrical antenna input RF2 connected to the circuit ground gnd, allows for the significant reduction of the number of nodes and the level of complexity of the construction of particular conditioner components. However, by connecting the power output of the harvester with modulator HM to the power supply bus Vdd, supplying digital core circuits DIG, it is possible to ensure an autonomous power supply of the entire tag exclusively with energy obtained from the antenna inputs RF1 and RF2, and therefore from the antenna.

[0056] The carrier frequency divider FD16 divides the carrier frequency of the received radio signal, providing a clock signal to the components: the demodulation interpreter DI and the response preparation and shaping circuit RPS, responsible for interacting with the demodulated signal from the demodulator Dmd and the modulated signal delivered to the modulation input of the harvester with modulator HM. The subcarrier frequency divider FD64 performs further clock frequency division for the remaining circuits, and those parts of the demodulation interpreter DI and the response preparation and shaping circuit RPS can be implemented using a lower clock frequency.

[0057] The RFID demodulation interpreter DI processes raw data from the demodulator Dmd in digital, asynchronous pulses correlated with the occurrences of subsequent modulations from the reader. The result of the RFID demodulation interpreter DI operation is information about the structure and content of the command frames received from the reader - high-level data containing information about the received command - delivered to the protocol handler ProtH. The demodulation interpreter DI is characterized by asynchronous operation, which results in its simplified architecture and achievement of the goal, which was a small and efficient implementation. Connecting the demodulation interpreter DI circuit to the voltage hold circuit VH allows for correct operation of the critical components inside the demodulation interpreter DI, which are sensitive to power failures. In addition, the demodulation interpreter DI sends a synchronization signal to the response preparation and shaping circuit RPS, ensuring that the response will be sent back with the correct timing parameters.

[0058] The main task of the response preparation and shaping circuit RPS is the ability to determine the start and the end of transmission and the ability to select the appropriate response message of the circuit, while the main task of the protocol handler ProtH is to perform high-level handling of the tag protocol. The response preparation and shaping circuit RPS receives high-level information about the message from the protocol handler ProtH that is to be sent back by the tag and then processes it into a packet, which, after encoding, is used to control the modulator via the modulation input of the harvester with modulator HM. Using the internally stored state of the communication with the reader and information about the newly received command, it decides which message must be sent back in response to this command.

[0059] In particular, in constructing the protocol handler ProtH, the protocol state machine PSM can be distinguished, which performs all the essential functions of the protocol handler ProtH. The protocol handler ProtH can be expanded with two subcircuits - checksum calculator CRC and clock phase synchronization circuit ClkS - performing additional functionality. The checksum calculator CRC verifies the consistency of data received from the demodulation interpreter DI, and it communicates in both directions with the protocol state machine PSM, receiving the control signal and sending information about the consistency of the processed data. The clock phase synchronization circuit ClkS controls the operation of the frequency dividers FD16 and FD64 - it can adjust the phase of the generated clock signals. It can also turn off the frequency dividers FD16 and FD64, which results in energy saving.

[0060] In the case of ASIC (Application-Specific Integrated Circuit) implementation, it is advantageous to use the initialization circuit Int connected to the demodulation interpreter DI, the response preparation and shaping circuit RPS, and the protocol handler ProtH, which allows setting the initial state in these circuits. Consequently, an implementation without requiring a supply voltage to maintain the states of the circuit registers is possible.

[0061] The invention allows for an efficient implementation in terms of space of the RFID tag in a-IGZO technology. The industrial application of the invention is in the industry and market for products requiring individual electronic markings.

[0062] The RFID analog conditioner circuit in the embodiment shown in fig. 3 contains the following circuits: a harvester with modulator HM, an initialization circuit Int, a reference voltage circuit Vref, a voltage hold circuit VH, a demodulator Dmd and an analog subcircuit of carrier frequency divider FD16. Moreover, the RFID analog conditioner circuit ANL has: an antenna input RF1, a demodulation output o-Dmd, a holding output o-VH, a modulation input i-Mod, and an initialization output o-Int.

[0063] The antenna input RF1 is connected to: the first antenna input harvester with modulator HM, the antenna input of the carrier frequency divider FD16, and the antenna input of the demodulator Dmd. The power output of the harvester with modulator HM is connected to: the power input of the carrier frequency divider FD16, the reference voltage circuit Vref, the power input of the demodulator Dmd, the input of the voltage hold circuit VH, and the input of the initialization circuit Int. The output of the reference voltage circuit Vref is connected to the reference input of the demodulator Dmd. The output of the demodulator Dmd is connected to the demodulation output o-Dmd. The voltage hold circuit VH output is connected to the holding output o-VH. The modulation input i-Mod is connected to the modulation input of the harvester with modulator HM. The output of the initialization circuit Int is connected to the initialization output o-Int.

[0064] The RFID analog conditioner circuit in the embodiment shown in fig. 4 contains the following circuits: a harvester with modulator HM, a shunt regulator circuit SR, an initialization circuit Int, a reference voltage circuit Vref, a ripple rejection circuit RR, a voltage hold circuit VH, a demodulator Dmd, and an analog subcircuit of carrier frequency divider FD16. Moreover, the RFID analog conditioner circuit ANL has: an antenna input RF1, a second antenna input RF2, a demodulation output o-Dmd, a holding output o-VH, a modulation input i-Mod, an initialization output o-Int, and a ground gnd.

[0065] The antenna input RF1 is connected to: the first antenna input harvester with modulator HM, the antenna input of the carrier frequency divider FD16, and the antenna input of the demodulator Dmd. The second antenna input RF1 is connected to the second antenna input of the harvester with modulator HM and the ground gnd. The power output of the harvester with modulator HM is connected to: the power input of the carrier frequency divider FD16, the reference voltage circuit Vref, the shunt regulator circuit SR, the power input of the ripple rejection circuit RR, the power input of the demodulator Dmd, the input of the voltage hold circuit VH, and the input of the initialization circuit Int. The output of the reference voltage circuit Vref is connected to the input of the ripple rejection circuit RR, and the output of the ripple rejection circuit RR is connected to the reference input of the demodulator Dmd. The output of the demodulator Dmd is connected to the demodulation output o-Dmd The voltage hold circuit VH output is connected to the holding output o-VH The modulation input i-Mod is connected to the modulation input of the harvester with modulator HM. The output of the initialization circuit Int is connected to the initialization output o-Int.

[0066] The harvester with modulator HM circuit converts the high-frequency voltage signal from the antenna input RF1 or the antenna inputs RF1 and RF2 to a constant voltage that supplies a number of components of the ANL conditioner circuit that are connected to the power output of the harvester with modulator HM. The maximum value of this voltage is limited by the shunt regulator circuit SR (to about 6 V), which ensures the correct operation of the ANL conditioner components at a high level of the high-frequency signal amplitude at the antenna input RF1 or the antenna inputs RF1 and RF2 while reducing the risk of damage caused by a too high voltage level. In addition to the power-delivering function, the harvester with modulator HM loads or unloads the antenna inputs RF1 and RF2, depending on the voltage level on the modulation input i-Mod supplied externally to the ANL conditioner, thus affecting the total impedance at the antenna inputs RF1 and RF2, which performs the return communication of the NFC tag. The high-frequency alternating voltage from the antenna input RF1, after being provided to the carrier frequency divider FD16, is converted into a signal with a sixteen-time lower frequency with preserved phase synchronism, which can additionally be regulated from the digital side of the circuit.

[0067] Due to the use of the reference voltage circuit Vref, it is possible to obtain a reference voltage independent of the temporary amplitude of the high-frequency signal at the input or inputs of the ANL conditioner and, consequently, at the power output of the harvester with modulator HM. Moreover, the voltage from the antenna input RF1 is fed to the input of the demodulator Dmd, which, by comparing the temporary values of the amplitude from the antenna input RF1 with the voltage from the reference voltage circuit Vref, converts the temporary values of this amplitude into a binary sequence assigning respectively high and low amplitude values to low and high logical levels on the demodulation output o-Dmd. The ripple rejection circuit RR has an additional beneficial effect on the operation of the demodulator Dmd by reducing its vulnerability to errors caused by unusual voltage interferences at the output of the reference voltage circuit Vref. The high-frequency alternating voltage from the antenna input RF1, after conversion to a constant voltage in the harvester with modulator HM, is also used to accumulate electrical energy in the voltage hold circuit VH, whose goal is to maintain a constant voltage at the holding output o-VH during short-term decays of the high-frequency signal, and for that reason, the circuits connected there, sensitive to the supply voltage declining, can operate correctly.

[0068] The invention allows for a small area and frequency efficient circuit implementation of the RFID analog conditioner circuit, and the power from the antenna RF signal is obtained efficiently enough to power all conditioner subcircuits. The industrial application of the invention is in the industry and market of products requiring individual electronic markings.

[0069] The RFID tag digital core in the embodiment shown in fig. 5 contains a digital part of a carrier frequency divider FD16, a subcarrier frequency divider FD64, a demodulation interpreter DI, a response preparation and shaping circuit RPS and a protocol handler ProtH. Moreover, the RFID tag digital core DIG has: a demodulation input i-Dmd, a holding input i-VH, a modulation output o-Mod, and an initialization input i-Int.

[0070] The output of the carrier frequency divider FD16 is connected to the subcarrier frequency divider FD64, the demodulation interpreter DI, and the response preparation and shaping circuit RPS. The subcarrier frequency divider FD64 output is connected to the demodulation interpreter DI, the response preparation and shaping circuit RPS, and the protocol state machine PSM. The demodulation input i-Dmd is connected to the demodulation interpreter DI. The first output of the demodulation interpreter DI is connected to the response preparation and shaping circuit RPS, and the second output of the demodulation interpreter DI is connected to the protocol handler ProtH. The output response preparation and shaping circuit RPS is connected to the modulation output o- Mod. The protocol handler ProtH output is connected to the response preparation and shaping circuit RPS. The holding input i-VH is connected to the holding input of the demodulation interpreter DI. What is more, the initialization input i-Int is connected to the initialization inputs of the following circuits: the demodulation interpreter DI, the response preparation and shaping circuit RPS, and the protocol handler ProtH.

[0071] The RFID tag digital core in the embodiment shown in fig. 6 contains a digital part of a carrier frequency divider FD16, a subcarrier frequency divider FD64, a demodulation interpreter DI, a response preparation and shaping circuit RPS and a protocol handler ProtH, which contains a protocol state machine PSM, a checksum calculator CRC and a clock phase synchronization circuit ClkS. Moreover, the RFID tag digital core DIG has: a demodulation input i-Dmd, a holding input i-VH, a modulation output o-Mod, and an initialization input i-Int.

[0072] The output of the carrier frequency divider FD16 is connected to the subcarrier frequency divider FD64, to the demodulation interpreter DI, and to the response preparation and shaping circuit RPS. The subcarrier frequency divider FD64 output is connected to the demodulation interpreter DI, to the response preparation and shaping circuit RPS, and to the protocol state machine PSM. The demodulation input i-Dmd is connected to the demodulation interpreter DI. The output of the demodulation interpreter DI is connected to the response preparation and shaping circuit RPS and to the clock phase synchronization circuit ClkS. The first output of the response preparation and shaping circuit RPS is connected to the modulation output o-Mod. The second output of the response preparation and shaping circuit RPS is connected to the clock phase synchronization circuit ClkS. The first output of the protocol state machine PSM is connected to the response preparation and shaping circuit RPS. The second output of the protocol state machine PSM is connected to the checksum calculator CRC. The output of the checksum calculator CRC is connected to the protocol state machine PSM. The clock phase synchronization circuit ClkS output is connected to the carrier frequency divider FD16 and to the subcarrier frequency divider FD64. The holding input i-VH is connected to the holding input of the demodulation interpreter DI. What is more, the initialization input i-Int is connected to the initialization inputs of the following circuits: the demodulation interpreter DI, the response preparation and shaping circuit RPS, and the protocol state machine PSM.

[0073] The carrier frequency divider FD16 divides the carrier frequency of the received radio signal, providing a clock signal to the components: the demodulation interpreter DI and the response preparation and shaping circuit RPS, responsible for interacting with the demodulated signal from the demodulation input i-Dmd and the modulated signal delivered to the modulation output o-Mod. The subcarrier frequency divider FD64 performs further clock frequency division for the remaining circuits, and those parts of the demodulation interpreter DI and the response preparation and shaping circuit RPS can be implemented using a lower clock frequency.

[0074] The RFID demodulation interpreter DI processes raw data from the demodulation input i- Dmd in digital, asynchronous pulses correlated with the occurrences of subsequent modulations from the reader. The result of the RFID demodulation interpreter DI operation is information about the structure and content of the command frames received from the reader - high-level data containing information about the received command - delivered to the protocol handler ProtH. The demodulation interpreter DI is characterized by asynchronous operation, which results in its simplified architecture and achievement of the goal, which was a small and efficient implementation. Connecting the demodulation interpreter DI circuit to the holding input i-VH allows for correct operation of the critical components inside the demodulation interpreter DI, which are sensitive to power failures. In addition, the demodulation interpreter DI sends a synchronization signal to the response preparation and shaping circuit RPS, ensuring that the response will be sent back with the correct timing parameters.

[0075] The main task of the response preparation and shaping circuit RPS is the ability to determine the start and the end of transmission and the ability to select the appropriate response message of the circuit, while the main task of the protocol handler ProtH is to perform high-level handling of the tag protocol. The response preparation and shaping circuit RPS receives high-level information about the message from the protocol handler ProtH that is to be sent back by the tag and then processes it into a packet, which, after encoding, is used to control the modulator via the modulation output o-Mod. Using the internally stored state of the communication with the reader and information about the newly received command, it decides which message must be sent back in response to this command.

[0076] In particular, in constructing the protocol handler ProtH, the protocol state machine PSM can be distinguished, which performs all the essential functions of the protocol handler ProtH. The protocol handler ProtH can be expanded with two subcircuits - checksum calculator CRC and clock phase synchronization circuit ClkS - performing additional functionality. The checksum calculator CRC verifies the consistency of data received from the demodulation interpreter DI, and it communicates in both directions with the protocol state machine PSM, receiving the control signal and sending information about the consistency of the processed data. The clock phase synchronization circuit ClkS controls the operation of the frequency dividers FD16 and FD64 - it can adjust the phase of the generated clock signals. It can also turn off the frequency dividers FD16 and FD64, which results in energy saving.

[0077] In the case of ASIC (Application-Specific Integrated Circuit) implementation, it is advantageous to use the initialization input i-Int connected to the demodulation interpreter DI, the response preparation and shaping circuit RPS, and the protocol handler ProtH, which allows setting the initial state in these circuits. Consequently, an implementation without requiring a supply voltage to maintain the states of the circuit registers is possible.

[0078] The invention allows for an efficient implementation in terms of speed and space. The industrial application of the invention is in the industry and market for products requiring individual electronic markings.

Claims

Claims1. An RFID tag having an antenna input (RF1) connected to an antenna input of a carrier frequency divider (FD16), to an antenna input of a demodulator (Dmd) and to a first antenna input of a harvester with modulator (HM), whose power output is connected to a power input of the carrier frequency divider (FD16), to a power input of the demodulator (Dmd) and to a reference voltage circuit (Vref), whose output is connected to a reference input of the demodulator (Dmd), whose output is connected to a demodulated signal input of a demodulation interpreter (DI), and having the frequency divider (FD16) output connected to a subcarrier frequency divider (FD64), to the demodulation interpreter (DI) and to a response preparation and shaping circuit (RPS), while the output of the subcarrier frequency divider (FD64) is connected to the demodulation interpreter (DI) and to the response preparation and shaping circuit (RPS), whose output is connected to a modulation input of the harvester with modulator (HM), and having at least one output of the demodulation interpreter (DI) connected to the response preparation and shaping circuit (RPS), characterized in that it comprises a voltage hold circuit (VH) and an initialization circuit (Int), whose inputs are connected to the power output of the harvester with modulator (HM), an output of the voltage hold circuit (VH) is connected to a holding input of the demodulation interpreter (DI), and an output of the initialization circuit (Int) is connected to initialization inputs of the demodulation interpreter (DI) and the response preparation and shaping circuit (RPS), and in that it comprises a protocol handler (ProtH), whose inputs are connected to an initialization circuit (Int), the demodulation interpreter (DI) and the subcarrier frequency divider (FD64), while an output of protocol handler (ProtH) is connected to the response preparation and shaping circuit (RPS).

2. The RFID tag according to claim 1, characterized in that the reference voltage circuit (Vref) is connected to the demodulator (Dmd) via a ripple rejection circuit (RR), which has a power input connected to the power output of the harvester with modulator (HM).

3. The RFID tag according to claim 1 or 2, characterized in that comprises a shunt regulator circuit (SR) connected to the power output of the harvester with modulator (HM).

4. The RFID tag according to claim 1 or 2 or 3, characterized in that the protocol handler (ProtH) comprises a clock phase synchronization circuit (ClkS), whose output is connected to the carrier frequency divider (FD16) and to the subcarrier frequency divider (FD64), the first input is connected to at least one of the outputs of the demodulation interpreter (DI), while the second input is connected to the response end-of-frame signal output of the response preparation and shaping circuit (RPS), and in that the protocol handler (ProtH) comprises a protocol state machine (PSM) and a checksum calculator (CRC), where both circuits are connected to the output of the subcarrier frequency divider (FD64), both circuits are connected to at least one output of thedemodulation interpreter (DI), the output of the protocol state machine (PSM) is connected to the checksum calculator (CRC), while the output of the checksum calculator (CRC) is connected to the protocol state machine (PSM), the output of the protocol state machine (PSM), which is also the output of the protocol handler (ProtH), is connected to the response preparation and shaping circuit (RPS), and the initialization input of the protocol state machine (PSM) is connected to the output of the initialization circuit (Int).

5. The RFID tag according to any of the claims from 1 to 4, characterized in that comprises a second antenna input (RF2) connected to a second antenna input of the harvester with modulator (HM).

6. The RFID tag according to any of the claims from 1 to 5, characterized in that the second antenna input (RF2) is connected to a ground (gnd) of the RFID tag.

7. The RFID tag according to any of the claims from 1 to 6, characterized in that a power supply bus (Vdd), supplying digital core circuits (DIG), is connected to the power output of the harvester with modulator (HM).

8. The RFID tag according to any of the claims from 1 to 7, characterized in that it operates substantially at a frequency of 13.56 MHz of the input signal.

9. The RFID tag according to any of the claims from 1 to 8, characterized in that the voltage hold circuit (VH) contains a diode and a capacitor connected in series between the input and the ground of this circuit, and the output is connected to the connection point of the diode and the capacitor.

10. The RFID tag according to claim 9, characterized in that the diode used in the voltage hold circuit (VH) is made of a transistor with its gate connected to its source and connected to the input of the circuit, and the drain of the transistor connected to the capacitor and the output of the circuit.

11. The RFID tag according to claim 9 or 10, characterized in that the capacitance of the capacitor used in the voltage hold circuit (VH) ranges from 5 pF to 20 pF.

12. The RFID tag according to any of the claims from 2 to 11, characterized in that the ripple rejection circuit (RR) has its input and output connected inside the circuit and connected to the power input of the circuit via a resistor, and to the ground of the circuit via a capacitor or capacitors connected in parallel.

13. The RFID tag according to claim 12, characterized in that the resistance of the resistor used in the ripple rejection circuit (RR) ranges from 2 MQ to 5 MO.

14. The RFID tag according to claim 12 or 13, characterized in that the cumulative capacitance of capacitors used in the ripple rejection circuit (RR) ranges from 3 pF to 50 pF.

15. An RFID analog conditioner circuit (ANL) having an antenna input (RF 1 ) connected to the antenna input of a carrier frequency divider (FD16), to an antenna input of a demodulator (Dmd) and to a first antenna input of a harvester with modulator (HM), whose power output is connected to a power input of the carrier frequency divider (FD16), to a power input of the demodulator (Dmd) and to a reference voltage circuit (Vref), whose output is connected to a reference input of the demodulator (Dmd), whose output is connected to a demodulation output (o-Dmd) of the RFID analog conditioner circuit (ANL), as well as having a modulation input (i-Mod) connected to a modulation input of the harvester with modulator (HM), characterized in that comprises a voltage hold circuit (VH) and an initialization circuit (Int), whose inputs are connected to the power output of the harvester with modulator (HM), an output of the voltage hold circuit (VH) isconnected to a holding output (o-VH) of the RFID analog conditioner circuit (ANL), and an output of the initialization circuit (Int) is connected to an initialization output (o-Int) of the RFID analog conditioner circuit (ANL).

16. The RFID analog conditioner circuit according to claim 15, characterized in that the reference voltage circuit (Vref) is connected to the demodulator (Dmd) via a ripple rejection circuit (RR), which has a power input connected to the power output of the harvester with modulator (HM).

17. The RFID analog conditioner circuit according to claim 15 or 16, characterized in that comprises a shunt regulator circuit (SR) connected to the power output of the harvester with modulator (HM).

18. The RFID analog conditioner circuit according to claim 15 or 16 or 17, characterized in that comprises a second antenna input (RF2) connected to a second antenna input of the harvester with modulator (HM).

19. The RFID analog conditioner circuit according to any of the claims from 15 to 18, characterized in that the second antenna input (RF2) is connected to a ground (gnd) of the RFID analog conditioner circuit (ANL).

20. The RFID analog conditioner circuit according to any of the claims from 15 to 19, characterized in that it operates substantially at a frequency of 13.56 MHz of the input signal.

21. The RFID analog conditioner circuit according to any of the claims from 15 to 20, characterized in that all transistors in the circuit are the FETs of "n" type.

22. The RFID analog conditioner circuit according to any of the claims from 15 to 21, characterized in that all transistors in the circuit are TFT-type transistors.

23. The RFID analog conditioner circuit according to any of the claims from 15 to 22, characterized in that the transistor channels are made of amorphous semiconductor material.

24. The RFID analog conditioner circuit according to any of the claims from 15 to 23, characterized in that the transistors contain indium-gallium zinc oxide.

25. The RFID analog conditioner circuit according to any of the claims from 15 to 24, characterized in that the voltage hold circuit (VH) contains a diode and a capacitor connected in series between the input and the ground of this circuit, and the output is connected to the connection point of the diode and the capacitor.

26. The RFID analog conditioner circuit according to claim 25, characterized in that the diode used in the voltage hold circuit (VH) is made of a transistor with its gate connected to its source and connected to the input of the circuit, and the drain of the transistor connected to the capacitor and the output of the circuit.

27. The RFID analog conditioner circuit according to claim 26, characterized in that the width-to-length ratio of transistor channel used to construct the diode in the voltage hold circuit (VH) ranges from 5 to 20.

28. The RFID analog conditioner circuit according to claim 25 or 26 or 27, characterized in that the capacitance of the capacitor used in the voltage hold circuit (VH) ranges from 5 pF to 20 pF.

29. The RFID analog conditioner circuit according to any of the claims from 16 to 28, characterized in that the ripple rejection circuit (RR) has its input and output connected insidethe circuit and connected to the power input of the circuit via a resistor, and to the ground of the circuit via a capacitor or capacitors connected in parallel.

30. The RFID analog conditioner circuit according to claim 29, characterized in that the resistance of the resistor used in the ripple rejection circuit (RR) ranges from 2 MQ to 5 MO.

31. The RFID analog conditioner circuit according to claim 29 or 30, characterized in that the cumulative capacitance of capacitors used in the ripple rejection circuit (RR) ranges from 3 pF to 50 pF.

32. An RFID tag digital core (DIG) comprising a carrier frequency divider (FD16), whose frequency divider (FD16)is connected to a demodulation interpreter (DI), to a response preparation and shaping circuit (RPS) and to a subcarrier frequency divider (FD64), whose output is connected to the demodulation interpreter (DI) and to the response preparation and shaping circuit (RPS), whose output is connected to a modulation output (o-Mod) of the RFID tag digital core (DIG), whose demodulation input (i-Dmd) is connected to the demodulated signal input of the demodulation interpreter (DI), of which at least one output is connected to the response preparation and shaping circuit (RPS), characterized in that it comprises a protocol handler (ProtH) and has a holding input (i-VH) and an initialization input (i-Int), where the holding input (i-VH) is connected to the holding input of the demodulation interpreter (DI), the initialization input (i-Int) is connected to the initialization inputs of the demodulation interpreter (DI), the response preparation and shaping circuit (RPS) and the protocol handler (ProtH), two further inputs of the protocol handler (ProtH) are connected to the subcarrier frequency divider (FD64) and the demodulation interpreter (DI), while the output of the protocol handler (ProtH) is connected to the response preparation and shaping circuit (RPS).

33. The RFID tag digital core according to claim 32, characterized in that the protocol handler (ProtH) comprises a clock phase synchronization circuit (ClkS), whose output is connected to the carrier frequency divider (FD16) and to the subcarrier frequency divider (FD64), the first input is connected to at least one of the outputs of the demodulation interpreter (DI), while the second input is connected to the response end-of-frame signal output of the response preparation and shaping circuit (RPS).

34. The RFID tag digital core according to claim 33, characterized in that the subcarrier frequency divider (FD64) comprises two sequentially connected "D" type flip-flops equipped with "R" and "S" inputs, where the input of the first flip-flop is connected to the input of the divider, the output of the second flip-flop is connected to the output of the divider, and the "R" and "S" inputs are connected to the outputs of the clock phase synchronization circuit (ClkS) accordingly to the expected initial state of the divider.

35. The RFID tag digital core according to claim 32 or 33 or 34, characterized in that the protocol handler (ProtH) comprises a protocol state machine (PSM) and a checksum calculator (CRC), where both circuits are connected to the output of the subcarrier frequency divider (FD64), both circuits are connected to at least one output of the demodulation interpreter (DI), the output of the protocol state machine (PSM) is connected to the checksum calculator (CRC), while the output of the checksum calculator (CRC) is connected to the protocol state machine (PSM), whose initialization input is connected to the initialization input (i-Int) of the RFID tag digital core (DIG), and further output of the protocol state machine (PSM) is connected to further input of the response preparation and shaping circuit (RPS).

36. The RFID tag digital core according to claim 35, characterized in that the protocol state machine (PSM) comprises a counter.

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