RFID tag digital core, RFID demodulation interpreter and RFID response preparation and shaping circuit

Abstract

An RFID tag digital core (DIG) comprises a carrier frequency divider (FD16), whose output is connected to a demodulation interpreter (DI), a response preparation and shaping circuit (RPS), and a subcarrier frequency divider (FD64), whose output is connected to the demodulation interpreter (DI) and the response preparation and shaping circuit (RPS), whose output is connected to a modulation output (o-Mod) of the RFID tag digital core (DIG), whose demodulation input (i- Dmd) is connected to the demodulated signal input of the demodulation interpreter (DI), of which at least one output is connected to the response preparation and shaping circuit (RPS). The RFID tag digital core (DIG) comprises a protocol handler (ProtH) and has a holding input (i-VH) and an initialization input (i-Int). The holding input (i-VH) is connected to the holding input of the demodulation interpreter (DI), the initialization input (i-Int) is connected to the initialization inputs of the demodulation interpreter (DI), the response preparation and shaping circuit (RPS) and the protocol handler (ProtH). Two further inputs of the protocol handler (ProtH) are connected to the subcarrier frequency divider (FD64) and the demodulation interpreter (DI), while the output of the protocol handler (ProtH) is connected to the response preparation and shaping circuit (RPS).

Description

[0001] RFID tag digital core, RFID demodulation interpreter and RFID response preparation and shaping circuit

[0002] The invention concerns an RFID tag digital core, an RFID demodulation interpreter, and an RFID response preparation and shaping circuit, intended especially for flexible integrated circuits for near-field communication (NFC).

[0003] There is known from publication titled „A Thin Elastic NFC Forum Type 1 Compatible RFID Tag” in IEEE Journal of Solid-State Circuits (Early Access), DOI: 10.1109 / JSSC.2023.3300256, an NFC RFID tag, whose architecture has been divided into an analog part and a digital part. The analog part consists of the following circuits: harvester with modulator, frequency divider, AM demodulator, reference voltage circuit, and symbol detector. The digital part consists of the following circuits: symbol decoder, NFC core, and NFC response circuit. In this tag, the antenna is connected to the harvester with modulator, the frequency divider, and the AM demodulator. The supply voltage from the harvester with modulator is connected to each analog and digital tag circuit. The output of the frequency divider is connected to the symbol decoder, the NFC core, the NFC response circuit, and the symbol detector. The output of the reference voltage circuit is connected to the AM demodulator and the symbol detector. The output of the AM demodulator is connected to the symbol detector and the frequency divider. Two other outputs of the AM demodulator are connected to the symbol detector. The output of the symbol detector is connected to the symbol decoder. The outputs of the symbol decoder are connected to the NFC core. The outputs of the NFC core are connected to the NFC response circuit. At least one output of the NFC response circuit is connected to the frequency divider, while the modulation output of the NFC response circuit is connected to the harvester with modulator. The symbol detector consists of a pulse counter made of a cascade of four flip-flops, a synchronizer of two flip-flops, and a delay circuit of five inverters. The NFC response circuit contains a 73 -bit shift register made of flip-flops. The digital part of the tag uses two clock signals with frequencies resulting from dividing the antenna signal frequency by 16 and 64.

[0004] There is known from American invention description US2002167405 Al a radio frequency identification (RFID) architecture, in which RFID tags are interrogated by a reader, which may be located in a network of readers. The reader transmits symbols to the tags. Tags respond to the interrogations with symbols that each represent one or more bits of data. An RFID tag includes an antenna pad, a receiver, a state machine, and a modulator. The receiver is coupled to the antenna pad. The receiver receives a symbol from the antenna pad and outputs a received signal. The state machine is configured to determine a response symbol from the received signal and an operating state of the tag. The modulator is coupled to the antenna pad. The modulator is configured to backscatter modulate the received symbol with the response symbol. The modulator is configured to output the backscatter modulated symbol to the antenna pad.

[0005] In particular, an RFID tag digital core solution is known from this invention, comprising two frequency dividers connected to an oscillator, a counter connected to one frequency divider, and a state machine to which an interface part comprising a rectifier, a charge pump, and a modulator is connected.

[0006] There are known from international patent description W02008013418A1 apparatus and method for integrated reader and tag. Provided are a reader-tag integrated RFID apparatus and a method for controlling the same. The apparatus includes a tag unit for communicating with an external reader, and transmitting a response signal and data corresponding to a signal transmitted from the external reader to the external reader, a reader unit for selecting a channel between other reader and the reader- tag integrated RFID apparatus with a different delay time, and communicating with an external tag using a random value to minimize collision; and a controller for selectively activating one of the tag unit and the reader unit if it necessary.

[0007] In particular, a functionally similar solution to an RFID response preparation and shaping circuit is known from this invention, comprising a tag memory connected to a tag controller, to which a message generator is connected, which is connected to a checksum calculator, which is connected to a coding system, which is connected to a digital modulator. In addition, the message generator is connected to a tag controller and an anti -collision state machine, to which a message buffer is connected, and a digital decoder and a demodulator are connected via a system for calculating and confirming the checksum.

[0008] There is known from patent description of Japanese invention JP2006157593A an RFID communication system and wireless communication device comprising interpreter. A wireless communication device is connected to a host device for outputting instruction information of RFID recording media in an RFID communication system. A plurality of antenna mechanisms for transmitting / receiving transmitting signals to the RFID recording media and received signals from the RFID recording media are provided to the wireless communication device for each of communication specifications of the RFID recording media. The wireless communication device is provided with a control mechanism having a signal processing means which generates a transmitting signal and analyzes a received signal on the basis of the communication specifications shown by the instruction information, and antenna switching means for selecting an antenna mechanism to transmit a transmitting signal and an antenna mechanism to receive a received signal.

[0009] In particular, a solution is known from this invention in which the controller encodes an instruction command as instruction information from the host computer using the encoder by the command interpreter unit and passes it to the tag driver. When the instruction is data writing, a value to be written is temporarily stored in the memory. The tag driver converts an instruction from the host computer into a radio wave format and passes it to the antenna module. The antenna module transmits the radio wave to the RFID tag as a transmission signal. The tag driver analyzes an analog signal as a radio wave received from the RFID tag via the antenna module, converts the content into a digital signal, and passes the digital signal to the command interpreter unit. The command interpreter unit decodes the received digital signal by the decoder and supplies it to the host computer as data read from the tag. There is known from patent description of Japanese invention JP2006319730A a system and method for receiving RFID tag signal comprising a command interpreter. In this invention the RFID tag signal receiving system comprises a demodulator for demodulating a base band signal in accordance with a communication protocol, a remaining signal memory for storing input signals of a signal which cannot be demodulated and afterward, a data determinator for inferring next data from the communication protocol, a signal pattern storage for storing a waveform pattern of a fundamental waveform in the communication protocol, and a signal comparator for retrieving the fundamental waveform matching the waveform pattern of a signal of the remaining signal pattern from the signal pattern storage. Further, the RFID tag signal receiving system comprises a data judgment forjudging whether or not data inferred by the data determination part matches data of the fundamental waveform retrieved by the signal comparator; and a signal subtracter for reading an original signal having the same length as a signal length of the fundamental waveform from a front portion of the signal stored in a remaining signal memory, based on a judgement result of the data judgement to resend the original signal to the demodulator.

[0010] In particular, a solution is known from this invention in which the receiving antenna receives the RFID tag signal a transmitted from the RFID tag. In the receiving circuit, the RFID tag signal received by the receiving antenna is adjusted so that the signal strength becomes constant by the signal strength automatic adjuster of the baseband extraction unit, and further, the baseband signal is generated from the RFID tag signal 110a. Abaseband signal is extracted by the band filter. The demodulator demodulates this baseband signal. Then, the protocol decoding unit decodes the demodulated data in accordance with the radio protocol of the RFID tag to extract data stored in the RFID tag and send it to the command interpreter. The command interpreter converts the data stored in the RFID tag into a data format that can be understood by the host computer installed outside, and sends the data to the host computer.

[0011] There are known from the American patent application US2007069859A1 a mobile RFID reader and a control method thereof, in which the mobile RFID reader includes: a reader controller for beginning a reader operation to communicate with a tag in response to a command of a terminal controller of the wireless communication terminal; an anti -collision state machine for controlling collision among a plurality of tags, and transferring the result of communication with the tag to the reader controller; a reader transmitter for generating a reader command message decided at the anti-collision state machine, and coding and modulating the generated reader command message; a reader receiver for demodulating and decoding a tag signal received through an antenna, and reporting a tag response state to the anti-collision state machine; and a channel controller for selecting a channel to use to communicate with a tag in response to a command of the reader controller.

[0012] In particular, a functionally similar solution to an RFID response preparation and shaping circuit is known from this invention, comprising a message generator connected to a checksum calculator, connected to a coding system, connected to a digital modulator. Furthermore, the message generator is connected to a tag controller and an anti-collision state machine, to which a message buffer is connected, to which a digital decoder and a demodulator are connected via a system for calculating and confirming the checksum.

[0013] In state-of-the-art electronics engineering, there are known (remote) radio-frequency identification (RFID) systems, and in particular near-field communication (NFC). There are known in the art field-effect transistors (FETs) with an insulated gate, thin-film transistors (TFTs), as well as transistors based on indium-gallium zinc oxide (IGZO or InGaZnO - from indium (In), gallium (Ga), zinc (Zn), oxygen (O)).

[0014] The invention aims to create a small, in terms of area occupied, and energy-efficient circuit for an NFC RFID in a-IGZO technology characterized by large TFT transistors. There is, therefore, a need to solve the problem of overly complex digital implementation, meeting critical time parameters and minimizing the power consumed by the circuit, which are necessary for the correct operation of the entire NFC RFID tag circuit.

[0015] The essence of the solution is that, an RFID tag digital core comprising a carrier frequency divider, whose output is connected to a demodulation interpreter, to a response preparation and shaping circuit and to a subcarrier frequency divider, whose output is connected to the demodulation interpreter and to the response preparation and shaping circuit, whose output is connected to a modulation output of the RFID tag digital core, whose demodulation input is connected to the demodulated signal input of the demodulation interpreter, of which at least one output is connected to the response preparation and shaping circuit, according to the invention, it comprises a protocol handler and has a holding input and an initialization input, where the holding input is connected to the holding input of the demodulation interpreter, the initialization input is connected to the initialization inputs of the demodulation interpreter, the response preparation and shaping circuit and the protocol handler. Moreover, two further inputs of the protocol handler are connected to the subcarrier frequency divider and the demodulation interpreter, while the output of the protocol handler is connected to the response preparation and shaping circuit. The technical advantage of such a circuit design is the management of the transmission protocol by the protocol handler, starting with the content of the transmitted data, down to the time parameters of the frames. Due to the use of holding input, the circuit can work uninterruptedly during short-term decays of the high-frequency signal. Due to the connection of subcircuits to the initialization input, their implementation does not require the use of a supply voltage maintaining the states of the registers.

[0016] Advantageously, the protocol handler comprises a clock phase synchronization circuit, whose output is connected to the carrier frequency divider and to the subcarrier frequency divider, the first input is connected to at least one of the outputs of the demodulation interpreter, while the second input is connected to the response end-of-frame signal output of the response preparation and shaping circuit. Therefore, the clock can be adjusted precisely to the signal phase, and thus the response time parameters.

[0017] Advantageously, the subcarrier frequency divider comprises two sequentially connected "D" type flip-flops equipped with "R" and "S" inputs, where the input of the first flip-flop is connected to the input of the divider, the output of the second flip-flop is connected to the output of the divider, and the "R" and "S" inputs are connected to the outputs of the clock phase synchronization circuit accordingly to the expected initial state of the divider. This makes it possible to choose a proper phase adjustment of the divider output signal.

[0018] Advantageously, the protocol handler comprises a protocol state machine and a checksum calculator, where both circuits are connected to the output of the subcarrier frequency divider, both circuits are connected to at least one output of the demodulation interpreter, the output of the protocol state machine is connected to the checksum calculator, while the output of the checksum calculator is connected to the protocol state machine, whose initialization input is connected to the initialization input of the RFID tag digital core, and further output of the protocol state machine is connected to further input of the response preparation and shaping circuit. This makes it possible to manage the content of transmitted data, including calculating checksums confirming the consistency of received commands. By comprising a counter, it allows some states encoded by the protocol state machine to require fewer registers for implementation.

[0019] Furthermore, the essence of the invention is that an RFID demodulation interpreter comprises an event detector, a modulation interval measurement circuit, a modulation interval discriminator, and a frame decoding circuit, where the modulation interval measurement circuit is connected to the subcarrier clock input of the RFID demodulation interpreter, the output of the modulation interval measurement circuit is connected to the modulation interval discriminator, the output of the modulation interval discriminator is connected to the event detector, whose first output is connected to the query start-of-frame signal output of the RFID demodulation interpreter, and its second output is connected to decoded query output of the RFID demodulation interpreter via the frame decoding circuit. Furthermore, the demodulated signal input of the RFID demodulation interpreter is connected to the modulation interval measurement circuit and to the modulation interval discriminator.

[0020] Such a construction is dedicated to processing raw data from the demodulator into information about the structure and content of command frames. An additional technical advantage of such a construction is asynchronous operation, which results in a simplified circuit architecture, which reduces area and power consumption.

[0021] Advantageously, the demodulated signal input is connected to the modulation interval measurement circuit and the modulation interval discriminator via at least one delay circuit. For this reason, the modulation interval measurement circuit and the modulation interval discriminator can be implemented simplified, reducing the required number of sequential elements.

[0022] Advantageously, the RFID demodulation interpreter comprises a synchronizer, by which the event detector is connected to the query start-of-frame signal output, and by which the frame decoding circuit is connected to the decoded query output, furthermore, the frame symbol clock input of the RFID demodulation interpreter is connected to the synchronizer. For this reason, the signal changes at the RFID demodulation interpreter outputs are aligned correctly in time and, therefore, compatible with the logic of the following circuit connected to them.

[0023] Advantageously, the frame decoding circuit comprises a symbol decoder and a frame decoder, sequentially connected from the input to the output of this circuit. This allows sequential decoding, which simplifies the frame decoding circuit.

[0024] Advantageously, a single delay circuit connected between the demodulated signal input and the modulation interval measurement circuit, or a combination of different delay circuits, forms a sequential connection of 4 inverters. For this reason, the delay circuit is characterized by simple implementation and, therefore, small system area occupancy.

[0025] Advantageously, a single delay circuit connected between the demodulated signal input and the modulation interval discriminator, or a combination of different delay circuits, forms a sequential connection of 5 inverters. For this reason, the delay circuit is characterized by simple implementation and, therefore, small system area occupancy.

[0026] Advantageously, the holding input is connected to a holding input of at least one delay circuit. For this reason, momentary signal amplitude sags at the antenna input, caused by modulation during communication or caused by power supply voltage surges, do not affect the operation of the circuit or the delay circuits.

[0027] Advantageously, the modulation interval measurement circuit is based on a counter and a register latching the value of this counter, triggered by a demodulated signal input. For this reason, the measurement of modulation intervals is performed digitally, which makes it minimally dependent on the production mismatches of the circuit.

[0028] Advantageously, the modulation interval discriminator is implemented as a comparator. For this reason, the modulation interval discriminator can be designed as a combinational circuit without using sequential elements such as flip-flops, saving the circuit's area.

[0029] Advantageously, the symbol decoder is implemented as a state machine. This enables the lossless conversion of measured intervals into protocol symbols.

[0030] Advantageously, the initialization input is connected to the initialization input of the event detector, to the initialization input of the symbol decoder, to the initialization input of the frame decoder and to the initialization input of the synchronizer. This makes it possible to set the initial state in these systems, and therefore, the implementation does not require a supply voltage to maintain the register states.

[0031] Advantageously, the symbol decoder is implemented as a combinational circuit. This allows the conversion of measured intervals into protocol symbols to be performed in a heuristic manner, greatly simplifying the implementation of the symbol decoder at the expense of the distinguishability of some command frames.

[0032] Advantageously, the frame decoder is implemented as a state machine. This makes it possible to identify command frames before their complete transmission.

[0033] Advantageously, the synchronizer comprises at least one cascade of flip-flops clocked with a common signal. This ensures that the signal changes at the synchronizer outputs are time-aligned to the clock edges, using a straightforward implementation.

[0034] Furthermore, the essence of the solution is that in an RFID response preparation and shaping circuit comprising a state machine connected to a response buffer and comprising an encoding circuit connected to the modulation output of the RFID response preparation and shaping circuit, according to the invention, the state machine is a response state machine, whose first output is connected to the response buffer, and whose first input is connected to the query start-of-frame signal input of the RFID response preparation and shaping circuit. Moreover, the encoding circuit is a response modulation bit encoder with three inputs: one is connected to the response buffer, second to the response state machine, and third to the subcarrier clock input of the RFID response preparation and shaping circuit. Furthermore, the RFID response preparation and shaping circuit comprises a frame symbol clock input connected to the response state machine and to the response end-of-frame detector, where the response end-of-frame detector has further input and output connected to the response state machine. Moreover, it comprises a response buffer initialization circuit, whose input is connected to the response selection input of the RFID response preparation and shaping circuit, and whose output is connected to the response buffer. The technical advantage of this circuit design is the ability to precisely determine the start and the end of a transmission and select a proper system response message.

[0035] Advantageously, the query start-of-frame signal input is connected to the response state machine via a response trigger delay circuit, which is also connected to the frame symbol clock input. This makes it possible to pre-adjust the response time parameters in accordance with the standard.

[0036] Advantageously, the output of the response state machine and the frame symbol clock input are connected to the input response end-of-frame detector via a response bits counter. This makes it possible to monitor the progress of sending messages. Advantageously, the response end-of-frame signal output is connected to an additional output of the response end-of-frame detector. This makes it possible to turn off temporarily unused circuits to save power.

[0037] Advantageously, the response trigger delay circuit comprises a counter coupled with a comparator. Using a counter clocked with a frame symbol clock input saves the power of this circuit.

[0038] Advantageously, the response end-of-frame detector is constituted by a comparator. This makes implementation low-cost.

[0039] Advantageously, the response modulation bit encoder is a combinational circuit. This allows the entire circuit to be clocked at a lower clock frequency.

[0040] Advantageously, the initialization input is connected to the initialization input of the response buffer initialization circuit and to the initialization input of the response state machine. This makes it possible to set the initial state in these circuits; therefore, the implementation does not require a supply voltage to maintain the register states.

[0041] Advantageously, the response buffer initialization circuit is a combinational circuit. This makes implementation low-cost.

[0042] Advantageously, the response buffer is constituted by a memory. This makes it possible to program the content of messages sent.

[0043] Advantageously, the response buffer comprises at least one shift register. This allows cheap and straightforward implementation.

[0044] Advantageously, at least one shift register is implemented as a cascade of "D" type flipflops equipped with "R" and "S" inputs, where these inputs are alternatively connected to a signal input from the response buffer initialization circuit accordingly to the expected binary word of the response buffer. This makes it possible to implement many different responses.

[0045] The invention has been described below in detail, with reference to the attached figures. Fig. 1 presents a schematic diagram of an RFID tag digital core with a general form of protocol handler, fig. 2 presents a schematic diagram of an RFID tag digital core comprising a detailed construction of protocol handler, fig. 3 presents a schematic diagram of an asynchronous RFID demodulation interpreter, fig. 4 presents a schematic diagram of a synchronized RFID demodulation interpreter, fig. 5 presents a schematic diagram of an RFID response preparation and shaping circuit with a single output, and fig. 6 - a schematic diagram of an RFID response preparation and shaping circuit with two outputs.

[0046] The RFID tag digital core in the embodiment shown in fig. 1 contains a digital part of a carrier frequency divider FD16, a subcarrier frequency divider FD64, a demodulation interpreter DI, a response preparation and shaping circuit RPS and a protocol handler ProtH. Moreover, the RFID tag digital core DIG has: a demodulation input i-Dmd, a holding input i-VH, a modulation output o-Mod, and an initialization input i-Int.

[0047] The output of the carrier frequency divider FD16 is connected to the subcarrier frequency divider FD64, the demodulation interpreter DI, and the response preparation and shaping circuit RPS. The subcarrier frequency divider FD64 output is connected to the demodulation interpreter DI, the response preparation and shaping circuit RPS, and the protocol state machine PSM. The demodulation input i-Dmd is connected to the demodulation interpreter DI. The first output of the demodulation interpreter DI is connected to the response preparation and shaping circuit RPS, and the second output of the demodulation interpreter DI is connected to the protocol handler ProtH. The output response preparation and shaping circuit RPS is connected to the modulation output o- Mod. The protocol handler ProtH output is connected to the response preparation and shaping circuit RPS. The holding input i-VH is connected to the holding input of the demodulation interpreter DI. What is more, the initialization input i-Int is connected to the initialization inputs of the following circuits: the demodulation interpreter DI, the response preparation and shaping circuit RPS, and the protocol handler ProtH.

[0048] The RFID tag digital core in the embodiment shown in fig. 2 contains a digital part of a carrier frequency divider FD16, a subcarrier frequency divider FD64, a demodulation interpreter DI, a response preparation and shaping circuit RPS and a protocol handler ProtH, which contains a protocol state machine PSM, a checksum calculator CRC and a clock phase synchronization circuit ClkS. Moreover, the RFID tag digital core DIG has: a demodulation input i-Dmd, a holding input i-VH, a modulation output o-Mod, and an initialization input i-Int.

[0049] The output of the carrier frequency divider FD16 is connected to the subcarrier frequency divider FD64, to the demodulation interpreter DI, and to the response preparation and shaping circuit RPS. The subcarrier frequency divider FD64 output is connected to the demodulation interpreter DI, to the response preparation and shaping circuit RPS, and to the protocol state machine PSM. The demodulation input i-Dmd is connected to the demodulation interpreter DI. The output of the demodulation interpreter DI is connected to the response preparation and shaping circuit RPS and to the clock phase synchronization circuit ClkS. The first output of the response preparation and shaping circuit RPS is connected to the modulation output o-Mod. The second output of the response preparation and shaping circuit RPS is connected to the clock phase synchronization circuit ClkS. The first output of the protocol state machine PSM is connected to the response preparation and shaping circuit RPS. The second output of the protocol state machine PSM is connected to the checksum calculator CRC. The output of the checksum calculator CRC is connected to the protocol state machine PSM. The clock phase synchronization circuit ClkS output is connected to the carrier frequency divider FD16 and to the subcarrier frequency divider FD64. The holding input i-VH is connected to the holding input of the demodulation interpreter DI. What is more, the initialization input i-Int is connected to the initialization inputs of the following circuits: the demodulation interpreter DI, the response preparation and shaping circuit RPS, and the protocol state machine PSM.

[0050] The carrier frequency divider FD16 divides the carrier frequency of the received radio signal, providing a clock signal to the components: the demodulation interpreter DI and the response preparation and shaping circuit RPS, responsible for interacting with the demodulated signal from the demodulation input i-Dmd and the modulated signal delivered to the modulation output o-Mod. The subcarrier frequency divider FD64 performs further clock frequency division for the remaining circuits, and those parts of the demodulation interpreter DI and the response preparation and shaping circuit RPS can be implemented using a lower clock frequency.

[0051] The RFID demodulation interpreter DI processes raw data from the demodulation input i- Dmd in digital, asynchronous pulses correlated with the occurrences of subsequent modulations from the reader. The result of the RFID demodulation interpreter DI operation is information about the structure and content of the command frames received from the reader - high-level data containing information about the received command - delivered to the protocol handler ProtH. The demodulation interpreter DI is characterized by asynchronous operation, which results in its simplified architecture and achievement of the goal, which was a small and efficient implementation. Connecting the demodulation interpreter DI circuit to the holding input i-VH allows for correct operation of the critical components inside the demodulation interpreter DI, which are sensitive to power failures. In addition, the demodulation interpreter DI sends a synchronization signal to the response preparation and shaping circuit RPS, ensuring that the response will be sent back with the correct timing parameters.

[0052] The main task of the response preparation and shaping circuit RPS is the ability to determine the start and the end of transmission and the ability to select the appropriate response message of the circuit, while the main task of the protocol handler ProtH is to perform high-level handling of the tag protocol. The response preparation and shaping circuit RPS receives high-level information about the message from the protocol handler ProtH that is to be sent back by the tag and then processes it into a packet, which, after encoding, is used to control the modulator via the modulation output o-Mod. Using the internally stored state of the communication with the reader and information about the newly received command, it decides which message must be sent back in response to this command.

[0053] In particular, in constructing the protocol handler ProtH, the protocol state machine PSM can be distinguished, which performs all the essential functions of the protocol handler ProtH. The protocol handler ProtH can be expanded with two subcircuits - checksum calculator CRC and clock phase synchronization circuit ClkS - performing additional functionality. The checksum calculator CRC verifies the consistency of data received from the demodulation interpreter DI, and it communicates in both directions with the protocol state machine PSM, receiving the control signal and sending information about the consistency of the processed data. The clock phase synchronization circuit ClkS controls the operation of the frequency dividers FD16 and FD64 - it can adjust the phase of the generated clock signals. It can also turn off the frequency dividers FD16 and FD64, which results in energy saving.

[0054] In the case of ASIC (Application-Specific Integrated Circuit) implementation, it is advantageous to use the initialization input i-Int connected to the demodulation interpreter DI, the response preparation and shaping circuit RPS, and the protocol handler ProtH, which allows setting the initial state in these circuits. Consequently, an implementation without requiring a supply voltage to maintain the states of the circuit registers is possible.

[0055] The RFID demodulation interpreter in the embodiment shown in fig. 3 contains a modulation interval measurement circuit IntM, a modulation interval discriminator IntD, an event detector EvD, and a frame decoding circuit FDC. The RFID demodulation interpreter DI additionally has: a demodulated signal input i-STR, a subcarrier clock input i-F16a, a query start- of-frame signal output o-CS, and a decoded query output o-Cmd.

[0056] The demodulated signal input i-STR is connected to the modulation interval measurement circuit IntM and to the modulation interval discriminator IntD. The subcarrier clock input i-F16a is connected to the modulation interval measurement circuit IntM. The modulation interval measurement circuit IntM output is connected to the modulation interval discriminator IntD. The modulation interval discriminator IntD output is connected to the event detector EvD. The first output of the event detector EvD is connected to the query start-of-frame signal output o-CS. The second output of the event detector EvD is connected to the frame decoding circuit FDC, and the output of the frame decoding circuit FDC is connected to the decoded query output o-Cmd.

[0057] The RFID demodulation interpreter in the embodiment shown in fig. 4 contains a first delay circuit Dell, a second delay circuit Dell, a modulation interval measurement circuit IntM, a modulation interval discriminator IntD, an event detector EvD, a synchronizer Sync and a frame decoding circuit FDC, which contains a symbol decoder SD and a frame decoder FD. The RFID demodulation interpreter DI additionally has: a demodulated signal input i-STR, a holding input i-VHa, a subcarrier clock input i-F16a, an initialization input i-Inta, a frame symbol clock input i-F64a, a query start-of-frame signal output o-CS, and a decoded query output o-Cmd.

[0058] The demodulated signal input i-STR is connected to the first delay circuit Dell and to the second delay circuit Dell. The holding input i-VHa is connected to the holding input of the first delay circuit Dell and to the holding input of the second delay circuit Dell. The subcarrier clock input i-F16a is connected to the modulation interval measurement circuit IntM. The initialization input i-Inta is connected to the event detector EvD, to the symbol decoder SD, to the frame decoder FD, and to the synchronizer Sync. The frame symbol clock input i-F64a is connected to the synchronizer Sync. The output of the first delay circuit Dell is connected to the modulation interval measurement circuit IntM. The output of the second delay circuit Dell is connected to the modulation interval discriminator IntD. The modulation interval measurement circuit IntM output is connected to the modulation interval discriminator IntD. The modulation interval discriminator IntD output is connected to the event detector EvD. The first output of the event detector EvD is connected to the synchronizer Sync. The second output of the event detector EvD is connected to the symbol decoder SD. The output of the symbol decoder SD is connected to the frame decoder FD. The output of the frame decoder FD is connected to the synchronizer Sync. The first output of the synchronizer Sync is connected to the query start-of-frame signal output o-CS, and the second output of the synchronizer Sync is connected to the decoded query output o-Cmd.

[0059] The RFID demodulation interpreter DI is designed to process raw data from the demodulator in digital, asynchronous pulses correlated with the occurrence of modulation from the reader. The result of the RFID demodulation interpreter DI is information on the structure and content of the command frames received from the reader. The circuit is characterized by asynchronous operation, which results in its simplified architecture and achievement of the goal, which was a small and efficient implementation.

[0060] The modulation interval measurement circuit IntM measures the time between consecutive modulations from the reader, using the subcarrier clock from the subcarrier clock input i-F16a as the time base. The implementation of modulation interval measurement circuit IntM comprises a counter and a register latching the value of this counter when detecting modulation from the reader. Information about the detection of modulation comes from the demodulated signal input i-STR. Additional use of the first delay circuit Dell and the second delay circuit Dell, asynchronously delaying the edge of the signal coming from the demodulated signal input i-STR, has a beneficial effect on the design complexity of the modulation interval measurement circuit IntM and the modulation interval discriminator IntD.

[0061] As an integer, the time measured by the modulation interval measurement circuit IntM is then interpreted by the modulation interval discriminator IntD, which qualifies it to one of the four-time ranges that enable unambiguous determination of the received symbols defined by the NFC standard.

[0062] The event detector EvD, based on the information about the received time range, detects the events of: (a) exceeding the maximum allowed time between modulations (i.e., end of frame), (b) the first modulation after the end of the last received frame, and (c) modulation within the frame. In the second of these cases (b), the event detector EvD indicates the occurrence of this event on the query start-of-frame signal output o-CS. In contrast, the information about the detected event is passed on to the FDC frame decoding circuit in the remaining cases. For that reason, the implementation of the event detector EvD can be reduced to only three "D" flip-flops and two logic gates. The frame decoding circuit FDC processes the received information in two stages - first, converting modulation symbols to data bits using symbol decoder SD, and next, using frame decoder FD, converting the received bit sequence (whose structure is defined by the NFC standard) to an internal representation of the frame, optimal for external circuits connected to the decoded query output o-Cmd. In the case of implementing the symbol decoder SD as a state machine, a lossless conversion of measured intervals to protocol symbols is possible. On the other hand, by implementing the symbol decoder SD as a combinational circuit, the conversion of measured intervals to protocol symbols is performed heuristically, significantly simplifying the implementation of symbol decoder SD. However, this happens at the cost of distinguishing some command frames, limiting the supported set of commands. However, interpretation of all commands is not always necessary because some commands may not be used due to the commercial application of the target product. Implementing frame decoder FD as a state machine allows the identification of command frames at an early stage of frame reception.

[0063] The optional synchronizer Sync receives asynchronous data on the input and, without modifying the information itself, synchronizes it to the edges of the clock received on the frame symbol clock input i-F64a. This ensures compatibility with the synchronous logic of the following circuit, connected to the outputs of the RFID demodulation interpreter DI, which are the outputs of the synchronizer Sync.

[0064] Providing an additional initialization input i-Inta allows setting the initial state in the event detector EvD, the symbol decoder SD, the frame decoder FD, and the synchronizer Sync. The symbol decoder SD is initialized if implemented as a state machine because the initialization is not required in the combinational circuit. The additional holding input i-VHa connected to the holding inputs of both delay circuits Dell and Dell causes momentary drops in the signal amplitude at the antenna input, caused by modulation during communication, or drops caused by supply voltage surges, do not affect the operation of these circuits, which are sensitive to supply voltage disturbances.

[0065] The RFID response preparation and shaping circuit in the embodiment shown in fig. 5 contains: a response state machine RSM, an response end-of-frame detector RED, a response buffer initialization circuit RBI, a response buffer RB, and a response modulation bit encoder REnc. The RFID response preparation and shaping circuit RPS additionally has: a frame symbol clock input i-F64b, an query start-of-frame signal input i-CS, a response selection input i-Sel, a subcarrier clock input i-F16b, and a modulation output o-Mod.

[0066] The frame symbol clock input i-F64b is connected to the response state machine RSM and to the response end-of-frame detector RED. The query start-of-frame signal input i-CS is connected to the response state machine RSM. The response selection input i-Sel is connected to the response buffer initialization circuit RBI, and the subcarrier clock input i-F16b is connected to the response modulation bit encoder REnc. The first output of the response state machine RSM is connected to the response end-of-frame detector RED. The second output of the response state machine RSM is connected to the response modulation bit encoder REnc. The third output of the response state machine RSM is connected to the response buffer RB. The response end-of-frame detector RED output is connected to the response state machine RSM. The response buffer initialization circuit RBI output is connected to the response buffer RB. The output of the response buffer RB is connected to the response modulation bit encoder REnc. What is more, the response modulation bit encoder REnc output is connected to the modulation output o-Mod. The RFID response preparation and shaping circuit in the embodiment shown in fig. 6 contains: a response trigger delay circuit RDel, a response state machine RSM, a response bits counter RBC, an response end-of-frame detector RED, a response buffer initialization circuit RBI, a response buffer RB and a response modulation bit encoder REnc. The RFID response preparation and shaping circuit RPS additionally has: a frame symbol clock input i-F64b, an query start-of-frame signal input i-CS, a response selection input i-Sel, a subcarrier clock input i-F16b, an initialization input i-Intb, a modulation output o-Mod, and an response end-of-frame signal output o-RE.

[0067] The frame symbol clock input i-F64b is connected to the response trigger delay circuit RDel, to the response state machine RSM, and to the response bits counter RBC. The query start- of-frame signal input i-CS is connected to the response trigger delay circuit RDel. The initialization input i-Intb is connected to the response buffer initialization circuit RBI and to the response state machine RSM. The response selection input i-Sel is connected to the response buffer initialization circuit RBI, while the subcarrier clock input i-F16b is connected to the response modulation bit encoder REnc. The output of the response trigger delay circuit RDel is connected to the response state machine RSM. The first output of the response state machine RSM is connected to the response bits counter RBC. The second output of the response state machine RSM is connected to the response modulation bit encoder REnc. The third output of the response state machine RSM is connected to the response buffer RB. The output of the response bits counter RBC is connected to the response end-of-frame detector RED. The first output of the response end-of-frame detector RED is connected to the response state machine RSM, and the second output of the response end-of-frame detector RED is connected to the response end-of-frame signal output o-RE. The response buffer initialization circuit RBI output is connected to the response buffer RB. The output of the response buffer RB is connected to the response modulation bit encoder REnc. What is more, the response modulation bit encoder REnc output is connected to the modulation output o-Mod.

[0068] The main task of the response state machine RSM is to manage the entire RFID response preparation and shaping circuit RPS, in particular, to provide control signals to the response buffer RB to select the currently transmitted bit and to the response modulation bit encoder REnc, to choose the current modulation state. The response state machine RSM works with the response end detection circuit RED, from which it receives information about the end of the sent message. Both of these circuits work using the clock from the subcarrier clock input i-F16b. The main task of the response buffer initialization circuit RBI is to select the message stored in the response buffer RB based on the input signal from the response selection input i-Sel. The design of the response buffer RB can be either simplified in the form of a shift register or more universal in the form of programmable memory. The response modulation bit encoder REnc uses the subcarrier clock input i-F16b to control the modulation signal according to the fundamental frequency of the circuit. The signal delivered to the modulation output o-Mod is usually a binary signal, which typically controls the antenna load in the RFID tag circuit, and thus the return communication from the tag.

[0069] The use of response trigger delay circuit RDel, which delays the query start-of-frame signal from i-CS input, allows for initial adjustment of response timing parameters in accordance with the NFC Type 1 standard. Therefore, it is unnecessary to include these parameters in the main state machine maintaining the protocol. The response bits counter RBC allows for monitoring the progress of message sending in cooperation with the response end-of-frame detector RED, which processes this information into a return signal to the response state machine RSM, informing about the end of the sent content. Moreover, delivering a signal from the response end-of-frame signal output o-RE to external circuits allows for switching off temporarily unused circuits connected to this output to save power. In the case of ASIC (Application-Specific Integrated Circuit) implementation, it is advantageous to use the initialization input i-Intb, connected to the response buffer initialization circuit RBI and the response state machine RSM, which allows for setting the initial state in these circuits. Consequently, an implementation that does not require a supply voltage to maintain the register states of the response buffer initialization circuit RBI and the response state machine RSM is possible.

[0070] The invention allows for an efficient implementation in terms of speed and space. The industrial application of the invention is in the industry and market for products requiring individual electronic markings.

Claims

Claims1. An RFID tag digital core (DIG) comprising a carrier frequency divider (FD16), whose frequency divider (FD16) is connected to a demodulation interpreter (DI), to a response preparation and shaping circuit (RPS) and to a subcarrier frequency divider (FD64), whose output is connected to the demodulation interpreter (DI) and to the response preparation and shaping circuit (RPS), whose output is connected to a modulation output (o-Mod) of the RFID tag digital core (DIG), whose demodulation input (i-Dmd) is connected to the demodulated signal input of the demodulation interpreter (DI), of which at least one output is connected to the response preparation and shaping circuit (RPS), characterized in that it comprises a protocol handler (ProtH) and has a holding input (i-VH) and an initialization input (i-Int), where the holding input (i-VH) is connected to the holding input of the demodulation interpreter (DI), the initialization input (i-Int) is connected to the initialization inputs of the demodulation interpreter (DI), the response preparation and shaping circuit (RPS) and the protocol handler (ProtH), two further inputs of the protocol handler (ProtH) are connected to the subcarrier frequency divider (FD64) and the demodulation interpreter (DI), while the output of the protocol handler (ProtH) is connected to the response preparation and shaping circuit (RPS).

2. The RFID tag digital core according to claim 1, characterized in that the protocol handler (ProtH) comprises a clock phase synchronization circuit (ClkS), whose output is connected to the carrier frequency divider (FD16) and to the subcarrier frequency divider (FD64), the first input is connected to at least one of the outputs of the demodulation interpreter (DI), while the second input is connected to the response end-of-frame signal output of the response preparation and shaping circuit (RPS).

3. The RFID tag digital core according to claim 2, characterized in that the subcarrier frequency divider (FD64) comprises two sequentially connected "D" type flip-flops equipped with "R" and "S" inputs, where the input of the first flip-flop is connected to the input of the divider, the output of the second flip-flop is connected to the output of the divider, and the "R" and "S" inputs are connected to the outputs of the clock phase synchronization circuit (ClkS) accordingly to the expected initial state of the divider.

4. The RFID tag digital core according to claim 1 or 2 or 3, characterized in that the protocol handler (ProtH) comprises a protocol state machine (PSM) and a checksum calculator (CRC), where both circuits are connected to the output of the subcarrier frequency divider (FD64), both circuits are connected to at least one output of the demodulation interpreter (DI), the output of the protocol state machine (PSM) is connected to the checksum calculator (CRC), while the output of the checksum calculator (CRC) is connected to the protocol state machine (PSM), whose initialization input is connected to the initialization input (i-Int) of the RFID tag digital core (DIG), and further output of the protocol state machine (PSM) is connected to further input of the response preparation and shaping circuit (RPS).

5. The RFID tag digital core according to claim 4, characterized in that the protocol state machine (PSM) comprises a counter.

6. An RFID demodulation interpreter (DI) comprising a decoder, characterized in that the decoder is an event detector (EvD), and in that it comprises a modulation interval measurement circuit (IntM), a modulation interval discriminator (IntD) and a frame decoding circuit (FDC), where the modulation interval measurement circuit (IntM) is connected to the subcarrier clock input (i-F16a) of the RFID demodulation interpreter (DI), the output of the modulation interval measurement circuit (IntM) is connected to the modulation interval discriminator (IntD), the output of the modulation interval discriminator (IntD) is connected to the event detector (EvD), whose first output is connected to the query start-of-frame signal output (o-CS) of the RFID demodulation interpreter (DI), and second output is connected to decoded query output (o-Cmd) of the RFID demodulation interpreter (DI) via the frame decoding circuit (FDC), and in that the demodulated signal input (i-STR) of the RFID demodulation interpreter (DI) is connected to the modulation interval measurement circuit (IntM) and to the modulation interval discriminator (IntD).

7. The RFID demodulation interpreter according to claim 6, characterized in that the demodulated signal input (i-STR) is connected to the modulation interval measurement circuit (IntM) and the modulation interval discriminator (IntD) via at least one delay circuit (Dell, Del2).

8. The RFID demodulation interpreter according to claim 6 or 7, characterized in that it comprises a synchronizer (Sync), by which the event detector (EvD) is connected to the query start-of-frame signal output (o-CS), and by which the frame decoding circuit (FDC) is connected to the decoded query output (o-Cmd), and in that the frame symbol clock input (i- F64a) of the RFID demodulation interpreter (DI) is connected to the synchronizer (Sync).

9. The RFID demodulation interpreter according to claim 6 or 7 or 8, characterized in that the frame decoding circuit (FDC) comprises a symbol decoder (SD) and a frame decoder (FD), sequentially connected from the input to the output of this circuit (FDC).

10. The RFID demodulation interpreter according to claim 7 or 8 or 9, characterized in that a single delay circuit (Dell) connected between the demodulated signal input (i-STR) and the modulation interval measurement circuit (IntM), or a combination of different delay circuits, forms a sequential connection of 4 inverters.

11. The RFID demodulation interpreter according to any of the claims from 7 to 10, characterized in that a single delay circuit (Del2) connected between the demodulated signalinput (i-STR) and the modulation interval discriminator (IntD), or a combination of different delay circuits, forms a sequential connection of 5 inverters.

12. The RFID demodulation interpreter according to any of the claims from 7 to 11, characterized in that the holding input (i-VHa) is connected to a holding input of at least one delay circuit (Dell, Del2).

13. The RFID demodulation interpreter according to any of the claims from 6 to 12, characterized in that the modulation interval measurement circuit (IntM) is based on a counter and a register latching the value of this counter, triggered by a demodulated signal input.

14. The RFID demodulation interpreter according to any of the claims from 6 to 13, characterized in that the modulation interval discriminator (IntD) is implemented as a comparator.

15. The RFID demodulation interpreter according to any of the claims from 9 to 14, characterized in that the symbol decoder (SD) is implemented as a state machine.

16. The RFID demodulation interpreter according to any of the claims from 9 to 15, characterized in that the initialization input (i-Inta) is connected to the initialization input of the event detector (EvD), to the initialization input of the symbol decoder (SD), to the initialization input of the frame decoder (FD) and to the initialization input of the synchronizer (Sync).

17. The RFID demodulation interpreter according to any of the claims from 9 to 14, characterized in that the symbol decoder (SD) is implemented as a combinational circuit.

18. The RFID demodulation interpreter according to any of the claims from 9 to 17, characterized in that the frame decoder (FD) is implemented as a state machine.

19. The RFID demodulation interpreter according to any of the claims from 8 to 18, characterized in that the synchronizer (Sync) comprises at least one cascade of flip-flops clocked with a common signal.

20. An RFID response preparation and shaping circuit (RPS) comprising a state machine connected to a response buffer (RB) and comprising an encoding circuit connected to the modulation output (o-Mod) of the RFID response preparation and shaping circuit (RPS), characterized in that the state machine is a response state machine (RSM), whose first output is connected to the response buffer (RB), and whose fist input is connected to the query start- of-frame signal input (i-CS) of the RFID response preparation and shaping circuit (RPS), and in that the encoding circuit is a response modulation bit encoder (REnc) with three inputs, of which one is connected to the response buffer (RB), second to the response state machine (RSM), and third to the subcarrier clock input (i-F 16b) of the RFID response preparation and shaping circuit (RPS), and in that the RFID response preparation and shaping circuit (RPS) comprises a frame symbol clock input (i-F64b) connected to the response state machine (RSM) and to the response end-of-frame detector (RED), where the response end-of-frame detector (RED) has further input and output connected to the response state machine (RSM), and in that it comprises a response buffer initialization circuit (RBI), whose input is connected to the response selection input (i-Sel) of the RFID response preparation and shaping circuit (RPS), and whose output is connected to the response buffer (RB).

21. The RFID response preparation and shaping circuit according to claim 20, characterized in that the query start-of-frame signal input (i-CS) is connected to the response state machine (RSM) via a response trigger delay circuit (RDel), which is also connected to the frame symbol clock input (i-F64b).

22. The RFID response preparation and shaping circuit according to claim 20 or 21, characterized in that the output of the response state machine (RSM) and the frame symbol clock input (i-F64b) are connected to the input response end-of-frame detector (RED) via a response bits counter (RBC).

23. The RFID response preparation and shaping circuit according to claim 20 or 21 or 22, characterized in that the response end-of-frame signal output (o-RE) is connected to an additional output of the response end-of-frame detector (RED).

24. The RFID response preparation and shaping circuit according to claim 21 or 22 or 23, characterized in that the response trigger delay circuit (RDel) comprises a counter coupled with a comparator.

25. The RFID response preparation and shaping circuit according to any of the claims from 20 to 24, characterized in that the response end-of-frame detector (RED) is constituted by a comparator.

26. The RFID response preparation and shaping circuit according to any of the claims from 20 to 25, characterized in that the response modulation bit encoder (REnc) is a combinational circuit.

27. The RFID response preparation and shaping circuit according to any of the claims from 20 to 26, characterized in that the initialization input (i-Intb) is connected to the initialization input of the response buffer initialization circuit (RBI) and to the initialization input of the response state machine (RSM).

28. The RFID response preparation and shaping circuit according to any of the claims from 20 to 27, characterized in that the response buffer initialization circuit (RBI) is a combinational circuit.

29. The RFID response preparation and shaping circuit according to any of the claims from 20 to 28, characterized in that the response buffer (RB) is constituted by a memory.

30. The RFID response preparation and shaping circuit according to any of the claims from 20 to 28, characterized in that the response buffer (RB) comprises at least one shift register.

31. The RFID response preparation and shaping circuit according to claim 30, characterized in that at least one shift register is implemented as a cascade of "D" type flip-flops equipped with "R" and "S" inputs, where these inputs are alternatively connected to a signal input from the response buffer initialization circuit (RBI) accordingly to the expected binary word of the response buffer (RB).

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