Semiconductor device production method and semiconductor device

Abstract

Provided is a semiconductor device production method that makes it possible to produce a compact semiconductor device, wherein performed are: a coating material preparation step 10 for preparing a coating material AS which is for coating a semiconductor body WF; an identification member preparation step 20 for preparing an identification member WK in which an identifier ID is formed; and a layering step 50 for layering the identification member WK on the semiconductor body WF with the coating material AS therebetween, to form a semiconductor device SD. In the coating material preparation step 10, prepared as the coating material AS is a material that is capable of bonding to both the semiconductor body WF and the identification member WK. In the layering step 50, the identification member WK is layered on the semiconductor body WF in a state in which the identification member WK is in direct contact with the coating material AS.

Description

Semiconductor device manufacturing method and semiconductor device

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

[0002] 2. Description of the Related Art A method for manufacturing a semiconductor device having an identifier and a semiconductor device having an identifier are known (see, for example, Japanese Patent Application Laid-Open No. 2003-122999).

[0003] JP 2022-67888 A

[0004] In a semiconductor package (semiconductor device) manufactured by the manufacturing method described in Patent Document 1, when a small piece (identification member) is laminated on an IC chip (semiconductor body), an adhesive is required between the sealing resin (coating material) that covers the semiconductor body and the identification member. However, since such semiconductor devices are required to be miniaturized in the order of μm (micrometers) or nm (nanometers), a semiconductor device manufactured by the manufacturing method described in Patent Document 1 has problems in terms of miniaturization.

[0005] An object of the present invention is to provide a method for manufacturing a semiconductor device that can manufacture a small-sized semiconductor device. Another object of the present invention is to provide a small-sized semiconductor device.

[0006] The present invention employs the configurations described in the claims.

[0007] According to the present invention, a coating material that can be adhered to both the semiconductor body and the identification member is used, and the identification member is laminated on the semiconductor body with the identification member in direct contact with the coating material, so there is no need for anything to adhere them between the identification member and the coating material, making it possible to manufacture a compact semiconductor device.Furthermore, according to the present invention, the identification member is laminated on the semiconductor body with the identification member in direct contact with the coating material, so there is no anything to adhere them between the identification member and the coating material, making it possible to produce a compact semiconductor device.

[0008] 1A to 1I are explanatory diagrams of a semiconductor device manufacturing apparatus according to an embodiment of the present invention, and 1J to 1M are explanatory diagrams of modified examples.

[0009] An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, the X-axis, Y-axis, and Z-axis are perpendicular to each other, with the X-axis and Y-axis being axes within a predetermined plane, and the Z-axis being an axis perpendicular to the predetermined plane. Furthermore, in this embodiment, the view from the front in FIG. 1A is used as the reference, and when directions are indicated without specifying the figure, "up" refers to the direction of the Z-axis arrow, "down" refers to the opposite direction, "left" refers to the direction of the X-axis arrow, "right" refers to the opposite direction, "front" refers to the direction of the Y-axis arrow, and "rear" refers to the opposite direction.

[0010] 1(A)-(F), the method for manufacturing a semiconductor device of the present invention includes a covering material preparation step 10 (see FIG. 1(A)), which prepares an adhesive sheet AS as a covering material for covering a semiconductor wafer (hereinafter simply referred to as "wafer") WF as a semiconductor body; an identification member preparation step 20 (see FIG. 1(B)), which prepares an identification member WK on which an identifier ID such as letters or symbols is formed; a thinning step 30 (see FIG. 1(C)), which thins the thickness of the identification member WK in a direction intersecting one surface WK1; a narrowing step 40 (see FIG. 1(D)), which narrows the width of the identification member WK along one surface WK1; a stacking step 50 (see FIG. 1(E)), which stacks the identification member WK on the wafer WF via the adhesive sheet AS to form a semiconductor device SD; and an energy application step 60 (see FIG. 1(F)), which applies a predetermined amount of heat HA to the adhesive sheet AS. In this embodiment, the wafer WF is made of a silicon semiconductor.

[0011] In the covering material preparation process 10, an adhesive sheet AS capable of adhering to both the wafer WF and the identification member WK is prepared. The adhesive sheet AS in this embodiment has the property of undergoing hardening as a change specific to heat HA when heat HA is applied.

[0012] 1(B), in the identification member preparation step 20, a laser irradiation device LD serving as an identifier forming device is used to mark the main body of the identification member WK, thereby preparing an identification member WK having an identifier ID formed on one surface WK1 (see FIG. 1(G)). Note that the main body of the identification member WK in this embodiment is made of the same material as the wafer WF.

[0013] 1(C), the other surface WK2 of the identification member WK is ground with a grinder WS as a grinding machine to reduce the thickness of the identification member WK. In the thinning process 30 of this embodiment, the thickness of the identification member WK is reduced to 30 μm.

[0014] In the narrowing step 40, as shown in Fig. 1(D), the width of the identification member WK is narrowed by cutting the identification member WK along the cutting line CL1 (see Figs. 1(C) and 1(G)) with a rotary cutter RC as a cutting member. Note that in the narrowing step 30 of this embodiment, the width of the identification member WK is narrowed to 100 µm in the left-right and front-back directions.

[0015] 1(E), in the laminating step 50, an adhesive sheet AS is interposed between one surface WF1 of the wafer WF and one surface WK1 of the identification member WK, and the identification member WK is laminated on the wafer WF in a state where the identification member WK is in direct contact with the adhesive sheet AS (see FIGS. 1(H) and 1(I)). Note that in the laminating step 40 of this embodiment, the identification member WK is laminated on the adhesive sheet AS so that the surface on which the identifier ID is formed faces the adhesive sheet AS.

[0016] In the energy application step 60, as shown in FIG. 1(F), heat HA is applied to the adhesive sheet AS by a hot air blower HF, thereby hardening the adhesive sheet AS.

[0017] The semiconductor device SD formed by the above process can be operated, for example, to detect counterfeiting or determine the authenticity of the semiconductor device SD, or to determine various processes to be performed on the semiconductor device SD, by allowing the identifier ID to be seen from the other side WK2 of the identification member WK or the other side WF2 of the wafer WF.

[0018] According to the above-described embodiment, an adhesive sheet AS capable of adhering to both the wafer WF and the identification member WK is used, and the identification member WK is laminated on the wafer WF while being in direct contact with the adhesive sheet AS. This eliminates the need for anything to adhere the identification member WK and the adhesive sheet AS to each other, making it possible to manufacture a small-sized semiconductor device SD.

[0019] The means and steps of the present invention are not limited in any way as long as they can perform the operations, functions, or steps described for those means and steps, and are in no way limited to the components and steps of a single embodiment shown in the above embodiment. For example, the identification member preparation step may be any step that prepares an identification member on which an identifier is formed, and is not limited in any way as long as it is within the scope of the common general technical knowledge at the time of filing (the same applies to other means and steps).

[0020] 1(H) to 1(L), the semiconductor device SD of the present invention is formed by laminating an identification member WK having an identifier ID formed thereon onto a wafer WF or a semiconductor chip (hereinafter simply referred to as a "chip") CP as a semiconductor body via an adhesive sheet AS as a covering material, and the identification member WK is laminated onto the wafer WF or the chip CP in direct contact with the adhesive sheet AS, and may be formed through the above-described embodiment or the processes exemplified below. According to such a semiconductor device SD, the identification member WK is laminated onto the wafer WF or the chip CP in direct contact with the adhesive sheet AS, and since there is nothing between the identification member WK and the adhesive sheet AS to adhere them, the semiconductor device SD can be made small.

[0021] In the covering material preparation step 10, an adhesive sheet AS may be prepared as a covering material for covering the chip CP as the semiconductor body, or any covering material may be prepared, such as an adhesive sheet, adhesive tape, glue, pressure-sensitive adhesive, resin, rubber, metal, solder, wax, varnish, or the like, as long as it is capable of adhering to both the semiconductor body and the identification member WK. The covering material may be a solid, liquid, or gel-like material. It may be a covering material larger than the semiconductor body, a covering material smaller than the semiconductor body, or a covering material the same size as the semiconductor body. The covering material preparation step 10 may be performed between the identification member preparation step 20 and the thinning step 30, between the thinning step 30 and the narrowing step 40, or between the narrowing step 40 and the stacking step 50. The covering material preparation step 10 may be performed at any stage during the manufacturing process of a semiconductor device SD in which the identification member WK is stacked on the semiconductor body while the identification member WK is in direct contact with the covering material.

[0022] In the identification member preparation step 20, the identifier ID may be formed on the main body of the identification member WK by using, for example, a cutting member such as a cutter blade or high-pressure water, a grinding member such as an end mill or a grinding stone, or an etching technique such as wet etching or dry etching. Any type of identifier forming device may be used, such as an inkjet printer, a letterpress printing machine, an intaglio printing machine, a lithographic printing machine, a silk screen printing machine, a thermal printing machine, a thermal transfer printing machine, a dot impact printing machine, an exposure device, an engraving device, an etching device, or a coloring device. The identifier ID may be formed on the main body of the identification member WK by printing, printing, transferring, exposing, engraving, etching, corrosion, coloring, discoloring, or the like. Any type of identifier ID may be formed, for example, letters, numbers, symbols, drawings, pictures, patterns, scratches, holes, or the like. An identifier ID that can be identified by a combination of letters and symbols may be formed. An identifier ID that can be identified by the arrangement or font of letters and symbols may be formed. An identifier ID that can be identified by code letters or code symbols may be formed. For example, as shown in FIG. 1(M), an identifier ID that can be identified may be formed by engraving. The identifier ID may be formed by a combination of engraved characters EL and inkjet-printed characters IL, or by an appropriate combination of engraved symbols, printed figures, inkjet-printed numbers, end-milled patterns, etc. For example, the identifier ID may be formed by only engraved pictures, only printed characters, only inkjet-printed symbols, only end-milled numbers, etc. For example, as shown in the enlarged view of FIG. 1(M), an identifier ID that can be identified may be formed by the irregular scraping of the contours of engraved characters EL, etc. For example, as shown in the enlarged view of FIG. 1(M), an identifier ID that can be identified may be formed by the irregular ink bleeding of inkjet-printed characters IL, etc. For example, as shown in the enlarged view of FIG. 1(M), an identifier ID that can be identified may be formed by irregular scattered marks SM caused by ink scattering by inkjet printing, etc. The identifier ID may be formed only on one surface WK1 of the identification member WK, or the identifier ID may be formed only on the other surface WK2 of the identification member WK.An identifier ID may be formed on both one surface WK1 and the other surface WK2 of the identification member WK, or one identifier ID may be formed on one identification member WK, or multiple identifiers IDs may be formed on one identification member WK. The identification member preparation step 20 may be performed before the covering material preparation step 10, or between the thinning step 30 and the narrowing step 40, or between the narrowing step 40 and the laminating step 50, or between the laminating step 50 and the energy application step 60, or after the energy application step 60. The identification member preparation step 20 may be performed at any stage in the process of manufacturing a semiconductor device SD in which the identification member WK is laminated on a semiconductor body while the identification member WK is in direct contact with the covering material, as long as it is possible to prepare the identification member WK. In the identification member preparation step 20, an identification member WK on which an identifier ID as described above has been pre-formed may be prepared without forming an identifier ID on a predetermined member, or an identification member WK on which some identifier ID has been pre-formed may be used, and an identifier ID as described above may be further formed on the identification member WK by an identifier forming device, thereby preparing the identification member WK.

[0023] In the thinning step 30, the thickness of the identification member WK may be thinned by scraping, cutting, punching, polishing, dissolving, or etching using a grinding machine such as an electric file, sander, slicing machine, electric cutter, shearing machine, press, polishing machine, or etching machine, or by thinning the identification member WK from one surface WK1 of the identification member WK, from the other surface WK2 of the identification member WK, or from both one surface WK1 and the other surface WK2 of the identification member WK. The thickness of the identification member WK may be thinned to be less than 30 μm, such as 300 nm or 10 μm, or may be thinned to be more than 30 μm, such as 100 μm or 1 mm, and the size and shape of the identification member WK are not limited. The thinning process 30 may be performed before the covering material preparation process 10, or between the covering material preparation process 10 and the identification member preparation process 20, or between the narrowing process 40 and the lamination process 50, or between the lamination process 50 and the energy application process 60, or may be performed after the energy application process 60.In the process of manufacturing a semiconductor device SD in which the identification member WK is laminated on the semiconductor body while the identification member WK is in direct contact with the covering material, the thinning process 30 may be performed at any stage as long as it is possible to thin the thickness of the identification member WK, and it may or may not be performed in the manufacturing method of the present invention.

[0024] In the narrowing step 40, an electric file, sander, slicing device, electric cutter, shearing device, press, polishing device, etching device, or the like may be used as a cutting tool to narrow the width of the identification member WK by scraping, cutting, punching, grinding, melting, or etching, or the width of the identification member WK may be narrowed from one surface WK1 side of the identification member WK, or from the other surface WK2 side of the identification member WK, or from both one surface WK1 side and the other surface WK2 side of the identification member WK, or a bottomed groove may be formed along the line to cut CL1 before the thinning step 30 is performed, and the identification member WK is thinned until it reaches the groove during the thinning step 30, thereby narrowing the width of the one surface WK1 side of the identification member WK, or a bottomed groove may be formed along the line to cut CL1 before the thinning step 30 is performed, A fragile layer may be formed along the fixed line CL1, and cracks may be generated in the fragile layer by the vibrations that occur during the thinning process 30, thereby narrowing the width of one surface WK1 of the identification member WK. Alternatively, the width of the identification member WK may be narrowed so that the widths in the left-right and front-to-back directions are less than 100 μm, such as 0.5 μm or 50 μm, or so that they are greater than 100 μm, such as 500 μm or 3 mm. Alternatively, the width of the identification member WK may be narrowed so that the widths in the left-right and front-to-back directions are the same, or so that the widths in the left-right and front-to-back directions are different. Alternatively, the width of the identification member WK may be narrowed so that the planar shape is any shape, such as a circle, an ellipse, a polygon such as a triangle or a pentagon, or any other shape, and the size and shape are not limited.The narrowing process 40 may be performed before the covering material preparation process 10, or between the covering material preparation process 10 and the identification member preparation process 20, or between the identification member preparation process 20 and the thinning process 30, or between the lamination process 50 and the energy application process 60, or may be performed after the energy application process 60.In the process of manufacturing a semiconductor device SD in which the identification member WK is laminated on the semiconductor body while the identification member WK is in direct contact with the covering material, the narrowing process 40 may be performed at any stage as long as it is possible to narrow the width of the identification member WK, and it may or may not be performed in the manufacturing method of the present invention.

[0025] In the lamination step 50, as shown by the two-dot chain line in FIG. 1(E), the adhesive sheet AS may be interposed between one surface CP1 of the chip CP and one surface WK1 of the identification member WK, and the identification member WK may be laminated on the chip CP in a state where the identification member WK is in direct contact with the adhesive sheet AS, or the adhesive sheet AS may be interposed between one surface WF1, CP1 of the wafer WF or chip CP and the other surface WK2 of the identification member WK, and the identification member WK may be laminated on the wafer WF or chip CP in a state where the identification member WK is in direct contact with the adhesive sheet AS, or The identification member WK may be laminated on the wafer WF or the chip CP with the adhesive sheet AS interposed between the other surface WF2, CP2 of the chip CP and one surface WK1 of the identification member WK, with the identification member WK in direct contact with the adhesive sheet AS, or the identification member WK may be laminated on the wafer WF or the chip CP with the adhesive sheet AS interposed between the other surface WF2, CP2 of the wafer WF or the chip CP and the other surface WK2 of the identification member WK, with the identification member WK in direct contact with the adhesive sheet AS, or The identification member WK may be laminated on the wafer WF or chip CP in a state where the identification member WK is in direct contact with an adhesive sheet AS coated so as to cover all or part of the other surfaces WF2, CP2 of the wafer WF or chip CP, or the identification member WK may be laminated on the wafer WF or chip CP in a state where the identification member WK is in direct contact with an adhesive sheet AS coated so as to cover all or part of one surface WF1, CP1 of the wafer WF or chip CP and all or part of the other surface WF2, CP2 of the wafer WF or chip CP. The identification member WK may be laminated on the wafer WF or chip CP with the identification member WK in direct contact with the sheet AS, or the identification member WK may be laminated on the wafer WF or chip CP with the identification member WK in direct contact with an adhesive sheet AS coated so as to cover all or part of one surface WF1, CP1 of the wafer WF or chip CP and all or part of the side surface of the wafer WF or chip CP, or the identification member WK may be laminated on the wafer WF or chip CP with the identification member WK in direct contact with an adhesive sheet AS coated so as to cover all or part of the other surface WF2, CP2 of the wafer WF or chip CP and all or part of the side surface of the wafer WF or chip CP.The identification member WK may be laminated on the wafer WF or the chip CP in a state where the identification member WK is in direct contact with the wafer WF or the chip CP, or the identification member WK may be laminated on the wafer WF or the chip CP in a state where the identification member WK is in direct contact with an adhesive sheet AS that covers the entire one surface WF1, the entire other surface WF2, and the entire side surface of the wafer WF, or the identification member WK may be laminated on the wafer WF or the chip CP in a state where the identification member WK is in direct contact with an adhesive sheet AS that covers the entire one surface CP1, the entire other surface CP2, and the entire side surface of the chip CP, or the identification member WK may be laminated on the wafer WF or the chip CP in a state where the identification member WK is in direct contact with an adhesive sheet AS that covers any surface of the wafer WF or the chip CP. The identification member WK may be laminated on the wafer WF or the chip CP while in contact with the wafer WF or the chip CP, or the wafer WF or the chip CP may be covered with an adhesive sheet AS, and then the identification member WK is directly adhered to the adhesive sheet AS and laminated on the wafer WF or the chip CP, or the identification member WK may be directly adhered to the adhesive sheet AS, and then the wafer WF or the chip CP may be covered with the adhesive sheet AS and then laminated on the wafer WF or the chip CP, or the wafer WF or the chip CP may be covered with the adhesive sheet AS, and at the same time the identification member WK is directly adhered to the adhesive sheet AS and laminated on the wafer WF or the chip CP. In the lamination step 50, for example, a liquid adhesive, liquid pressure-sensitive adhesive, or liquid resin material may be used as the coating material and sprayed or sprayed onto the wafer WF, chips CP, or identification member WK, thereby laminating the identification member WK on the wafer WF or chip CP in a state where the identification member WK is in direct contact with the coating material; or, as shown in FIGS. 1(H) and 1(J), one identification member WK may be laminated on one wafer WF or one chip CP in a state where one identification member WK is in direct contact with one adhesive sheet AS; or, as shown in the upper part of FIG. 1(I) and FIG. 1(K), multiple identification members WK may be laminated on one wafer WF or one chip CP in a state where one adhesive sheet AS is in direct contact with multiple identification members WK; or, as shown in the lower part of FIG. 1(I) and FIG. 1(L), multiple identification members WK may be laminated on one wafer WF or one chip CP in a state where one adhesive sheet AS is in direct contact with multiple adhesive sheets AS, respectively; orOne or more identification members WK may be laminated on only one side or only the other side of one wafer WF or one chip CP while being in direct contact with one or more adhesive sheets AS, or one or more identification members WK may be laminated on both one and the other sides of one wafer WF or one chip CP while being in direct contact with one or more adhesive sheets AS. The laminating step 50 may be performed between the covering material preparing step 10 and the identification member preparing step 20, between the identification member preparing step 20 and the thinning step 30, between the thinning step 30 and the narrowing step 40, or after the energy applying step 60. In the process of manufacturing a semiconductor device SD in which the identification members WK are laminated on the semiconductor body while being in direct contact with the covering material, the laminating step 50 may be performed at any stage as long as it is possible to laminate the identification members WK on the semiconductor body via the covering material. In the lamination step 50, when the identification member WK is laminated on the wafer WF via the adhesive sheet AS, the adhesive sheet AS may be configured to fill the entire interior of the engraved identifier ID, as shown in Figures 1(E) and 1(F), the adhesive sheet AS may be configured to fill only a portion of the engraved identifier ID, or the adhesive sheet AS may not be configured to fill the entire interior of the engraved identifier ID, or as shown in Figures 1(E) and 1(F), the identification member WK may be configured to be partially embedded in the adhesive sheet AS, or the identification member WK may be configured to not be embedded in the adhesive sheet AS, or the identification member WK on the adhesive sheet AS may be covered with a cover member such as a sheet or adhesive that is the same as or different from the covering material.

[0026] In the energy application step 60, any type of energy may be applied to the coating material as the predetermined energy, such as application of electromagnetic waves such as ultraviolet rays, infrared rays, visible light, sound waves, X-rays, or gamma rays, application of a heating medium such as hot water or hot air, or application of a cooling medium such as cold water or cold air. Any type of energy may be applied to the coating material as long as it can cause a change specific to that energy in the coating material, taking into account the characteristics, properties, properties, material, composition, and configuration of the coating material. The energy application step 60 may be performed between the coating material preparation step 10 and the identification member preparation step 20, or between the identification member preparation step 20 and the thinning step 30, or between the thinning step 30 and the narrowing step 40, or between the narrowing step 40 and the lamination step 50. In the process of manufacturing a semiconductor device SD in which the identification member WK is laminated on the semiconductor body while the identification member WK is in direct contact with the coating material, the energy application step 60 may be performed at any stage at which it is possible to apply the predetermined energy to the adhesive sheet AS, and may or may not be performed in the manufacturing method of the present invention.

[0027] The main body of the identification member WK may be made of the same material as the semiconductor body, or a different material. It may be made of any material, including silicon semiconductors, compound semiconductors, metals, glass, ceramics, wood, resins, etc. The coating material may be any material that can adhere to both the semiconductor body and the identification member WK, such as an adhesive sheet, adhesive tape, glue, pressure-sensitive adhesive, resin, rubber, metal, solder, wax, varnish, etc. It may be a solid, liquid, or gel-like substance, may be larger, smaller, or the same size as the semiconductor body, and may have any shape other than a circle, such as a polygon (e.g., triangular or pentagonal), or an ellipse. It may also be a material that does not undergo a change specific to the specified energy when a specified energy is applied. The change specific to the specified energy that the coating material undergoes may be any change, such as hardening, softening, shrinkage, expansion, vaporization, liquefaction, solidification, discoloration, oxidation, penetration, fixation, a decrease in adhesive strength, or an increase in adhesive strength. The wafer WF may have an orientation flat or a V-notch formed on its outer edge to indicate orientation, or may not have an orientation flat or a V-notch formed on its outer edge, may have a circuit formed on one surface WF1, may have a circuit formed on the other surface WF2, may have a circuit formed on both the one surface WF1 and the other surface WF2, or may have no circuit formed on either the one surface WF1 or the other surface WF2. The chips CP may be formed by cutting the wafer WF along a cut line CL2, or may not be cut along the cut line CL2, may have a circuit formed on one surface CP1, may have a circuit formed on the other surface CP2, may have a circuit formed on both the one surface CP1 and the other surface CP2, or may have no circuit formed on either the one surface WF1 or the other surface WF2.The semiconductor body may be thinned from a thickness of, for example, 1 mm or 750 μm to a thickness of 100 μm or 10 μm and used in the lamination process 50, or may be thinned to a thickness of, for example, 150 μm or 20 μm by using a semiconductor body with a thickness of, for example, 2 mm or 500 μm and then performing a semiconductor thinning process after the lamination process 50. The various processes performed on the semiconductor device SD may be any process, such as an installation process for installing the semiconductor device SD on another object, a marking process for imprinting or printing on the semiconductor device SD, a transport process for transporting the semiconductor device SD, a cutting process or grinding process for the semiconductor device SD, or an inspection or cleaning process for the semiconductor device SD.

[0028] The semiconductor device SD as shown in Fig. 1(H) may be cut along the cut line CL2 to form a semiconductor device SD in which an adhesive sheet AS is attached to a chip CP, or may not be cut. The semiconductor device SD as shown in the upper part of Fig. 1(I) may be cut along the cut line CL2 to form a semiconductor device SD as shown in Fig. 1(J), or may not be cut. The semiconductor device SD as shown in the lower part of Fig. 1(I) may be cut along the cut line CL2, or may not be cut.

[0029] The materials, types, shapes, etc. of the identification member WK, covering material, and semiconductor body in the present invention are not particularly limited. For example, the identification member WK, covering material, and semiconductor body may be circular, elliptical, polygonal (e.g., triangular, rectangular), or other shapes. The covering material may be pressure-sensitive, heat-sensitive, or other adhesive. If a heat-sensitive covering material is used, the covering material may be adhered by an appropriate method, such as providing a heating means such as a coil heater or the heated side of a heat pipe. Furthermore, adhesive sheets used as such covering materials may be of any type, such as a single-layer adhesive layer, a two-layer structure in which a substrate and an adhesive layer are laminated, a three-layer structure in which one or more intermediate layers are laminated between the substrate and the adhesive layer, a three-layer structure in which one or more cover layers are laminated on the top surface of the substrate, a structure in which the substrate, intermediate layer, or cover layer are releasably provided, a double-sided adhesive sheet in which only the adhesive layer is formed, or a double-sided adhesive sheet in which adhesive layers are laminated on both outermost surfaces of one or more intermediate layers. The covering material may be any sheet, film, tape, etc., such as an information label, a decorative label, a protective sheet, a dicing tape, a die attach film, a die bonding tape, a recording layer forming resin sheet, etc. The semiconductor body may be any semiconductor, such as a silicon semiconductor, a compound semiconductor, a diamond semiconductor, etc.

[0030] 10...Covering material preparation step 20...Identification member preparation step 30...Thinning step 40...Narrowing step 50...Lamination step 60...Energy application step AS...Adhesive sheet (covering material) CP...Semiconductor chip (semiconductor body) HA...Heat (predetermined energy) ID...Identifier SD...Semiconductor device WF...Semiconductor wafer (semiconductor body) WK...Identification member WK1...One surface

Claims

1. A manufacturing method of a semiconductor device, comprising: a coating material preparation step of preparing a coating material for coating a semiconductor body; an identification member preparation step of preparing an identification member having an identifier formed thereon; and a lamination step of laminating the identification member on the semiconductor body via the coating material to form a semiconductor device. In the coating material preparation step, a coating material that can adhere to both the semiconductor body and the identification member is prepared. In the lamination step, the identification member is laminated on the semiconductor body in a state where the identification member is in direct contact with the coating material.

2. The manufacturing method of a semiconductor device according to claim 1, wherein in the lamination step, the identification member is laminated on the coating material such that the identifier is on the coating material side.

3. The manufacturing method of a semiconductor device according to claim 1 or 2, further comprising a thinning step of thinning a thickness in a direction intersecting one surface of the identification member.

4. The manufacturing method of a semiconductor device according to claim 1 or 2, further comprising a narrowing step of narrowing a width in one surface direction of the identification member.

5. The manufacturing method of a semiconductor device according to claim 1 or 2, wherein the coating material has a property of causing a change specific to the predetermined energy by applying the predetermined energy, and an energy application step of applying the predetermined energy to the coating material is performed.

6. A semiconductor device in which an identification member having an identifier formed thereon is laminated on a semiconductor body via a coating material, wherein the identification member is laminated on the semiconductor body in a state where the identification member is in direct contact with the coating material.

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