Multilayer ceramic circuit board, method for manufacturing same, and semiconductor device

Abstract

A method for manufacturing a multilayer ceramic circuit board, the method comprising: a step (I) for forming a first wiring layer containing copper on a core substrate selected from the group consisting of a ceramic substrate and a glass substrate; and a step (II) for forming, on the first wiring layer, a unit layer including a ceramic insulating layer containing a ceramic material and a second wiring layer containing copper, the step (II) including a step (II-1) for forming the ceramic insulating layer by an aerosol deposition method, a step (II-2) for flattening the surface on the side opposite to the core substrate of the ceramic insulating layer formed by the aerosol deposition method, and a step (II-4) for forming the second wiring layer on the flattened surface of the ceramic insulating layer.

Description

Multilayer ceramic circuit board, manufacturing method thereof, and semiconductor device

[0001] The present invention relates to a multilayer ceramic circuit board, a method for manufacturing the same, and a semiconductor device.

[0002] Semiconductor devices generally include electronic components such as inductors, capacitors, resistors, and filters (see Patent Documents 1 and 2). Hereinafter, these electronic components may be simply referred to as "components." These components are typically mounted on circuit boards such as printed wiring boards and semiconductor package substrates (see Patent Document 3). In many cases, the insulating layer of a circuit board has been formed from an organic material. However, in order to address the increased electrical signal loss and higher temperatures that have accompanied the recent increase in communication traffic, a ceramic circuit board technology has been proposed in which the insulating layer is formed from a ceramic material (see Patent Document 4).

[0003] JP 2003-166077 A JP 2016-130350 A JP 2005-294767 A JP 2021-155244 A

[0004] Conventionally, ceramic circuit boards have generally been manufactured using green sheets. The green sheets contain raw powder of ceramic material. By firing the green sheets, insulating layers made of ceramic material can be formed. For example, a method for manufacturing a circuit board using a green sheet is as follows.

[0005] That is, via holes are formed in the green sheets as necessary, and a conductive paste containing a metal powder such as silver powder is printed on them. The green sheets with the conductive paste printed on them are stacked and laminated by heating and pressure. A firing process is then performed. The raw material powder is sintered by the firing process to form an insulating layer. The metal powder is also sintered by the firing process to form wiring. Thus, a ceramic circuit board is obtained that includes an insulating layer containing a ceramic material and wiring containing a metal. Unless otherwise specified, the term "wiring" includes not only wiring in the narrow sense but also electrodes.

[0006] However, since the firing process is performed at high temperatures, such as 900°C or higher, the firing process may accelerate oxidation of the metal contained in the wiring. Generally, when a metal oxidizes, its resistance increases. Therefore, the use of easily oxidized metal powders, such as copper, is limited to applications that do not require high electrical properties for the wiring, and it has been difficult to form wiring using copper in circuit board applications that require high electrical properties. In this regard, surface wiring can be formed after the firing process. However, wiring inside the board cannot be formed after the firing process. Therefore, in conventional circuit board manufacturing methods using green sheets, it has been difficult to form copper wiring containing copper as wiring inside the board. Furthermore, a firing process involving reduction with formic acid or hydrogen has been proposed, but its application in mass production has been difficult from safety and technical standpoints.

[0007] In addition, when forming wiring using a conductor paste, it is usually difficult to form wiring with a fine pattern shape. Furthermore, when using a conductor paste, it is difficult to increase the wiring thickness, making it difficult to increase the wiring aspect ratio. Furthermore, the cross-sectional shape of the wiring is prone to bending, making it difficult to form wiring with a rectangular cross-sectional shape. For these reasons, it has been difficult to develop wiring using a conductor paste in applications requiring excellent electrical properties. Here, the "wiring aspect ratio" refers to the ratio obtained by dividing the thickness of the wiring by the width of the wiring. Furthermore, unless otherwise specified, the "cross-sectional shape" of a wiring refers to the shape of the cross section of the wiring cut by a plane perpendicular to the direction in which the wiring extends.

[0008] The present invention has been made in view of the above-mentioned problems, and has as its object to provide a multilayer ceramic circuit substrate including copper-containing wiring therein, a method for manufacturing the same, and a semiconductor device including the multilayer ceramic circuit substrate.

[0009] The present inventors have conducted extensive research to solve the above-mentioned problems. As a result, the present inventors have found that the above-mentioned problems can be solved by a method for manufacturing a multilayer ceramic circuit board, the method comprising: step (I) of forming a first wiring layer containing copper on a core substrate such as a ceramic substrate or a glass substrate; and step (II) of forming unit layers each having a ceramic insulating layer and a second wiring layer on the first wiring layer, wherein step (II) comprises step (II-1) of forming a ceramic insulating layer by an aerosol deposition method, step (II-2) of planarizing the surface of the ceramic insulating layer, and step (II-4) of forming a second wiring layer on the planarized surface of the ceramic insulating layer. This finding led to the completion of the present invention. Specifically, the present invention comprises the following:

[0010] <1> A method for producing a multilayer ceramic circuit board, comprising: step (I) of forming a first wiring layer containing copper on a core substrate selected from the group consisting of a ceramic substrate and a glass substrate; and step (II) of forming, on the first wiring layer, a unit layer including a ceramic insulating layer containing a ceramic material and a second wiring layer containing copper, wherein step (II) comprises: step (II-1) of forming a ceramic insulating layer by an aerosol deposition method; step (II-2) of planarizing a surface of the ceramic insulating layer formed by the aerosol deposition method opposite to the core substrate; and step (II-4) of forming a second wiring layer on the planarized surface of the ceramic insulating layer; and step (II) of repeating step (II) two or more times. <2> A method for producing a multilayer ceramic circuit board according to <1>, wherein step (II) comprises step (II-3) of forming via holes in the ceramic insulating layer between steps (II-2) and (II-4). <3> A method for producing a multilayer ceramic circuit board according to <1> or <2>, wherein the first wiring layer includes a relatively high pillar portion and a relatively low wiring portion. <4> A method for producing a multilayer ceramic circuit board according to <3>, wherein step (II-2) includes polishing the ceramic insulating layer so as to expose the pillar portion. <5> A method for producing a multilayer ceramic circuit board according to any one of <1> to <4>, wherein the first wiring layer and the second wiring layer are formed by a plating method. <6> A method for producing a multilayer ceramic circuit board according to <5>, wherein the plating method includes forming a seed layer by sputtering and forming an electrolytic plating layer on the seed layer by electrolytic plating. <7> A method for producing a multilayer ceramic circuit board according to any one of <1> to <6>, wherein step (I) includes laminating a copper foil on a core substrate directly or via an adhesive layer. <8> A method for producing a multilayer ceramic circuit board according to any one of <1> to <7>, wherein the ceramic material is alumina. <9> The method for producing a multilayer ceramic circuit board according to any one of <1> to <8>, wherein, after step (II-1) and before step (II-2), the ceramic insulating layer is thicker than the first wiring layer.<10> A multilayer ceramic circuit board comprising: a core substrate selected from the group consisting of a ceramic substrate and a glass substrate, a first wiring layer formed on the core substrate, and a plurality of unit layers formed on the first wiring layer; the first wiring layer contains copper; each unit layer comprises a ceramic insulating layer containing a ceramic material and a second wiring layer containing copper; the surface of the ceramic insulating layer opposite to the core substrate is flattened; and the second wiring layer is formed on the flattened surface of the ceramic insulating layer. <11> The multilayer ceramic circuit board according to <10>, which is a semiconductor package substrate. <12> A semiconductor device comprising the multilayer ceramic circuit board according to <10> or <11>.

[0011] According to the present invention, it is possible to provide a multilayer ceramic circuit board including copper-containing wiring therein, a method for manufacturing the same, and a semiconductor device including the multilayer ceramic circuit board.

[0012] FIG. 1 is a cross-sectional view schematically illustrating a multilayer ceramic circuit board according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view schematically illustrating a method for forming a core wiring layer by a semi-additive process in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view schematically illustrating a method for forming a core wiring layer by a semi-additive process in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view schematically illustrating a method for forming a core wiring layer by a semi-additive process in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view schematically illustrating a method for forming a core wiring layer by a semi-additive process in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a method for forming a core wiring layer by a semi-additive process in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention. FIG. 7 is a schematic diagram illustrating an example of an apparatus for forming a ceramic insulating layer. FIG. 8 is a cross-sectional view schematically illustrating an enlarged aerosol generator included in the apparatus for forming a ceramic insulating layer according to the example. FIG. 9 is a cross-sectional view schematically illustrating step (II-1) in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention. FIG. 10 is a schematic cross-sectional view illustrating step (II-2) in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention. FIG. 11 is a schematic cross-sectional view illustrating step (II-3) in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention. FIG. 12 is a schematic cross-sectional view illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention. FIG. 13 is a schematic cross-sectional view illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention. FIG. 14 is a schematic cross-sectional view illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention. FIG. 15 is a schematic cross-sectional view illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention.FIG. 16 is a schematic cross-sectional view illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention. FIG. 17 is a schematic cross-sectional view illustrating the second step (II) in the method for manufacturing a multilayer ceramic circuit board according to the first embodiment of the present invention. FIG. 18 is a schematic cross-sectional view illustrating a multilayer ceramic circuit board according to a second embodiment of the present invention. FIG. 19 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a semi-additive method in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 20 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a semi-additive method in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 21 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a semi-additive method in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 22 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a semi-additive method in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 23 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a semi-additive method in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 24 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a semi-additive process in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 25 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a semi-additive process in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 26 is a schematic cross-sectional view illustrating step (II-1) in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 27 is a schematic cross-sectional view illustrating step (II-2) in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 28 is a schematic cross-sectional view illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 29 is a schematic cross-sectional view illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention.FIG. 30 is a schematic cross-sectional view illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 31 is a schematic cross-sectional view illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 32 is a schematic cross-sectional view illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 33 is a schematic cross-sectional view illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 34 is a schematic cross-sectional view illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 35 is a schematic cross-sectional view illustrating a second step (II) in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. FIG. 36 is a schematic cross-sectional view illustrating a multilayer ceramic circuit board according to a third embodiment of the present invention. FIG. 37 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a subtractive method in the method for manufacturing a multilayer ceramic circuit board according to the third embodiment of the present invention. FIG. 38 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a subtractive method in the method for manufacturing a multilayer ceramic circuit board according to the third embodiment of the present invention. Fig. 39 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to a third embodiment of the present invention. Fig. 40 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to a third embodiment of the present invention. Fig. 41 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to the third embodiment of the present invention. Fig. 42 is a schematic cross-sectional view illustrating a method for forming a build-up wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to the third embodiment of the present invention. Fig. 43 is a schematic cross-sectional view illustrating a method for forming a build-up wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to the third embodiment of the present invention.FIG. 44 is a schematic cross-sectional view illustrating a subtractive method for forming a build-up wiring layer in the method for manufacturing a multilayer ceramic circuit board according to the third embodiment of the present invention. FIG. 45 is a schematic cross-sectional view illustrating a subtractive method for forming a build-up wiring layer in the method for manufacturing a multilayer ceramic circuit board according to the third embodiment of the present invention. FIG. 46 is a schematic cross-sectional view illustrating a subtractive method for forming a build-up wiring layer in the method for manufacturing a multilayer ceramic circuit board according to the third embodiment of the present invention. FIG. 47 is a schematic cross-sectional view illustrating a multilayer ceramic circuit board according to a fourth embodiment of the present invention. FIG. 48 is a schematic cross-sectional view illustrating a subtractive method for forming a core wiring layer in the method for manufacturing a multilayer ceramic circuit board according to the fourth embodiment of the present invention. FIG. 49 is a schematic cross-sectional view illustrating a subtractive method for forming a core wiring layer in the method for manufacturing a multilayer ceramic circuit board according to the fourth embodiment of the present invention. FIG. 50 is a schematic cross-sectional view illustrating a subtractive method for forming a core wiring layer in the method for manufacturing a multilayer ceramic circuit board according to the fourth embodiment of the present invention. FIG. 51 is a schematic cross-sectional view illustrating a subtractive method for forming a core wiring layer in the method for manufacturing a multilayer ceramic circuit board according to the fourth embodiment of the present invention. Fig. 52 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to a fourth embodiment of the present invention. Fig. 53 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to the fourth embodiment of the present invention. Fig. 54 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to the fourth embodiment of the present invention. Fig. 55 is a schematic cross-sectional view illustrating a method for forming a core wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to the fourth embodiment of the present invention.FIG. 56 is a schematic cross-sectional view illustrating a method for forming a build-up wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to a fourth embodiment of the present invention. FIG. 57 is a schematic cross-sectional view illustrating a method for forming a build-up wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to a fourth embodiment of the present invention. FIG. 58 is a schematic cross-sectional view illustrating a method for forming a build-up wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to a fourth embodiment of the present invention. FIG. 59 is a schematic cross-sectional view illustrating a method for forming a build-up wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to a fourth embodiment of the present invention. FIG. 60 is a schematic cross-sectional view illustrating a method for forming a build-up wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to a fourth embodiment of the present invention. FIG. 61 is a schematic cross-sectional view illustrating a method for forming a build-up wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to a fourth embodiment of the present invention. FIG. 62 is a schematic cross-sectional view illustrating a method for forming a build-up wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to a fourth embodiment of the present invention. FIG. 63 is a schematic cross-sectional view illustrating a method for forming a build-up wiring layer by a subtractive method in a method for manufacturing a multilayer ceramic circuit board according to a fourth embodiment of the present invention.

[0013] The present invention will be described in detail below with reference to embodiments and examples. However, the present invention is not limited to the embodiments and examples described below, and may be modified and implemented within the scope of the claims and their equivalents.

[0014] In the following description, unless otherwise specified, a layer (first layer) being "directly below" another layer (second layer) means that the first layer and the second layer are in contact with each other without any other layer in between, and that the first layer is closer to the core substrate than the second layer.

[0015] In the following description, unless otherwise specified, when a layer (first layer) is "directly on" another layer (second layer), it means that the first layer and the second layer are in contact with each other without any other layer in between, and that the first layer is farther from the core substrate than the second layer.

[0016] First Embodiment (Overview of Multilayer Ceramic Circuit Board 1 According to First Embodiment) FIG. 1 is a cross-sectional view schematically illustrating a multilayer ceramic circuit board 1 according to a first embodiment of the present invention. As shown in FIG. 1, the multilayer ceramic circuit board 1 according to the first embodiment of the present invention includes a core substrate 100, a first wiring layer 200 formed on the core substrate 100, and a plurality of unit layers 300A and 300B formed on the first wiring layer 200. In the following description, the "first wiring layer" 200 may be referred to as the "core wiring layer" 200. In this embodiment, a multilayer ceramic circuit board 1 including two unit layers 300A and 300B will be described as an example, but the number of unit layers may be three or more. The multilayer ceramic circuit board 1 may further include a surface coating layer 400.

[0017] The core substrate 100 represents a substrate selected from the group consisting of a ceramic substrate and a glass substrate.

[0018] The ceramic substrate may contain a ceramic material or may contain only a ceramic material. Examples of ceramic materials include metal oxides, transition metal oxides, metal nitrides, metal carbides, boride-based ceramics, and silicon. Here, the metal oxides and transition metal oxides may contain composite oxides. Specific examples of ceramic materials include metal oxides such as aluminum oxide (alumina), zinc oxide, silicon oxide, magnesium oxide, and calcium oxide; composite oxides such as diamond, sapphire, cordierite, β-spondumene, forsterite, cermet, steatite, aluminum titanate, barium titanate, calcium titanate, strontium titanate, zinc titanate, mullite, spinel, calcium zirconate, strontium zirconate, barium zirconate titanate, bismuth titanate, and strontium bismuth titanate; and metal carbides such as silicon carbide. Examples of suitable ceramic substrates include oxides; metal nitrides such as silicon nitride, aluminum nitride, boron nitride, and titanium nitride; transition metal oxides such as zirconium oxide, yttrium oxide, nickel oxide, iron oxide, titanium oxide, tantalum oxide, tin oxide, vanadium oxide, cerium oxide, and chromium oxide; soft magnetic materials such as ferrites, including Mg-Zn ferrite, Mn-Zn ferrite, Mn-Mg ferrite, Cu-Zn ferrite, Mg-Mn-Sr ferrite, Ni-Zn ferrite, Ni-Cu-Zn ferrite, Ni-Cu-Zn-Mg ferrite, and Ba ferrite; silicon; and boride-based ceramics. Among these, metal oxides are preferred, with aluminum oxide being more preferred. Ceramic substrates containing aluminum oxide are particularly excellent in heat dissipation and mechanical reliability. The ceramic materials may be used singly or in combination of two or more.

[0019] The glass substrate may contain a glass material, or may contain only a glass material. Examples of the glass material include alkali-free glass, quartz glass, and borosilicate glass, with alkali-free glass being preferred. The glass material may be used alone or in combination of two or more.

[0020] There are no particular limitations on the thickness range of the core substrate 100, but it is preferably 10 μm or more, more preferably 100 μm or more, even more preferably 300 μm or more, and preferably 10 mm or less, more preferably 5 mm or less, even more preferably 2 mm or less.

[0021] The core wiring layer 200 may be formed on one surface or both surfaces of the core substrate 100. In this embodiment, an example in which the core wiring layer 200 is formed on one surface 110 of the core substrate 100 will be described.

[0022] The core wiring layer 200 contains copper. The core wiring layer 200 may contain only copper, or may contain copper and any metal other than copper. For example, the core wiring layer 200 may include a layer of an alloy containing copper and any metal. Furthermore, for example, the core wiring layer 200 may include a layer containing copper and another layer containing any metal. Examples of the any metal include gold, platinum, palladium, silver, aluminum, cobalt, chromium, zinc, nickel, titanium, tungsten, iron, tin, and indium. One type of any metal may be used alone, or two or more types may be used in combination.

[0023] From the viewpoint of obtaining high conductivity, the core wiring layer 200 is preferably a plating layer formed by a plating method, and more preferably a copper plating layer formed by copper plating. In this embodiment, a core wiring layer 200 including a seed layer 210 and an electrolytic plating layer 220 will be described as an example. The seed layer 210 preferably contains any metal such as titanium, and may contain a combination of copper and any metal. When the seed layer 210 that contacts the core wiring layer 200 with the core substrate 100 contains any metal, the adhesion between the metal wiring layer 200 and the core substrate 100 can be improved. On the other hand, the electrolytic plating layer 220 preferably contains copper, and may contain only copper.

[0024] The thickness of the core wiring layer 200 depends on the design of the multilayer ceramic circuit substrate 1, but is preferably 0.3 μm or more, more preferably 0.5 μm or more, and even more preferably 1 μm or more, and is preferably 70 μm or less, more preferably 50 μm or less, and even more preferably 30 μm or less. Furthermore, when the core wiring layer 200 includes a seed layer 210, the thickness of the seed layer 210 is preferably 5 nm or more, more preferably 10 nm or more, and is preferably 1000 nm or less, and even more preferably 500 nm or less. Furthermore, when the core wiring layer 200 includes an electroplated layer 220, the thickness of the electroplated layer 220 is preferably 0.2 μm or more, more preferably 1 μm or more, and even more preferably 2 μm or more, and is preferably 60 μm or less, more preferably 40 μm or less, and even more preferably 20 μm or less.

[0025] The core wiring layer 200 may be formed over the entire surface 110 of the core substrate 100, but is usually formed on a portion of the surface 110 of the core substrate 100. Preferably, the core wiring layer 200 is patterned so that it can have a pattern shape corresponding to the design of the multilayer ceramic circuit board 1. Unless otherwise specified, the term "pattern shape" refers to the shape seen from the thickness direction.

[0026] From the viewpoint of increasing the density of the core wiring layers 200, it is preferable that the minimum spacing between the core wiring layers 200 be small. The range of the minimum spacing between the core wiring layers 200 is preferably 20 μm or less, more preferably 15 μm or less, and even more preferably 10 μm or less. The lower limit may be, for example, 0.5 μm or more. From the same viewpoint, it is also preferable that the minimum line / space ratio of the core wiring layer 200 be small. Unless otherwise specified, "line" refers to the wiring width of the wiring layer, and "space" refers to the spacing between the wirings. The range of the minimum line / space ratio is preferably 20 μm / 20 μm or less (i.e., a minimum pitch of 40 μm or less), more preferably 15 μm / 15 μm or less (i.e., a minimum pitch of 30 μm or less), and even more preferably 10 μm / 10 μm or less (i.e., a pitch of 20 μm or less). The lower limit may be, for example, 0.5 μm / 0.5 μm or more (i.e., a pitch of 1.0 μm or more). The pitch may be uniform or non-uniform across the entire core wiring layer 200 .

[0027] Each unit layer 300A and 300B includes a ceramic insulating layer 310A or 310B and a second wiring layer 320A or 320B. In the following description, the "second wiring layers" 320A and 320B may be referred to as "build-up wiring layers" 320A and 320B.

[0028] The ceramic insulating layers 310A and 310B may contain a ceramic material or may contain only a ceramic material. The ceramic material contained in the ceramic insulating layers 310A and 310B may be the same as or different from the ceramic material contained in the ceramic substrate. The ceramic material contained in the ceramic insulating layers 310A and 310B is preferably one that can be deposited by aerosol deposition, and more preferably a metal oxide. Examples of such metal oxides include aluminum oxide (alumina), zinc oxide, silicon oxide, magnesium oxide, calcium oxide, zirconium oxide, yttrium oxide, nickel oxide, iron oxide, titanium oxide, tantalum oxide, tin oxide, vanadium oxide, cerium oxide, and chromium oxide; titanates such as aluminum titanate, barium titanate, calcium titanate, strontium titanate, zinc titanate, bismuth titanate, and strontium bismuth titanate; zirconates such as calcium zirconate, strontium zirconate, and barium zirconate; and ferrites such as Mg—Zn ferrite, Mn—Zn ferrite, Mn—Mg ferrite, Cu—Zn ferrite, Mg—Mn—Sr ferrite, Ni—Zn ferrite, Ni—Cu—Zn ferrite, Ni—Cu—Zn—Mg ferrite, and Ba ferrite. One type of metal oxide may be used alone, or two or more types may be used in combination.

[0029] Among metal oxides, highly insulating oxides are preferred. Highly insulating oxides have a volume resistivity of 1.0×10 at room temperature. ８ Ω m to 1.0 x 10 １７ This refers to oxides with a volume resistivity in the range of Ω·m. The volume resistivity can be measured using a High Resistance Meter (4339B) manufactured by Hewlett Packard at an applied voltage of 100 mV to 10 V. Examples of highly insulating oxides include alumina, silicon oxide, magnesium oxide, and calcium oxide, with alumina being preferred. The ceramic insulating layers 310A and 310B containing alumina are particularly excellent in heat dissipation and mechanical reliability.

[0030] The thickness of each ceramic insulating layer 310A and 310B is preferably 100 nm or more, more preferably 500 nm or more, even more preferably 1 μm or more, and even more preferably 2 μm or more. When the ceramic insulating layers 310A and 310B are thick in this manner, the heat dissipation performance of the ceramic insulating layers 310A and 310B can be effectively improved. There is no particular upper limit to the thickness, and it can be, for example, 10 μm or less. When the thickness of the ceramic insulating layers 310A and 310B is not uniform, it is preferable that the maximum thickness be within the above range.

[0031] In each unit layer 300A and 300B, surfaces 330A and 330B of the ceramic insulating layers 310A and 310B opposite the core substrate 100 are planarized. Build-up wiring layers 320A and 320B are formed on the planarized surfaces 330A and 330B of the ceramic insulating layers 310A and 310B, respectively. These planarized surfaces 330A and 330B preferably have low surface roughness. In one example, the arithmetic mean roughness Ra of the surfaces 330A and 330B is preferably less than 1000 Å, more preferably 500 Å or less, even more preferably 300 Å or less, and even more preferably 200 Å or less. The lower limit is not particularly limited and may be, for example, 0.1 Å or more, 0.5 Å or more, or 1 Å or more. Furthermore, the maximum height Ry of the surfaces 330A and 330B may be less than 5000 Å. Unless otherwise specified, the arithmetic mean roughness Ra and the maximum height Ry are values ​​measured in accordance with ISO 25178 and can be measured using an atomic force microscope.

[0032] Via holes 340A and 340B may be formed in the ceramic insulating layers 310A and 310B, penetrating the ceramic insulating layers 310A and 310B. The opening diameter of the via holes 340A and 340B may be selected depending on the design of the multilayer ceramic circuit substrate 1, and is preferably 70 μm or less, more preferably 60 μm or less, even more preferably 50 μm or less, and still more preferably 30 μm or less. The lower limit is not particularly limited, but may be 1 μm or more.

[0033] The build-up wiring layers 320A and 320B may contain copper or may contain only copper. The build-up wiring layers 320A and 320B may be formed in the same manner as the core wiring layer 200, except that they are formed on the surfaces 330A and 330B of the ceramic insulating layers 310A and 310B. Therefore, the ranges of the composition, layer structure, dimensions, and pattern shape of the build-up wiring layers 320A and 320B may be the same as the ranges of the composition, layer structure, dimensions, and pattern shape of the core wiring layer 200.

[0034] In this embodiment, a build-up wiring layer 320A including a seed layer 321A and an electrolytically plated layer 322A, and a build-up wiring layer 320B including a seed layer 321B and an electrolytically plated layer 322B are described as examples. The seed layers 321A and 321B preferably contain a metal such as titanium, and may contain copper in combination with a metal. When the seed layers 321A and 321B in contact with the ceramic insulating layers 310A and 310B contain a metal, adhesion between the build-up wiring layers 320A and 320B and the ceramic insulating layers 310A and 310B can be improved. On the other hand, the electrolytically plated layers 322A and 322B preferably contain copper, and may contain only copper. When via holes 340A and 340B are formed in the ceramic insulating layers 310A and 310B, the build-up wiring layers 320A and 320B may be formed in the via holes 340A and 340B.

[0035] The surface coating layer 400 is an insulating layer provided on the build-up wiring layer 320B, which is the furthest from the core substrate 100 among the multiple build-up wiring layers 320A and 320B provided in the multilayer ceramic circuit substrate 1, and can protect the build-up wiring layer 320B. The surface coating layer 400 may be formed of a resin material such as solder resist, but is preferably formed of a ceramic material. Therefore, the surface coating layer 400 preferably contains a ceramic material, and more preferably contains only a ceramic material. There are no particular limitations on the thickness range of the surface coating layer 400, and it may, for example, be in the same range as the thickness of the ceramic insulating layers 310A and 310B.

[0036] (Overview of manufacturing method of multilayer ceramic circuit board 1 according to the first embodiment) The multilayer ceramic circuit board 1 according to this embodiment can be manufactured by a manufacturing method including: a step (I) of forming a core wiring layer 200 on a core substrate 100; and a step (II) of forming unit layers 300A and 300B on the core wiring layer 200.

[0037] Typically, one unit layer 300A or 300B including a combination of a ceramic insulating layer and a build-up wiring layer is formed by performing step (II) once. Therefore, a method for manufacturing a multilayer ceramic circuit substrate 1 including multiple unit layers 300A and 300B typically involves repeating step (II) two or more times. In this embodiment, an example is described in which step (II) is repeated twice: step (II) of forming a first unit layer 300A directly on the core wiring layer 200, and step (II) of forming a second unit layer 300B indirectly on the core wiring layer 200 via the first unit layer 300A. Unless otherwise specified, "directly" forming a layer on another layer means that there is no other layer between the two layers. Furthermore, "indirectly" forming a layer on another layer means that there is another layer between the two layers.

[0038] (Explanation of Step (I) According to First Embodiment) Step (I) includes step (I-1) of preparing a core substrate 100. The core substrate 100 may be prepared by manufacturing or may be purchased from the market.

[0039] Step (I) includes step (I-1) of preparing a core substrate 100, followed by step (I-2) of forming a core wiring layer 200 on the core substrate 100. The core wiring layer 200 is preferably formed by a plating method. When a plating method is employed, the plating method preferably includes forming a seed layer 210 on the core substrate 100 and forming an electrolytic plating layer 220 on the seed layer 210.

[0040] Step (I-2) may include a step of patterning the core wiring layer 200 from the viewpoint of forming the core wiring layer 200 having a desired pattern shape. "Patterning" refers to processing to have a desired pattern shape. From the viewpoint of smoothly forming a fine core wiring layer 200, the patterning is preferably performed by a semi-additive method. An example of a method for forming the core wiring layer 200 by the semi-additive method will be described below.

[0041] 2 is a schematic cross-sectional view illustrating a method for forming a core wiring layer 200 by a semi-additive method in the manufacturing method of a multilayer ceramic circuit board 1 according to the first embodiment of the present invention. When forming the core wiring layer 200 by a semi-additive method as in the example shown in FIG. 2, step (I-2) includes forming a seed layer 210 on the surface 110 of the core substrate 100. The seed layer 210 may be formed by electroless plating, but is preferably formed by sputtering from the viewpoint of forming a uniform seed layer 210. Sputtering can be performed using various sputtering devices, such as magnetron sputtering and mirror tron ​​sputtering.

[0042] The step (I-2) may include cleaning the surface on which the seed layer 210 is to be formed (specifically, the surface 110 of the core substrate 100) by reverse sputtering before forming the seed layer 210 by sputtering. Gases used for reverse sputtering include Ar gas, O ２ Gas, N ２ When the seed layer 210 is made of Cu or a Cu alloy, Ar gas is preferred; ２ gas; or Ar and O ２ When the seed layer 210 is made of Ti or a Ti alloy, a mixed gas of Ar gas; N ２ gas; or Ar and N ２ Furthermore, when the seed layer 210 is made of Cr or a Cr alloy (such as nichrome), a mixture of Ar gas and O ２ gas; or Ar and O ２ A mixed gas of the above is preferred.

[0043] 3 is a schematic cross-sectional view illustrating a method for forming a core wiring layer 200 by a semi-additive process in the method for manufacturing a multilayer ceramic circuit substrate 1 according to a first embodiment of the present invention. As shown in FIG. 3, step (I-2) according to this embodiment includes forming a seed layer 210 and then forming a mask layer 500 on the seed layer 210. The mask layer 500 is formed so as to expose a portion of the seed layer 210 in accordance with the pattern shape of the core wiring layer 200 to be formed. Typically, the mask layer 500 is formed to have a pattern shape that does not cover the portion where the core wiring layer 200 is to be formed, but can cover the other portions.

[0044] The mask layer 500 can be formed using, for example, a dry film (not shown). Specifically, the mask layer 500 can be formed by laminating a dry film on the seed layer 210, and then performing exposure and development using a photomask (not shown) corresponding to the pattern shape to be formed. The dry film can be a photosensitive dry film formed from a photoresist composition. Examples of photoresist compositions include novolac resin compositions and acrylic resin compositions. Commercially available dry films can be used, such as "RY-5115" manufactured by Resonac Corporation and "ALPHO 20A263" manufactured by Nikko Materials Co., Ltd.

[0045] 4 is a schematic cross-sectional view illustrating a method for forming a core wiring layer 200 by a semi-additive method in a manufacturing method for a multilayer ceramic circuit board 1 according to a first embodiment of the present invention. As shown in FIG. 4, step (I-2) according to this embodiment includes forming a mask layer 500 and then forming an electrolytic plating layer 220 on the seed layer 210 by electrolytic plating. Specifically, in step (I-2), the electrolytic plating layer 220 is formed by electrolytic plating on the portion of the seed layer 210 that is not covered by the mask layer 500.

[0046] In electrolytic plating, the electroplated layer 220 is typically formed in an electrolytic plating solution, which is a solution containing metal ions. For example, the seed layer 210 and an electrode (not shown) are placed in the plating solution, and a direct current is applied between the seed layer 210 and the electrode from a power source. The metal ions are reduced on the surface of the seed layer 210, causing the metal to deposit, forming the electroplated layer 220 containing the metal.

[0047] Typically, an aqueous solution of a metal salt is used as the electroplating solution. There are no limitations on the metal salt as long as it allows the formation of an electroplated layer. When copper is used as the metal, examples of the copper salt include copper sulfate such as copper sulfate pentahydrate, copper halides such as copper chloride, copper acetate, copper nitrate, copper tetrafluoroborate, copper alkylsulfonate, copper arylsulfonate, copper sulfamate, copper perchlorate, and copper gluconate, with copper sulfate being preferred. The concentration of the metal salt in the electroplating solution may be, for example, 50 g / L or more and 400 g / L or less. It is more preferable that the concentration of the metal salt in the electroplating solution be a saturated concentration. The electroplating solution may also contain additives such as acids such as sulfuric acid, methanesulfonic acid, ethanesulfonic acid, propanesulfonic acid, and hydrochloric acid; halide ion suppliers; brighteners; and surfactants.

[0048] FIG. 5 is a schematic cross-sectional view illustrating a method for forming a core wiring layer 200 by a semi-additive process in a manufacturing method for a multilayer ceramic circuit board 1 according to a first embodiment of the present invention. As shown in FIG. 5 , step (I-2) according to this embodiment includes removing the mask layer 500 after forming the electroplated layer 220. There are no limitations on the method for removing the mask layer 500. For example, a mask layer 500 formed using a dry film can be removed by contacting it with an appropriate stripping solution depending on the composition of the mask layer 500. In one example, the mask layer 500 can be removed using an alkaline stripping solution such as a sodium hydroxide solution.

[0049] 6 is a schematic cross-sectional view illustrating a method for forming a core wiring layer 200 by a semi-additive method in a manufacturing method for a multilayer ceramic circuit substrate 1 according to a first embodiment of the present invention. As shown in FIG. 6, step (I-2) according to this embodiment includes removing unnecessary portions of the seed layer 210 after removing the mask layer 500. Typically, the portions of the seed layer 210 that were covered by the mask layer 500 are removed. This allows for the core wiring layer 200 including the seed layer 210 and the electrolytic plating layer 220 to be obtained.

[0050] The unnecessary portions of the seed layer 210 can be removed using, for example, an etchant such as an etching solution. Specific examples of the etching solution include an etching solution containing hydrogen peroxide as a main component (hydrogen peroxide-based etching solution), an acidic etching solution, and an alkaline etching solution, with a hydrogen peroxide-based etching solution being preferred.

[0051] The hydrogen peroxide-based etching solution is preferably an etching solution containing hydrogen peroxide and an inorganic acid. Examples of inorganic acids include sulfuric acid, nitric acid, and phosphoric acid. Examples of commercially available hydrogen peroxide-based etching solutions include the SAC series of etching solutions manufactured by JCU Corporation. Examples of acidic etching solutions include an aqueous solution of ferric chloride, an aqueous solution containing sodium peroxodisulfate and sulfuric acid, and an etching solution mainly composed of nitric acid and sulfuric acid. Examples of commercially available acidic etching solutions include "NH-1865" manufactured by MEC and "Melstrip N-950" manufactured by Meltex. Examples of commercially available alkaline etching solutions include "CF-6000" manufactured by MEC and "E-Process-WL" manufactured by Meltex.

[0052] The removal of unnecessary portions of the seed layer 210 using an etching solution can be performed by, for example, immersing the seed layer 210 in the etching solution, spraying the etching solution onto the seed layer 210, etc. In one example, the temperature of the etching solution is preferably 5°C or higher, more preferably 10°C or higher, and even more preferably 15°C or higher, and is preferably 60°C or lower, more preferably 50°C or lower, and even more preferably 40°C or lower.

[0053] Step (I-2) may optionally include a step of performing an annealing treatment after the formation of the core wiring layer 200. In this annealing treatment, the core substrate 100, the seed layer 210, and the electrolytic plating layer 220 are heated. Typically, the entire intermediate product including the core substrate 100, the seed layer 210, and the electrolytic plating layer 220 is heated. The heating temperature is preferably 120°C or higher, more preferably 150°C or higher, and even more preferably 180°C or higher, and preferably 250°C or lower, more preferably 230°C or lower, and even more preferably 210°C or lower. The heating time is preferably 10 minutes or longer, more preferably 20 minutes or longer, and even more preferably 30 minutes or longer, and preferably 120 minutes or shorter, more preferably 100 minutes or shorter, and even more preferably 80 minutes or shorter. The annealing treatment can improve the adhesion between the core substrate 100 and the core wiring layer 200.

[0054] (Explanation of Step (II) According to First Embodiment) The method for manufacturing a multilayer ceramic circuit substrate 1 according to this embodiment includes, after step (I), step (II) of forming unit layers 300A and 300B on the core wiring layer 200. Each step (II) includes, in this order: step (II-1) of forming a ceramic insulating layer by aerosol deposition; step (II-2) of planarizing the surface of the ceramic insulating layer formed by aerosol deposition, opposite to the core substrate; and step (II-4) of forming a build-up wiring layer on the planarized surface of the ceramic insulating layer. Furthermore, step (II) may further include step (II-3) of forming via holes in the ceramic insulating layer between steps (II-2) and (II-4).

[0055] Step (II-1) includes forming a ceramic insulating layer by aerosol deposition. Aerosol deposition is a technique in which raw material powder aerosolized by gas is sprayed onto a target component to form a coating on the surface of the target component. This aerosol deposition generally utilizes room-temperature impact consolidation to form a coating on the surface of the target component. Specifically, it is believed that the kinetic energy of raw material powder particles accelerated by gas is converted into localized thermal energy upon impact with the surface of the target component, forming bonds between the component and the particles and between the particles themselves, thereby achieving the formation of a coating. However, the mechanism of the aerosol deposition method described above does not limit the technical scope of the present invention.

[0056] In this embodiment, the ceramic insulating layer is formed by aerosol deposition using ceramic powder as raw material powder. An example of a method for forming a ceramic insulating layer by aerosol deposition will be described below with reference to the drawings.

[0057] Fig. 7 is a schematic diagram showing an example of a ceramic insulating layer forming apparatus 10. Fig. 8 is an enlarged cross-sectional view showing an aerosol generator 40 included in the forming apparatus 10. As shown in Fig. 7, the ceramic insulating layer forming apparatus 10 according to the example includes a chamber 20 capable of accommodating a target member, an exhaust pump 30 capable of exhausting air from the chamber 20, the aerosol generator 40 provided outside the chamber 20, and a gas cylinder 50 as a supply source of a winding gas and a carrier gas. Here, a core substrate 100 having a core wiring layer 200 formed thereon will be described as an example of the target member.

[0058] The chamber 20 is provided with a stage 21 on which a target member can be placed and a nozzle 22 capable of spraying aerosol gas onto the target member placed on the stage 21. The stage 21 is typically provided so that its position can be adjusted so that the relative positional relationship between the target member placed on the stage 21 and the nozzle 22 can be adjusted. The nozzle 22 is also connected to the aerosol generator 40 via a carrier pipe 51 so that the aerosol gas can be supplied from the aerosol generator 40. The nozzle 22 is typically provided facing the stage 21. For example, the nozzle 22 preferably has a horizontal diameter of 1.0 mm to 200 mm and a vertical diameter of 0.1 mm to 2.0 mm, more preferably a horizontal diameter of 50 mm to 100 mm and a vertical diameter of 0.1 mm to 0.5 mm. If necessary, a mask (not shown) may be provided between the stage 21 and the nozzle 22. When spraying aerosol gas from the nozzle 22 onto the target member on the stage 21 through the mask, the aerosol can be selectively sprayed onto an area on the target member according to the shape of the mask.

[0059] 8, ceramic powder 41 is stored as raw material powder inside an aerosol generator 40. Also connected to the aerosol generator 40 are a carrier pipe 52 that can introduce a winding gas from a gas cylinder 50 into the aerosol generator 40, and a carrier pipe 53 that can introduce a carrier gas from the gas cylinder 50 into the aerosol generator 40.

[0060] The carrier pipe 52 is inserted into the ceramic powder 41 accumulated in the aerosol generator 40 so that the ceramic powder 41 can be stirred up by the stirring gas introduced into the aerosol generator 40 through the carrier pipe 52. In this embodiment, an example will be described in which a diffusion member 54 capable of diffusing the stirring gas introduced through the carrier pipe 52 is attached to the tip of the carrier pipe 52. The aerosol generator 40 is provided so that the stirring gas can stir up the ceramic powder 41 to generate an aerosol gas.

[0061] The carrier pipe 53 is connected to the upper part of the ceramic powder 41 deposited in the aerosol generator 40 so that the aerosol gas can be carried by the carrier gas introduced into the aerosol generator 40 through the carrier pipe 53. In this embodiment, an example in which the carrier pipe 53 is connected to the upper surface of the aerosol generator 40 will be described.

[0062] The aerosol generator 40 is connected to the transfer pipe 51, which is connected to the nozzle 22. The transfer pipe 51 is connected to an upper portion of the ceramic powder 41 deposited in the aerosol generator 40 so as to allow the aerosol gas generated in the aerosol generator 40 to be discharged. The flow rate of the aerosol gas discharged through the transfer pipe 51 is generally controlled by two systems: a winding gas flow rate and a carrier gas flow rate. In this case, the transfer pipes 51, 52, and 53 are preferably disposed in the aerosol generator 40 in a positional relationship that minimizes the interference with the flow rate of the aerosol gas. Specifically, the transfer pipe 52 for the winding gas and the transfer pipe 53 for the carrier gas are preferably disposed away from the transfer pipe 51 connected to the nozzle 22 so as not to interfere with the flow rate of the generated aerosol gas.

[0063] Particles of the ceramic material to be contained in the ceramic insulating layer can be used as the ceramic powder 41. The ceramic powder 41 may be heat-treated in advance to remove residual moisture and impurities.

[0064] The average particle size of the ceramic powder 41 particles is preferably equal to or smaller than the spacing between the core wiring layers 200, and more preferably equal to or smaller than the minimum spacing. Specifically, the average particle size of the ceramic powder 41 particles is preferably equal to or smaller than 1.5 μm, more preferably equal to or smaller than 1.0 μm. In particular, when the minimum pitch of the core wiring layers 200 is equal to or smaller than 4 μm, the average particle size of the ceramic powder 41 is preferably within this range. In this case, the ceramic material can be stably filled between the core wiring layers 200, thereby achieving a highly reliable multilayer ceramic circuit substrate 1 having core wiring layers 200 with a fine pattern shape. While there is no particular lower limit for the average particle size of the ceramic powder 41 particles, a particle size greater than 0.50 μm is preferred from the viewpoint of forming a ceramic insulating layer with excellent volumetric electrical resistivity. The average particle size of the ceramic powder 41 particles represents the volume-based median diameter. Specifically, the average particle size can be determined as a median diameter from a particle size distribution measured on a volume basis using a particle size distribution measuring device (DT1200 manufactured by Disperion Technology).

[0065] The particle shape of the ceramic powder 41 is not particularly limited, but a flat shape is preferred. When the ceramic powder 41 particles have a flat shape, the aerosolized ceramic powder 41 particles are more likely to deposit on the surface of the target component, thereby accelerating the formation rate of the ceramic insulating layer. Specifically, the ceramic powder 41 particles preferably have a flat shape with an aspect ratio greater than 1.3 and less than 100. The aspect ratio of the ceramic powder 41 particles is expressed as "D50 / t" using the particle thickness t and the average particle diameter D50 of the particles. The average particle diameter D50 of the ceramic powder 41 particles can be measured using the method described above. The particle thickness of the ceramic powder 41 can also be measured by embedding the powder in acrylic resin, polishing the sample, observing it with a scanning electron microscope (SEM), and analyzing the cross-sectional image of the powder particles. The aspect ratio is preferably calculated from the average value measured for 30 randomly selected powder particles.

[0066] In the method for forming a ceramic insulating layer using the forming device 10, a winding gas and a carrier gas supplied from a gas cylinder 50 are introduced into an aerosol generator 40 to generate an aerosol gas, which is then sprayed from a nozzle 22 onto a target component to form a ceramic insulating layer.

[0067] 7, a core substrate 100 having a core wiring layer 200 formed thereon is placed as a target member on a stage 21 in a chamber 20. At this time, the core substrate 100 is set so that the core wiring layer 200 faces a nozzle 22 so that the aerosol gas can be sprayed onto the core wiring layer 200. Then, the chamber 20 is evacuated by an exhaust pump 30 as necessary to adjust the pressure within the chamber 20. The pressure within the chamber 20 may be set appropriately within a range that allows the formation of a ceramic insulating layer, and may be, for example, 0.01 kPa to 10 kPa.

[0068] Thereafter, a stirring gas is introduced from the gas cylinder 50 through the carrier pipe 52 into the aerosol generator 40. Examples of the stirring gas include argon gas, helium gas, and nitrogen gas. The ceramic powder 41 is stirred up by the stirring gas, and an aerosol gas is generated in the aerosol generator 40. The flow rate of the stirring gas may be appropriately set within a range in which a ceramic insulating layer can be formed, and is preferably 20 SLM to 120 SLM, and more preferably 40 SLM to 60 SLM. Unless otherwise specified, "SLM" means "Standard Litter per Minute" and represents the flow rate (liters) at 1 atm and 0°C.

[0069] If necessary, a carrier gas is introduced from a gas cylinder 50 into the aerosol generator 40 through a carrier pipe 53. The carrier gas can usually be the same as the winding gas. The winding gas and the carrier gas send the aerosol gas generated in the aerosol generator 40 to the nozzle 22 through a carrier pipe 51. The flow rate of the carrier gas may be appropriately set within a range that allows the formation of a ceramic insulating layer, and is preferably 0 SLM to 30 SLM, and more preferably 20 SLM to 30 SLM. The ratio of the carrier gas flow rate to the winding gas flow rate (carrier gas flow rate:winding gas flow rate) is preferably 1:1.5 to 1:7, and more preferably 1:1.5 to 1:5.5.

[0070] The aerosol gas sent to the nozzle 22 through the transfer pipe 51 is sprayed from the nozzle 22 onto the target member on the stage 21. The ceramic powder contained in the sprayed aerosol gas collides with the target member to form a ceramic insulating layer. The formed ceramic insulating layer may be a dense coating in which particles of the ceramic powder 41 are bonded together.

[0071] The aerosol gas may be sprayed by causing the nozzle 22 to scan the target member. For example, the nozzle 22 may be fixed and the stage 21 may be moved to move the nozzle 22 relative to the target member, causing the nozzle 22 to scan the target member. Alternatively, for example, the nozzle 22 may be moved while the stage 21 is fixed, causing the nozzle 22 to scan the target member. In this case, the scanning speed of the nozzle 22 is preferably 200 mm / min to 400 mm / min, and more preferably 250 mm / min to 350 mm / min. The nozzle 22 may be scanned only once, or two or more times.

[0072] 9 is a schematic cross-sectional view illustrating step (II-1) in the manufacturing method of the multilayer ceramic circuit board 1 according to the first embodiment of the present invention. As shown in FIG. 9 , by performing the aerosol deposition method described above, a ceramic insulating layer 310A can be formed on the core substrate 100 and the core wiring layer 200, which are the target components. Specifically, the ceramic insulating layer 310A is formed on the core wiring layer 200 in the portion where the core wiring layer 200 is formed. Furthermore, if the surface 110 of the core substrate 100 includes an exposed portion where the core wiring layer 200 is not formed, the ceramic insulating layer 310A is formed on the core substrate 100 in the exposed portion.

[0073] In step (II-1), the ceramic insulating layer 310A is formed so as to bury the core wiring layer 200, which serves as the wiring layer directly below the ceramic insulating layer 310A. Therefore, after step (II-1) and before step (II-2), the ceramic insulating layer 310A is typically thicker than the core wiring layer 200. Therefore, the ceramic insulating layer 310A can be formed higher than the core wiring layer 200, so that the ceramic insulating layer 310A can cover the core wiring layer 200 even after the ceramic insulating layer 310A is polished in step (II-2), which will be described later. Unless otherwise specified, when an element formed on the core substrate 100 is "high," it means that the surface of the element opposite the core substrate 100 is far from the core substrate 100. Furthermore, when an element formed on the core substrate 100 is "low," it means that the surface of the element opposite the core substrate 100 is close to the core substrate 100.

[0074] Typically, the surface 330A of the ceramic insulating layer 310A formed in step (II-1) has irregularities. Specifically, the surface 330A generally has irregularities that reflect the shapes of the surface 110 of the core substrate 100 and the core wiring layer 200. Furthermore, since the aerosol deposition method forms a coating by the collision of ceramic powder, minute irregularities are likely to be formed on the surface 330A. Therefore, step (II) includes step (II-2) of planarizing the surface 330A after step (II-1).

[0075] 10 is a schematic cross-sectional view illustrating step (II-2) in the method for manufacturing multilayer ceramic circuit board 1 according to the first embodiment of the present invention. As shown in FIG. 10, step (II) includes, after step (II-1), step (II-2) of flattening surface 330A of ceramic insulating layer 310A formed by aerosol deposition, the surface being opposite core substrate 100.

[0076] The planarization is usually performed by polishing the surface 330A of the ceramic insulating layer 310A. Examples of methods for polishing the ceramic insulating layer 310A include chemical mechanical polishing (CMP), buff polishing, and belt polishing. Among these, CMP is preferred.

[0077] In CMP, for example, a polishing process is performed by supplying a polishing liquid between a flexible polishing pad and the surface 330A of the ceramic insulating layer 310A, while rotating the polishing pad and sliding it relative to the ceramic insulating layer 310A. An alkaline slurry is preferably used as the polishing liquid. The pH of the slurry is preferably 8 or more and 10 or less. Examples of particles contained in the slurry include alumina, colloidal silica, ceria, and zirconia. The average particle size (average primary particle size) of the particles in the slurry is preferably 0.1 μm or less. During CMP polishing, a pressure of 3 kPa to 20 kPa is preferably applied to the surface 330A of the ceramic insulating layer 310A in order to achieve uniform polishing.

[0078] By polishing, the surface 330A of the ceramic insulating layer 310A can be made smooth. Therefore, the surface 330A of the ceramic insulating layer 310A can be formed as a flat surface with small surface roughness. The surface roughness of the surface 330A of the ceramic insulating layer 310A after polishing is as described above. Because the surface 330A of the ceramic insulating layer 310A becomes a smooth flat surface with such small surface roughness, a fine build-up wiring layer 320A can be formed on the surface 330A.

[0079] Typically, polishing reduces the thickness of the ceramic insulating layer 310A. Therefore, the ceramic insulating layer 310A after step (II-2) is thinner than the ceramic insulating layer 310A before step (II-2). In this embodiment, polishing in step (II-2) is performed so that the core wiring layer 200, which serves as the wiring layer directly below the ceramic insulating layer 310A, is not exposed even after the ceramic insulating layer 310A has been thinned. Therefore, in the example shown in this embodiment, the ceramic insulating layer 310A is higher than the core wiring layer 200 even after polishing. In this case, the core wiring layer 200 can be covered and insulated by the ceramic insulating layer 310A even after polishing. Therefore, step (II) may include step (II-3) of forming via holes in the ceramic insulating layer 310A for interlayer connection, as necessary.

[0080] FIG. 11 is a schematic cross-sectional view illustrating step (II-3) in the manufacturing method of the multilayer ceramic circuit substrate 1 according to the first embodiment of the present invention. As shown in FIG. 11 , step (II) may include step (II-3) of forming a via hole 340A in the ceramic insulating layer 310A after step (II-2) and before step (II-4). The via hole 340A is generally formed for interlayer connection between the core wiring layer 200 located directly below the ceramic insulating layer 310A and the build-up wiring layer 320A (see FIG. 1 ) located directly above the ceramic insulating layer 310A. Therefore, the via hole 340A is formed so that the core wiring layer 200 is exposed at the bottom of the via hole 340A. Examples of methods for forming the via hole 340A include drilling, laser processing, and plasma processing, with laser processing being preferred. Examples of lasers that can be used include UV lasers and excimer lasers. As a specific example, the via hole 340A may be formed using a UV-YAG laser processing machine ("LU-2L212 / M50L" manufactured by Via Mechanics Co., Ltd.).

[0081] 12 to 16 are schematic cross-sectional views illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit substrate 1 according to the first embodiment of the present invention. Step (II) includes step (II-4), which follows step (II-2), of forming a build-up wiring layer 320A on the planarized surface 330A of the ceramic insulating layer 310A. If via holes 340A are formed in the ceramic insulating layer 310A, the build-up wiring layer 320A is formed not only on the surface 330A but also in the via holes 340A in step (II-4).

[0082] The build-up wiring layer 320A may be formed by the same method as the core wiring layer 200. In particular, the build-up wiring layer 320A is preferably formed by a plating method. The build-up wiring layer 320A may also be formed by a semi-additive method. When the semi-additive method is employed, step (II-4) typically includes, in this order, forming a seed layer 321A on the surface 330A of the ceramic insulating layer 310A as shown in FIG. 12 , forming a mask layer 600 on the seed layer 321A as shown in FIG. 13 , forming an electroplated layer 322A on the seed layer 321A as shown in FIG. 14 , removing the mask layer 600 as shown in FIG. 15 , and removing unnecessary portions of the seed layer 321A as shown in FIG. 16 . Furthermore, step (II-4) may include performing an annealing treatment after the formation of the electroplated layer 322A. The formation of the seed layer 321A, the formation of the mask layer 600, the electrolytic plating, the removal of the mask layer 600, the removal of unnecessary portions of the seed layer 321A, and the annealing treatment in step (II-4) may be performed in the same manner as the formation method of the core wiring layer 200.

[0083] When the build-up wiring layer 320A is formed by the same method as the core wiring layer 200, the build-up wiring layer 320A can have the same advantages as the core wiring layer 200. For example, when an annealing treatment is performed, the adhesion between the ceramic insulating layer 310A and the build-up wiring layer 320A can be improved.

[0084] In this embodiment, the step (II-4) can provide a build-up wiring layer 320A including a seed layer 321A and an electrolytic plating layer 322A. The first unit layer 300A can be formed by combining the build-up wiring layer 320A thus formed with a ceramic insulating layer 310A. Furthermore, if a via hole 340A is formed in the ceramic insulating layer 310A, an interlayer connection between the core wiring layer 200 and the build-up wiring layer 320A can be achieved through the via hole 340A.

[0085] 17 is a schematic cross-sectional view illustrating the second step (II) in the method for manufacturing a multilayer ceramic circuit substrate 1 according to the first embodiment of the present invention. In the method for manufacturing a multilayer ceramic circuit substrate 1 according to this embodiment, the above-described step (II) is repeated two or more times. Thus, in the method for manufacturing a multilayer ceramic circuit substrate 1 according to this embodiment, the first step (II) is performed as described above to form a first unit layer 300A including a ceramic insulating layer 310A and a build-up wiring layer 320A, and then the second step (II) is performed to form a second unit layer 300B including a ceramic insulating layer 310B and a build-up wiring layer 320B, as shown in FIG. 17 . The second unit layer 300B can be formed using the same method as the method for forming the first unit layer 300A.

[0086] The second unit layer 300B offers the same advantages as the first unit layer 300A. For example, when a ceramic insulating layer 310B is formed directly on the build-up wiring layer 320A by aerosol deposition using ceramic particles having an average particle size equal to or smaller than the spacing between the build-up wiring layers 320A, the ceramic material can be stably filled between the build-up wiring layers 320A even if the build-up wiring layers 320A are fine. Therefore, a highly reliable multilayer ceramic circuit substrate 1 can be obtained. Furthermore, for example, the ceramic insulating layer 310B is formed on the ceramic insulating layer 310A and the build-up wiring layer 320A by aerosol deposition. In this case, the ceramic insulating layer 310B is typically formed thicker than the build-up wiring layer 320A, which serves as the wiring layer directly below the ceramic insulating layer 310B. Therefore, before the surface 330B of the ceramic insulating layer 310B is planarized, the ceramic insulating layer 310B is formed higher than the build-up wiring layer 320A and can cover the build-up wiring layer 320A. Immediately after the formation of the ceramic insulating layer 310B, the surface 330B of the ceramic insulating layer 310B may have irregularities, but because the ceramic insulating layer 310B is formed higher than the build-up wiring layer 320A, the surface 330B of the ceramic insulating layer 310B can be smoothed by planarization. Therefore, a fine build-up wiring layer 320B can be formed on the planarized surface 330B.

[0087] (Explanation of Optional Steps According to the First Embodiment) The manufacturing method of the multilayer ceramic circuit board 1 according to this embodiment may include an optional step in addition to the steps described above. For example, the manufacturing method according to this embodiment may include a step of forming a surface coating layer 400. There are no limitations on the method of forming the surface coating layer 400. For example, when the surface coating layer 400 is formed from a resin material such as solder resist, the surface coating layer 400 may be formed by a coating method, a lamination method, or the like.

[0088] The surface coating layer 400 is preferably formed by aerosol deposition using a ceramic material. The surface coating layer 400 may be formed by the same method as the method for forming the ceramic insulating layers 310A and 310B by aerosol deposition. After the surface coating layer 400 is formed, the surface of the surface coating layer 400 may be polished and flattened, if necessary. When the surface coating layer 400 is formed in this manner, a multilayer ceramic circuit substrate 1 including the surface coating layer 400 can be obtained, as shown in FIG. 1.

[0089] (Major Advantages of the First Embodiment) The manufacturing method according to this embodiment makes it possible to manufacture a multilayer ceramic circuit substrate 1 including copper-containing wiring layers (specifically, the core wiring layer 200, the build-up wiring layer 320A, and the build-up wiring layer 320B). The manufacturing method does not require high-temperature processing. For example, forming the ceramic insulating layers 310A and 310B using the aerosol deposition method does not require high temperatures like those used in the firing process of green sheets, and can be carried out at low temperatures. Furthermore, forming the wiring layers using a plating method does not require high temperatures like those used in the firing process of conductive pastes, and can also be carried out at low temperatures. Therefore, the manufacturing method according to this embodiment makes it possible to suppress oxidation of metals such as copper contained in the wiring layers. This makes it possible to increase the conductivity of the wiring layers.

[0090] If the only goal is to prevent metal oxidation, it is conceivable to perform firing in an inert or reducing gas atmosphere in a manufacturing method using a green sheet. However, using an inert or reducing gas atmosphere can increase costs and reduce safety, making it less suitable for mass production. In contrast, aerosol deposition and plating methods do not require an inert or reducing gas atmosphere, making them more suitable for mass production.

[0091] Furthermore, compared to methods using a conductive paste printed on a green sheet, plating methods can smoothly form fine wiring layers with excellent conductivity. For example, when using a conductive paste, it is difficult to narrow the wiring width of the wiring layer, making it difficult to reduce the minimum line / space ratio, and therefore miniaturization is difficult. Furthermore, when using a conductive paste, it is difficult to increase the thickness of the wiring layer, and the cross-sectional shape of the wiring layer is prone to curvature. Therefore, it is difficult to increase the cross-sectional area of ​​a wiring layer formed using a conductive paste, making it difficult to reduce resistance. In contrast, plating methods can narrow the wiring width of the wiring layer, thereby reducing the minimum line / space ratio and achieving finer wiring layers. Furthermore, plating methods can increase the thickness of the wiring layer and make the cross-sectional shape of the wiring layer rectangular. Therefore, plating methods can increase the cross-sectional area of ​​the wiring layer. Furthermore, plating methods can use copper, a metal with excellent conductivity. Therefore, resistance can be reduced and excellent conductivity can be achieved.

[0092] Generally, the surface of a coating formed by aerosol deposition is prone to unevenness. Therefore, if an insulating layer is simply formed by aerosol deposition, it is difficult to form a fine wiring layer on the insulating layer. In contrast, in the manufacturing method according to the present embodiment, ceramic insulating layers 310A and 310B are formed by aerosol deposition, and then their surfaces 330A and 330B are planarized, and then build-up wiring layers 320A and 320B are formed on the surfaces 330A and 330B. In particular, when planarization is performed using CMP, the surfaces 330A and 330B can be made highly smooth. Therefore, the build-up wiring layers 320A and 320B can be made finer, which contributes to higher density wiring layers.

[0093] The insulating layers (specifically, ceramic insulating layers 310A and 310B) of the manufactured multilayer ceramic circuit substrate 1 can be formed from ceramic materials rather than organic materials. Therefore, the multilayer ceramic circuit substrate 1 can be formed entirely or mostly from inorganic materials. For example, portions other than the surface coating layer 400 can be formed from inorganic materials, or all portions, including the surface coating layer 400, can be formed from inorganic materials. Therefore, the multilayer ceramic circuit substrate 1 can have high mechanical strength and heat dissipation properties. Furthermore, ceramic materials generally have superior dielectric properties compared to organic materials such as resins. Therefore, the multilayer ceramic circuit substrate 1 can generally effectively suppress electrical signal loss.

[0094] Unlike components, the multilayer ceramic circuit substrate 1 does not perform a specific function; it is a substrate that can only perform its function when components are mounted on it. Therefore, it is required to form complex wiring layers inside the substrate, assuming that the components will be mounted on it. Furthermore, in response to recent demands for higher density wiring layers, the wiring layers must be formed with high density. The multilayer ceramic circuit substrate 1 according to this embodiment includes multiple wiring layers, such as a core wiring layer 200, a build-up wiring layer 320A, and a build-up wiring layer 320B, stacked in the thickness direction. Furthermore, since these wiring layers can be miniaturized, it is possible to form complex and high-density wiring layers.

[0095] Second Embodiment In the first embodiment described above, an example was shown in which via holes were used to achieve interlayer connection between wiring layers in the thickness direction, but the method of interlayer connection is not limited to via holes. For example, pillars may be used to achieve interlayer connection. Below, an embodiment of a multilayer ceramic circuit board in which interlayer connection is achieved using pillars in this manner will be described. In the second embodiment described below, the same components as in the first embodiment will be described with the same reference numerals as in the first embodiment.

[0096] (Overview of Multilayer Ceramic Circuit Substrate 2 According to Second Embodiment) FIG. 18 is a cross-sectional view schematically illustrating a multilayer ceramic circuit substrate 2 according to a second embodiment of the present invention. As shown in FIG. 18, the multilayer ceramic circuit substrate 2 according to the second embodiment of the present invention includes a core wiring layer 700 including a relatively tall pillar portion 750 and a relatively short wiring portion 760, instead of the core wiring layer 200. The multilayer ceramic circuit substrate 2 also includes a first unit layer 800A, instead of the first unit layer 300A. The first unit layer 800A is provided in the same manner as the first unit layer 300A described in the first embodiment, except that the first unit layer 800A includes a build-up wiring layer 820A including a relatively tall pillar portion 850A and a relatively low wiring portion 860A, instead of the build-up wiring layer 320A.

[0097] In the multilayer ceramic circuit substrate 2 according to this embodiment, the pillar portions 750 of the core wiring layer 700 establish interlayer connection between the core wiring layer 700 and the build-up wiring layer 820A. Furthermore, the pillar portions 850A of the build-up wiring layer 820A establish interlayer connection between the build-up wiring layer 820A and the build-up wiring layer 320B. Except for the above, the multilayer ceramic circuit substrate 2 according to the second embodiment has the same configuration as the multilayer ceramic circuit substrate 1 according to the first embodiment, and can obtain the same advantages as the multilayer ceramic circuit substrate 1 according to the first embodiment.

[0098] (Outline of Manufacturing Method of Multilayer Ceramic Circuit Board 2 According to Second Embodiment) The multilayer ceramic circuit board 2 according to this embodiment can be manufactured by a manufacturing method including: a step (I) of forming a core wiring layer 700 on a core substrate 100; and a step (II) of forming unit layers 800A and 300B on the core wiring layer 700. This manufacturing method may be the same as the manufacturing method according to the first embodiment, except that it includes forming pillar portions 750 and 850A in the core wiring layer 700 and the build-up wiring layer 820A instead of forming via holes. Below, an example will be described in which two steps (II) are repeated: a step (II) of forming a first unit layer 800A directly on the core wiring layer 700, and a step (II) of forming a second unit layer 300B indirectly on the core wiring layer 700 via the first unit layer 800A.

[0099] (Explanation of Step (I) According to Second Embodiment) Step (I) includes step (I-1) of preparing the core substrate 100. In the second embodiment, step (I-1) can be performed in the same manner as in the first embodiment.

[0100] The step (I) includes a step (I-1) of preparing a core substrate 100, followed by a step (I-2) of forming a core wiring layer 700 on the core substrate 100. In this embodiment, as in the first embodiment, an example of a method of forming a core wiring layer 700 by a semi-additive method will be described.

[0101] 19 to 25 are schematic cross-sectional views illustrating a method for forming a core wiring layer 700 by a semi-additive method in a manufacturing method for a multilayer ceramic circuit board 2 according to a second embodiment of the present invention. When forming the core wiring layer 700 by a semi-additive method, step (I-2) includes, in this order, forming a seed layer 710 on the surface 110 of the core substrate 100 as in the example shown in FIG. 19, forming a mask layer 510 on the seed layer 710 as shown in FIG. 20, and forming an electrolytic plating layer 720 on the seed layer 710 by electrolytic plating as shown in FIG. 21. The formation of the seed layer 710, the formation of the mask layer 510, and the electrolytic plating may be performed by the same method as in the first embodiment.

[0102] As shown in FIG. 21 , electrolytic plating typically forms an electrolytic plating layer 720 of a certain thickness. Therefore, after the electrolytic plating, further electrolytic plating is performed to form pillar portions 750. Typically, as shown in FIG. 22 , a mask layer 520 is formed to cover the electrolytic plating layer 720 except for a portion 770 on the electrolytic plating layer 720 where the pillar portions 750 are to be formed. At this time, if necessary, the mask layer 510 may be removed before forming the mask layer 520. After forming the mask layer 520, electrolytic plating is performed to increase the thickness of the electrolytic plating layer 720 in the portion 770, as shown in FIG. 23 . Thereafter, the mask layer 520 is removed as shown in FIG. 24 , and unnecessary portions of the seed layer 710 are further removed as shown in FIG. 25 , thereby forming a core wiring layer 700 including pillar portions 750 and wiring portions 760. The formation of the mask layer 520, electrolytic plating, removal of the mask layers 510 and 520, and removal of unnecessary portions of the seed layer 710 may be performed in the same manner as in the first embodiment. The pillar portion 750 and the wiring portion 760 of the formed core wiring layer 700 each include a seed layer 710 and an electrolytic plating layer 720. The pillar portion 750 is formed to be relatively thick, and the wiring portion 760 is formed to be relatively thin. If necessary, an annealing treatment may be performed after the formation of the core wiring layer 700.

[0103] (Explanation of Step (II) According to the Second Embodiment) The method for manufacturing a multilayer ceramic circuit substrate 2 according to this embodiment includes, after step (I), step (II) of forming a unit layer 800A on the core wiring layer 700. This step (II) may be performed in the same manner as step (II) according to the first embodiment, except that step (II-2) includes polishing the ceramic insulating layer 310A so that the pillar portions 750 are exposed and the wiring portions 760 are not exposed.

[0104] The details are as follows. Fig. 26 is a schematic cross-sectional view illustrating step (II-1) in the method for manufacturing a multilayer ceramic circuit board according to the second embodiment of the present invention. As shown in Fig. 26, step (II) according to this embodiment includes step (II-1) of forming a ceramic insulating layer 310A by aerosol deposition. Step (II-1) may be performed in the same manner as in the first embodiment.

[0105] FIG. 27 is a schematic cross-sectional view illustrating step (II-2) in the manufacturing method of a multilayer ceramic circuit board 2 according to a second embodiment of the present invention. As shown in FIG. 27, step (II) includes, after step (II-1), step (II-2) of planarizing the surface 330A of the ceramic insulating layer 310A formed by aerosol deposition, opposite the core substrate 100. As in the first embodiment, step (II-2) typically involves polishing the surface 330A of the ceramic insulating layer 310A. This polishing is performed so that the pillar portions 750 are exposed while the wiring portions 760 are not. The specific polishing method may be the same as that in the first embodiment. Furthermore, the pillar portions 750 of the core wiring layer 700 may be polished simultaneously when polishing the ceramic insulating layer 310A. Typically, this polishing forms a single plane including the surface 330A of the ceramic insulating layer 310A and the surface 780 of the pillar portions 750 opposite the core substrate 100, and this plane can have low surface roughness.

[0106] 28 to 34 are schematic cross-sectional views illustrating step (II-4) in the method for manufacturing a multilayer ceramic circuit substrate 2 according to the second embodiment of the present invention. Step (II) includes, after step (II-2), step (II-4) of forming a build-up wiring layer 820A on the planarized surface 330A of the ceramic insulating layer 310A.

[0107] The build-up wiring layer 820A may be formed by the same method as the formation of the core wiring layer 700. Therefore, for example, the build-up wiring layer 820A can be formed by a method including, in this order, forming a seed layer 821A on the surface 330A of the ceramic insulating layer 310A as shown in FIG. 28 , forming a mask layer 610 on the seed layer 821A as shown in FIG. 29 , forming an electrolytically plated layer 822A on the seed layer 821A as shown in FIG. 30 , forming a mask layer 620 that covers all but a portion 870A on the electrolytically plated layer 822A where the pillar portion 850A will be formed as shown in FIG. 31 , performing electrolytic plating to increase the thickness of the electrolytically plated layer 822A in the portion 870A as shown in FIG. 32 , removing the mask layer 620 as shown in FIG. 33 , and removing unnecessary portions of the seed layer 821A as shown in FIG. 34 . Furthermore, step (II-4) may include a step of performing an annealing treatment after the formation of the electrolytically plated layer 822A. The formation of the seed layer 821A, the formation of the mask layers 610 and 620, the electrolytic plating, the removal of the mask layers 610 and 620, the removal of unnecessary portions of the seed layer 821A, and the annealing treatment may be performed in the same manner as the formation of the core wiring layer 700. This step (II-4) results in a build-up wiring layer 820A including a relatively thick pillar portion 850A and a relatively thin wiring portion 860A. The pillar portion 850A and the wiring portion 860A of the formed build-up wiring layer 820A both include the seed layer 821A and the electrolytic plating layer 822A. The first unit layer 800A can then be formed by combining the thus formed build-up wiring layer 820A with the ceramic insulating layer 310A. Typically, the build-up wiring layer 820A can be formed not only on the surface 330A of the ceramic insulating layer 310A but also on the surface 780 of the pillar portion 750. Therefore, the build-up wiring layer 820A can be in contact with and electrically connected to the pillar portion 750 of the core wiring layer 700, thereby achieving interlayer connection between the core wiring layer 700 and the build-up wiring layer 820A.

[0108] FIG. 35 is a schematic cross-sectional view illustrating the second step (II) in the method for manufacturing a multilayer ceramic circuit substrate according to a second embodiment of the present invention. In the method for manufacturing a multilayer ceramic circuit substrate 2 according to this embodiment, the above-described step (II) is repeated two or more times. Thus, in the method for manufacturing a multilayer ceramic circuit substrate 2 according to this embodiment, the first step (II) is performed as described above to form a first unit layer 800A including a ceramic insulating layer 310A and a build-up wiring layer 820A, and then the second step (II) is performed to form a second unit layer 300B including a ceramic insulating layer 310B and a build-up wiring layer 320B, as shown in FIG. 35 . While this embodiment shows an example in which the second unit layer 300B is formed including a build-up wiring layer 320B having a uniform thickness, a second unit layer may also be formed that includes a build-up wiring layer including a pillar portion and a wiring portion, as with the first unit layer 800A.

[0109] In the second step (II) of forming the second unit layer 300B, polishing of the ceramic insulating layer 310B can be performed in step (II-2), similar to the first step (II) of forming the first unit layer 800A. By polishing the ceramic insulating layer 310B, a single plane including the surface 330B of the ceramic insulating layer 310B and the surface 880A of the pillar portion 850A opposite the core substrate 100 is formed, and this plane can have low surface roughness. The build-up wiring layer 320B is then formed on this plane. At this time, the build-up wiring layer 320B is in contact with and electrically conductive to the pillar portion 850A of the build-up wiring layer 820A, thereby achieving interlayer connection between the build-up wiring layer 820A and the build-up wiring layer 320B.

[0110] (Explanation of Optional Steps According to the Second Embodiment) The method for manufacturing the multilayer ceramic circuit substrate 2 according to this embodiment may further include optional steps in combination with the steps described above. For example, the manufacturing method according to this embodiment may include the step of forming the surface coating layer 400, as in the first embodiment.

[0111] (Major Advantages of Second Embodiment) According to the multilayer ceramic circuit board 2 and the manufacturing method thereof of this embodiment, it is possible to obtain the same advantages as those described in the first embodiment.

[0112] <Third Embodiment> In the first and second embodiments described above, examples have been shown and described in which the wiring layer is patterned by a semi-additive method, but the wiring layer may be patterned by a method other than the semi-additive method. For example, a subtractive method may be employed. An embodiment in which the wiring layer is patterned using a subtractive method will be described below. In the third embodiment described below, the same components as those in the first and second embodiments will be described with the same reference numerals as those in the first and second embodiments.

[0113] (Outline of Multilayer Ceramic Circuit Substrate 3 According to Third Embodiment) Fig. 36 is a cross-sectional view schematically showing a multilayer ceramic circuit substrate 3 according to a third embodiment of the present invention. As shown in Fig. 36, the multilayer ceramic circuit substrate 3 according to the third embodiment of the present invention has the same configuration as the multilayer ceramic circuit substrate 1 according to the first embodiment, and can obtain the same advantages as the multilayer ceramic circuit substrate 1 according to the first embodiment.

[0114] (Outline of Manufacturing Method of Multilayer Ceramic Circuit Board 3 According to Third Embodiment) The multilayer ceramic circuit board 3 according to this embodiment can be manufactured by a manufacturing method including: a step (I) of forming a core wiring layer 200 on a core substrate 100; and a step (II) of forming unit layers 300A and 300B on the core wiring layer 200. This manufacturing method may be the same as the manufacturing method according to the first embodiment, except that the wiring layers, such as the core wiring layer 200 and the build-up wiring layer 320A and the build-up wiring layer 320B, are formed by a subtractive method. Hereinafter, an example will be described in which, as in the first embodiment, two steps (II) are repeated: a step (II) of forming a first unit layer 300A directly on the core wiring layer 200, and a step (II) of forming a second unit layer 300B indirectly on the core wiring layer 200 via the first unit layer 300A.

[0115] (Explanation of Step (I) According to Third Embodiment) Step (I) includes step (I-1) of preparing a core substrate 100. In the third embodiment, step (I-1) can be performed in the same manner as in the first and second embodiments.

[0116] The step (I) includes a step (I-1) of preparing a core substrate 100, followed by a step (I-2) of forming a core wiring layer 200 on the core substrate 100. In this embodiment, the core wiring layer 200 is formed by a subtractive method.

[0117] 37 to 41 are schematic cross-sectional views illustrating a subtractive method for forming a core wiring layer 200 in a manufacturing method for a multilayer ceramic circuit board 3 according to a third embodiment of the present invention. When forming the core wiring layer 200 by a subtractive method, step (I-2) may include, in this order, forming a seed layer 210 on the surface 110 of the core substrate 100 as shown in FIG. 37 , forming an electrolytically plated layer 220 on the seed layer 210 by electrolytic plating as shown in FIG. 38 , forming a mask layer 530 that covers the portion of the electrolytically plated layer 220 where the core wiring layer 200 will be formed as shown in FIG. 39 , removing the seed layer 210 and the electrolytically plated layer 220 that are not covered by the mask layer 530 as shown in FIG. 40 , and removing the mask layer 530 as shown in FIG. 41 . The formation of the seed layer 210, electrolytic plating, formation of the mask layer 530, and removal of the mask layer 530 may be performed in the same manner as in the first embodiment. The seed layer 210 and the electrolytic plating layer 220 may be removed by the same method as that for removing the seed layer 210 described in the first embodiment. If necessary, an annealing treatment may be performed after the formation of the core wiring layer 200. By such a subtractive method, the core wiring layer 200 including the seed layer 210 and the electrolytic plating layer 220 can be obtained.

[0118] (Explanation of Step (II) According to the Third Embodiment) The method for manufacturing a multilayer ceramic circuit substrate 3 according to this embodiment includes, after step (I), step (II) of forming unit layers 300A and 300B on the core wiring layer 200. This step (II) may be performed in the same manner as step (II) according to the first embodiment, except that the build-up wiring layer in step (II-4) is formed by a subtractive method.

[0119] Thus, step (II) according to this embodiment may include steps (II-1) to (II-3) similar to those of the first embodiment (see FIGS. 9 to 11 ). Specifically, step (II) may include step (II-1) of forming a ceramic insulating layer 310A by aerosol deposition as shown in FIG. 9 , step (II-2) of planarizing a surface 330A of the ceramic insulating layer 310A as shown in FIG. 10 , and step (II-3) of forming via holes 340A in the ceramic insulating layer 310A as shown in FIG. 11 . By performing these steps (II-1) to (II-3), the ceramic insulating layer 310A is formed on the core wiring layer 200 as shown in FIG. 11 . This ceramic insulating layer 310A has a planarized surface 330A. Furthermore, via holes 340A are formed in the ceramic insulating layer 310A.

[0120] 42 to 46 are schematic cross-sectional views illustrating a method for forming a build-up wiring layer 320A by a subtractive method in a manufacturing method for a multilayer ceramic circuit substrate 3 according to a third embodiment of the present invention. Step (II) according to this embodiment includes a step (II-4) of forming a build-up wiring layer 320A by a subtractive method on the ceramic insulating layer 310A. The build-up wiring layer 320A may be formed by the same method as the formation of the core wiring layer 200. Therefore, step (II-4) may include, in this order, forming a seed layer 321A on surface 330A of ceramic insulating layer 310A as in the example shown in Fig. 42, forming an electrolytically plated layer 322A on seed layer 321A by electrolytic plating as in the example shown in Fig. 43, forming a mask layer 630 that covers the portion of electrolytically plated layer 322A where build-up wiring layer 320A is to be formed as in the example shown in Fig. 44, removing the portion of seed layer 321A and electrolytically plated layer 322A that is not covered by mask layer 630 as in the example shown in Fig. 45, and removing mask layer 630 as shown in Fig. 46. Step (II-4) may also include a step of performing an annealing treatment after forming electrolytically plated layer 322A. The formation of the seed layer 321A, electrolytic plating, formation of the mask layer 630, removal of the seed layer 321A and the electrolytic plated layer 322A, removal of the mask layer 630, and annealing may be performed by the same method as the above-described method for forming the core wiring layer 200. This step (II-4) makes it possible to obtain a build-up wiring layer 320A including the seed layer 321A and the electrolytic plated layer 322A. Then, the first unit layer 300A can be formed by combining the build-up wiring layer 320A thus formed with the ceramic insulating layer 310A.

[0121] In the method for manufacturing the multilayer ceramic circuit substrate 3 according to this embodiment, as in the first embodiment, the above-described step (II) is repeated two or more times. Thus, in the method for manufacturing the multilayer ceramic circuit substrate 3 according to this embodiment, the first step (II) is performed as described above to form a first unit layer 300A including a ceramic insulating layer 310A and a build-up wiring layer 320A, and then the second step (II) is performed to form a second unit layer 300B including a ceramic insulating layer 310B and a build-up wiring layer 320B, as shown in FIG. 17 . As in the first embodiment, the second unit layer 300B may be formed by the same method as the method for forming the first unit layer 300A.

[0122] (Explanation of Optional Steps According to the Third Embodiment) The method for manufacturing the multilayer ceramic circuit substrate 3 according to this embodiment may further include optional steps in combination with the steps described above. For example, the manufacturing method according to this embodiment may include the step of forming the surface coating layer 400, as in the first and second embodiments.

[0123] (Major Advantages of Third Embodiment) According to the multilayer ceramic circuit board 3 and the manufacturing method thereof of this embodiment, it is possible to obtain the same advantages as those described in the first and second embodiments.

[0124] Fourth Embodiment The formation of wiring layers by a subtractive method may be applied to a multilayer ceramic circuit board in which interlayer connections are achieved using pillars, as described in the second embodiment. An embodiment in which the subtractive method is applied to a multilayer ceramic circuit board in which interlayer connections are achieved using pillars will be described below. In the fourth embodiment described below, the same components as those in the first to third embodiments will be described with the same reference numerals as those in the first to third embodiments.

[0125] (Outline of Multilayer Ceramic Circuit Substrate 4 According to Fourth Embodiment) Fig. 47 is a cross-sectional view schematically showing a multilayer ceramic circuit substrate 4 according to a fourth embodiment of the present invention. As shown in Fig. 47, the multilayer ceramic circuit substrate 4 according to the fourth embodiment of the present invention has the same configuration as the multilayer ceramic circuit substrate 2 according to the second embodiment, and can obtain the same advantages as the multilayer ceramic circuit substrate 2 according to the second embodiment.

[0126] (Outline of Manufacturing Method of Multilayer Ceramic Circuit Board 4 According to Fourth Embodiment) The multilayer ceramic circuit board 4 according to this embodiment can be manufactured by a manufacturing method including: a step (I) of forming a core wiring layer 700 on a core substrate 100; and a step (II) of forming unit layers 800A and 300B on the core wiring layer 700. This manufacturing method may be the same as the manufacturing method according to the second embodiment, except that the wiring layers, such as the core wiring layer 700, the build-up wiring layer 820A, and the build-up wiring layer 320B, are formed by a subtractive method. Hereinafter, an example will be described in which, as in the second embodiment, two steps (II) are repeated: a step (II) of forming a first unit layer 800A directly on the core wiring layer 700, and a step (II) of forming a second unit layer 300B indirectly on the core wiring layer 700 via the first unit layer 800A.

[0127] (Explanation of Step (I) According to Fourth Embodiment) Step (I) includes step (I-1) of preparing a core substrate 100. In the fourth embodiment, step (I-1) can be performed in the same manner as in the first to third embodiments.

[0128] The step (I) includes a step (I-1) of preparing a core substrate 100, followed by a step (I-2) of forming a core wiring layer 700 on the core substrate 100. In this embodiment, the core wiring layer 700 is formed by a subtractive method.

[0129] 48 to 55 are schematic cross-sectional views illustrating a method of forming a core wiring layer 700 by a subtractive method in a method of manufacturing a multilayer ceramic circuit board 4 according to a fourth embodiment of the present invention. When the core wiring layer 700 is formed by a subtractive method, the step (I-2) may include, in this order, forming a seed layer 710 on the surface 110 of the core substrate 100 as in the example shown in FIG. 48, forming an electrolytic plated layer 720 on the seed layer 710 by electrolytic plating as in the example shown in FIG. 49, forming a mask layer 540 that covers the portion of the electrolytic plated layer 720 where the core wiring layer 700 is to be formed as in the example shown in FIG. 50, removing the seed layer 710 and the electrolytic plated layer 720 that are not covered by the mask layer 540 as in the example shown in FIG. 51, removing the mask layer 540 as in the example shown in FIG. 52, forming a mask layer 550 that covers all but a portion 770 on the electrolytic plated layer 720 where the pillar portion 750 is to be formed as in the example shown in FIG. 53, performing electrolytic plating to increase the thickness of the electrolytic plated layer 720 at the portion 770 as in the example shown in FIG. 54, and removing the mask layer 550 as in FIG. 55. The formation of the seed layer 710, electrolytic plating, formation of the mask layers 540 and 550, removal of the mask layers 540 and 550, and removal of the seed layer 710 and electrolytic plating layer 720 may be performed by the same methods as in the third embodiment. If necessary, an annealing treatment may be performed after the formation of the core wiring layer 700. By such a subtractive method, it is possible to obtain the core wiring layer 700 including a relatively thick pillar portion 750 and a relatively thin wiring portion 760. The pillar portion 750 and the wiring portion 760 of the formed core wiring layer 700 both include the seed layer 710 and the electrolytic plating layer 720.

[0130] (Explanation of Step (II) According to Fourth Embodiment) The method for manufacturing a multilayer ceramic circuit substrate 4 according to this embodiment includes, after step (I), step (II) of forming unit layers 800A and 300B on the core wiring layer 700. This step (II) may be performed in the same manner as step (II) according to the second embodiment, except that the build-up wiring layer in step (II-4) is formed by a subtractive method.

[0131] Thus, step (II) according to this embodiment may include steps (II-1) to (II-2) similar to those of the second embodiment (see FIGS. 26 and 27 ). Specifically, step (II) may include step (II-1) of forming a ceramic insulating layer 310A by aerosol deposition as shown in FIG. 26 , and step (II-2) of planarizing a surface 330A of the ceramic insulating layer 310A as shown in FIG. 27 . By performing these steps (II-1) to (II-2), the ceramic insulating layer 310A is formed on the core wiring layer 700 as shown in FIG. 27 . This ceramic insulating layer 310A has a planarized surface 330A. Furthermore, this surface 330A, together with the surface 780 of the pillar portion 750, can form a single plane having low surface roughness.

[0132] 56 to 63 are schematic cross-sectional views illustrating a method for forming a build-up wiring layer 820A by a subtractive method in a manufacturing method for a multilayer ceramic circuit substrate 4 according to a fourth embodiment of the present invention. Step (II) according to this embodiment includes step (II-4) of forming a build-up wiring layer 320A by a subtractive method on the ceramic insulating layer 310A. The formation of this build-up wiring layer 320A may be performed by the same method as the formation of the core wiring layer 700. 56, forming an electroplated layer 822A on the seed layer 821A by electroplating as in the example shown in FIG. 57, forming a mask layer 640 that covers the portion of the electroplated layer 822A where the build-up wiring layer 820A is to be formed as in the example shown in FIG. 58, removing the seed layer 821A and the electroplated layer 822A that are not covered by the mask layer 640 as in the example shown in FIG. 59, removing the mask layer 640 as in FIG. 60, forming a mask layer 650 that covers all but a portion 870A on the electroplated layer 822A where the pillar portion 850A is to be formed as in FIG. 61, performing electroplating to increase the thickness of the electroplated layer 822A at the portion 870A as in FIG. 62, and removing the mask layer 650 as in FIG. 63. Furthermore, step (II-4) may include a step of performing an annealing treatment after the formation of the electroplated layer 822A. The formation of the seed layer 821A, electroplating, formation of the mask layers 640 and 650, removal of the seed layer 821A and the electroplated layer 822A, removal of the mask layers 640 and 650, and annealing may be performed using the same method as the method for forming the core wiring layer 700 described above. This step (II-4) results in a build-up wiring layer 820A including a relatively thick pillar portion 850A and a relatively thin wiring portion 860A. The pillar portion 850A and the wiring portion 860A of the formed build-up wiring layer 820A both include the seed layer 821A and the electroplated layer 822A. The first unit layer 800A can then be formed by combining the thus formed build-up wiring layer 820A with the ceramic insulating layer 310A.

[0133] In the method for manufacturing a multilayer ceramic circuit substrate 4 according to this embodiment, as in the second embodiment, the above-described step (II) is repeated two or more times. Thus, in the method for manufacturing a multilayer ceramic circuit substrate 4 according to this embodiment, after the first step (II) is performed as described above to form a first unit layer 800A including a ceramic insulating layer 310A and a build-up wiring layer 820A, the second step (II) is performed to form a second unit layer 300B including a ceramic insulating layer 310B and a build-up wiring layer 320B, as shown in FIG. 35 . As in the second embodiment, the second unit layer 300B may be formed by the same method as the method for forming the first unit layer 800A.

[0134] (Explanation of Optional Steps According to the Fourth Embodiment) The method for manufacturing the multilayer ceramic circuit substrate 4 according to this embodiment may further include optional steps in combination with the steps described above. For example, the manufacturing method according to this embodiment may include the step of forming the surface coating layer 400, as in the first to third embodiments.

[0135] (Major Advantages of the Fourth Embodiment) According to the multilayer ceramic circuit board 4 and the manufacturing method thereof of this embodiment, it is possible to obtain the same advantages as those described in the first to third embodiments.

[0136] <Modifications> The above-described embodiment may be further modified. For example, in the above-described embodiment, an example in which the wiring layer is formed by plating has been shown, but part or all of the wiring layer may be formed by a method other than plating. As a specific example, the core wiring layers 200 and 700 or their seed layers 210 and 710 may be formed using copper foil. When copper foil is used, step (I) may include laminating the copper foil on the core substrate 100 directly or via an adhesive layer.

[0137] When copper foil is laminated directly on core substrate 100, step (I) may include bonding the copper foil to surface 110 of core substrate 100 using a surface activation method. For example, bonding may be performed by a method including performing a surface activation treatment such as sputter etching on surface 110 of core substrate 100, performing a surface activation treatment such as sputter etching on the surface of copper foil, and pressing the surfaces that have been subjected to the surface activation treatment together. According to the surface activation method, core wiring layers 200 and 700 or their seed layers 210 and 710 can be formed by the copper foil bonded to surface 110 of core substrate 100.

[0138] When copper foil is laminated on core substrate 100 via an adhesive layer, step (I) may include forming an adhesive layer on surface 110 of core substrate 100 and laminating copper foil on the adhesive layer. Alternatively, step (I) may include forming an adhesive layer on the copper foil and bonding the adhesive layer to surface 110 of core substrate 100. When an adhesive layer is used, core wiring layers 200 and 700 or their seed layers 210 and 710 can be formed by copper foil formed on surface 110 of core substrate 100 via the adhesive layer.

[0139] In the above-described embodiment, the core wiring layer and the unit layers are formed on one side of the core substrate, but the core wiring layer and the unit layers may be formed on both sides of the core substrate.

[0140] <Applications of Multilayer Ceramic Circuit Board> The applications of the above-described multilayer ceramic circuit board are not particularly limited. Preferred applications of the multilayer ceramic circuit board include, for example, printed wiring boards, semiconductor package substrates, and interposers. Among these, semiconductor package substrates are preferred. Examples of semiconductor chip packages to which this semiconductor package substrate can be applied include FC-CSP, MIS-BGA package, ETS-BGA package, fan-out type WLP (Wafer Level Package), fan-in type WLP, fan-out type PLP (Panel Level Package), and fan-in type PLP.

[0141] <Semiconductor Device> The multilayer ceramic circuit substrate described above can be used to manufacture a semiconductor device. The semiconductor device includes the multilayer ceramic circuit substrate described above. Typically, a semiconductor device includes a multilayer ceramic circuit substrate and components mounted on the multilayer ceramic circuit substrate. The combination of the wiring layers and components provided on the multilayer ceramic circuit substrate can function as an electronic circuit. Examples of such semiconductor devices include various semiconductor devices used in electrical products (e.g., computers, mobile phones, smartphones, tablet devices, wearable devices, digital cameras, medical equipment, televisions, etc.) and vehicles (e.g., motorcycles, automobiles, trains, ships, aircraft, etc.).

[0142] REFERENCE SIGNS LIST 1 Multilayer ceramic circuit board 2 Multilayer ceramic circuit board 3 Multilayer ceramic circuit board 4 Multilayer ceramic circuit board 10 Forming apparatus 20 Chamber 21 Stage 22 Nozzle 30 Exhaust pump 40 Aerosol generator 41 Ceramic powder 50 Gas cylinder 51 Transfer pipe 52 Transfer pipe 53 Transfer pipe 54 Diffusion member 100 Core substrate 110 Surface 200 Core wiring layer (first wiring layer) 210 Seed layer 220 Electrolytic plating layer 300A, 300B Unit layer 310A, 310B Ceramic insulating layer 320A, 320B Build-up wiring layer (second wiring layer) 321A, 321B Seed layer 322A, 322B Electrolytic plating layer 330A, 330B Surface 340A, 340B Via hole 400 Surface coating layer 500 Mask layer 510 Mask layer 520 Mask layer 530 Mask layer 540 Mask layer 550 Mask layer 600 Mask layer 610 Mask layer 620 Mask layer 630 Mask layer 640 Mask layer 650 Mask layer 700 Core wiring layer (first wiring layer) 710 Seed layer 720 Electrolytic plating layer 750 Pillar portion 760 Wiring portion 770 Portion where pillar portion is to be formed 780 Surface 800A Unit layer 820A Build-up wiring layer (second wiring layer) 821A Seed layer 822A Electrolytic plating layer 850A Pillar portion 860A Wiring portion 870A Portion where pillar portion is to be formed 880A Surface

Claims

1. A method for manufacturing a multilayer ceramic circuit board, comprising: a step (I) of forming a first wiring layer containing copper on a core board selected from the group consisting of a ceramic board and a glass board; and a step (II) of forming a unit layer including a ceramic insulating layer containing a ceramic material and a second wiring layer containing copper on the first wiring layer, wherein step (II) includes: a step (II-1) of forming the ceramic insulating layer by an aerosol deposition method; a step (II-2) of planarizing a surface of the ceramic insulating layer formed by the aerosol deposition method, which is opposite to the core board; and a step (II-4) of forming the second wiring layer on the planarized surface of the ceramic insulating layer; and the method includes repeating step (II) two or more times.

2. The method for manufacturing a multilayer ceramic circuit board according to claim 1, wherein step (II) includes a step (II-3) of forming via holes in the ceramic insulating layer between step (II-2) and step (II-4).

3. The method for manufacturing a multilayer ceramic circuit board according to claim 1, wherein the first wiring layer includes a relatively high pillar portion and a relatively low wiring portion.

4. The method for manufacturing a multilayer ceramic circuit board according to claim 3, wherein step (II-2) includes polishing the ceramic insulating layer so that the pillar portion is exposed.

5. The method for manufacturing a multilayer ceramic circuit board according to claim 1, wherein the first wiring layer and the second wiring layer are formed by a plating method.

6. The plating method according to claim 5 includes forming a seed layer by sputtering and forming an electrolytic plating layer on the seed layer by electrolytic plating.

7. The method for manufacturing a multilayer ceramic circuit board according to claim 1, wherein step (I) includes laminating a copper foil on the core board directly or via an adhesive layer.

8. The method for manufacturing a multilayer ceramic circuit board according to claim 1, wherein the ceramic material is alumina.

9. The method for manufacturing a multilayer ceramic circuit board according to claim 1, wherein at a point in time after step (II-1) and before step (II-2), the ceramic insulating layer is thicker than the first wiring layer.

10. A multilayer ceramic circuit board comprising: a core board selected from the group consisting of a ceramic board and a glass board; a first wiring layer formed on the core board; and a plurality of unit layers formed on the first wiring layer; the first wiring layer containing copper; each unit layer comprising a ceramic insulating layer containing a ceramic material and a second wiring layer containing copper; the surface of the ceramic insulating layer opposite to the core board being planarized; and the second wiring layer being formed on the planarized surface of the ceramic insulating layer.

11. The multilayer ceramic circuit board according to claim 10, wherein the multilayer ceramic circuit board is a semiconductor package board.

12. A semiconductor device comprising the multilayer ceramic circuit board according to claim 10 or 11.

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