Semiconductor device

Abstract

This semiconductor device includes an n-type semiconductor layer, a p-type well region formed in the semiconductor layer at a higher concentration than the semiconductor layer, and an n-type high-concentration region formed in the semiconductor layer at a higher concentration than the semiconductor layer and forming a pn junction with the well region.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2023-221774 filed with the Japan Patent Office on December 27, 2023, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2003 / 0227051A1) discloses a semiconductor device having an active groove formed in an n-type semiconductor layer, in which a p-type buried region is disposed on the bottom side of the active groove, and a gate electrode is disposed on the opening side of the active groove via a gate insulating film.

[0003] US Patent Application Publication No. 2003 / 0227051

[0004] SUMMARY The present disclosure provides a semiconductor device having a novel layout.

[0005] The present disclosure provides a semiconductor device including a semiconductor layer of a first conductivity type having a main surface, a body region of a second conductivity type formed in a surface layer portion of the main surface, a trench-type gate structure formed in the main surface so as to penetrate the body region, and a well region of the second conductivity type formed in a region below the gate structure within the semiconductor layer, the well region having a bulge region that protrudes horizontally along the main surface relative to a sidewall of the gate structure.

[0006] The present disclosure provides a semiconductor device including: a semiconductor layer of a first conductivity type having a main surface; a body region of a second conductivity type formed in a surface layer portion of the main surface; a trench-type gate structure formed in the main surface so as to penetrate the body region; and a high-concentration body region formed in a bottom portion of the body region and having an impurity concentration higher than the impurity concentration of the body region.

[0007] The present disclosure provides a semiconductor device including a first conductivity type semiconductor layer including a SiC single crystal and having a primary surface, a trench-type gate structure formed on the primary surface, and a second conductivity type well region formed in the semiconductor layer in a region below the gate structure and extending along an axial channel of the SiC single crystal.

[0008] The present disclosure provides a semiconductor device including an n-type semiconductor layer, a p-type well region formed in the semiconductor layer to have a higher concentration than the semiconductor layer, and an n-type high concentration region formed in the semiconductor layer to have a higher concentration than the semiconductor layer and forming a p-n junction with the well region.

[0009] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing an example layout of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of an active region. FIG. 5 is an enlarged plan view showing another main portion of the active region. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5. FIG. 9 is an enlarged cross-sectional view showing a main portion of an active region. FIG. 10 is a cross-sectional perspective view showing a main portion of an active region. FIG. 11 is a cross-sectional perspective view showing a main portion of an active region. FIG. 12 is a graph showing the impurity concentration of a well region. FIG. 13 is a graph showing the impurity concentration of a high-concentration region. FIG. 14 is a graph showing the impurity concentration of a body region. FIG. 15 is a cross-sectional perspective view for explaining operation when a drain-source voltage is applied when the gate structure is in an off state. FIG. 16 is a cross-sectional perspective view showing a first modified example of the semiconductor device. FIG. 17 is a sectional perspective view showing a second modified example of the semiconductor device. FIG. 18 is a sectional perspective view showing a third modified example of the semiconductor device. FIG. 19 is a sectional perspective view showing a fourth modified example of the semiconductor device. FIG. 20 is a sectional perspective view showing a fifth modified example of the semiconductor device. FIG. 21 is a sectional perspective view showing a sixth modified example of the semiconductor device. FIG. 22 is a sectional perspective view showing a seventh modified example of the semiconductor device. FIG. 23 is a sectional perspective view showing an eighth modified example of the semiconductor device. FIG. 24 is a sectional perspective view showing a ninth modified example of the semiconductor device. FIG. 25 is a sectional perspective view showing a tenth modified example of the semiconductor device. FIG. 26 is a sectional perspective view showing an eleventh modified example of the semiconductor device. FIG. 27 is a sectional perspective view showing a twelfth modified example of the semiconductor device. FIG. 28 is a sectional perspective view showing a thirteenth modified example of the semiconductor device. FIG. 29 is a sectional perspective view showing a fourteenth modified example of the semiconductor device. FIG. 30 is a sectional perspective view showing a fifteenth modified example of the semiconductor device. FIG. 31 is a sectional perspective view showing a sixteenth modified example of the semiconductor device. FIG. 32 is a sectional perspective view showing a semiconductor device according to the second embodiment. FIG. 33 is a graph showing the impurity concentration of a well region. FIG. 34 is a graph showing the impurity concentration of a high-concentration region. FIG. 35 is a plan view showing a semiconductor device according to the third embodiment.Fig. 36 is an enlarged plan view showing a main portion of the active region shown in Fig. 35. Fig. 37 is a cross-sectional view taken along line XXXVII-XXXVII shown in Fig. 36. Fig. 38 is a plan view showing a semiconductor device according to a fourth embodiment. Fig. 39 is a cross-sectional view taken along line XXXIX-XXXIX shown in Fig. 38. Fig. 40 is an enlarged cross-sectional view showing a main portion of the active region shown in Fig. 39.

[0011] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0012] In this specification, open language such as "including" and "having" is described as a concept that encompasses closed language such as "consisting of." When the term "substantially" is used in this specification, this term not only includes a numerical value (form) that is equal to the numerical value (form) of the comparison target, but also includes a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target.

[0013] In this specification, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation, and are not intended to limit the names of each structure.

[0014] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type."

[0015] "P-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0016] Fig. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a first main surface 3. Fig. 4 is an enlarged plan view showing a main portion of an active region 8. Fig. 5 is an enlarged plan view showing another main portion of the active region 8.

[0017] Fig. 6 is a cross-sectional view taken along line VI-VI shown in Fig. 4. Fig. 7 is a cross-sectional view taken along line VII-VII shown in Fig. 4. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 5. Fig. 9 is an enlarged cross-sectional view showing a main part of the active region 8. Fig. 10 is a cross-sectional perspective view showing a main part of the active region 8. Fig. 11 is a cross-sectional perspective view showing a main part of the active region 8.

[0018] 1 to 11, a semiconductor device 1A is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate vertical structure.

[0019] Semiconductor device 1A includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1A is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0020] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1A is a "SiC semiconductor device."

[0021] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0022] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0023] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0024] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0025] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. The first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0026] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off-angle from a vertical line along the vertical direction Z toward the off-direction. Furthermore, the c-plane of the SiC single crystal is inclined by the off-angle with respect to the horizontal plane.

[0027] The off-direction is preferably the a-axis direction of the SiC single crystal (second direction Y in this embodiment). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0028] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0029] The semiconductor device 1A includes an n-type first semiconductor layer 6 formed in a surface layer portion of the second main surface 4. A drain potential as a first potential (high potential) is applied to the first semiconductor layer 6. The first semiconductor layer 6 may also be referred to as a "semiconductor region (layer)," a "base region (layer)," a "drain region (layer)," or the like.

[0030] The first semiconductor layer 6 extends in a layered form along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor layer 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor layer 6 (substrate) has the off direction and off angle described above.

[0031] The first semiconductor layer 6 has a concentration adjusted with a base element (base impurity) made of a pentavalent element. The base element may include at least one of nitrogen, phosphorus, and arsenic. The first semiconductor layer 6 preferably has a concentration adjusted with a single base element. The base element may be nitrogen. The first semiconductor layer 6 has a substantially uniform n-type impurity concentration (substantially constant n-type impurity concentration) in the thickness direction.

[0032] The first semiconductor layer 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or more, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0033] The semiconductor device 1A includes an n-type second semiconductor layer 7 formed in a surface layer portion of the first main surface 3. The second semiconductor layer 7 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. The second semiconductor layer 7 has an n-type impurity concentration that is lower than the n-type impurity concentration of the first semiconductor layer 6.

[0034] The second semiconductor layer 7 has a concentration adjusted with a first element (first impurity) made of a pentavalent element. The first element may include at least one of nitrogen, phosphorus, and arsenic. The first semiconductor layer 6 preferably has a concentration adjusted with a single first element. The first element may be nitrogen. The second semiconductor layer 7 has a substantially uniform n-type impurity concentration (substantially constant n-type impurity concentration) in the thickness direction.

[0035] The second semiconductor layer 7 is formed in a region on the first main surface 3 side of the first semiconductor layer 6 in a cross-sectional view, and is electrically connected to the first semiconductor layer 6. The second semiconductor layer 7 extends in a layered form along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor layer 7 is made of an n-type semiconductor layer.

[0036] Specifically, the second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal), and has a first main surface 3 and first to fourth side surfaces 5A to 5D. The second semiconductor layer 7 (epitaxial layer) has the off direction and off angle described above. The second semiconductor layer 7 preferably has a thickness less than that of the first semiconductor layer 6. The thickness of the second semiconductor layer 7 may be greater than that of the first semiconductor layer 6.

[0037] The thickness of the second semiconductor layer 7 may be 5 μm or more and 25 μm or less. The thickness of the second semiconductor layer 7 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, 12.5 μm or more and 15 μm or less, 15 μm or more and 17.5 μm or less, 17.5 μm or more and 20 μm or less, 20 μm or more and 22.5 μm or less, and 22.5 μm or more and 25 μm or less.

[0038] The semiconductor device 1A includes an active region 8 set in a chip 2. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 is set in an inner portion of the chip 2 at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).

[0039] The active region 8 is set to a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The ratio (area ratio) of the planar area of ​​the active region 8 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. The area ratio may have a value belonging to at least one of the ranges of 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 0.95 or less.

[0040] The semiconductor device 1A includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is a region that does not include a device structure (transistor structure Tr). The peripheral region 9 is set on the periphery of the chip 2. That is, the peripheral region 9 is provided in the region between the periphery of the chip 2 and the active region 8 in plan view. The peripheral region 9 extends in a strip shape along the active region 8 in plan view and is set in the shape of a polygonal ring (a square ring in this embodiment) that surrounds the active region 8.

[0041] The semiconductor device 1A includes a transistor structure Tr formed in an active region 8. The configuration within the active region 8 as the configuration of the transistor structure Tr will be described below.

[0042] The semiconductor device 1A includes a p-type body region 10 formed in the active region 8 (inner portion of the first main surface 3) in a surface layer portion of the first main surface 3. The body region 10 may be referred to as a "channel region" or the like. A source potential may be applied to the body region 10. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential.

[0043] The body region 10 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity (trivalent element) in the body region 10 may be either or both of boron and aluminum.

[0044] The body region 10 is formed in the inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer peripheral region 9. In this embodiment, the body region 10 is formed throughout the active region 8. The body region 10 is formed in the surface layer portion of the second semiconductor layer 7, and extends in a layered form along the first main surface 3.

[0045] The body region 10 is formed at a distance from the bottom of the second semiconductor layer 7 (the first semiconductor layer 6) toward the first major surface 3, and faces the first semiconductor layer 6 across a part of the second semiconductor layer 7. The body region 10 is formed at a distance from a depth position of the middle part of the second semiconductor layer 7 toward the first major surface 3.

[0046] The body region 10 is formed in a region on the first major surface 3 side of the second semiconductor layer 7 in a cross-sectional view, and is electrically connected to the second semiconductor layer 7. The body region 10 forms a pn junction (body diode) with the second semiconductor layer 7. The body region 10 spreads a depletion layer into the second semiconductor layer 7 when a reverse bias voltage is applied. The depletion layer originating from the body region 10 spreads in the horizontal direction and thickness direction within the second semiconductor layer 7.

[0047] The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) gate structures 15 formed in the active region 8 (inner portion of the first main surface 3). The gate structures 15 may also be referred to as "trench structures," "trench gate structures," or the like. A gate potential (gate signal) serving as a control potential is applied to the plurality of gate structures 15. The plurality of gate structures 15 controls inversion and non-inversion of the channel CH in the body region 10 in response to the gate potential (see FIG. 10 ).

[0048] The multiple gate structures 15 are formed in the active region 8 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the peripheral region 9. The multiple gate structures 15 are arranged at intervals in the first direction X (= m-axis direction) in plan view, and each extend in a strip shape in the second direction Y (= a-axis direction). The multiple gate structures 15 are arranged in stripes extending in the second direction Y in plan view.

[0049] The extension direction of the multiple gate structures 15 coincides with the off-direction of the SiC single crystal. With respect to the second direction Y, both end portions of the multiple gate structures 15 are located inward from the periphery of the body region 10. Both end portions of the multiple gate structures 15 may be located outward from the periphery of the body region 10. The multiple gate structures 15 may be arranged at intervals in the second direction Y in a plan view, and each extend in a strip shape in the first direction X.

[0050] The plurality of gate structures 15 penetrate the body region 10 to reach the second semiconductor layer 7. The plurality of gate structures 15 are formed at intervals from the depth position of the bottom of the second semiconductor layer 7 toward the first main surface 3, and face the first semiconductor layer 6 with a part of the second semiconductor layer 7 interposed therebetween.

[0051] The multiple gate structures 15 may be formed at intervals from a depth position of an intermediate portion of the second semiconductor layer 7 toward the first major surface 3, or may be located on the bottom side of the second semiconductor layer 7 (the second major surface 4 side) with respect to the depth position of the intermediate portion of the second semiconductor layer 7. The multiple gate structures 15 are formed approximately perpendicular to the first major surface 3. The multiple gate structures 15 may be formed in a shape that tapers toward the bottom of the second semiconductor layer 7.

[0052] The side walls (long sides) of the plurality of gate structures 15 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls (long sides) of the plurality of gate structures 15 may be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 15. The side walls of the plurality of gate structures 15, together with the first main surface 3, define an opening end curved in an arc shape (circular arc shape).

[0053] The bottom walls of the gate structures 15 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the gate structures 15 preferably extend substantially flat in the horizontal direction. The bottom walls of the gate structures 15 may be curved in an arc shape toward the second main surface 4.

[0054] The inclination angle (absolute value) of the sidewall (long side) of the gate structure 15 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0055] The gate structure 15 may have a width of 0.1 μm to 2 μm. The width of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm. The width of the gate structure 15 is preferably 1 μm or less.

[0056] The gate structure 15 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the gate structure 15 is measured from the first main surface 3. The depth of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less.

[0057] The gate structure 15 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0058] The multiple gate structures 15 may be arranged at a pitch of 0.1 μm to 2 μm. The pitch is the distance between the multiple gate structures 15 in the horizontal direction (first direction X). The pitch may have a value belonging to at least one of the following ranges: 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm. The pitch is preferably 1 μm or less.

[0059] The plurality of gate structures 15 each include a trench 16, an insulating film 17, a buried electrode 18, and a buried insulator 19. The trench 16 may be referred to as a "gate trench," the insulating film 17 may be referred to as a "gate insulating film," the buried electrode 18 may be referred to as a "gate electrode," and the buried insulator 19 may be referred to as a "cap insulator (film)." The trench 16 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 15.

[0060] The insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 17 includes a silicon oxide film made of an oxide of the chip 2.

[0061] The insulating film 17 covers the wall surface of the trench 16. In this embodiment, the insulating film 17 has an upper end portion positioned on the bottom wall side of the trench 16 relative to the height position of the first main surface 3, and exposes a part of the chip 2 from the wall surface of the opening end of the trench 16. The upper end portion of the insulating film 17 is preferably positioned on the opening side of the trench 16 relative to the depth position of the intermediate part of the trench 16.

[0062] The insulating film 17 includes a first film portion and a second film portion. The first film portion covers the sidewall of the trench 16 in a film-like manner. The second film portion covers the bottom wall of the trench 16 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to that of the first film portion.

[0063] The insulating film 17 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0064] The buried electrode 18 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried electrode 18 is preferably made of n-type conductive polysilicon. The buried electrode 18 is buried in the trench 16 with an insulating film 17 sandwiched therebetween. The buried electrode 18 faces the second semiconductor layer 7 and the body region 10 with the insulating film 17 sandwiched therebetween.

[0065] The buried electrode 18 has an electrode surface exposed from the trench 16. The electrode surface is located on the bottom wall side of the trench 16 at a distance from the height position of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth position of the intermediate portion of the trench 16. The electrode surface may also be located on the bottom wall side of the trench 16 with respect to the depth position of the intermediate portion of the trench 16.

[0066] The electrode surface is located closer to the bottom wall of the trench 16 than the upper end of the insulating film 17, and exposes a portion of the insulating film 17 covering the side wall (first film portion) at the opening side of the trench 16. The electrode surface may be located closer to the first main surface 3 than the upper end of the insulating film 17. The electrode surface defines a recess space within the trench 16 together with the side wall of the trench 16 (first film portion of the insulating film 17).

[0067] The buried insulator 19 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The buried insulator 19 may include an insulating material different from the insulating material of the insulating film 17, or may include the same type of insulating material as the insulating material of the insulating film 17. In this form, the buried insulator 19 includes a silicon oxide film having properties different from the properties of the insulating film 17.

[0068] The buried insulator 19 may have a single layer structure or a multilayer structure including at least one of an undoped silicon oxide film, a silicon oxide film containing phosphorus, and a silicon oxide film containing both phosphorus and boron. The undoped silicon oxide film may be called an NSG film (nondoped silicate glass film), the phosphorus-containing silicon oxide film may be called a PSG film (phosphorus silicon glass film), and the silicon oxide film containing both phosphorus and boron may be called a BPSG film (boron phosphorus silicon glass film).

[0069] The buried insulator 19 preferably has a single-layer structure or a multilayer structure including at least an NSG film. The buried insulator 19 may have a multilayer structure including an NSG film and a PSG film stacked in this order from the chip 2 side. The buried insulator 19 may have a multilayer structure including an NSG film, a PSG film, and a BPSG film stacked in this order from the chip 2 side. The buried insulator 19 may have a single-layer structure or a multilayer structure including a silicon oxide film containing an oxide of the buried electrode 18.

[0070] The buried insulator 19 is buried in the trench 16 above the buried electrode 18, and covers the buried electrode 18. In this embodiment, the buried insulator 19 is buried in the trench 16 with the insulating film 17 sandwiched therebetween, and is in contact with the insulating film 17 and the buried electrode 18 within the trench 16.

[0071] The buried insulator 19 has a portion that faces the chip 2 in the horizontal direction across the insulating film 17, and exposes the first main surface 3. The buried insulator 19 is buried in the trench 16 at a distance from the height position of the first main surface 3 toward the bottom wall of the trench 16, and exposes a portion of the chip 2 from the opening end of the trench 16.

[0072] The buried insulator 19 has an insulating surface exposed from the trench 16. The insulating surface is located on the bottom wall side of the trench 16 relative to the height of the first main surface 3. The insulating surface is located on the opening side of the trench 16 relative to the depth of the intermediate portion of the trench 16. The insulating surface may also be located on the bottom wall side of the trench 16 relative to the depth of the intermediate portion of the trench 16.

[0073] The insulating surface exposes the upper end of the insulating film 17. In this embodiment, the insulating surface is flat and continuous with the upper end of the insulating film 17. That is, the insulating surface is formed flush with the upper end of the insulating film 17. The insulating surface may be located closer to the first main surface 3 than the upper end of the insulating film 17, or may be located closer to the bottom wall of the trench 16 than the upper end of the insulating film 17. The insulating surface may be formed flush with the first main surface 3 together with the upper end of the insulating film 17.

[0074] In this embodiment, the insulating surface has a raised portion that rises from the sidewall of the trench 16 toward the inside of the trench 16. The raised portion of the insulating surface is located closer to the bottom wall of the trench 16 than the height position of the first main surface 3. The raised portion of the insulating surface may protrude above the height position of the first main surface 3. Instead of the raised portion, the insulating surface may have a recessed portion that sinks from the sidewall of the trench 16 toward the inside of the trench 16. The insulating surface may be formed flush with the first main surface 3.

[0075] In this embodiment, the buried insulator 19 has a thickness greater than the thickness of the first film portion of the insulating film 17. The thickness of the buried insulator 19 may be less than the thickness of the first film portion of the insulating film 17. In this embodiment, the thickness of the buried insulator 19 is greater than the thickness of the second film portion of the insulating film 17. The thickness of the buried insulator 19 may be less than the thickness of the second film portion of the insulating film 17.

[0076] The thickness of the buried insulator 19 is preferably less than the thickness of the buried electrode 18. The ratio of the thickness of the buried insulator 19 to the depth of the trench 16 may be greater than 0 and less than 0.5. The thickness ratio may have a value belonging to at least one of the ranges of greater than 0 and less than 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, and 0.4 to 0.5.

[0077] The semiconductor device 1A includes a plurality of mesa portions 20 defined in the active region 8 (inner portion of the first main surface 3) on the first main surface 3. The plurality of mesa portions 20 are defined in regions between adjacent gate structures 15, respectively.

[0078] The multiple mesa portions 20 are partitioned at intervals in the first direction X in accordance with the layout of the multiple gate structures 15, and each extends in a strip-like manner in the second direction Y. In other words, the multiple mesa portions 20 extend in the second direction Y in a strip-like manner. The width of each mesa portion 20 corresponds to the pitch of the multiple gate structures 15. The multiple mesa portions 20 may extend in the first direction X in accordance with the extension direction of the multiple gate structures 15.

[0079] The semiconductor device 1A includes a plurality of p-type well regions 25 formed in the chip 2 (second semiconductor layer 7). The plurality of well regions 25 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7, and convert the conductivity type of the second semiconductor layer 7 from n-type to p-type. A source potential is applied to the plurality of well regions 25.

[0080] The multiple well regions 25 are formed in the second semiconductor layer 7 in regions below (specifically, directly below) the multiple gate structures 15, spaced apart from one another in the horizontal direction (first direction X). The multiple well regions 25 are formed in the thickness range between the bottom of the second semiconductor layer 7 and the bottom walls of the multiple gate structures 15, and overlap the multiple gate structures 15 in a one-to-one correspondence in the thickness direction.

[0081] The multiple well regions 25 each extend in a strip shape in the second direction Y in plan view, following the extension direction of the corresponding gate structures 15. That is, the multiple well regions 25 are arranged in a stripe shape extending in the second direction Y in plan view. The extension direction of the multiple well regions 25 coincides with the off-direction of the SiC single crystal.

[0082] With respect to the second direction Y, both ends of the multiple well regions 25 may be located on the inner side of the active region 8 relative to both ends of the multiple gate structures 15, or may be located on the peripheral side of the active region 8. The multiple well regions 25 may extend in the first direction X according to the extending direction of the multiple gate structures 15. In this case, the multiple well regions 25 intersect (specifically, perpendicular to) the off direction.

[0083] The multiple well regions 25 are formed at intervals from the bottom of the second semiconductor layer 7 to the bottom wall sides of the multiple gate structures 15, and face the first semiconductor layer 6 across a part of the second semiconductor layer 7. Each of the multiple well regions 25 has an upper end located on the bottom wall side of the corresponding gate structure 15, and a bottom located on the bottom side of the second semiconductor layer 7.

[0084] The upper ends of the multiple well regions 25 are formed at intervals from the bottom of the body region 10 toward the bottom wall of the corresponding gate structure 15. The upper ends of the multiple well regions 25 may be connected to the bottom wall of the corresponding gate structure 15. The upper ends of the multiple well regions 25 may have portions that extend along the sidewall of the corresponding gate structure 15. The upper ends of the multiple well regions 25 may be formed at intervals from the bottom wall of the corresponding gate structure 15 toward the bottom of the second semiconductor layer 7.

[0085] The bottoms of the multiple well regions 25 may be located on the bottom wall side of the multiple gate structures 15 with respect to the depth position of the intermediate portion of the second semiconductor layer 7, or may be located on the bottom side of the second semiconductor layer 7 (the second main surface 4 side) with respect to the depth position of the intermediate portion of the second semiconductor layer 7. The bottoms of the multiple well regions 25 are directly connected to the second semiconductor layer 7. The multiple well regions 25 form a JFET region Tj (Junction Field-Effect Transistor region) together with the second semiconductor layer 7 in the region below the gate structure 15.

[0086] Well region 25 may have a depth of 0.5 μm to 5 μm from the bottom wall of gate structure 15. The depth of well region 25 may have a value belonging to at least one of the ranges of 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0087] Each of the multiple well regions 25 has one or more (two in this embodiment) bulging regions 26 and one or more (one in this embodiment) constricted regions 27 in the thickness direction of the second semiconductor layer 7.

[0088] The multiple bulge regions 26 are formed at different depth positions in the thickness direction of the chip 2. The multiple bulge regions 26 include a first bulge region 26A located on the bottom wall side of the gate structure 15 and a second bulge region 26B located on the bottom side of the second semiconductor layer 7. The first bulge region 26A is located on the bottom wall side of the gate structure 15 with respect to the depth position of the middle part of the well region 25, and forms the upper end part of the well region 25.

[0089] The first bulge region 26A extends in a strip shape in the second direction Y in accordance with the extension direction of the gate structure 15. With respect to the second direction Y, both ends of the first bulge region 26A may be located on the inner side of the active region 8 relative to both ends of the gate structure 15, or may be located on the peripheral side of the active region 8.

[0090] The first bulge region 26A bulges horizontally from a region directly below the corresponding gate structure 15 to both sides of the corresponding gate structure 15. Specifically, the first bulge region 26A bulges horizontally in an arc shape (circular arc shape) from the sidewall of the corresponding gate structure 15 and overlaps the bottom of the body region 10 in the thickness direction of the second semiconductor layer 7. The first bulge region 26A is formed with a gap from the midpoint between two adjacent gate structures 15 toward the corresponding gate structure 15.

[0091] A first protrusion amount of the first bulging region 26A with respect to the sidewall of the gate structure 15 may be greater than 0 nm and less than or equal to 200 nm. The first protrusion amount may have a value belonging to at least one of the following ranges: greater than 0 nm and less than or equal to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm.

[0092] The first bulging region 26A may have a width of 0.1 μm to 2.5 μm. The width of the first bulging region 26A may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, and 2.25 μm to 2.5 μm.

[0093] The ratio of the depth of the first bulge region 26A to the depth of the well region 25 (first depth ratio) may be greater than 0 and less than or equal to 0.5. The depth of the first bulge region 26A is determined based on the bottom wall of the gate structure 15. The first depth ratio may have a value belonging to at least one of the following ranges: greater than 0 and less than or equal to 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, and 0.4 to 0.5. The first depth ratio is preferably less than 0.5.

[0094] The depth of the first bulge region 26A is smaller than the depth of the gate structure 15 relative to the first main surface 3. The depth of the first bulge region 26A may be greater than 0 μm and less than or equal to 1 μm. The depth of the first bulge region 26A may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, 0.5 μm to 0.6 μm, 0.6 μm to 0.7 μm, 0.7 μm to 0.8 μm, 0.8 μm to 0.9 μm, and 0.9 μm to 1 μm. The depth of the first bulge region 26A is preferably less than or equal to 0.5 μm.

[0095] The second bulge region 26B is located closer to the bottom of the second semiconductor layer 7 than the first bulge region 26A, and forms the bottom of the well region 25. The second bulge region 26B extends in a strip shape in the second direction Y, following the extension direction of the gate structure 15. With respect to the second direction Y, both ends of the second bulge region 26B may be located on the inner side of the active region 8 relative to both ends of the gate structure 15, or may be located on the peripheral side of the active region 8.

[0096] In this embodiment, the second bulge region 26B has a portion located on the bottom wall side of the gate structure 15 corresponding to the depth position of the middle part of the well region 25, and a portion located on the bottom side of the second semiconductor layer 7 corresponding to the depth position of the middle part of the well region 25.

[0097] The second bulge region 26B bulges horizontally from a region directly below the corresponding gate structure 15 to both sides of the corresponding gate structure 15. Specifically, the second bulge region 26B bulges horizontally in an arc shape (circular arc shape) from the sidewall of the corresponding gate structure 15 and overlaps the bottom of the body region 10 in the thickness direction of the second semiconductor layer 7. The curvature of the second bulge region 26B may be less than the curvature of the first bulge region 26A.

[0098] The second bulge region 26B is formed at a distance from the midpoint between two adjacent gate structures 15 toward the corresponding gate structure 15. A second protrusion amount of the second bulge region 26B based on the sidewall of the gate structure 15 is smaller than the first protrusion amount of the first bulge region 26A. The second protrusion amount may be approximately equal to the first protrusion amount or may be larger than the first protrusion amount.

[0099] The second protrusion amount may be greater than 0 nm and less than or equal to 200 nm. The second protrusion amount may have a value belonging to at least one of the ranges of greater than 0 nm and less than or equal to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm.

[0100] The second bulging region 26B may have a width of 0.1 μm to 2.5 μm. The width of the second bulging region 26B may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, and 2.25 μm to 2.5 μm.

[0101] The second bulge region 26B does not necessarily have to protrude outward beyond the sidewall of the gate structure 15. Therefore, the second bulge region 26B may be located in a region below the bottom wall of the gate structure 15 and below the sidewall of the gate structure 15.

[0102] The ratio of the depth of the second bulge region 26B to the depth of the well region 25 (second depth ratio) is calculated by "1 - first depth ratio." The depth of the second bulge region 26B is the depth when the bottom wall of the gate structure 15 is used as the reference. The second depth ratio is preferably 0.5 or more. It is particularly preferable that the second depth ratio be greater than 0.5.

[0103] The depth of the second bulge region 26B is obtained by subtracting the depth of the first bulge region 26A from the depth of the well region 25. In this embodiment, the depth of the second bulge region 26B is smaller than the depth of the gate structure 15 relative to the first main surface 3. The depth of the second bulge region 26B may be larger than the depth of the gate structure 15 relative to the first main surface 3.

[0104] The depth of second bulging region 26B may be 0.5 μm or more and 5 μm or less. The depth of second bulging region 26B may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0105] The constricted region 27 is recessed below the first bulging region 26A in the horizontal direction along the first main surface 3 relative to the first bulging region 26A. The constricted region 27 may be considered to be the lower end of the first bulging region 26A. Specifically, the constricted region 27 forms a connection between the first bulging region 26A and the second bulging region 26B in the region between the first bulging region 26A and the second bulging region 26B, and is recessed in an arc shape horizontally inward from the first bulging region 26A and the second bulging region 26B.

[0106] The constricted region 27 may be located in a region below the bottom wall of the gate structure 15 and may face the bottom wall of the gate structure 15 in the thickness direction. The constricted region 27 may be located outward from the side walls of the gate structure 15. The constricted region 27 may be located in a region closer to the bottom wall of the gate structure 15 with respect to the depth position of the intermediate portion of the well region 25. The constricted region 27 may be located in a region closer to the bottom of the second semiconductor layer 7 with respect to the depth position of the intermediate portion of the well region 25.

[0107] The width of the constricted region 27 is less than the width of the first bulging region 26 A. The width of the constricted region 27 is less than the width of the second bulging region 26 B. The width of the constricted region 27 may be greater than the width of the gate structure 15 or may be less than the width of the gate structure 15.

[0108] The width of the constricted region 27 may be 0.1 μm or more and 2 μm or less. The width of the constricted region 27 may be a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or more, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0109] The multiple well regions 25 each include a first well region 28 that forms a first bulging region 26A, and a second well region 29 that forms a second bulging region 26B. The configuration of the first well region 28 can be obtained by replacing "first bulging region 26A" with "first well region 28" in the above description. The configuration of the second well region 29 can be obtained by replacing "first bulging region 26A" with "second well region 29" in the above description. It may be considered that the first well region 28 includes the first bulging region 26A, and the second well region 29 includes the second bulging region 26B.

[0110] The concentration gradient of the well region 25 will be described below with reference to Fig. 12. Fig. 12 is a graph showing the impurity concentration of the well region 25. In Fig. 12, the vertical axis represents the p-type impurity concentration of the well region 25, and the horizontal axis represents the depth.

[0111] 12, first well region 28 is a high-concentration well region having a relatively high p-type impurity concentration, and is formed by introducing p-type impurities (trivalent elements) into second semiconductor layer 7. First well region 28 has a p-type impurity concentration higher than the n-type impurity concentration of second semiconductor layer 7, and converts the conductivity type of second semiconductor layer 7 from n-type to p-type.

[0112] The p-type impurity concentration of the first well region 28 is higher than the p-type impurity concentration of the body region 10. The first well region 28 contains a second element consisting of a trivalent element in addition to the pentavalent element of the second semiconductor layer 7 (i.e., the first element, nitrogen in this form). The second element may contain at least one of boron and aluminum. The concentration of the first well region 28 is preferably adjusted by a single second element. The second element is preferably aluminum.

[0113] The first well region 28 is made of a random region in which a large amount of trivalent elements are scattered in random directions in the SiC single crystal (second semiconductor layer 7), and has a concentration gradient that increases and decreases downward from the bottom wall of the gate structure 15. The random direction is a direction other than the axial channel of the SiC single crystal (second semiconductor layer 7). The random direction is, for example, a direction intersecting the axial channel (for example, the vertical direction Z).

[0114] The axial channel is a region (channel) in the SiC single crystal (second semiconductor layer 7) where the interatomic distance (atomic spacing) is relatively large, and is surrounded by atomic rows that form a crystal axis extending in the thickness direction (crystal growth direction). In other words, the axial channel is a region in which an area where atomic rows are sparse extends in the thickness direction, and where atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a plan view.

[0115] The axial channel is preferably a region surrounded by a row of atoms along a low-index crystal axis among the crystal axes. The low-index crystal axis is a crystal axis in which the absolute values ​​of "a1," "a2," "a3," and "c" are all expressed as 0 to 2 (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c).

[0116] In this embodiment, the axial channel is composed of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal. That is, the axial channel extends along the c-axis and has the off-direction and off-angle described above. In other words, the axial channel is inclined by the off-angle from the vertical axis toward the off-direction.

[0117] The concentration gradient of the first well region 28 includes an increasing portion 28A, a peak portion 28B, and a decreasing portion 28C within the thickness range of the first well region 28. The increasing portion 28A is a region in which the p-type impurity concentration increases sharply downward from the bottom wall of the gate structure 15.

[0118] Peak portion 28B is a region where the p-type impurity concentration is at its maximum. Peak portion 28B is formed at a depth position in the middle of first well region 28. Decreasing portion 28C is a region where the p-type impurity concentration decreases sharply downward from peak portion 28B.

[0119] The second well region 29 is a low-concentration well region having a p-type impurity concentration lower than the p-type impurity concentration of the first well region 28, and is formed by introducing p-type impurities (trivalent elements) into the second semiconductor layer 7. The second well region 29 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7, and converts the conductivity type of the second semiconductor layer 7 from n-type to p-type.

[0120] The p-type impurity concentration of the second well region 29 may be higher or lower than the p-type impurity concentration of the body region 10. The second well region 29 contains a third element consisting of a trivalent element in addition to the pentavalent element of the second semiconductor layer 7 (i.e., the first element, nitrogen in this embodiment).

[0121] The third element may include at least one of boron and aluminum. The third element (trivalent element) of the second well region 29 may be the same as or different from the second element (trivalent element) of the first well region 28. The concentration of the second well region 29 is preferably adjusted with a single third element. The third element is preferably aluminum.

[0122] The second well region 29 has a concentration gradient different from the concentration gradient of the first well region 28. The second well region 29 is made of a channeling region in which a large amount of trivalent elements are scattered along the axial channel of the SiC single crystal (second semiconductor layer 7), and has a concentration gradient that decreases (monotonically decreases in this form) downward from the bottom wall of the gate structure 15. That is, in this form, the second well region 29 extends along the c-axis of the SiC single crystal and is inclined at the off direction and off angle described above.

[0123] The channeling region is formed by introducing impurity ions into the second semiconductor layer 7 along the axial channel. The impurity ions are introduced into the second semiconductor layer 7 while repeatedly undergoing small-angle scattering due to the channeling effect, which reduces the probability of collision with atomic columns of the SiC single crystal. This results in the formation of a channeling region that maintains a relatively high impurity concentration up to a relatively deep target position. The depth of the channeling region is adjusted by the introduction energy of the impurity ions.

[0124] The second well region 29 has a concentration gradient that gradually decreases from the bottom wall toward the bottom of the gate structure 15. The concentration gradient of the second well region 29 preferably decreases monotonically toward the bottom. The concentration gradient of the second well region 29 includes a gradual portion 29A and a decreasing portion 29B downward from the bottom (lower end) of the first well region 28.

[0125] The gradual decrease portion 29A has a concentration decrease rate that is smaller than that of the decrease portion 28C of the first well region 28, and maintains a constant p-type impurity concentration within a certain depth range. The bottom (lower end) of the first well region 28 and the upper end of the second well region 29 are formed by a concentration transition portion between the decrease portion 28C of the first well region 28 and the gradual decrease portion 29A of the second well region 29.

[0126] The p-type impurity concentration of gradual decrease portion 29A gradually decreases within a concentration range lower than the p-type impurity concentration of decrease portion 29B of first well region 28. In other words, gradual decrease portion 29A (second well region 29) does not have a concentration gradient that increases sharply from first well region 28 (decrease portion 28C).

[0127] The gradual portion 29A may have a concentration decrease rate of 50% or less over a depth range of at least 0.25 μm. The gradual portion 29A may have a concentration decrease rate of 50% or less over a depth range of at least 0.5 μm. The gradual portion 29A may have a concentration decrease rate of 50% or less over a thickness range of 25% of the well region 25.

[0128] The decreasing portion 29B is a portion that forms the bottom of the well region 25 (second well region 29). The decreasing portion 29B has a concentration decrease rate that is greater than that of the gradual portion 29A, and is a portion where the p-type impurity concentration decreases steeply from the gradual portion 29A toward the bottom. The p-type impurity concentration of the decreasing portion 29B decreases monotonically toward the bottom. The concentration decrease rate per unit depth of the decreasing portion 29B is greater than the concentration decrease rate per unit depth of the gradual portion 29A.

[0129] The bottom of the well region 25 (second well region 29), which has the lowest p-type impurity concentration, is directly connected to the second semiconductor layer 7, which has a relatively low n-type impurity concentration. In other words, the bottom of the well region 25 (second well region 29) properly forms the JFET region Tj together with the second semiconductor layer 7.

[0130] The semiconductor device 1A includes a plurality of n-type high-concentration regions 30 formed in the chip 2 (second semiconductor layer 7) in regions on the sides of the plurality of gate structures 15. The plurality of high-concentration regions 30 have a higher n-type impurity concentration than the n-type impurity concentration of the second semiconductor layer 7, and are regions in which the n-type impurity concentration of the second semiconductor layer 7 is increased.

[0131] The multiple high concentration regions 30 may be considered as high concentration portions of the second semiconductor layer 7. The n-type impurity concentration of the multiple high concentration regions 30 can be appropriately compared by comparing it with the n-type impurity concentration on the bottom side of the second semiconductor layer 7. The high concentration regions 30 may also be referred to as "high concentration drift regions."

[0132] The plurality of high concentration regions 30 are formed in regions on both sides of the plurality of gate structures 15. Specifically, the plurality of high concentration regions 30 are formed in regions between the plurality of gate structures 15. In this embodiment, the plurality of high concentration regions 30 are formed in a one-to-one correspondence with the plurality of mesa portions 20.

[0133] The multiple high-concentration regions 30 extend in a strip-like manner in the second direction Y in a plan view, following the extension direction of the multiple gate structures 15. That is, the multiple high-concentration regions 30 extend in a strip-like manner in the second direction Y in a plan view. The multiple high-concentration regions 30 may be formed in a one-to-many correspondence with the multiple mesas 20. In this case, the multiple high-concentration regions 30 may be formed in the corresponding mesa portions 20 at intervals in the second direction Y.

[0134] The multiple high concentration regions 30 are formed in the region on the bottom wall side of the multiple gate structures 15 relative to the bottom of the body region 10 so as to be positioned at least in the thickness range between the bottom of the body region 10 and the bottom walls of the multiple gate structures 15.

[0135] In this embodiment, the multiple high-concentration regions 30 have portions located on the bottom side of the second semiconductor layer 7 relative to the depth positions of the bottom walls of the multiple gate structures 15. In other words, the multiple high-concentration regions 30 are formed in regions on the sides of the multiple well regions 25 within the chip 2 (second semiconductor layer 7).

[0136] The plurality of high-concentration regions 30 are respectively interposed between the plurality of well regions 25 in the region below the plurality of gate structures 15. The plurality of high-concentration regions 30 are connected to one or both (both in this embodiment) of the plurality of adjacent well regions 25. Specifically, the plurality of high-concentration regions 30 form pn junctions with the plurality of well regions 25, respectively.

[0137] The plurality of high-concentration regions 30 may form a charge balance with the plurality of well regions 25. Charge balance refers to a state in which depletion layers extending from pn junctions between the plurality of high-concentration regions 30 and the plurality of well regions 25 are connected by the plurality of high-concentration regions 30.

[0138] According to this configuration, the multiple high-concentration regions 30 form a super junction structure together with the multiple well regions 25. The multiple high-concentration regions 30 do not necessarily have to form a super junction structure together with the multiple well regions 25, and may simply form a body diode structure.

[0139] In this embodiment, the plurality of high concentration regions 30 each include an upper end located on the first main surface 3 side relative to the bottom walls of the plurality of gate structures 15, and a bottom located on the bottom side of the second semiconductor layer 7 relative to the bottom walls of the plurality of gate structures 15. The bottoms of the plurality of high concentration regions 30 are defined by a concentration transition portion where the n-type impurity concentration gradually decreases toward the bottom side of the second semiconductor layer 7.

[0140] The upper ends of the multiple high-concentration regions 30 are electrically connected to the body region 10. The upper ends of the multiple high-concentration regions 30 are connected to one or both (in this embodiment, both) of the multiple adjacent gate structures 15. The upper ends of the multiple high-concentration regions 30 have portions that face the buried electrodes 18 of the corresponding gate structures 15, with the insulating film 17 of the corresponding gate structure 15 interposed therebetween.

[0141] The upper ends of the multiple high concentration regions 30 are formed in a thickness range between the bottom of the body region 10 and the upper ends of the multiple well regions 25. The multiple high concentration regions 30 suppress an increase in p-type impurity concentration in portions along the sidewalls of the multiple gate structures 15, and separate the multiple well regions 25 from the body region 10.

[0142] The bottoms of the multiple high-concentration regions 30 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first major surface 3, and face the first semiconductor layer 6 across a part of the second semiconductor layer 7. The bottoms of the multiple high-concentration regions 30 may be formed at intervals from a depth position of the intermediate portion of the second semiconductor layer 7 toward the first major surface 3, or may be located closer to the bottom of the second semiconductor layer 7 than the depth position of the intermediate portion of the second semiconductor layer 7.

[0143] In this embodiment, the bottoms of the multiple high-concentration regions 30 are located closer to the first main surface 3 than the depth positions of the bottoms of the multiple well regions 25 (second well regions 29). In other words, the bottoms of the multiple high-concentration regions 30 are formed at intervals from the bottoms of the well regions 25 (second well regions 29) toward the first main surface 3, maintaining a configuration in which the well regions 25 (second well regions 29) are directly connected to the second semiconductor layer 7.

[0144] The bottoms of the multiple high-concentration regions 30 are connected to the well region 25 in a region on the bottom side relative to the depth position of the middle part of the multiple well regions 25. Specifically, the bottoms of the multiple high-concentration regions 30 are connected to a region on the bottom side of the second well region 29.

[0145] A specific configuration of the high-concentration region 30 will be described below with reference to Fig. 13. Fig. 13 is a graph showing the impurity concentration of the high-concentration region 30. In Fig. 13, the vertical axis represents the n-type impurity concentration of the high-concentration region 30, and the horizontal axis represents the depth.

[0146] The multiple high concentration regions 30 include a first high concentration region 31 located on the first main surface 3 side relative to the bottom wall of the gate structure 15, and a second high concentration region 32 located on the bottom side of the second semiconductor layer 7 relative to the bottom wall of the gate structure 15.

[0147] The first high concentration region 31 forms the upper end of the high concentration region 30. The first high concentration region 31 extends in a strip shape in the second direction Y following the extension direction of the gate structure 15. With respect to the second direction Y, both ends of the first high concentration region 31 may be located on the inner side of the gate structure 15 with respect to both ends of the gate structure 15, or may be located on the peripheral side of the active region 8.

[0148] The first heavily doped region 31 is positioned in a thickness range between the bottom of the body region 10 and the upper end of the well region 25 (the bottom wall of the gate structure 15), and separates the multiple well regions 25 from the body region 10. In this embodiment, the first heavily doped region 31 has a thickness smaller than the thickness between the bottom of the body region 10 and the bottom wall of the gate structure 15 (the upper end of the well region 25), and is positioned closer to the bottom of the body region 10 than the bottom wall of the gate structure 15. The first heavily doped region 31 faces the buried electrode 18 with the insulating film 17 sandwiched therebetween.

[0149] The first heavily doped region 31 may have a thickness greater than the thickness between the bottom of the body region 10 and the bottom wall of the gate structure 15 (the upper end of the well region 25), and may have a portion located closer to the bottom of the second semiconductor region than the depth position of the bottom wall of the gate structure 15. In this case, the first heavily doped region 31 may have a portion connected to the well region 25.

[0150] The first high-concentration region 31 is a region having a relatively high n-type impurity concentration, and is formed by introducing n-type impurities (pentavalent elements) into the second semiconductor layer 7. The n-type impurity concentration of the first high-concentration region 31 is higher than the p-type impurity concentration of the body region 10. The n-type impurity concentration of the first high-concentration region 31 may be lower than the p-type impurity concentration of the body region 10. The n-type impurity concentration of the first high-concentration region 31 may be lower than the p-type impurity concentration of the first well region 28.

[0151] The first high concentration region 31 contains a fourth element consisting of a pentavalent element in addition to the pentavalent element (i.e., the first element, nitrogen in this form) of the second semiconductor layer 7. The fourth element is an additional pentavalent element to the first element of the second semiconductor layer 7. The fourth element may contain at least one of nitrogen, phosphorus, and arsenic.

[0152] The fourth element in the first high concentration region 31 may be the same type as the first element in the second semiconductor layer 7, or may be a different type from the first element in the second semiconductor layer 7. The fourth element is preferably different from the first element. That is, the first high concentration region 31 preferably contains multiple types of pentavalent elements. The concentration of the first high concentration region 31 is preferably adjusted by a single fourth element. The fourth element is preferably phosphorus. That is, the concentration of the first high concentration region 31 is preferably adjusted by nitrogen and phosphorus.

[0153] The impurity concentration of the first high concentration region 31 is separated from both the impurity concentration of the first well region 28 and the impurity concentration of the second well region 29. The concentration of the second element (trivalent element) of the first well region 28 in the first high concentration region 31 is lower than the concentration of the second element of the first well region 28. The concentration of the third element (trivalent element) of the second well region 29 in the first high concentration region 31 is lower than the concentration of the third element of the second well region 29.

[0154] The first high concentration region 31 does not contain the second element of the first well region 28 or the third element of the second well region 29. "The first high concentration region 31 does not contain the second element or the third element" means that the concentrations of the second element and the third element in the inner part of the first high concentration region 31 are lower than the detection limit, and even if they are detected, they are at the noise level.

[0155] Similarly, the concentration of the fourth element in the first high concentration region 31 in the first well region 28 is lower than the concentration of the fourth element in the first high concentration region 31. The first well region 28 does not contain the fourth element. "The first well region 28 does not contain the fourth element" means that the concentration of the fourth element in the inner part of the first well region 28 is lower than the detection limit, and even if it is detected, it is at the noise level.

[0156] Similarly, the concentration of the fourth element in the first high concentration region 31 in the second well region 29 is lower than the concentration of the fourth element in the first high concentration region 31. The second well region 29 does not contain the fourth element. "The second well region 29 does not contain the fourth element" means that the concentration of the fourth element in the inner part of the second well region 29 is lower than the detection limit, and even if it is detected, it is at the noise level.

[0157] The first high concentration region 31 is composed of a random region in which, in addition to the pentavalent elements of the second semiconductor layer 7, a large amount of additional pentavalent elements are scattered in random directions in the SiC single crystal (second semiconductor layer 7), and has a concentration gradient that increases and decreases downward from the bottom wall of the gate structure 15.

[0158] The concentration gradient of the first high-concentration region 31 includes an increasing portion 31A, a peak portion 31B, and a decreasing portion 31C within the thickness range of the first high-concentration region 31. The increasing portion 31A is a region where the n-type impurity concentration increases steeply downward from the bottom of the body region 10. The peak portion 31B is a region where the n-type impurity concentration is at its maximum. The peak portion 31B is formed at a depth position in the middle portion of the first high-concentration region 31.

[0159] The decrease portion 31C is a region where the n-type impurity concentration decreases steeply downward from the peak portion 31B. The p-type impurity concentration in the decrease portion 31C decreases monotonically toward the bottom. The n-type impurity concentrations in the increase portion 31A, the peak portion 31B, and the decrease portion 31C are all higher than the n-type impurity concentration on the bottom side of the second semiconductor layer 7.

[0160] The thickness of the first high-concentration region 31 may be greater than 0 μm and less than or equal to 1 μm. The thickness of the first high-concentration region 31 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, 0.4 μm to 0.5 μm, 0.5 μm to 0.6 μm, 0.6 μm to 0.7 μm, 0.7 μm to 0.8 μm, 0.8 μm to 0.9 μm, and 0.9 μm to 1 μm.

[0161] For example, the distance between the bottom wall of gate structure 15 and the lower end (bottom) of first heavily doped region 31 may be 0 μm or more and 0.5 μm or less. The distance may have a value belonging to at least one of the ranges of 0 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, and 0.4 μm or more and 0.5 μm or less.

[0162] The second high concentration region 32 forms the bottom of the high concentration region 30. The second high concentration region 32 extends in a strip shape in the second direction Y following the extension direction of the gate structure 15. With respect to the second direction Y, both ends of the second high concentration region 32 may be located on the inner side of the gate structure 15 with respect to both ends of the gate structure 15, or may be located on the peripheral side of the active region 8.

[0163] The second high concentration region 32 has an n-type impurity concentration lower than the n-type impurity concentration of the first high concentration region 31, and is located below the first high concentration region 31. In this embodiment, the second high concentration region 32 has a portion interposed in a region between the plurality of gate structures 15 and a portion interposed in a region between the plurality of well regions 25.

[0164] The second heavily doped region 32 is connected to the side walls of the plurality of gate structures 15 in a region above the bottom walls of the plurality of gate structures 15. The second heavily doped region 32 faces the buried electrode 18 with the insulating film 17 interposed therebetween. The second heavily doped region 32 is electrically connected to both the first well region 28 and the second well region 29 in a region below the bottom walls of the plurality of gate structures 15.

[0165] The second high-concentration region 32 is formed by introducing an n-type impurity (pentavalent element) into the second semiconductor layer 7. The n-type impurity concentration of the second high-concentration region 32 may be higher than the p-type impurity concentration of the body region 10, or may be lower than the p-type impurity concentration of the body region 10. The n-type impurity concentration of the second high-concentration region 32 may be lower than the p-type impurity concentration of the first well region 28. The n-type impurity concentration of the second high-concentration region 32 may be higher than the p-type impurity concentration of the second well region 29, or may be lower than the p-type impurity concentration of the first well region 28.

[0166] The second high concentration region 32 contains a fifth element consisting of a pentavalent element in addition to the pentavalent element (i.e., the first element, nitrogen in this form) of the second semiconductor layer 7. The fifth element is an additional pentavalent element to the first element of the second semiconductor layer 7. The fifth element may contain at least one of nitrogen, phosphorus, and arsenic.

[0167] The fifth element in the second high concentration region 32 may be the same type as the fourth element in the first high concentration region 31, or may be a different type from the fourth element in the first high concentration region 31. The fifth element in the second high concentration region 32 may be the same type as the first element in the second semiconductor layer 7, or may be a different type from the first element in the second semiconductor layer 7.

[0168] The fifth element is preferably different from the first element. That is, the second high concentration region 32 preferably contains a plurality of pentavalent elements. The concentration of the second high concentration region 32 is preferably adjusted by a single fifth element. The fifth element is preferably phosphorus. That is, the concentration of the second high concentration region 32 is preferably adjusted by nitrogen and phosphorus.

[0169] The impurity concentration of the second high concentration region 32 is separated from both the impurity concentration of the first well region 28 and the impurity concentration of the second well region 29. The concentration of the second element (trivalent element) of the first well region 28 in the second high concentration region 32 is lower than the concentration of the second element of the first well region 28. The concentration of the third element (trivalent element) of the second well region 29 in the second high concentration region 32 is lower than the concentration of the third element of the second well region 29.

[0170] The second high concentration region 32 does not contain the second element of the first well region 28 or the third element of the second well region 29. "The second high concentration region 32 does not contain the second element or the third element" means that the concentrations of the second element and the third element in the inner part of the second high concentration region 32 are lower than the detection limit, and even if they are detected, they are at the noise level.

[0171] Similarly, the concentration of the fifth element in the second high concentration region 32 in the first well region 28 is lower than the concentration of the fifth element in the second high concentration region 32. The first well region 28 does not contain the fifth element in the second high concentration region 32. "The first well region 28 does not contain the fifth element" means that the concentration of the fifth element in the inner part of the first well region 28 is lower than the detection limit, and even if it is detected, it is at the noise level.

[0172] In other words, the first well region 28 may contain the base concentration of the second semiconductor layer 7 (i.e., the concentration of the first element, in this embodiment, the nitrogen concentration), but preferably does not contain concentrations of pentavalent elements other than the base concentration of the second semiconductor layer 7.

[0173] Similarly, the concentration of the fifth element in the second high concentration region 32 in the second well region 29 is lower than the concentration of the fifth element in the second high concentration region 32. The second well region 29 does not contain the fifth element in the second high concentration region 32. "The second well region 29 does not contain the fifth element" means that the fifth element in the inner part of the second well region 29 is lower than the detection limit, and even if it is detected, it is at the noise level.

[0174] In other words, the second well region 29 may contain the base concentration of the second semiconductor layer 7 (i.e., the concentration of the first element, in this embodiment, the nitrogen concentration), but preferably does not contain concentrations of pentavalent elements other than the base concentration of the second semiconductor layer 7.

[0175] The second high concentration region 32 has a concentration gradient different from the concentration gradient of the first high concentration region 31. The second high concentration region 32 is composed of a channeling region in which, in addition to the pentavalent element of the second semiconductor layer 7, a large amount of additional pentavalent element is scattered along the axial channel of the SiC single crystal (second semiconductor layer 7), and has a concentration gradient that decreases (monotonically decreases in this form) downward from the first high concentration region 31. That is, in this form, the second high concentration region 32 extends along the c-axis of the SiC single crystal and is inclined at the off direction and off angle described above.

[0176] The concentration gradient of the second high concentration region 32 includes a gradual portion 32A and a decreasing portion 32B extending downward from the bottom (lower end) of the first high concentration region 31. The gradual portion 32A has a concentration decrease rate that is smaller than the concentration decrease rate of the decreasing portion 31C of the first high concentration region 31, and is a portion that maintains a constant n-type impurity concentration over a certain depth range. The bottom (lower end) of the first high concentration region 31 and the upper end of the second high concentration region 32 are formed by a concentration transition portion between the decreasing portion 31C of the first high concentration region 31 and the gradual portion 32A of the second high concentration region 32.

[0177] The n-type impurity concentration of the gradual decrease portion 32A gradually decreases within a concentration range that is lower than the n-type impurity concentration of the decrease portion 31C of the first high concentration region 31. In other words, the gradual decrease portion 32A (second high concentration region 32) does not have a concentration gradient that increases sharply from the first high concentration region 31 (decrease portion 31C).

[0178] The gradual portion 32A may have a concentration decrease rate of 50% or less over a depth range of at least 0.25 μm. The gradual portion 32A may have a concentration decrease rate of 50% or less over a depth range of at least 0.5 μm. The gradual portion 32A may have a concentration decrease rate of 50% or less over a thickness range of 25% of the well region 25.

[0179] The decreasing portion 32B is a portion that forms the bottom of the high-concentration region 30. The decreasing portion 32B has a concentration decrease rate that is greater than that of the gradual portion 32A, and is a portion where the n-type impurity concentration decreases sharply from the gradual portion 32A toward the bottom. The n-type impurity concentration of the decreasing portion 32B decreases monotonically toward the bottom. The concentration decrease rate per unit depth of the decreasing portion 32B is greater than the concentration decrease rate per unit depth of the gradual portion 32A.

[0180] The second high concentration region 32 has a depth greater than the depth of the first high concentration region 31. The depth of the second high concentration region 32 may be smaller than the depth of the second well region 29, or may be greater than the depth of the second well region 29.

[0181] The depth of the second high concentration region 32 may be 0.5 μm or more and 5 μm or less from the bottom (lower end) of the first high concentration region 31. The depth of the second high concentration region 32 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0182] The semiconductor device 1A includes a plurality of n-type source regions 35 formed in the body region 10 in the active region 8. The source regions 35 have a higher n-type impurity concentration than the p-type impurity concentration of the body region 10, and convert the conductivity type of the body region 10 from p-type to n-type.

[0183] The n-type impurity concentration of the source region 35 is higher than the n-type impurity concentration of the second semiconductor layer 7. The n-type impurity concentration of the source region 35 is higher than the n-type impurity concentration of the second high concentration region 32. The n-type impurity concentration of the source region 35 is higher than the n-type impurity concentration of the first high concentration region 31.

[0184] The plurality of source regions 35 are formed in the plurality of mesas 20 in the surface layer portion of the body region 10. In this embodiment, the plurality of source regions 35 are formed in a one-to-many correspondence with the plurality of mesas 20, respectively.

[0185] The multiple source regions 35 are formed in the corresponding mesa portions 20 at intervals in the second direction Y, and are adjacent to two gate structures 15 corresponding to the first direction X. In this embodiment, the multiple source regions 35 each extend in a strip shape in the second direction Y in accordance with the extension direction of the multiple gate structures 15 in plan view.

[0186] The plurality of source regions 35 on one side in the first direction X face the plurality of source regions 35 on the other side in the first direction X, with a corresponding gate structure 15 sandwiched between them. That is, the plurality of source regions 35 are arranged in a line in the first direction X in a planar view. The plurality of source regions 35 are arranged in a matrix with intervals in the first direction X and the second direction Y in a planar view.

[0187] The plurality of source regions 35 on one side in the first direction X may face regions between the plurality of source regions 35 on the other side in the first direction X, with a corresponding gate structure 15 sandwiched therebetween. In other words, the plurality of source regions 35 may be arranged in a staggered pattern at intervals in the first direction X and the second direction Y in a plan view.

[0188] The source regions 35 each have a thickness (depth) less than the thickness (depth) of the body region 10, and are formed at intervals from the bottom of the body region 10 toward the first main surface 3. The source regions 35 face the second semiconductor layer 7 (high-concentration region 30) with a part (bottom) of the body region 10 between them.

[0189] The plurality of source regions 35 each have a bottom located closer to the bottom of the body region 10 than the height of the electrode surfaces of the plurality of buried electrodes 18. Specifically, the plurality of source regions 35 each have a portion located closer to the bottom walls of the plurality of trenches 16 than the electrode surfaces of the plurality of buried electrodes 18, and a portion located closer to the first main surface 3 than the electrode surfaces of the plurality of buried electrodes 18.

[0190] Each of the plurality of source regions 35 has a portion facing the corresponding buried electrode 18 with the corresponding insulating film 17 interposed therebetween, and a portion facing the buried insulator 19 with the corresponding insulating film 17 interposed therebetween. Each of the plurality of source regions 35 has a portion located on the bottom wall side of the plurality of trenches 16 with respect to the insulating surfaces of the plurality of buried insulators 19, and a portion located on the first main surface 3 side with respect to the insulating surfaces of the plurality of buried insulators 19. In this embodiment, each of the plurality of source regions 35 has a portion exposed from the opening end of the corresponding trench 16.

[0191] The source region 35 has a thickness (depth) greater than the thickness between the bottom of the body region 10 and the bottom of the source region 35. The thickness of the source region 35 may be less than the thickness between the bottom of the body region 10 and the bottom of the source region 35. The thickness (depth) of the peripheral portions of the multiple source regions 35 gradually decreases along the second direction Y from the bottom side of the body region 10 toward the first main surface 3. The multiple source regions 35, together with the second semiconductor layer 7 (high concentration region 30), define a channel CH that serves as a current path on the bottom side of the body region 10 (see FIG. 10 ).

[0192] The channel CH may have a channel length greater than 0 nm and less than or equal to 300 nm. The channel length is the distance between the bottom of the body region 10 and the bottom of the source region 35. The channel length may have a value belonging to at least one of the following ranges: greater than 0 nm and less than or equal to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, and 250 nm to 300 nm.

[0193] The semiconductor device 1A includes a plurality of p-type high concentration body regions 36 partially formed within the body region 10 in the active region 8. The high concentration body regions 36 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 10. The high concentration body regions 36 may be considered as high concentration portions of the body region 10.

[0194] The p-type impurity (trivalent element) in the high-concentration body region 36 may be the same type as the p-type impurity (trivalent element) in the body region 10, or may be different from the p-type impurity (trivalent element) in the body region 10. The p-type impurity (trivalent element) in the high-concentration body region 36 may be either or both of boron and aluminum.

[0195] The p-type impurity concentration of the high-concentration body region 36 is higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the high-concentration body region 36 is lower than the n-type impurity concentration of the source region 35. The p-type impurity concentration of the high-concentration body region 36 is lower than the p-type impurity concentration of the first well region 28. The p-type impurity concentration of the high-concentration body region 36 may be higher than the p-type impurity concentration of the second well region 29 or may be lower than the p-type impurity concentration of the second well region 29.

[0196] The p-type impurity concentration of the high-concentration body region 36 may be higher than the n-type impurity concentration of the first high-concentration region 31, or may be lower than the n-type impurity concentration of the first high-concentration region 31. The p-type impurity concentration of the high-concentration body region 36 may be higher than the n-type impurity concentration of the second high-concentration region 32, or may be lower than the n-type impurity concentration of the second high-concentration region 32.

[0197] In this embodiment, the multiple high-concentration body regions 36 are formed in a one-to-one correspondence with the multiple mesas 20. The multiple high-concentration body regions 36 extend in a strip shape in the second direction Y in the corresponding mesa 20, following the extension direction of the multiple gate structures 15.

[0198] The plurality of high-concentration body regions 36 are formed in the bottom of the body region 10 in the plurality of mesas 20. Specifically, the plurality of high-concentration body regions 36 are formed in the thickness range of the bottom of the plurality of source regions 35 and the bottom of the body region 10, respectively.

[0199] In this embodiment, the multiple high-concentration body regions 36 are formed at intervals from the bottoms of the multiple source regions 35 toward the bottom of the body region 10, and face the multiple source regions 35 with part of the body region 10 sandwiched between them in the thickness direction. In other words, the multiple high-concentration body regions 36 are not directly connected to the multiple source regions 35. The multiple high-concentration body regions 36 may be connected to the multiple source regions 35.

[0200] The bottoms of the multiple high-concentration body regions 36 may be located closer to the first major surface 3 than the bottom of the body region 10 and may face the second semiconductor layer 7 (high-concentration region 30) across a portion of the body region 10. The bottoms of the multiple high-concentration body regions 36 may be located closer to the bottom wall of the gate structure 15 than the bottom of the body region 10 and may be electrically connected to the second semiconductor layer 7 (high-concentration region 30). In this case, the bottoms of the multiple high-concentration body regions 36 may be considered to form part of the bottom of the body region 10.

[0201] The multiple high-concentration body regions 36 are located closer to the bottom of the body region 10 than the depth positions of the multiple buried insulators 19. In this embodiment, the multiple high-concentration body regions 36 are formed at intervals from the depth positions of the electrode surfaces of the multiple buried electrodes 18 toward the bottom walls of the multiple gate structures 15 (trenches 16), and do not face the multiple buried insulators 19 in the horizontal direction. Of course, the multiple high-concentration body regions 36 may be located closer to the first main surface 3 than the depth positions of the electrode surfaces of the multiple buried electrodes 18, and may have portions facing the multiple buried insulators 19 in the horizontal direction.

[0202] The plurality of high-concentration body regions 36 may be located on the bottom wall side of the plurality of gate structures 15 relative to the depth positions of the intermediate portions of the plurality of gate structures 15. The plurality of high-concentration body regions 36 may have portions located on the first main surface 3 side relative to the depth positions of the intermediate portions of the plurality of gate structures 15.

[0203] The multiple high-concentration body regions 36 are formed at intervals in the horizontal direction from the multiple gate structures 15 and face the multiple gate structures 15 in the horizontal direction with a portion of the body region 10 sandwiched therebetween. That is, the multiple high-concentration body regions 36 define multiple channels CH extending along the sidewalls of the multiple gate structures 15 between themselves and the sidewalls of the multiple gate structures 15 (see FIG. 10 ). Of course, the multiple high-concentration body regions 36 may be connected to either or both of the multiple adjacent gate structures 15 to form one or both of the channels CH.

[0204] The plurality of high concentration body regions 36 each have a thickness (depth) less than the thickness (depth) of the plurality of source regions 35. In this embodiment, the depth of the high concentration body regions 36 is less than the channel length.

[0205] The ratio of the thickness of the high-concentration body region 36 to the thickness of the body region 10 may be greater than 0 and less than or equal to 0.5. The thickness ratio may have a value belonging to at least one of the following ranges: greater than 0 and less than or equal to 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, and 0.4 to 0.5.

[0206] The depth of the high-concentration body region 36 may be greater than 0 nm and less than or equal to 300 nm. The depth of the high-concentration body region 36 may have a value belonging to at least one of the following ranges: greater than 0 nm and less than or equal to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, and 250 nm to 300 nm.

[0207] Fig. 14 is a graph showing the impurity concentration of the body region 10. In Fig. 14, the vertical axis represents the p-type impurity concentration, and the horizontal axis represents the horizontal distance from the sidewall of the gate structure 15 to the midpoint of the mesa portion 20. In Fig. 14, the sidewall of the gate structure 15 is set as the zero point.

[0208] 14 shows a first concentration gradient G1 (see dashed line) and a second concentration gradient G2 (see solid line). The first concentration gradient G1 is the concentration gradient of the p-type impurity concentration (body region 10) when the high-concentration body region 36 is not present. The second concentration gradient G2 is the concentration gradient of the p-type impurity concentration (body region 10) when the high-concentration body region 36 is present.

[0209] With reference to the first concentration gradient G1, the p-type impurity concentration has a substantially uniform concentration gradient in the horizontal direction starting from the sidewall of the gate structure 15. On the other hand, with reference to the second concentration gradient G2, the p-type impurity concentration has a concentration gradient that increases (specifically, monotonically increases) in the horizontal direction starting from the sidewall of the gate structure 15.

[0210] In the horizontal direction, the second concentration gradient G2 has a minimum value at the end and a maximum value at the center, the minimum value of which is formed by the p-type impurity concentration in the body region 10, and the maximum value of which is formed by the p-type impurity concentration in the high-concentration body region 36.

[0211] The minimum value of the p-type impurity concentration is formed by the portion (end portion) of the body region 10 that contacts the sidewall of the gate structure 15. In other words, the minimum value of the p-type impurity concentration is formed by the body region 10 alone. The maximum value of the p-type impurity concentration is a region that includes the body region 10 and the high-concentration body region 36, and is located in the center of the mesa portion 20.

[0212] The concentration ratio of the maximum p-type impurity concentration to the minimum p-type impurity concentration is greater than 1 and not greater than 10. The concentration ratio may have a value belonging to at least one of the ranges greater than 1 and not greater than 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10. The concentration ratio is preferably 5 or less.

[0213] The semiconductor device 1A includes a plurality of contact regions 37 formed in the chip 2 (second semiconductor layer 7) in the active region 8. A source potential is applied to the contact regions 37. The contact regions 37 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the contact regions 37 is higher than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the contact regions 37 is higher than the p-type impurity concentration of the body high-concentration region 36.

[0214] The p-type impurity concentration of the contact region 37 is higher than the p-type impurity concentration of the second well region 29. The p-type impurity concentration of the contact region 37 may be higher than the p-type impurity concentration of the first well region 28, or may be lower than the p-type impurity concentration of the first well region 28. The p-type impurity concentration of the contact region 37 may be higher than the n-type impurity concentration of the source region 35, or may be lower than the n-type impurity concentration of the source region 35.

[0215] The plurality of contact regions 37 are formed in regions along the plurality of gate structures 15. The plurality of contact regions 37 are formed in a one-to-many correspondence with the plurality of gate structures 15. The plurality of contact regions 37 are formed at intervals in the second direction Y following the extension direction of the corresponding gate structures 15.

[0216] Specifically, the plurality of contact regions 37 are respectively interposed in regions between the plurality of source regions 35. The plurality of contact regions 37 may be connected to the plurality of source regions 35 in the second direction Y. The plurality of contact regions 37 may be formed at intervals from the plurality of source regions 35 in the second direction Y. In this case, the plurality of contact regions 37 may face the plurality of source regions 35 with a part of the body region 10 interposed therebetween.

[0217] With respect to one and the other gate structures 15, the plurality of contact regions 37 along one gate structure 15 face the plurality of contact regions 37 along the other gate structure 15 in the first direction X in plan view. In other words, the plurality of contact regions 37 are generally arranged in a matrix at intervals in the first direction X and the second direction Y in plan view.

[0218] In plan view, one of the plurality of contact regions 37 may face a region between the other of the plurality of contact regions 37 in the first direction X. In other words, the plurality of contact regions 37 may be generally arranged in a staggered pattern with intervals in the first direction X and the second direction Y in plan view.

[0219] The contact regions 37 may extend in a strip shape in the second direction Y in a plan view, following the extension direction of the gate structures 15. The lengths of the contact regions 37 in the second direction Y may be equal to each other or may be different from each other. The lengths of the contact regions 37 in the second direction Y are adjusted depending on the area of ​​the channel to be formed.

[0220] The channel area is the total area of ​​the portions of the source regions 35 that are exposed from the regions between the gate structures 15. That is, the channel area increases or decreases depending on the ratio of the total planar area of ​​the contact regions 37. It is preferable that the total planar area of ​​the contact regions 37 is less than the channel area.

[0221] That is, in the region between the plurality of gate structures 15, the total planar area of ​​the plurality of contact regions 37 is preferably less than the planar area of ​​the plurality of source regions 35. With such a configuration, an increase in the resistance value (on-resistance) due to a short channel is suppressed.

[0222] The length of the contact region 37 may be greater than or less than the width of the gate structure 15. The length of the contact region 37 may be greater than or less than the pitch between the plurality of gate structures 15.

[0223] The interval between the multiple contact regions 37 may be greater than the width of the gate structures 15 or may be smaller than the width of the gate structures 15. The interval between the contact regions 37 may be greater than the pitch between the multiple gate structures 15 or may be smaller than the pitch between the multiple gate structures 15.

[0224] The contact regions 37 each include a first region 37A, a second region 37B, and a third region 37C. The first region 37A extends along the bottom wall of the corresponding gate structure 15. The first region 37A is interposed in a region between the corresponding gate structure 15 and the bottom of the corresponding well region 25, and is connected to the bottom wall of the corresponding gate structure 15 and the corresponding well region 25.

[0225] The first region 37A has a thickness greater than that of the first well region 28, and has a bottom located closer to the bottom of the second well region 29 than the depth position of the lower end (bottom) of the first well region 28. The thickness of the first region 37A is the thickness of the first region 37A in the vertical direction Z, with the bottom wall of the gate structure 15 as the reference.

[0226] The bottom of the first region 37A is formed at a distance from the bottom of the second well region 29 toward the bottom wall of the gate structure 15, and faces the second semiconductor layer 7 across a part of the second well region 29. The bottom of the first region 37A may be located on the bottom wall side of the gate structure 15 relative to the depth position of the intermediate portion of the second well region 29. The bottom of the first region 37A may be located on the bottom side of the second well region 29 relative to the depth position of the intermediate portion of the second well region 29.

[0227] The first region 37A is connected to the first well region 28 and the second well region 29, and increases the p-type impurity concentration of the first well region 28 and the p-type impurity concentration of the second well region 29. The first region 37A may have a thickness less than that of the first well region 28, and may be formed at a distance from the depth position of the lower end of the first well region 28 toward the bottom wall of the gate structure 15. In this case, the first region 37A may face the second well region 29 with a part of the first well region 28 in between.

[0228] The first region 37A has a width greater than that of the gate structure 15, and extends horizontally from a region directly below the corresponding gate structure 15 to both sides of the corresponding gate structure 15. Specifically, the first region 37A extends horizontally in an arc shape (circular arc shape) from the sidewall of the corresponding gate structure 15, and faces the body region 10 in the thickness direction. The first region 37A may face the high-concentration body region 36 in the thickness direction.

[0229] The curvature of the first region 37A may be greater than or less than the curvature of the first bulging region 26A. The curvature of the first region 37A may be greater than or less than the curvature of the second bulging region 26B.

[0230] The protrusion amount of the first region 37A relative to the sidewall of the gate structure 15 may be greater than or less than the protrusion amount of the first bulging region 26A. The protrusion amount of the first region 37A may be greater than or less than the protrusion amount of the second bulging region 26B.

[0231] The second region 37B is a portion extending along the sidewall of the gate structure 15. The second region 37B is connected to the first region 37A on the bottom wall side of the gate structure 15, and is connected to the body region 10 on the first main surface 3 side. In other words, the second region 37B electrically connects the corresponding well region 25 to the body region 10. This prevents the well region 25 from being electrically floating, and improves the electrical response characteristics of the well region 25.

[0232] The second region 37B may be connected to the high-concentration body region 36 in the body region 10. The second region 37B may be formed at a distance from the high-concentration body region 36. The second region 37B has a thickness less than the thickness of the first region 37A. The thickness of the second region 37B is the horizontal thickness of the second region 37B relative to the sidewall of the gate structure 15.

[0233] The third region 37C is a portion that extends in a layer shape along the first main surface 3 in the surface layer portion of the first main surface 3 and is exposed from the first main surface 3. In other words, the third region 37C forms the upper end portion of the contact region 37. In this embodiment, the upper end portion of the third region 37C is exposed from the sidewall of the trench 16 at the opening end of the trench 16.

[0234] The third region 37C is formed integrally with the third region 37C of the adjacent contact region 37. In other words, the multiple contact regions 37 are electrically connected to one another via the multiple third regions 37C.

[0235] The third region 37C has a thickness (depth) less than the thickness (depth) of the body region 10, and faces the high-concentration body region 36 across a portion (bottom) of the body region 10. The thickness of the third region 37C is the thickness of the third region 37C in the vertical direction Z relative to the first major surface 3. The third region 37C faces the second semiconductor layer 7 (high-concentration region 30) in the thickness direction.

[0236] The third region 37C has a bottom located on the bottom side of the body region 10 relative to the height position of the electrode surfaces of the multiple buried electrodes 18. Specifically, the third region 37C has a portion located on the bottom wall side of the multiple trenches 16 relative to the electrode surfaces of the multiple buried electrodes 18, and a portion located on the first main surface 3 side relative to the electrode surfaces of the multiple buried electrodes 18.

[0237] The third region 37C has a portion facing the corresponding buried electrode 18 across the corresponding insulating film 17, and a portion facing the buried insulator 19 across the corresponding insulating film 17. The third region 37C has a portion located on the bottom wall side of the trenches 16 with respect to the insulating surfaces of the buried insulators 19, and a portion located on the first main surface 3 side with respect to the insulating surfaces of the buried insulators 19. In this embodiment, the third region 37C has a portion exposed from the opening end of the corresponding trench 16.

[0238] The thickness of the third region 37C is greater than the thickness of the second region 37B. The thickness of the third region 37C may be approximately equal to the thickness of the first region 37A. The thickness of the third region 37C may be greater than the thickness of the first region 37A or may be less than the thickness of the first region 37A. The thickness of the third region 37C is less than the thickness (depth) of the source region 35. Therefore, the third region 37C has a bottom located closer to the first main surface 3 than the bottom of the source region 35.

[0239] The thickness of the third region 37C may be greater than the thickness of the source region 35. The thickness of the third region 37C may be less than the thickness between the bottom of the body region 10 and the bottom of the third region 37C. The thickness of the third region 37C may be less than the thickness between the bottom of the body region 10 and the bottom of the third region 37C.

[0240] The semiconductor device 1A includes a p-type outer well region 40 formed in a surface layer portion of the first main surface 3 in the peripheral region 9 (the peripheral portion of the first main surface 3). A source potential is applied to the outer well region 40. The outer well region 40 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the outer well region 40 may be higher than the p-type impurity concentration of the body region 10, or may be lower than the p-type impurity concentration of the body region 10.

[0241] The p-type impurity concentration of the outer well region 40 is lower than the p-type impurity concentration of the contact region 37. The p-type impurity concentration of the outer well region 40 is lower than the p-type impurity concentration of the first well region 28. The p-type impurity concentration of the outer well region 40 may be higher than the p-type impurity concentration of the second well region 29, or may be lower than the p-type impurity concentration of the second well region 29.

[0242] The outer well region 40 is formed in a surface layer portion of the second semiconductor layer 7 and extends in a layered manner along the first main surface 3. The outer well region 40 is formed at an interval from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 to the inward side (active region 8 side) of the first main surface 3. The outer well region 40 extends in a band shape along the periphery of the first main surface 3 (periphery of the active region 8) in a plan view.

[0243] In this embodiment, the outer well region 40 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 8) of the first main surface 3. In other words, the outer well region 40 collectively surrounds the multiple gate structures 15. The outer well region 40 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0244] The outer well region 40 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer well region 40 defines the boundary between the active region 8 and the outer peripheral region 9. The inner edge portion of the outer well region 40 is connected to ends of the multiple gate structures 15 in a portion extending in the first direction X.

[0245] The inner edge of the outer well region 40 may be located closer to the inner side of the plurality of gate structures 15 than the ends of the plurality of gate structures 15. The inner edge of the outer well region 40 may have a portion located in a region between the plurality of gate structures 15 and connected to the body region 10. The outer edge of the outer well region 40 is formed spaced inward from the periphery of the chip 2 and extends approximately parallel to the inner edge of the outer well region 40.

[0246] The outer well region 40 may have a width greater than 0 μm and less than 300 μm. The width of the outer well region 40 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0247] The outer well region 40 is formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 across a part of the second semiconductor layer 7. The outer well region 40 may be formed at a distance from the depth position of the intermediate portion of the second semiconductor layer 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor layer 7 (toward the second main surface 4) with respect to the depth position of the intermediate portion of the second semiconductor layer 7.

[0248] In this embodiment, the outer well region 40 is formed at an interval toward the first main surface 3 from the depth position of the bottom walls of the plurality of gate structures 15. The outer well region 40 may be formed deeper than the body region 10, or may be formed shallower than the body region 10.

[0249] The outer well region 40 may have a portion located on the bottom side of the second semiconductor layer 7 with respect to the depth positions of the bottom walls of the plurality of gate structures 15. In this case, the outer well region 40 may be connected to either or both of the first well region 28 and the second well region 29.

[0250] The outer well region 40 forms a pn junction with the second semiconductor layer 7. The outer well region 40 spreads a depletion layer into the second semiconductor layer 7 when a reverse bias voltage is applied. The depletion layer in the outer well region 40 spreads in the horizontal and thickness directions and integrates with the depletion layers spreading from the body region 10 and the well region 25. The outer well region 40 expands the depletion layers spreading from the body region 10 and the well region 25 toward the peripheral edge of the first main surface 3, thereby reducing the electric field intensity (electric field concentration) in the peripheral portion (peripheral region 9) of the first main surface 3.

[0251] The semiconductor device 1A includes a main surface insulating film 41 that selectively covers the first main surface 3. The main surface insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 41 preferably includes the same type of insulating material as the insulating film 17. In this embodiment, the main surface insulating film 41 has a single-layer structure made of a silicon oxide film. The main surface insulating film 41 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0252] The main surface insulating film 41 covers the first main surface 3 in the peripheral region 9 in a film form. Specifically, the main surface insulating film 41 covers the outer well region 40 in the peripheral region 9. The main surface insulating film 41 is extended from the peripheral region 9 to the active region 8, and is selectively connected to the insulating films 17 of the plurality of gate structures 15 in the peripheral portion of the active region 8, exposing the buried electrodes 18 of the plurality of gate structures 15.

[0253] In this embodiment, the main surface insulating film 41 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. The main surface insulating film 41 may be formed at an interval inward from the first to fourth side surfaces 5A to 5D, exposing the periphery of the first main surface 3.

[0254] The semiconductor device 1A includes one or more (in this embodiment, multiple) gate wirings 42 arranged on the first main surface 3 in the peripheral region 9. The multiple gate wirings 42 apply a gate potential to the multiple gate structures 15. The multiple gate wirings 42 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. It is preferable that the multiple gate wirings 42 have the same conductivity type as the conductivity type of the buried electrodes 18 of the multiple gate structures 15.

[0255] The plurality of gate wirings 42 are disposed on the main surface insulating film 41. The plurality of gate wirings 42 are selectively routed on the main surface insulating film 41 at intervals from the periphery of the first main surface 3 toward the active region 8, and face the outer well region 40 with the main surface insulating film 41 in between.

[0256] The multiple gate wirings 42 include a gate wiring 42 on one side in the second direction Y and a gate wiring 42 on the other side in the second direction Y. One of the gate wirings 42 is formed in a band shape with ends extending in the first direction X so as to intersect (specifically, perpendicular to) one ends of the multiple gate structures 15. The other gate wiring 42 is formed in a band shape with ends extending in the first direction X so as to intersect (specifically, perpendicular to) the other ends of the multiple gate structures 15.

[0257] The plurality of gate wirings 42 each have an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portions of the plurality of gate wirings 42 cover one end or the other end of the plurality of gate structures 15 and are mechanically and electrically connected to the plurality of gate structures 15. Specifically, the plurality of gate wirings 42 are mechanically and electrically connected to the plurality of buried electrodes 18. In this embodiment, the plurality of gate wirings 42 are formed integrally with the plurality of buried electrodes 18 as lead-out portions of the plurality of buried electrodes 18.

[0258] In this embodiment, the outer edges of the plurality of gate wirings 42 are spaced apart from the outer edge of the outer well region 40 toward the active region 8. The plurality of gate wirings 42 may be drawn out toward the periphery of the first main surface 3 beyond the outer edge of the outer well region 40, and may have a portion facing the second semiconductor layer 7 with the main surface insulating film 41 interposed therebetween.

[0259] The semiconductor device 1A may include a single gate wiring 42. In this case, the gate wiring 42 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view. For example, the gate wiring 42 may have a portion extending along the first side surface 5A, a portion extending along the second side surface 5B, and a portion extending along the third side surface 5C, and may intersect (specifically, perpendicular to) both one end and the other end of the plurality of gate structures 15.

[0260] In this case, the gate wiring 42 may have a portion extending along the fourth side surface 5D. Furthermore, the portion of the gate wiring 42 extending in the second direction Y may be mechanically and electrically connected to one or both of the plurality of gate structures 15 (buried electrodes 18) arranged on both sides in the first direction X.

[0261] The gate wiring 42 may be formed in a band shape with four sides parallel to the periphery of the first main surface 3 and may surround a plurality of gate structures 15 (active regions 8). The gate wiring 42 may be formed in an endless polygonal ring shape (e.g., a quadrangular ring) in plan view having four sides parallel to the periphery of the first main surface 3. The gate wiring 42 may have an edge portion that connects a portion extending in the first direction X and a portion extending in the second direction Y in plan view in an arc shape (preferably a quadrant arc shape).

[0262] The semiconductor device 1A includes an insulating interlayer film 43 that covers the main surface insulating film 41. The interlayer film 43 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 43 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 43 preferably includes a silicon oxide film.

[0263] The interlayer film 43 may contain an insulating material different from that of the main surface insulating film 41, or may contain the same type of insulating material as that of the main surface insulating film 41. In this embodiment, the interlayer film 43 contains a silicon oxide film having properties different from those of the main surface insulating film 41. The interlayer film 43 may have a single layer structure or a multilayer structure including at least one of an NSG film, a PSG film, and a BPSG film.

[0264] The interlayer film 43 preferably has a single layer structure or a laminated structure including at least an NSG film. The interlayer film 43 may have a laminated structure including an NSG film and a PSG film laminated in this order from the chip 2 side. The interlayer film 43 may have a laminated structure including an NSG film, a PSG film, and a BPSG film laminated in this order from the chip 2 side.

[0265] The interlayer film 43 covers the first main surface 3 in a film-like manner, sandwiching the main surface insulating film 41. The interlayer film 43 covers the outer well region 40 in the peripheral region 9, sandwiching the main surface insulating film 41. In this embodiment, the interlayer film 43 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. The interlayer film 43 may be formed spaced inward from the first to fourth side surfaces 5A to 5D, exposing the periphery of the first main surface 3.

[0266] The interlayer film 43 covers the gate wiring 42 in the peripheral region 9. The interlayer film 43 is drawn from the peripheral region 9 to the active region 8, and covers both ends of the plurality of gate structures 15 in the periphery of the active region 8. Specifically, the interlayer film 43 covers the plurality of buried electrodes 18 at both ends of the plurality of gate structures 15, and is connected to the plurality of buried insulators 19.

[0267] The interlayer film 43 may have a thickness of 0.5 μm or more and 3 μm or less. The thickness of the interlayer film 43 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0268] The semiconductor device 1A includes one or more (one in this embodiment) source openings 44 formed in the interlayer film 43. The source openings 44 expose the plurality of gate structures 15 and the plurality of mesa portions 20 collectively in the inner part of the active region 8.

[0269] The source openings 44 are formed at intervals inward from both ends of the plurality of gate structures 15 to the first main surface 3, exposing the inner portions of the plurality of gate structures 15 and the inner portions of the plurality of mesa portions 20. In this embodiment, the source openings 44 are formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in plan view.

[0270] The semiconductor device 1A includes the aforementioned source electrode 45 disposed on the first main surface 3. The source electrode 45 may also be referred to as a "first main surface electrode," a "first terminal (electrode)," a "first pad (electrode)," a "source pad (electrode)," or the like. The source electrode 45 is disposed on the interlayer film 43.

[0271] In this embodiment, the source electrode 45 has a first pad portion 45 a, a second pad portion 45 b, and a third pad portion 45 c. The first pad portion 45 a has a relatively large planar area and forms the main body of the source electrode 45. In this embodiment, the first pad portion 45 a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first main surface 3.

[0272] The second pad portion 45b has a planar area smaller than that of the first pad portion 45a, and is drawn out in a strip shape (rectangular shape) from one end of the first pad portion 45a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 45c has a planar area smaller than that of the first pad portion 45a, and is drawn out in a strip shape (rectangular shape) from the other end of the first pad portion 45a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 45b in the second direction Y.

[0273] The planar area of ​​the third pad portion 45c may be approximately equal to the planar area of ​​the second pad portion 45b. The planar area of ​​the third pad portion 45c may be larger than the planar area of ​​the second pad portion 45b, or may be smaller than the planar area of ​​the second pad portion 45b. Either or both of the second pad portion 45b and the third pad portion 45c may be used as a terminal portion for monitoring current.

[0274] The source electrode 45 does not necessarily have to have both the second pad portion 45 b and the third pad portion 45 c at the same time. The source electrode 45 may have only one of the second pad portion 45 b and the third pad portion 45 c. The source electrode 45 may be composed of only the first pad portion 45 a, and may not have both the second pad portion 45 b and the third pad portion 45 c.

[0275] The source electrode 45 covers the entire region of the interlayer film 43 where the source opening 44 is formed, and extends into the source opening 44 from above the interlayer film 43. The source electrode 45 has a portion that covers the interlayer film 43 in a film-like manner, a portion that covers the wall surface of the source opening 44 in a film-like manner, and a portion that covers the first main surface 3 within the source opening 44 in a film-like manner.

[0276] The source electrode 45 has a portion covering the plurality of gate structures 15 in the source opening 44 and a portion covering the plurality of mesa portions 20. The source electrode 45 directly covers the plurality of buried insulators 19 in the portion covering the plurality of gate structures 15, and is electrically separated from the plurality of buried electrodes 18 by the plurality of buried insulators 19.

[0277] In this embodiment, the source electrode 45 extends into the trenches 16 from above the first main surface 3 and covers the embedded insulators 19 in the trenches 16. The source electrode 45 has a portion that covers the insulating surfaces of the embedded insulators 19 in a region on the bottom wall side of the trenches 16 relative to the height position of the first main surface 3.

[0278] The source electrode 45 has portions that cover the sidewalls and open ends of the trenches 16 within the trenches 16. The source electrode 45 is mechanically and electrically connected to the source regions 35 and the contact regions 37 in the portions that cover the sidewalls and open ends of the trenches 16. The source electrode 45 is mechanically and electrically connected to the source regions 35 and the contact regions 37 in the portions that cover the mesa portions 20.

[0279] The source electrode 45 has a peripheral portion facing the ends (both ends) of the multiple gate structures 15 with the interlayer film 43 interposed therebetween. The peripheral portion of the source electrode 45 may be drawn from the active region 8 to the peripheral region 9 and face one or more gate wirings 42 with the interlayer film 43 interposed therebetween. The peripheral portion of the source electrode 45 may face the outer well region 40 with the interlayer film 43 interposed therebetween.

[0280] In this embodiment, the source electrode 45 has a laminated structure including a lower electrode film 46 and a main electrode film 47, which are laminated in this order from the chip 2 side. In this embodiment, the lower electrode film 46 has a laminated structure including a first electrode film 48 and a second electrode film 49.

[0281] In this embodiment, the first electrode film 48 includes a Ti film, and the second electrode film 49 includes a TiN film. The lower electrode film 46 does not necessarily have a laminated structure, and may have a single-layer structure consisting of either the first electrode film 48 (Ti film) or the second electrode film 49 (TiN film).

[0282] The first electrode film 48 has a thickness less than the thickness of the interlayer film 43. The thickness of the first electrode film 48 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 48 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0283] The second electrode film 49 has a thickness less than that of the interlayer film 43. The thickness of the second electrode film 49 is preferably greater than that of the first electrode film 48. The thickness of the second electrode film 49 may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 49 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.

[0284] The first electrode film 48 covers the entire region of the interlayer film 43 where the source opening 44 is formed, and extends into the source opening 44 from above the interlayer film 43. The first electrode film 48 has a portion that covers the insulating main surface of the interlayer film 43 in a film-like manner, a portion that covers the wall surface of the source opening 44 in a film-like manner, and a portion that covers the first main surface 3 within the source opening 44 in a film-like manner.

[0285] The first electrode film 48 has a portion covering the plurality of gate structures 15 in the source opening 44 and a portion covering the plurality of mesa portions 20. The first electrode film 48 directly covers the plurality of buried insulators 19 in the portion covering the plurality of gate structures 15, and is electrically isolated from the plurality of buried electrodes 18 by the plurality of buried insulators 19.

[0286] In this embodiment, the first electrode film 48 enters the trenches 16 from above the first main surface 3 and covers the embedded insulators 19 in the trenches 16. In this embodiment, the first electrode film 48 has a portion that covers the insulating surfaces of the embedded insulators 19 in a region on the bottom wall side of the trenches 16 relative to the height position of the first main surface 3.

[0287] The first electrode film 48 has portions that cover the sidewalls and open ends of the trenches 16 within the trenches 16. The first electrode film 48 is mechanically and electrically connected to the source regions 35 and the contact regions 37 in the portions that cover the sidewalls and open ends of the trenches 16. The first electrode film 48 is mechanically and electrically connected to the source regions 35 and the contact regions 37 in the portions that cover the mesa portions 20.

[0288] The first electrode film 48 has a peripheral portion facing the ends (both ends) of the multiple gate structures 15 with the interlayer film 43 interposed therebetween. The peripheral portion of the first electrode film 48 may be drawn out from the active region 8 to the peripheral region 9 and may face one or multiple gate wirings 42 with the interlayer film 43 interposed therebetween. The peripheral portion of the first electrode film 48 may face the outer well region 40 with the interlayer film 43 interposed therebetween.

[0289] The second electrode film 49 directly covers the first electrode film 48. The second electrode film 49 collectively covers the region of the interlayer film 43 where the source opening 44 is formed, sandwiching the first electrode film 48 therebetween, and extends from above the interlayer film 43 into the source opening 44.

[0290] The second electrode film 49 has a portion that covers the interlayer film 43 in a film state with the first electrode film 48 sandwiched therebetween, a portion that covers the wall surface of the source opening 44 in a film state with the first electrode film 48 sandwiched therebetween, and a portion that covers the first main surface 3 in a film state with the first electrode film 48 sandwiched therebetween within the source opening 44. The second electrode film 49 has a portion that covers the plurality of gate structures 15 in the source opening 44 with the first electrode film 48 sandwiched therebetween, and a portion that covers the plurality of mesa portions 20 with the first electrode film 48 sandwiched therebetween.

[0291] The second electrode film 49 covers the plurality of embedded insulators 19 with the first electrode film 48 interposed therebetween and is electrically isolated from the plurality of embedded electrodes 18. In this embodiment, the second electrode film 49 enters the plurality of trenches 16 from above the first main surface 3 and covers the plurality of embedded insulators 19 in the plurality of trenches 16 with the first electrode film 48 interposed therebetween.

[0292] In this embodiment, the second electrode film 49 covers the first electrode film 48 in regions on the bottom wall side of the plurality of trenches 16 relative to the height position of the first main surface 3. In this embodiment, the second electrode film 49 has portions that cover the side walls and opening ends of the plurality of trenches 16 with the first electrode film 48 sandwiched therebetween.

[0293] The second electrode film 49 is electrically connected to the source regions 35 and the contact regions 37 via the first electrode film 48 in a portion covering the sidewalls and opening ends of the trenches 16. The second electrode film 49 may be connected to the first electrode film 48 above the first main surface 3. The second electrode film 49 is electrically connected to the source regions 35 and the contact regions 37 via the first electrode film 48 in a portion covering the mesas 20.

[0294] The main electrode film 47 contains a metal material different from the metal material of the lower electrode film 46 (first electrode film 48 and second electrode film 49). The main electrode film 47 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film (Cu alloy film) may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 47 has a thickness greater than the thickness (total thickness) of the lower electrode film 46. The thickness of the main electrode film 47 is preferably greater than the thickness of the interlayer film 43.

[0295] The thickness of the main electrode film 47 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 47 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0296] The main electrode film 47 directly covers the lower electrode film 46 (second electrode film 49). The main electrode film 47 backfills the source opening 44 and collectively covers the region of the interlayer film 43 where the source opening 44 is formed. The main electrode film 47 has a portion that covers the interlayer film 43 with the lower electrode film 46 in between, a portion that covers the wall surface of the source opening 44 with the lower electrode film 46 in between, and a portion that covers the first main surface 3 with the lower electrode film 46 in between.

[0297] The main electrode film 47 has a portion that covers the plurality of gate structures 15 with the lower electrode film 46 interposed therebetween in the source opening 44, and a portion that covers the plurality of mesa portions 20 with the lower electrode film 46 interposed therebetween. The main electrode film 47 covers the plurality of buried insulators 19 with the lower electrode film 46 interposed therebetween, and is electrically isolated from the plurality of buried electrodes 18.

[0298] The main electrode film 47 may enter the plurality of trenches 16 from above the first main surface 3 and cover the plurality of embedded insulators 19 in the plurality of trenches 16 with the lower electrode film 46 sandwiched therebetween. In this case, the main electrode film 47 may have a portion that covers the sidewalls and opening ends of the plurality of trenches 16 with the lower electrode film 46 sandwiched therebetween in a region on the bottom wall side of the plurality of trenches 16 with respect to the height position of the first main surface 3.

[0299] The main electrode film 47 is electrically connected to the source regions 35 and the contact regions 37 via the lower electrode film 46 in a portion covering the sidewalls and opening ends of the trenches 16. The main electrode film 47 is electrically connected to the source regions 35 and the contact regions 37 via the lower electrode film 46 in a portion covering the mesa portions 20.

[0300] The semiconductor device 1A includes one or more (multiple in this embodiment) gate openings 50 formed in the interlayer film 43. The multiple gate openings 50 penetrate the interlayer film 43 and selectively expose the multiple gate wirings 42. In this embodiment, the multiple gate openings 50 extend in a strip shape following the extension direction of the multiple gate wirings 42.

[0301] The gate openings 50 may be formed at intervals along the extension direction of the gate wirings 42. The gate openings 50 may be formed in a polygonal or circular shape in a plan view. For example, the gate structures 15 may be formed in a quadrangular or hexagonal shape in a plan view.

[0302] The plurality of gate openings 50 may have a portion extending in a band shape in the first direction X in a plan view and a portion extending in a band shape in the second direction Y. The plurality of gate openings 50 may have an edge portion connecting the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view.

[0303] The semiconductor device 1A includes a gate electrode 51 disposed on the first main surface 3. The gate electrode 51 may also be referred to as a "second main surface electrode," a "second terminal (electrode)," a "second pad (electrode)," a "gate pad (electrode)," or the like. The gate electrode 51 is disposed on the interlayer film 43 at a distance from the source electrode 45.

[0304] In this embodiment, the gate electrode 51 is disposed in a region on the third side surface 5C side of the first pad portion 45a, and faces the center of the third side surface 5C and the first pad portion 45a in the first direction X. The gate electrode 51 is interposed in a region between the second pad portion 45b and the third pad portion 45c, and faces both the second pad portion 45b and the third pad portion 45c in the second direction Y.

[0305] The gate electrode 51 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate electrode 51 has a planar area less than the planar area of ​​the source electrode 45. The gate electrode 51 has a planar area less than the planar area of ​​the first pad portion 45a. The gate electrode 51 may also have a planar area less than the planar area of ​​the second pad portion 45b (third pad portion 45c).

[0306] The gate electrode 51 faces the plurality of gate structures 15 across the interlayer film 43. Specifically, the gate electrode 51 is disposed inwardly from both ends of the plurality of gate structures 15 at a distance, and faces the inner portions of the plurality of gate structures 15 across the interlayer film 43. The portions of the plurality of gate structures 15 that are located under the gate electrode 51 may be removed.

[0307] In this case, the gate electrode 51 may face at least one of the second semiconductor layer 7, the body region 10, and the outer well region 40, with the main surface insulating film 41 and the interlayer film 43 sandwiched therebetween. Although not shown, the gate electrode 51 includes a lower electrode film 46 and a main electrode film 47 laminated in this order from the interlayer film 43 side, similar to the source electrode 45. In this embodiment, the lower electrode film 46 has a laminated structure including a first electrode film 48 and a second electrode film 49.

[0308] The semiconductor device 1A includes a gate finger electrode 52 extending from the gate electrode 51 onto the first main surface 3. The gate finger electrode 52 may be referred to as a "gate finger" or the like. The gate finger electrode 52 transmits the gate potential applied to the gate electrode 51 to other regions.

[0309] The gate finger electrodes 52 extend from the gate electrode 51 onto a portion of the interlayer film 43 that covers the plurality of gate wirings 42. The gate finger electrodes 52 are routed in a strip shape around the periphery of the first main surface 3 and in a region between the source electrodes 45. The gate finger electrodes 52 have a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in plan view.

[0310] In this embodiment, the gate finger electrode 52 is formed in a strip shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 45. The gate finger electrode 52 is disposed closer to the periphery of the first main surface 3 than both ends of the multiple gate structures 15.

[0311] The gate finger electrodes 52 extend into the plurality of gate openings 50 from above the interlayer film 43, and are mechanically and electrically connected to the plurality of gate wirings 42 within the plurality of gate openings 50. As a result, the gate potential applied to the gate electrode 51 is applied to the plurality of gate structures 15 via the gate finger electrodes 52.

[0312] Gate finger electrode 52 is drawn out from above the plurality of gate wirings 42 toward the peripheral edge of first main surface 3, and has a portion facing outer well region 40 in a region outside the plurality of gate wirings 42, with main surface insulating film 41 and interlayer film 43 sandwiched between them. The peripheral portion of gate finger electrode 52 may be located closer to the peripheral edge of first main surface 3 than the outer edge of outer well region 40, or may be located closer to the plurality of gate wirings 42 than the outer edge of outer well region 40.

[0313] In this embodiment, the gate finger electrode 52 has a layered structure including a lower electrode film 46 and a main electrode film 47, which are layered in this order from the chip 2 side, similar to the source electrode 45. In this embodiment, the lower electrode film 46 has a layered structure including a first electrode film 48 and a second electrode film 49.

[0314] The first electrode film 48 collectively covers the region of the interlayer film 43 where the multiple gate openings 50 are formed, and extends into the multiple gate openings 50 from above the interlayer film 43. The first electrode film 48 has a portion that covers the insulating main surface of the interlayer film 43 in a film-like manner, a portion that covers the wall surfaces of the multiple gate openings 50 in a film-like manner, and a portion that covers the multiple gate wirings 42 in the multiple gate openings 50. The first electrode film 48 is mechanically and electrically connected to the multiple gate wirings 42 in the multiple gate openings 50.

[0315] The second electrode film 49 directly covers the first electrode film 48. The second electrode film 49 collectively covers the region of the interlayer film 43 where the multiple gate openings 50 are formed, sandwiching the first electrode film 48 therebetween, and extends from above the interlayer film 43 into the multiple gate openings 50.

[0316] The second electrode film 49 has a portion that covers the interlayer film 43 in a film state with the first electrode film 48 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of gate openings 50 in a film state with the first electrode film 48 sandwiched therebetween, and a portion that covers the first main surface 3 in a film state with the first electrode film 48 sandwiched therebetween within the plurality of gate openings 50. The second electrode film 49 is electrically connected to the plurality of gate wirings 42 with the first electrode film 48 sandwiched therebetween within the plurality of gate openings 50.

[0317] The main electrode film 47 directly covers the lower electrode film 46 (second electrode film 49). The main electrode film 47 backfills the gate openings 50 and collectively covers the region of the interlayer film 43 where the gate openings 50 are formed.

[0318] The main electrode film 47 has a portion that covers the interlayer film 43 with the lower electrode film 46 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of gate openings 50 with the lower electrode film 46 sandwiched therebetween, and a portion that covers the first main surface 3 with the lower electrode film 46 sandwiched therebetween. The main electrode film 47 is electrically connected to the plurality of gate wirings 42 within the plurality of gate openings 50 with the lower electrode film 46 sandwiched therebetween.

[0319] The semiconductor device 1A includes a drain electrode 53 covering the second main surface 4. The drain electrode 53 may also be referred to as a "third main surface electrode," a "third terminal (electrode)," a "third pad (electrode)," a "drain pad (electrode)," or the like. The drain electrode 53 is electrically connected to the first semiconductor layer 6. The drain electrode 53 forms ohmic contact with the first semiconductor layer 6.

[0320] The drain electrode 53 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 53 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0321] A breakdown voltage that can be applied between the source electrode 45 and the drain electrode 53 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0322] 15 is a cross-sectional perspective view illustrating the operation when a drain-source voltage is applied when the gate structure 15 is in an off state. In the semiconductor device 1A, when a drain-source voltage is applied between the second semiconductor layer 7 (drain electrode 53) and the body region 10 (source electrode 45), a current path is formed through the channel CH in the region between the second semiconductor layer 7 and the body region 10, generating a drain-source current. The drain-source voltage is a voltage that sets the second semiconductor layer 7 at a positive potential and the body region 10 at a negative potential.

[0323] Devices using SiC single crystals have relatively high channel resistance due to the relatively low channel mobility of the SiC single crystals. Therefore, devices using SiC single crystals need to have a shorter channel length to reduce the channel resistance. However, shortening the channel length may cause an increase in leakage current (drain leakage current) due to the short channel effect when a drain-source voltage is applied with the gate structure 15 in the off state.

[0324] The off state of the gate structure 15 is a state in which a gate voltage (off signal) lower than the gate threshold voltage is applied to the gate structure 15. The short channel effect is a phenomenon in which the gate threshold voltage decreases due to the influence of the drain-source voltage, making the control of the gate threshold voltage by the gate structure 15 unstable, resulting in the generation of a leakage current through the channel CH.

[0325] The semiconductor device 1A includes a well region 25 formed below the gate structure 15. The well region 25 has a bulging region 26 that bulges out horizontally from the sidewall of the gate structure 15 along the first main surface 3. When a drain-source voltage is applied with the gate structure 15 in an off state, the well region 25 reduces the effect of the drain-source voltage on the channel CH due to the bulging region 26, thereby suppressing a decrease in the gate threshold voltage.

[0326] This suppresses leakage current due to the short channel effect. Such a configuration is effective in improving the breakdown voltage and shortening the channel length. For example, the shortened channel length is 300 nm or less.

[0327] The semiconductor device 1A includes a high-concentration body region 36 formed at the bottom of the body region 10. When a drain-source voltage is applied while the gate structure 15 is in the off state, the high-concentration body region 36 reduces the effect of the drain-source voltage on the channel CH and suppresses a decrease in the gate threshold voltage. This suppresses leakage current due to the short channel effect. This configuration is effective in improving the breakdown voltage and shortening the channel length.

[0328] The high-concentration body region 36 is preferably formed in a part of the bottom of the body region 10. In this case, the location where the high-concentration body region 36 is formed (the location where the p-type impurity is introduced) in the body region 10 is limited, thereby suppressing an increase in the gate threshold voltage due to the work function of the p-type impurity. A structure in which the high-concentration body region 36 is separated from the gate structure 15 is effective in suppressing an increase in channel resistance and an increase in the gate threshold voltage.

[0329] The well region 25 forms a JFET region Tj together with the second semiconductor layer 7 in the region below the gate structure 15. In this case, the well region 25 may include a first bulge region 26A and a second bulge region 26B as the multiple bulge regions 26.

[0330] The first bulge region 26A may be formed in a portion along the bottom wall of the gate structure 15, and the second bulge region 26B may be formed below the first bulge region 26A. With this configuration, the first bulge region 26A suppresses a decrease in the gate threshold voltage, and the second bulge region 26B allows the JFET region Tj to be formed.

[0331] The semiconductor device 1A includes a high-concentration region 30 on the side of the well region 25. With this configuration, the high-concentration region 30 reduces the JFET resistance. The well region 25 may include a second well region 29 made of a channeling region. With this configuration, the p-type impurity concentration and depth of the second well region 29 are appropriately adjusted, and the JFET region Tj is appropriately formed. Therefore, the breakdown voltage can be appropriately improved by the JFET region Tj.

[0332] Similarly, the high concentration region 30 may include a second high concentration region 32 made of a channeling region. With this configuration, the n-type impurity concentration and depth of the second high concentration region 32 are appropriately adjusted, and the JFET region Tj is appropriately formed. Therefore, the breakdown voltage can be appropriately improved by the JFET region Tj.

[0333] The second well region 29 contains almost no n-type impurity (pentavalent element) of the second high concentration region 32, and is formed separately from the second high concentration region 32. In other words, the p-type impurity concentration of the second well region 29 is hardly affected by the n-type impurity concentration of the second high concentration region 32. Therefore, the impurity concentration and depth of the second well region 29 are appropriately adjusted, and the JFET region Tj is appropriately formed.

[0334] The second high concentration region 32 contains almost no p-type impurity (trivalent element) of the second well region 29, and is formed separately from the second well region 29. In other words, the n-type impurity concentration of the second high concentration region 32 is hardly affected by the p-type impurity concentration of the second well region 29. Therefore, the impurity concentration and depth of the second high concentration region 32 are appropriately adjusted, and the JFET region Tj is appropriately formed.

[0335] As described above, the semiconductor device 1A may include an n-type second semiconductor layer 7 (semiconductor layer), a p-type body region 10, a trench-type gate structure 15, and a p-type well region 25. The second semiconductor layer 7 may have a first main surface 3. The body region 10 may be formed in a surface layer portion of the first main surface 3.

[0336] The gate structure 15 may be formed on the first major surface 3 so as to penetrate the body region 10. The well region 25 may be formed in a region below the gate structure 15 within the second semiconductor layer 7. The well region 25 may have a bulging region 26 that bulges out in the horizontal direction along the first major surface 3 relative to a sidewall of the gate structure 15.

[0337] This configuration provides a semiconductor device 1A having a novel layout. For example, in this semiconductor device 1A, the bulge region 26 located in the region below the gate structure 15 enhances the electrical stability of the channel CH along the gate structure 15, thereby suppressing a decrease in the gate threshold voltage. This suppresses leakage current due to the short channel effect.

[0338] The second semiconductor layer 7 may contain SiC. This configuration provides the semiconductor device 1A as a SiC semiconductor device having a novel layout. The semiconductor device 1A further improves the breakdown voltage due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the suppression effect of the short channel effect by the bulge region 26 is effective.

[0339] The bulge region 26 may have an impurity concentration higher than the impurity concentration of the body region 10. With this configuration, the short channel effect is suppressed by utilizing the bulge region 26 having a relatively high impurity concentration. The bulge region 26 may be connected to the bottom wall of the gate structure 15. With this configuration, the short channel effect is suppressed by the bulge region 26 connected to the bottom wall of the gate structure 15. The bulge region 26 may protrude in an arc shape. With this configuration, the short channel effect is suppressed by the bulge region 26 protruding in an arc shape.

[0340] The well region 25 may have a constricted region 27 below the bulging region 26, which is recessed in the horizontal direction along the first main surface 3 relative to the bulging region 26. With this configuration, the bulging region 26 is appropriately defined by the constricted region 27. This appropriately suppresses the short channel effect. The constricted region 27 may have a portion located inward from the sidewall of the gate structure 15. With this configuration, the bulging region 26 is appropriately defined by the constricted region 27.

[0341] The bulge region 26 may extend horizontally along the first main surface 3 beyond both sidewalls of the gate structure 15. With this configuration, the bulge region 26 suppresses the short channel effect in the regions on both sidewalls of the gate structure 15. The well region 25 may include a plurality of bulge regions 26 formed at different depth positions.

[0342] The well region 25 may include a p-type first well region 28 and a p-type second well region 29. The first well region 28 may be formed below the bottom wall of the gate structure 15. The second well region 29 may be formed below the first well region 28. In this case, the bulge region 26 may be formed by the first well region 28. According to this configuration, the bulge region 26 is appropriately formed by utilizing the first well region 28.

[0343] The second well region 29 may have a p-type impurity concentration lower than the p-type impurity concentration of the first well region 28. According to this configuration, the electrical response characteristics of the second well region 29 can be improved by the first well region 28.

[0344] The second well region 29 may form a JFET region Tj together with the second semiconductor layer 7. With this configuration, the breakdown voltage can be improved by the JFET region Tj. The second well region 29 may have a thickness greater than that of the first well region 28. With this configuration, the JFET region Tj can be appropriately formed by the relatively thick second well region 29.

[0345] The gate structure 15 may include a trench 16 formed in the first main surface 3, an insulating film 17 covering the wall surface of the trench 16, and a buried electrode 18 buried in the trench 16 via the insulating film 17. The buried electrode 18 may be buried at a distance from a height position of the first main surface 3 toward the bottom wall of the trench 16.

[0346] The gate structure 15 may include a buried insulator 19 buried in the trench 16 at a distance from the height position of the first main surface 3 toward the bottom wall of the trench 16 so as to cover the buried electrode 18. With this configuration, the dielectric strength voltage on the opening side of the gate structure 15 is improved by the buried insulator 19. Furthermore, since the area covered by the insulating structure with respect to the first main surface 3 is reduced, electrical contact points with the first main surface 3 can be appropriately secured.

[0347] The semiconductor device 1A may include a p-type contact region 37. The contact region 37 may extend along the sidewall of the gate structure 15 and electrically connect the bulge region 26 to the body region 10. This configuration prevents the bulge region 26 from becoming electrically floating, improving the electrical response characteristics of the bulge region 26. The contact region 37 may have a p-type impurity concentration higher than the p-type impurity concentration of the body region 10.

[0348] The semiconductor device 1A may include an n-type source region 35. The source region 35 may be formed in a surface layer portion of the body region 10. With this configuration, the channel CH is formed along the gate structure 15 in a region between the bottom of the body region 10 and the bottom of the source region 35. In this case, the channel length can be appropriately shortened by the suppression effect of the bulge region 26 on the short channel effect. For example, the channel length may be 300 nm or less.

[0349] The semiconductor device 1A may include an n-type high concentration region 30. The high concentration region 30 may be formed in the second semiconductor layer 7 in a thickness range of the bottom of the body region 10 and the bottom wall of the gate structure 15. The high concentration region 30 may have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7.

[0350] According to this configuration, the high-concentration region 30 offsets undesired p-type impurities introduced into the sides of the gate structure 15 due to process errors or the like. This appropriately prevents the bulge region 26 from integrating with the body region 10, thereby suppressing fluctuations in the gate threshold voltage due to undesired p-type impurities. Furthermore, the high-concentration region 30 reduces the resistance below the body region 10. This configuration is effective in reducing the on-resistance and JFET resistance.

[0351] The semiconductor device 1A may include a source electrode 45. The source electrode 45 may be electrically connected to the body region 10 on the first major surface 3 and electrically isolated from the gate structure 15.

[0352] From another perspective, the semiconductor device 1A may include an n-type second semiconductor layer 7 (semiconductor layer), a p-type body region 10, a trench-type gate structure 15, and a p-type high-concentration body region 36. The second semiconductor layer 7 may have a first main surface 3. The body region 10 may be formed in a surface layer portion of the first main surface 3.

[0353] The gate structure 15 may be formed on the first main surface 3 so as to penetrate the body region 10. The high-concentration body region 36 may be formed in a bottom portion of the body region 10. The high-concentration body region 36 may have a p-type impurity concentration higher than the p-type impurity concentration of the body region 10.

[0354] This configuration provides a semiconductor device 1A with a novel layout. For example, in this semiconductor device 1A, the high-concentration body region 36 enhances the electrical stability of the channel CH along the gate structure 15, thereby suppressing a decrease in the gate threshold voltage. This suppresses leakage current due to the short-channel effect and improves the breakdown voltage. This configuration is also effective in shortening the channel length.

[0355] The second semiconductor layer 7 may contain SiC. This configuration provides the semiconductor device 1A as a SiC semiconductor device having a novel layout. The semiconductor device 1A further improves the breakdown voltage due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high-voltage environments, the suppression effect of the high-concentration body region 36 on the short-channel effect is effective.

[0356] The high-concentration body region 36 may be formed at a distance from the gate structure 15. With this configuration, the high-concentration portion of the body region 10 is limited. This suppresses an increase in the gate threshold voltage caused by the work function of the high-concentration body region 36. In this case, the high-concentration body region 36 may face the gate structure 15 across a part of the body region 10. With this configuration, a channel CH is appropriately formed in the body region 10, which has a relatively low concentration.

[0357] The high-concentration body regions 36 may extend along the extension direction of the gate structure 15. With this configuration, the high-concentration body regions 36 exert an effect of suppressing the short channel effect by following the extension direction of the gate structure 15. The high-concentration body regions 36 may extend in strips along the gate structure 15, or may be formed at intervals along the gate structure 15.

[0358] The gate structure 15 may include a trench 16 formed in the first main surface 3, an insulating film 17 covering the wall surface of the trench 16, and a buried electrode 18 buried in the trench 16 via the insulating film 17. The buried electrode 18 may be buried at a distance from a height position of the first main surface 3 toward the bottom wall of the trench 16.

[0359] Gate structure 15 may include a buried insulator 19 buried in trench 16 at a distance from the height position of first main surface 3 toward the bottom wall of trench 16 so as to cover buried electrode 18. With this configuration, the area of ​​first main surface 3 hidden by the insulating structure for gate structure 15 is reduced, and therefore electrical contact points with first main surface 3 can be appropriately secured.

[0360] The semiconductor device 1A may include an n-type source region 35. The source region 35 may be formed in a surface layer portion of the body region 10. With this configuration, the channel CH is formed along the gate structure 15 in a region between the bottom of the body region 10 and the bottom of the source region 35. In this case, the high-concentration body region 36 suppresses the short-channel effect, thereby appropriately shortening the channel length. For example, the channel length may be 300 nm or less.

[0361] The high-concentration body region 36 may be formed in a thickness range between the bottom of the body region 10 and the bottom of the source region 35. This configuration allows the short-channel effect to be appropriately suppressed and the channel length to be appropriately shortened. In this case, the high-concentration body region 36 may be formed at a distance from the bottom of the source region 35 toward the bottom of the body region 10, and may face the source region 35 with a part of the body region 10 in between.

[0362] The semiconductor device 1A may include a p-type contact region 37. The contact region 37 may be formed along the gate structure 15 in a surface layer portion of the body region 10. The contact region 37 may have a p-type impurity concentration higher than the p-type impurity concentration of the body region 10. With this configuration, the contact region 37 can improve the electrical response characteristics of the body region 10.

[0363] The contact region 37 may be electrically connected to the high-concentration body region 36 in the body region 10. With this configuration, the electrical response characteristics of the high-concentration body region 36 can be improved by the contact region 37. The contact region 37 may have a portion connected to the high-concentration body region 36 in the body region 10. With this configuration, the electrical response characteristics of the high-concentration body region 36 can be appropriately improved.

[0364] The semiconductor device 1A may include a p-type well region 25. The well region 25 may be formed in the second semiconductor layer 7 in a region below the gate structure 15, spaced apart from the bottom of the body region 10. With this configuration, a JFET region Tj including the second semiconductor layer 7 and the well region 25 can be formed in the region below the gate structure 15. This allows the breakdown voltage to be improved by the JFET region Tj.

[0365] The well region 25 may be formed at a distance from the bottom of the high-concentration body region 36. This configuration prevents the well region 25 from merging with the high-concentration body region 36. This prevents fluctuations in the gate threshold voltage caused by undesired p-type impurities.

[0366] The well region 25 may include a p-type first well region 28 and a p-type second well region 29. The first well region 28 may be formed below the bottom wall of the gate structure 15. The second well region 29 may be formed below the first well region 28.

[0367] The second well region 29 may have a p-type impurity concentration lower than the p-type impurity concentration of the first well region 28. According to this configuration, the electrical response characteristics of the second well region 29 can be improved by the first well region 28.

[0368] The second well region 29 may form a JFET region Tj together with the second semiconductor layer 7. With this configuration, the breakdown voltage can be improved by the JFET region Tj. The second well region 29 may have a thickness greater than that of the first well region 28. With this configuration, the JFET region Tj can be appropriately formed by the relatively thick second well region 29.

[0369] The semiconductor device 1A may include a p-type contact region 37. The contact region 37 may extend along the sidewall of the gate structure 15 and electrically connect the well region 25 to the high-concentration body region 36. This configuration prevents the well region 25 from being electrically floating, improving the electrical response characteristics of the well region 25. The contact region 37 may have a p-type impurity concentration higher than the p-type impurity concentration of the second well region 29.

[0370] The semiconductor device 1A may include an n-type high concentration region 30. The high concentration region 30 may be formed in the second semiconductor layer 7 in a thickness range of the bottom of the body high concentration region 36 and the bottom wall of the gate structure 15. The high concentration region 30 may have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7.

[0371] According to this configuration, the high-concentration region 30 offsets undesired p-type impurities introduced laterally into the gate structure 15 due to process errors or the like. This suppresses fluctuations in the gate threshold voltage caused by the undesired p-type impurities. The high-concentration region 30 also reduces the resistance below the body high-concentration region 36. This configuration is effective in reducing the on-resistance and JFET resistance.

[0372] The semiconductor device 1A may include a source electrode 45. The source electrode 45 may be electrically connected to the body region 10 on the first major surface 3 and electrically isolated from the gate structure 15.

[0373] From another perspective, the semiconductor device 1A may include an n-type second semiconductor layer 7 (semiconductor layer), a trench-type gate structure 15, and a p-type second well region 29 (well region 25). The second semiconductor layer 7 may include SiC single crystal and have a first main surface 3. The gate structure 15 may be formed on the first main surface 3. The second well region 29 may be formed in a region below the gate structure 15 within the second semiconductor layer 7. The second well region 29 may extend vertically along an axial channel of the SiC single crystal.

[0374] This configuration provides a semiconductor device 1A having a novel layout. For example, in this semiconductor device 1A, the p-type impurity concentration and depth of the second well region 29 are appropriately adjusted, and the JFET region Tj is appropriately formed. Therefore, the breakdown voltage can be appropriately improved by the JFET region Tj.

[0375] The second well region 29 may have an impurity concentration higher than the impurity concentration of the second semiconductor layer 7, and may change the conductivity type of the second semiconductor layer 7 from n-type to p-type. With this configuration, the JFET region Tj can be appropriately formed.

[0376] The second well region 29 may have a concentration gradient that decreases in the thickness direction. According to this configuration, the JFET region Tj can be appropriately formed by the second well region 29 having a concentration gradient that decreases in the thickness direction.

[0377] The second well region 29 may have a depth of 0.5 μm or more and 5 μm or less, based on the bottom wall of the gate structure 15. In this case, the second well region 29 may include a gradual portion 29A having a concentration decrease rate of 50% or less in a depth range of at least 0.25 μm. With this configuration, the concentration change rate of the second well region 29 becomes gradual, allowing the JFET region Tj to be appropriately formed.

[0378] The second well region 29 may have a depth, when the bottom wall of the gate structure 15 is used as a reference, that is smaller than the depth of the gate structure 15, when the first main surface 3 is used as a reference. The second well region 29 may have a depth, when the bottom wall of the gate structure 15 is used as a reference, that is larger than the depth of the gate structure 15, when the first main surface 3 is used as a reference. The depth of the second well region 29 is adjusted appropriately depending on the JFET region Tj to be achieved.

[0379] The second well region 29 may be formed in a shape tapering toward the bottom in a cross-sectional view. The second well region 29 may extend horizontally along the first main surface 3 beyond the sidewall of the gate structure 15 in a cross-sectional view.

[0380] The semiconductor device 1A may include an n-type high concentration region 30. The high concentration region 30 may be formed in a region on the side of the second well region 29 in the second semiconductor layer 7. The high concentration region 30 may have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. According to this configuration, the high concentration region 30 forms a JFET region Tj together with the second well region 29. As a result, the JFET resistance is reduced by the high concentration region 30.

[0381] The high concentration region 30 may extend along the axial channel of the SiC single crystal. With this configuration, the n-type impurity concentration and depth of the high concentration region 30 are appropriately adjusted, and the JFET region Tj is appropriately formed. Therefore, the breakdown voltage can be appropriately improved by the JFET region Tj.

[0382] The high concentration region 30 may have a bottom located closer to the first main surface 3 than the bottom of the second well region 29. The high concentration region 30 may have a bottom located lower than the bottom of the second well region 29. The depth of the high concentration region 30 is adjusted appropriately depending on the JFET region Tj to be achieved.

[0383] The high concentration region 30 may have a concentration gradient that decreases in the thickness direction. According to this configuration, the JFET region Tj can be appropriately formed by the high concentration region 30 having a concentration gradient that decreases in the thickness direction.

[0384] The high concentration region 30 may include a first high concentration region 31 and a second high concentration region 32. The first high concentration region 31 may be located above the depth position of the bottom wall of the gate structure 15. The second high concentration region 32 may be located below the depth position of the bottom wall of the gate structure 15.

[0385] According to this configuration, the first heavily doped region 31 offsets undesired p-type impurities introduced laterally into the gate structure 15 due to process errors or the like. This suppresses fluctuations in the gate threshold voltage caused by the undesired p-type impurities. The first heavily doped region 31 also reduces the resistance below the body region 10. This configuration is effective in reducing the on-resistance and JFET resistance.

[0386] The second high concentration region 32 may form a JFET region Tj together with the second well region 29. This reduces the JFET resistance by the high concentration region 30. The second high concentration region 32 may have a concentration gradient that monotonically decreases in the thickness direction. According to this configuration, the JFET region Tj can be appropriately formed by the second high concentration region 32 having a concentration gradient that is controlled to monotonically decrease.

[0387] The second high concentration region 32 may have a depth of 0.5 μm or more and 5 μm or less, based on the bottom wall of the gate structure 15. In this case, the second high concentration region 32 may include a gradual portion 32A having a concentration decrease rate of 50% or less in a depth range of at least 0.25 μm. With this configuration, the concentration change rate of the second high concentration region 32 becomes gradual, allowing the JFET region Tj to be appropriately formed.

[0388] The semiconductor device 1A may include a p-type first well region 28 (high concentration well region). The first well region 28 may be formed below the bottom wall of the gate structure 15 in the second semiconductor layer 7. In this case, the second well region 29 may be formed below the first well region 28.

[0389] The second well region 29 may have a p-type impurity concentration lower than the p-type impurity concentration of the first well region 28. With this configuration, the electrical response characteristics of the second well region 29 can be improved by the first well region 28. The second well region 29 may have a thickness greater than that of the first well region 28. With this configuration, the JFET region Tj is appropriately formed by the second well region 29 that is thicker than the first well region 28.

[0390] The second well region 29 may have a concentration gradient different from the concentration gradient of the first well region 28. This configuration can suppress the electrical influence of the p-type impurity concentration of the first well region 28 on the JFET region Tj. The first well region 28 may have a concentration gradient that increases or decreases from the bottom wall side of the gate structure 15 downward.

[0391] The semiconductor device 1A may include a p-type body region 10. The body region 10 may be formed in a surface layer portion of the first main surface 3. In this case, the gate structure 15 may penetrate the body region 10. With this configuration, the second well region 29 can be appropriately provided below the body region 10.

[0392] The second well region 29 may be formed at a distance from the bottom of the body region 10. This configuration appropriately prevents the second well region 29 from being integrated with the body region 10, and suppresses fluctuations in the gate threshold voltage due to undesired p-type impurities.

[0393] The semiconductor device 1A may include a p-type contact region 37. The contact region 37 may extend along a sidewall of the gate structure 15 and electrically connect the second well region 29 to the body region 10. This configuration prevents the second well region 29 from being electrically floating, improving the electrical response characteristics of the second well region 29.

[0394] The contact region 37 may have a p-type impurity concentration higher than the p-type impurity concentration of the second well region 29. The contact region 37 may have a p-type impurity concentration higher than the p-type impurity concentration of the body region 10.

[0395] The semiconductor device 1A may include an n-type source region 35. The source region 35 may be formed in a surface layer portion of the body region 10. According to this configuration, the source region 35 defines a channel CH at the bottom of the body region 10. The semiconductor device 1A may include a source electrode 45. The source electrode 45 may be electrically connected to the first main surface 3 and electrically separated from the gate structure 15.

[0396] From another perspective, the semiconductor device 1A may include an n-type second semiconductor layer 7 (semiconductor layer), a p-type second well region 29 (well region 25), and an n-type second high concentration region 32 (high concentration region 30). The second well region 29 may be formed in the second semiconductor layer 7 to have a higher concentration than the second semiconductor layer 7. The second high concentration region 32 may be formed in the second semiconductor layer 7 to have a higher concentration than the second semiconductor layer 7. The second high concentration region 32 may form a pn junction with the second well region 29.

[0397] This configuration provides a semiconductor device 1A having a novel layout. For example, in this semiconductor device 1A, the second heavily doped region 32 forms a JFET region Tj together with the second well region 29. Therefore, the breakdown voltage can be appropriately improved by the JFET region Tj.

[0398] The second semiconductor layer 7 may contain SiC. This configuration provides the semiconductor device 1A as a SiC semiconductor device having a novel layout. The semiconductor device 1A further improves the breakdown voltage due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high-voltage environments, the effect of improving the breakdown voltage by the JFET region Tj including the second well region 29 and the second heavily doped region 32 is effective.

[0399] The second well region 29 may have a p-type impurity concentration that is separated from the n-type impurity concentration of the second high concentration region 32. With this configuration, the p-type impurity concentration of the second well region 29 is appropriately adjusted, and the JFET region Tj is appropriately formed. Therefore, the breakdown voltage can be appropriately improved by the JFET region Tj.

[0400] The second high-concentration region 32 may have an impurity concentration that is separated from the impurity concentration of the second well region 29. With this configuration, the n-type impurity concentration of the second high-concentration region 32 is appropriately adjusted, and the JFET region Tj is appropriately formed. Therefore, the breakdown voltage can be appropriately improved by the JFET region Tj.

[0401] The concentration of the second semiconductor layer 7 may be adjusted by a first element consisting of a pentavalent element. The concentration of the second well region 29 may be adjusted by a third element consisting of a trivalent element in addition to the first element. The concentration of the second high-concentration region 32 may be adjusted by a fifth element consisting of a pentavalent element in addition to the first element.

[0402] The concentration of the fifth element in the second well region 29 may be less than the concentration of the fifth element in the second high concentration region 32. With this configuration, the p-type impurity concentration of the second well region 29 can be appropriately separated from the n-type impurity concentration of the second high concentration region 32. In this case, the inner portion of the second well region 29 does not need to contain the fifth element.

[0403] The concentration of the third element in the second high concentration region 32 may be less than the concentration of the third element in the second well region 29. With this configuration, the n-type impurity concentration of the second high concentration region 32 can be appropriately separated from the p-type impurity concentration of the second well region 29. In this case, the inner portion of the second high concentration region 32 does not need to contain the third element.

[0404] The first element may include at least one of nitrogen, phosphorus, and arsenic. The first element may be composed of a single pentavalent element. The first element may be nitrogen.

[0405] The third element may include at least one of boron and aluminum. The third element may be composed of a single trivalent element. The third element may be aluminum.

[0406] The fifth element may include at least one of nitrogen, phosphorus, and arsenic. The fifth element may be the same species as the first element. The fifth element may be a different species from the first element. The fifth element may be composed of a single pentavalent element. The fifth element may be nitrogen.

[0407] The second high concentration region 32 may have a bottom located higher than the depth position of the bottom of the second well region 29. The second high concentration region 32 may have a bottom located lower than the bottom of the second well region 29. The depth of the second high concentration region 32 is adjusted appropriately depending on the JFET region Tj to be achieved.

[0408] The second heavily doped region 32 may form a superjunction structure together with the second well region 29. With this configuration, the breakdown voltage can be appropriately improved by the superjunction structure.

[0409] The semiconductor device 1A may include a trench-type gate structure 15. The gate structure 15 may be formed in the second semiconductor layer 7. In this case, the second well region 29 may be formed below the gate structure 15. The second heavily doped region 32 may be formed below the depth position of the bottom wall of the gate structure 15.

[0410] According to this configuration, the second heavily doped region 32 forms a JFET region Tj together with the second well region 29 in a region below the gate structure 15. Therefore, in a configuration including the trench-type gate structure 15, the breakdown voltage can be appropriately improved by the JFET region Tj.

[0411] The semiconductor device 1A may include a p-type first well region 28 (high concentration well region). The first well region 28 may be formed below the bottom wall of the gate structure 15. In this case, the second well region 29 may be formed in a region below the first well region 28 with a lower concentration than the first well region 28. With this configuration, the electrical response characteristics of the second well region 29 are improved by the first well region 28.

[0412] The semiconductor device 1A may include an n-type first high concentration region 31 (upper high concentration region). The first high concentration region 31 may be formed above the depth position of the bottom wall of the gate structure 15. In this case, the second high concentration region 32 may be formed in a region below the first high concentration region 31 and have a lower concentration than the first high concentration region 31.

[0413] According to this configuration, the first heavily doped region 31 cancels out undesired p-type impurities introduced into the sides of the gate structure 15 due to process errors or the like. This suppresses fluctuations in the gate threshold voltage caused by the undesired p-type impurities. The first heavily doped region 31 also reduces the resistance value of the sides of the gate structure 15. This configuration is effective in reducing the on-resistance and JFET resistance.

[0414] The semiconductor device 1A may include a p-type body region 10. The body region 10 may be formed in the second semiconductor layer 7. In this case, the gate structure 15 may penetrate the body region 10. With this configuration, the second well region 29 can be appropriately formed below the body region 10.

[0415] The second well region 29 may be formed at a distance from the bottom of the body region 10. This configuration appropriately prevents the second well region 29 from being integrated with the body region 10, and suppresses fluctuations in the gate threshold voltage due to undesired p-type impurities.

[0416] The semiconductor device 1A may include a p-type contact region 37. The contact region 37 may extend along a sidewall of the gate structure 15. The contact region 37 may electrically connect the second well region 29 to the body region 10. This configuration prevents the second well region 29 from being electrically floating, improving the electrical response characteristics of the second well region 29.

[0417] The contact region 37 may have a p-type impurity concentration higher than the p-type impurity concentration of the second well region 29. The contact region 37 may have a p-type impurity concentration higher than the p-type impurity concentration of the body region 10.

[0418] The semiconductor device 1A may include an n-type source region 35. The source region 35 may be formed in a surface layer portion of the body region 10. According to this configuration, the source region 35 defines a channel CH at the bottom of the body region 10. The semiconductor device 1A may include a source electrode 45. The source electrode 45 may be electrically connected to the first main surface 3 and electrically separated from the gate structure 15.

[0419] Modifications applied to the semiconductor device 1A are shown below. Figures 16 to 30 are cross-sectional perspective views showing first to fifteenth modifications of the semiconductor device 1A. Figure 31 is a cross-sectional view showing a sixteenth modification of the semiconductor device 1A.

[0420] The semiconductor device 1A can include any one feature of the first to sixteenth modifications. The first to sixteenth modifications can be combined as appropriate. Therefore, the semiconductor device 1A can simultaneously include at least two features of the first to sixteenth modifications in the same cross-sectional area or different cross-sectional areas.

[0421] 16 (first modified example), semiconductor device 1A may include a plurality of high concentration regions 30 (second high concentration regions 32) that are deeper than the plurality of well regions 25 (second well regions 29). In other words, the plurality of high concentration regions 30 (second high concentration regions 32) may have bottoms that are located closer to the bottom of second semiconductor layer 7 than the depth positions of the bottoms of the plurality of well regions 25 (second well regions 29).

[0422] In this case, the bottoms of the multiple high-concentration regions 30 may overlap the bottoms of the multiple well regions 25. It is preferable that the bottoms of the multiple high-concentration regions 30 partially overlap the bottoms of the multiple well regions 25.

[0423] That is, it is preferable that the bottoms of the multiple high-concentration regions 30 are formed at intervals from one another in a region below the bottoms of the multiple well regions 25, and are opposed to one another in the horizontal direction across a part of the second semiconductor layer 7. In other words, it is preferable that the bottoms of the multiple high-concentration regions 30 do not entirely overlap the bottoms of the multiple well regions 25, leaving direct connection portions of the multiple well regions 25 to the second semiconductor layer 7.

[0424] 17 (second modified example), semiconductor device 1A may include second well region 29 formed in a shape tapering in the thickness direction. In other words, second well region 29 does not necessarily have to have second bulging region 26B. Of course, second well region 29 may extend in the thickness direction with a substantially constant width.

[0425] 18 (third modification), the semiconductor device 1A may include a plurality of high-concentration body regions 36 formed at intervals in the second direction Y following the extension direction of the gate structure 15. The plurality of high-concentration body regions 36 may each extend in a strip shape in the second direction Y.

[0426] The length of the multiple high concentration body regions 36 may be greater than or less than the width of the gate structure 15. The length of the multiple high concentration body regions 36 may be greater than or less than the pitch between the multiple gate structures 15.

[0427] The interval between the multiple high concentration body regions 36 may be larger or smaller than the width of the gate structures 15. The interval between the multiple high concentration body regions 36 may be larger or smaller than the pitch between the multiple gate structures 15.

[0428] Referring to Figure 19 (fourth variant), the semiconductor device 1A may have a first bulge region 26A (first well region 28), a second bulge region 26B (second well region 29), and a constriction region 27 positioned inward from the sidewall of the corresponding gate structure 15.

[0429] The first bulging region 26A may be located outward from the side wall of the gate structure 15, while the second bulging region 26B may be located inward from the side wall of the gate structure 15. In this case, the constricted region 27 may be located inward from the side wall of the gate structure 15 or outward from the side wall of the gate structure 15.

[0430] The first bulging region 26A may be located inward from the side wall of the gate structure 15, while the second bulging region 26B may be located outward from the side wall of the gate structure 15. In this case, the constricted region 27 may be located inward from the side wall of the gate structure 15 or outward from the side wall of the gate structure 15.

[0431] 20 (fifth modification), semiconductor device 1A may include a first well region 28 having a width smaller than that of gate structure 15, and a second well region 29 having a width larger than that of first well region 28. First well region 28 may be formed in a region along the bottom wall of gate structure 15, spaced inward from the sidewall of gate structure 15.

[0432] The second well region 29 may have a portion (upper end portion) connected to the bottom wall of the gate structure 15 in a region closer to the sidewall of the gate structure 15 than the periphery of the first well region 28. In this embodiment, the second well region 29 does not have the bulging region 26 and is formed in a shape tapering in the depth direction. Of course, the second well region 29 may extend in the thickness direction with a substantially constant width. Alternatively, the second well region 29 may have a width greater than the width of the gate structure 15 and form the bulging region 26.

[0433] 21 (sixth modified example), the semiconductor device 1A does not necessarily have to have the body high-concentration region 36. With reference to FIG. 22 (seventh modified example), the semiconductor device 1A does not necessarily have to have the first high-concentration region 31. With reference to FIG. 23 (eighth modified example), the semiconductor device 1A does not necessarily have to have the second high-concentration region 32.

[0434] 24 (ninth modified example), semiconductor device 1A does not necessarily have to have high concentration region 30 (first high concentration region 31 and second high concentration region 32). With reference to FIG. 25 (tenth modified example), semiconductor device 1A does not necessarily have to have second high concentration region 32 and second well region 29. With reference to FIG. 26 (eleventh modified example), semiconductor device 1A does not necessarily have to have high concentration region 30 (first high concentration region 31 and second high concentration region 32) and second well region 29.

[0435] 27 (twelfth modified example), semiconductor device 1A does not necessarily have to include first well region 28. In this embodiment, second well region 29 does not have bulging region 26 and is formed in a shape tapering in the depth direction. Of course, second well region 29 may extend in the thickness direction with a substantially constant width. Also, second well region 29 may have a width greater than the width of gate structure 15 and may form bulging region 26.

[0436] 28 (a thirteenth modification), semiconductor device 1A does not necessarily have to have second high-concentration region 32 and well region 25 (first well region 28 and second well region 29). Referring to Fig. 29 (a fourteenth modification), semiconductor device 1A does not necessarily have to have high-concentration region 30 (first high-concentration region 31 and second high-concentration region 32) and well region 25 (first well region 28 and second well region 29).

[0437] 30 (a fifteenth modification), semiconductor device 1A may include insulating film 17 having an upper end formed at a distance from the height position of first main surface 3 toward the bottom wall of trench 16. The upper end of insulating film 17 may expose chip 2 from the side wall and opening end of trench 16.

[0438] The electrode surface of the buried electrode 18 may protrude toward the first main surface 3 beyond the upper end of the insulating film 17. The electrode surface of the buried electrode 18 may be located closer to the bottom wall of the trench 16 than the upper end of the insulating film 17. The buried insulator 19 may be buried within the trench 16 above the upper end of the insulating film 17 and the electrode surface of the buried electrode 18.

[0439] The buried insulator 19 may cover the upper end of the insulating film 17 and the electrode surface of the buried electrode 18. The buried insulator 19 may have a portion that directly covers the sidewall of the trench 16. The body region 10, the source region 35, and the contact region 37 may each have a portion that is in direct contact with the buried insulator 19 in a portion along the gate structure 15.

[0440] 31 (sixteenth modification), the semiconductor device 1 does not have embedded insulators 19 in the multiple gate structures 15. A main surface insulating film 41 selectively covers the first main surface 3 in the active region 8. The main surface insulating film 41 directly covers the first main surface 3 (multiple mesa portions 20) around the inner parts of the multiple gate structures 15 and is connected to the multiple insulating films 17. The main surface insulating film 41 is formed integrally with the multiple insulating films 17 and is formed as an extension extended from the multiple insulating films 17 onto the first main surface 3.

[0441] In this embodiment, the interlayer film 43 collectively covers the plurality of gate structures 15 and the main surface insulating film 41 in the active region 8. The interlayer film 43 extends into the trench 16 from above the main surface insulating film 41, and covers the insulating film 17 and the buried electrode 18 within the trench 16. The interlayer film 43 has portions that cover the plurality of source regions 35 and the plurality of contact regions 37 with the main surface insulating film 41 in between.

[0442] In this embodiment, the semiconductor device 1 includes a plurality of source openings 44 formed in the interlayer film 43. The plurality of source openings 44 penetrate the interlayer film 43 and the main surface insulating film 41, and selectively expose a plurality of mesa portions 20. The plurality of source openings 44 may be formed in a one-to-one correspondence with one mesa portion 20.

[0443] In this case, the plurality of source openings 44 are formed in strip shapes extending in the second direction Y in accordance with the extension direction of the corresponding mesa portions 20. The plurality of source openings 44 selectively expose the plurality of source regions 35 and the plurality of contact regions 37 from the corresponding mesa portions 20, respectively.

[0444] Of course, a plurality of source openings 44 may be formed in a one-to-many correspondence with one mesa portion 20. In this case, the plurality of source openings 44 are formed at intervals along the extension direction of the corresponding mesa portion 20.

[0445] The source openings 44 may be formed in a strip shape, a square shape, a circle shape, or the like extending in the second direction Y. The source openings 44 selectively expose the source regions 35 and the contact regions 37 from the corresponding mesa portions 20.

[0446] The source electrode 45 extends from above the interlayer film 43 into the plurality of source openings 44 and is electrically connected to the plurality of source regions 35 and the plurality of contact regions 37 within the plurality of source openings 44 .

[0447] The source electrode 45 includes a lower electrode film 46 and a main electrode film 47. The lower electrode film 46 has a laminated structure including a first electrode film 48 and a second electrode film 49. Of course, the lower electrode film 46 may have a single-layer structure made of the first electrode film 48.

[0448] The first electrode film 48 collectively covers the region of the interlayer film 43 where the multiple source openings 44 are formed, and extends into the multiple source openings 44 from above the interlayer film 43. The first electrode film 48 has a portion that covers the insulating surface of the interlayer film 43 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 44 in a film-like manner, and a portion that covers the first main surface 3 within the multiple source openings 44. The first electrode film 48 is mechanically and electrically connected to the multiple source regions 35 and the multiple contact regions 37.

[0449] The second electrode film 49 directly covers the first electrode film 48. The second electrode film 49 collectively covers the region of the interlayer film 43 where the multiple source openings 44 are formed, sandwiching the first electrode film 48 therebetween, and extends from above the interlayer film 43 into the multiple source openings 44.

[0450] The second electrode film 49 has a portion that covers the insulating surface of the interlayer film 43 in a film-like manner with the first electrode film 48 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of source openings 44 in a film-like manner with the first electrode film 48 sandwiched therebetween, and a portion that covers the first main surface 3 in a film-like manner with the first electrode film 48 sandwiched therebetween within the plurality of source openings 44. The second electrode film 49 is electrically connected to the plurality of source regions 35 and the plurality of contact regions 37 via the first electrode film 48 within the source openings 44.

[0451] The main electrode film 47 directly covers the lower electrode film 46 (second electrode film 49). The main electrode film 47 collectively covers the region of the interlayer film 43 where the plurality of source openings 44 are formed, and backfills the plurality of source openings 44.

[0452] The main electrode film 47 has a portion that covers the insulating surface of the interlayer film 43 with the lower electrode film 46 in between, a portion that covers the wall surfaces of the plurality of source openings 44 with the lower electrode film 46 in between, and a portion that covers the first main surface 3 with the lower electrode film 46 in between. The main electrode film 47 is electrically connected to the plurality of source regions 35 and the plurality of contact regions 37 via the lower electrode film 46 in the plurality of source openings 44.

[0453] The structure (technical concept) in which the second well region 29 and the second high-concentration region 32 are separately formed as described above is also applicable to other embodiments. Below, a configuration in which the technical concept of the second well region 29 and the second high-concentration region 32 is adopted will be described as a semiconductor device 1B according to a second embodiment. Figure 32 is a cross-sectional perspective view showing the semiconductor device 1B according to the second embodiment.

[0454] 32, the semiconductor device 1B may include various device structures. The semiconductor device 1B may have one or more device structures. The device structure may include at least one of a semiconductor switching device, a semiconductor rectifying device, and a semiconductor passive device. The multiple device structures may form an LSI (Large Scale Integration).

[0455] The semiconductor switching device may include at least one of a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a junction field effect transistor (JFET).

[0456] The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0457] Similar to the semiconductor device 1A, the semiconductor device 1B includes a chip 2, a first semiconductor layer 6, a second semiconductor layer 7, an active region 8, and a peripheral region 9. Fig. 32 shows a cross-sectional perspective view of a main portion of the active region 8. The first semiconductor layer 6 has its concentration adjusted by a base element, and the second semiconductor layer 7 has its concentration adjusted by a first element (nitrogen in this embodiment).

[0458] The semiconductor device 1B includes a plurality of p-type well regions 60 formed in the chip 2 (second semiconductor layer 7). The well regions 60 correspond to the second well region 29 (well region 25) described above. The plurality of well regions 60 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7, and convert the conductivity type of the second semiconductor layer 7 from n-type to p-type.

[0459] The multiple well regions 60 are formed in the second semiconductor layer 7 at intervals in the horizontal direction (first direction X). The multiple well regions 60 each extend in a strip shape in the second direction Y in a plan view. In other words, the multiple well regions 60 are arranged in stripes extending in the second direction Y in a plan view.

[0460] The extending direction of the multiple well regions 60 coincides with the off-direction of the SiC single crystal. The multiple well regions 60 may extend in the first direction X. In this case, the multiple well regions 60 intersect (specifically, are perpendicular to) the off-direction.

[0461] The multiple well regions 60 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first major surface 3, and face the first semiconductor layer 6 across a part of the second semiconductor layer 7. Each of the multiple well regions 60 has an upper end located on the first major surface 3 side, and a bottom (lower end) located on the bottom side of the second semiconductor layer 7.

[0462] In this embodiment, the upper ends of the multiple well regions 60 are formed at intervals from the first major surface 3 toward the bottom of the second semiconductor layer 7. The upper ends of the multiple well regions 60 may be exposed from the first major surface 3. The upper ends of the multiple well regions 60 are located on the first major surface 3 side with respect to a depth position of an intermediate portion of the second semiconductor layer 7.

[0463] The bottoms of the multiple well regions 60 may be located on the bottom side of the second semiconductor layer 7 (closer to the second main surface 4) with respect to the depth position of the intermediate portion of the second semiconductor layer 7, or may be located on the first main surface 3 side with respect to the depth position of the intermediate portion of the second semiconductor layer 7. The bottoms of the multiple well regions 60 are directly connected to the second semiconductor layer 7. The multiple well regions 60, together with the second semiconductor layer 7, form a JFET region Tj.

[0464] The well region 60 may have a depth of 0.5 μm to 5 μm. The depth of the well region 60 may have a value belonging to at least one of the ranges of 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0465] The well region 60 may have a width of 0.1 μm to 10 μm. The width of the well region 60 may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, 4.5 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0466] The concentration gradient of the well region 60 will be described below with reference to Fig. 33. Fig. 33 is a graph showing the impurity concentration of the well region 60. In Fig. 33, the vertical axis represents the p-type impurity concentration of the well region 60, and the horizontal axis represents the depth.

[0467] The well region 60 is formed by introducing a p-type impurity (trivalent element) into the second semiconductor layer 7. The well region 60 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7, and converts the conductivity type of the second semiconductor layer 7 from n-type to p-type. The well region 60 contains a second element consisting of a trivalent element in addition to the pentavalent element of the second semiconductor layer 7 (i.e., the first element, nitrogen in this form).

[0468] The second element may include at least one of boron and aluminum. The well region 60 is preferably adjusted in concentration with a single second element. The second element is preferably aluminum.

[0469] The well region 60 has a concentration gradient that is different from the concentration gradient of the second semiconductor layer 7. The well region 60 is made of a channeling region in which a large amount of trivalent elements is dispersed along the axial channel of the SiC single crystal (second semiconductor layer 7). That is, in this form, the well region 60 extends along the c-axis of the SiC single crystal and is inclined at the off direction and off angle described above.

[0470] The concentration gradient of well region 60 includes, from the top to the bottom, a first increasing portion 61, a first peak portion 62, a first gradual portion 63, and a first decreasing portion 64. First increasing portion 61 forms the top end of well region 60, and is a region where the p-type impurity concentration increases steeply and gradually toward the bottom.

[0471] The first peak portion 62 is a concentration transition region where the p-type impurity concentration changes from increasing to decreasing, and has a maximum value of the p-type impurity concentration. The first peak portion 62 is formed in a region closer to the upper end of the well region 60 than the depth position of the middle portion of the well region 60.

[0472] The first gradual decrease portion 63 has a concentration decrease rate that is smaller than the concentration decrease rate of the first peak portion 62 (decreasing region), and is a portion that maintains a constant p-type impurity concentration within a certain depth range. The first gradual decrease portion 63 forms an intermediate portion of the well region 60 as the main body of the well region 60.

[0473] The p-type impurity concentration of the first gradual decrease portion 63 gradually decreases (in this form, monotonically decreases) in a concentration range that is lower than the p-type impurity concentration of the first peak portion 62. In other words, the first gradual decrease portion 63 does not have a concentration gradient that increases sharply from the first peak portion 62.

[0474] The first gradual region 63 may have a concentration decrease rate of 50% or less over a depth range of at least 0.25 μm. The first gradual region 63 may have a concentration decrease rate of 50% or less over a depth range of at least 0.5 μm. The first gradual region 63 may have a concentration decrease rate of 50% or less over a thickness range of 25% of the well region 60. The first gradual region 63 may have a concentration decrease rate of 50% or less over a thickness range of 50% of the well region 60.

[0475] The first decreasing portion 64 forms the bottom of the well region 60, and is a region in which the p-type impurity concentration gradually decreases (in this form, monotonically decreases) from the first gradual portion 63 toward the bottom. The first decreasing portion 64 has a concentration decrease rate that is greater than that of the first gradual portion 63. The concentration decrease rate per unit depth of the first decreasing portion 64 is greater than that of the first gradual portion 63. The first decreasing portion 64, which has the lowest p-type impurity concentration in the well region 60, is directly connected to the second semiconductor layer 7.

[0476] The semiconductor device 1B includes a plurality of n-type high-concentration regions 70 formed in the chip 2 (second semiconductor layer 7). The high-concentration regions 70 are regions corresponding to the second high-concentration regions 32 (high-concentration regions 30) described above. The plurality of high-concentration regions 70 have a higher n-type impurity concentration than the n-type impurity concentration of the second semiconductor layer 7, thereby increasing the n-type impurity concentration of the second semiconductor layer 7.

[0477] The multiple high concentration regions 70 may be considered as high concentration portions of the second semiconductor layer 7. The n-type impurity concentration of the multiple high concentration regions 70 can be appropriately compared by comparing it with the n-type impurity concentration on the bottom side of the second semiconductor layer 7. The high concentration regions 70 may also be referred to as "high concentration drift regions."

[0478] The multiple high concentration regions 70 are formed at intervals from one another in the horizontal direction (first direction X) within the second semiconductor layer 7. The multiple high concentration regions 70 each extend in a strip shape in the second direction Y in a planar view. In other words, the multiple high concentration regions 70 are arranged in stripes extending in the second direction Y in a planar view.

[0479] The extending direction of the multiple high-concentration regions 70 coincides with the off-direction of the SiC single crystal. The multiple high-concentration regions 70 may extend in the first direction X. In this case, the multiple high-concentration regions 70 intersect (specifically, are perpendicular to) the off-direction.

[0480] The plurality of high-concentration regions 70 are formed in regions between the plurality of well regions 60, and are electrically connected to the plurality of well regions 60 located on both sides thereof. The plurality of high-concentration regions 70 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3, and face the first semiconductor layer 6 with a part of the second semiconductor layer 7 interposed therebetween.

[0481] Each of the multiple high-concentration regions 70 has an upper end located on the first major surface 3 side and a bottom (lower end) located on the bottom side of the second semiconductor layer 7. In this embodiment, the upper ends of the multiple high-concentration regions 70 are formed at intervals from the first major surface 3 to the bottom side of the second semiconductor layer 7.

[0482] The upper ends of the multiple high-concentration regions 70 may be located closer to the first major surface 3 than the depth positions of the upper ends of the multiple well regions 60, or may be located closer to the bottom of the second semiconductor layer 7 than the depth positions of the upper ends of the multiple well regions 60. The upper ends of the multiple high-concentration regions 70 may be exposed from the first major surface 3. The upper ends of the multiple high-concentration regions 70 are located closer to the first major surface 3 than the depth position of an intermediate portion of the second semiconductor layer 7.

[0483] The bottoms of the multiple high-concentration regions 70 may be located on the bottom side of the second semiconductor layer 7 (the second major surface 4 side) relative to the depth position of the intermediate part of the second semiconductor layer 7, or may be located on the first major surface 3 side relative to the depth position of the intermediate part of the second semiconductor layer 7.

[0484] In this embodiment, the bottoms of the multiple high-concentration regions 70 are located closer to the first main surface 3 than the depth positions of the bottoms of the multiple well regions 60. In other words, the bottoms of the multiple high-concentration regions 70 are formed at intervals from the bottoms of the well regions 60 toward the first main surface 3, maintaining a configuration in which the well regions 60 are directly connected to the second semiconductor layer 7. The bottoms of the multiple high-concentration regions 70 are connected to the well regions 60 in regions on the bottom side relative to the depth positions of the intermediate portions of the multiple well regions 60.

[0485] The multiple high-concentration regions 70 may be formed deeper than the multiple well regions 60 (see also FIG. 16 ). That is, the bottoms of the multiple high-concentration regions 70 may be located closer to the bottom of the second semiconductor layer 7 than the depth positions of the bottoms of the multiple well regions 60. In this case, the bottoms of the multiple high-concentration regions 70 may overlap the bottoms of the multiple well regions 60. It is preferable that the bottoms of the multiple high-concentration regions 70 partially overlap the bottoms of the multiple well regions 60.

[0486] That is, it is preferable that the bottoms of the multiple high-concentration regions 70 are formed at intervals from one another in a region below the bottoms of the multiple well regions 60, and are opposed to one another in the horizontal direction across a part of the second semiconductor layer 7. In other words, it is preferable that the bottoms of the multiple high-concentration regions 70 do not entirely overlap the bottoms of the multiple well regions 60, leaving direct connection portions of the multiple well regions 60 to the second semiconductor layer 7.

[0487] The high concentration region 70 may have a width approximately equal to the width of the well region 60. The width of the high concentration region 70 may be smaller than the width of the well region 60. The width of the high concentration region 70 may be larger than the width of the well region 60.

[0488] The width of the high-concentration region 70 may be 0.1 μm or more and 5 μm or less. The width of the high-concentration region 70 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0489] The high concentration region 70 may have a depth approximately equal to the depth of the well region 60. The depth of the high concentration region 70 may be smaller than the depth of the well region 60. The depth of the high concentration region 70 may be greater than the depth of the well region 60.

[0490] The depth of the high-concentration region 70 may be 0.1 μm or more and 10 μm or less. The depth of the high-concentration region 70 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less.

[0491] The plurality of high-concentration regions 70 respectively form pn junctions with the plurality of well regions 60. The bottoms of the plurality of high-concentration regions 70 form a JFET region Tj together with the plurality of well regions 60. The plurality of high-concentration regions 70 may form a charge balance with the plurality of well regions 60.

[0492] According to this configuration, the multiple high concentration regions 70 form a super junction structure together with the multiple well regions 60. The multiple high concentration regions 70 do not necessarily have to form a super junction structure together with the multiple well regions 60, and may simply form a body diode structure.

[0493] The concentration gradient of the high concentration region 70 will be described below with reference to Fig. 34. Fig. 34 is a graph showing the impurity concentration of the high concentration region 70. In Fig. 34, the vertical axis represents the p-type impurity concentration of the high concentration region 70, and the horizontal axis represents the depth.

[0494] The high concentration region 70 is formed by introducing an n-type impurity (a pentavalent element) into the second semiconductor layer 7. The n-type impurity concentration of the high concentration region 70 may be lower than the p-type impurity concentration of the well region 60, or may be lower than the p-type impurity concentration of the well region 60.

[0495] The high concentration region 70 includes a third element consisting of a pentavalent element in addition to the pentavalent element (i.e., the first element, nitrogen in this form) of the second semiconductor layer 7. The third element is an additional pentavalent element to the first element of the second semiconductor layer 7. The third element may include at least one of nitrogen, phosphorus, and arsenic.

[0496] The third element in the high concentration region 70 may be the same type as the first element in the second semiconductor layer 7, or may be a different type from the first element in the second semiconductor layer 7. The third element is preferably different from the first element. That is, the high concentration region 70 preferably contains multiple types of pentavalent elements. The concentration of the high concentration region 70 is preferably adjusted by a single third element. The third element is preferably phosphorus. That is, the concentration of the high concentration region 70 is preferably adjusted by nitrogen and phosphorus.

[0497] The impurity concentration of the high concentration region 70 is separated from the impurity concentration of the well region 60. The concentration of the second element (trivalent element) in the high concentration region 70 is lower than the concentration of the second element in the well region 60. The high concentration region 70 does not contain the second element of the well region 60. "The high concentration region 70 does not contain the second element" means that the concentration of the second element in the inner part of the high concentration region 70 is lower than the detection limit, and even if it is detected, it is at the noise level.

[0498] Similarly, the concentration of the third element in the high concentration region 70 in the well region 60 is lower than the concentration of the third element in the high concentration region 70. The well region 60 does not contain the third element in the high concentration region 70. "The well region 60 does not contain the third element" means that the concentration of the third element in the inner part of the well region 60 is lower than the detection limit, and even if it is detected, it is at the noise level.

[0499] The high concentration region 70 has a concentration gradient that is different from the concentration gradient of the second semiconductor layer 7. The high concentration region 70 is made of a channeling region in which a large amount of pentavalent elements is scattered along the axial channel of the SiC single crystal (second semiconductor layer 7). That is, in this form, the high concentration region 70 extends along the c-axis of the SiC single crystal and is inclined at the off direction and off angle described above.

[0500] The concentration gradient of the high concentration region 70 includes, from the top to the bottom, a second increasing portion 71, a second peak portion 72, a second gradual portion 73, and a second decreasing portion 74. The second increasing portion 71 forms the top end of the high concentration region 70, and is a region where the n-type impurity concentration increases steeply and gradually toward the bottom.

[0501] The second increased portion 71 may be connected to the first increased portion 61 of the well region 60. The second increased portion 71 may be formed at a depth position substantially equal to that of the first increased portion 61. The second increased portion 71 may be located closer to the first major surface 3 than the depth position of the first increased portion 61, or may be located closer to the bottom of the second semiconductor layer 7.

[0502] The second peak portion 72 is a concentration transition region where the n-type impurity concentration changes from increasing to decreasing, and the n-type impurity concentration reaches its maximum value. The second peak portion 72 is formed in a region closer to the upper end of the high-concentration region 70 than the depth position of the middle portion of the high-concentration region 70.

[0503] The second peak portion 72 may be connected to the first peak portion 62 of the well region 60. The second peak portion 72 may be formed at a depth position substantially equal to that of the first peak portion 62. The second peak portion 72 may be located closer to the first main surface 3 than the depth position of the first peak portion 62, or may be located closer to the bottom of the second semiconductor layer 7.

[0504] The second gradual decrease portion 73 has a concentration decrease rate that is smaller than the concentration decrease rate of the second peak portion 72 (decreasing region), and is a portion that maintains a constant n-type impurity concentration within a certain depth range. The second gradual decrease portion 73 forms an intermediate portion of the high-concentration region 70 as the main body of the high-concentration region 70.

[0505] The n-type impurity concentration of the second gradual decrease portion 73 gradually decreases (in this form, monotonically decreases) in a concentration range that is lower than the n-type impurity concentration of the second peak portion 72. In other words, the second gradual decrease portion 73 does not have a concentration gradient that increases sharply from the second peak portion 72 as a starting point.

[0506] The second gradual portion 73 may have a concentration decrease rate of 50% or less over a depth range of at least 0.25 μm. The second gradual portion 73 may have a concentration decrease rate of 50% or less over a depth range of at least 0.5 μm. The second gradual portion 73 may have a concentration decrease rate of 50% or less over a thickness range of 25% of the high-concentration region 70. The second gradual portion 73 may have a concentration decrease rate of 50% or less over a thickness range of 50% of the high-concentration region 70.

[0507] The second gentle slope portion 73 may be connected to the first gentle slope portion 63 of the well region 60. The second gentle slope portion 73 may be formed at a depth position substantially equal to that of the first gentle slope portion 63. The second gentle slope portion 73 may be located closer to the first main surface 3 than the depth position of the first gentle slope portion 63, or may be located closer to the bottom of the second semiconductor layer 7.

[0508] The second decreasing portion 74 forms the bottom of the high-concentration region 70, and is a region in which the n-type impurity concentration gradually decreases (in this form, monotonically decreases) from the second gradual portion 73 toward the bottom. The second decreasing portion 74 has a concentration decrease rate that is greater than that of the second gradual portion 73. The concentration decrease rate per unit depth of the second decreasing portion 74 is greater than that of the second gradual portion 73. The second decreasing portion 74, which has the lowest n-type impurity concentration in the high-concentration region 70, is directly connected to the second semiconductor layer 7.

[0509] The second reduced portion 74 may be connected to the first reduced portion 64 of the well region 60. The second reduced portion 74 may be formed at a depth position substantially equal to that of the first reduced portion 64. The second reduced portion 74 may be located closer to the first main surface 3 than the depth position of the first reduced portion 64, or may be located closer to the bottom of the second semiconductor layer 7.

[0510] As described above, the semiconductor device 1B may include an n-type second semiconductor layer 7 (semiconductor layer), a p-type well region 60 (well region 60), and an n-type high-concentration region 70. The well region 60 may be formed in the second semiconductor layer 7 to have a higher concentration than the second semiconductor layer 7. The high-concentration region 70 may be formed in the second semiconductor layer 7 to have a higher concentration than the second semiconductor layer 7. The high-concentration region 70 may form a pn junction with the well region 60.

[0511] This configuration provides a semiconductor device 1B having a novel layout. For example, in this semiconductor device 1B, the high-concentration region 70 forms a JFET region Tj together with the well region 60. Therefore, the breakdown voltage can be appropriately improved by the JFET region Tj.

[0512] The second semiconductor layer 7 may contain SiC. This configuration provides a semiconductor device 1B as a SiC semiconductor device having a novel layout. The semiconductor device 1B further improves the breakdown voltage due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high-voltage environments, the effect of improving the breakdown voltage by the JFET region Tj including the well region 60 and the high-concentration region 70 is effective.

[0513] The well region 60 may have a p-type impurity concentration that is separated from the n-type impurity concentration of the high concentration region 70. With this configuration, the p-type impurity concentration of the well region 60 is appropriately adjusted, and the JFET region Tj is appropriately formed. Therefore, the breakdown voltage can be appropriately improved by the JFET region Tj.

[0514] The high-concentration region 70 may have an impurity concentration that is separated from the impurity concentration of the well region 60. With this configuration, the n-type impurity concentration of the high-concentration region 70 is appropriately adjusted, and the JFET region Tj is appropriately formed. Therefore, the breakdown voltage can be appropriately improved by the JFET region Tj.

[0515] The concentration of the second semiconductor layer 7 may be adjusted by a first element consisting of a pentavalent element. The concentration of the well region 60 may be adjusted by a second element consisting of a trivalent element in addition to the first element. The concentration of the high concentration region 70 may be adjusted by a third element consisting of a pentavalent element in addition to the first element.

[0516] The concentration of the third element in the well region 60 may be less than the concentration of the third element in the high concentration region 70. With this configuration, the p-type impurity concentration of the well region 60 can be appropriately separated from the n-type impurity concentration of the high concentration region 70. In this case, the inner portion of the well region 60 does not need to contain the third element.

[0517] The concentration of the second element in the high concentration region 70 may be less than the concentration of the second element in the well region 60. According to this configuration, the n-type impurity concentration of the high concentration region 70 can be appropriately separated from the p-type impurity concentration of the well region 60. In this case, the inner part of the high concentration region 70 does not need to contain the second element.

[0518] The first element may include at least one of nitrogen, phosphorus, and arsenic. The first element may be composed of a single pentavalent element. The first element may be nitrogen.

[0519] The third element may include at least one of boron and aluminum. The third element may be composed of a single trivalent element. The third element may be aluminum.

[0520] The fifth element may include at least one of nitrogen, phosphorus, and arsenic. The fifth element may be the same species as the first element. The fifth element may be a different species from the first element. The fifth element may be composed of a single pentavalent element. The fifth element may be phosphorus.

[0521] The high concentration region 70 may have a bottom located higher than the depth position of the bottom of the well region 60. The high concentration region 70 may have a bottom located lower than the bottom of the well region 60. The depth of the high concentration region 70 is adjusted appropriately depending on the JFET region Tj to be achieved.

[0522] The high concentration region 70 may form a super junction structure with the well region 60. According to this configuration, the breakdown voltage can be appropriately improved by the super junction structure.

[0523] Fig. 35 is a plan view showing a semiconductor device 1C according to the third embodiment. Fig. 36 is an enlarged plan view showing a main part of the active region 8 shown in Fig. 35. Fig. 37 is a cross-sectional view taken along line XXXVII-XXXVII shown in Fig. 36.

[0524] The semiconductor device 1C has a configuration in which the configuration of the semiconductor device 1B (well region 60 and high-concentration region 70) is combined with a planar gate type transistor structure Tr, which is an example of a device structure, into the planar gate structure. Similar to the semiconductor device 1A, the semiconductor device 1C includes a chip 2, a first semiconductor layer 6, a second semiconductor layer 7, an active region 8, and a peripheral region 9.

[0525] The semiconductor device 1C includes a plurality of p-type body regions 80 formed in a surface layer portion of the first main surface 3 in the active region 8. The plurality of body regions 80 are arranged at intervals in the first direction X and extend in a strip shape in the second direction Y. In other words, the plurality of body regions 80 are arranged in stripes extending in the second direction Y. The extension direction of the plurality of body regions 80 coincides with the off-direction of the SiC single crystal.

[0526] Of course, the multiple body regions 80 may be arranged at intervals in the second direction Y and extend in strip shapes in the first direction X. In this case, the extending direction of the multiple body regions 80 intersects (is perpendicular to) the off-direction of the SiC single crystal.

[0527] The plurality of body regions 80 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first major surface 3, and face the first semiconductor layer 6 across a part of the second semiconductor layer 7. The plurality of body regions 80 are preferably formed at intervals from a depth position of an intermediate portion of the second semiconductor layer 7 toward the first major surface 3. The plurality of body regions 80 are exposed from the first major surface 3.

[0528] The semiconductor device 1C includes a plurality of n-type source regions 81 (impurity regions) formed in the surface layer portions of the plurality of body regions 80. The plurality of source regions 81 each have an n-type impurity concentration higher than the p-type impurity concentration of the plurality of body regions 80, thereby converting the conductivity type of the corresponding body region 80 from p-type to n-type. The n-type impurity concentration of the plurality of source regions 81 is higher than the n-type impurity concentration of the second semiconductor layer 7.

[0529] In this embodiment, the multiple source regions 81 are formed in a one-to-one correspondence with the multiple body regions 80. The multiple source regions 81 are formed spaced apart inward from both sides of the corresponding body region 80 in the first direction X, and extend in a strip-like shape along the extension direction (second direction Y) of the corresponding body region 80. Of course, when the extension direction of the multiple body regions 80 is the first direction X, the multiple source regions 81 may each extend in a strip-like shape in the first direction X.

[0530] The plurality of source regions 81 are formed at intervals from the bottoms of the corresponding body regions 80 toward the first main surface 3, and face the second semiconductor layer 7 in the thickness direction with a part of the corresponding body region 80 sandwiched therebetween. The plurality of source regions 81 are exposed from the first main surface 3.

[0531] The semiconductor device 1C includes a plurality of p-type contact regions 82 formed in the surface layer portions of the plurality of body regions 80. The contact regions 82 have a p-type impurity concentration higher than the p-type impurity concentration of the body regions 80.

[0532] In this embodiment, the plurality of contact regions 82 are formed in a one-to-one correspondence with the plurality of body regions 80. The plurality of contact regions 82 are formed spaced apart inward from both sides of the corresponding body region 80 in the first direction X, and extend in a strip-like shape along the extension direction (second direction Y) of the corresponding body region 80. Of course, when the extension direction of the plurality of body regions 80 is the first direction X, the plurality of source regions 81 may also extend in a strip-like shape in the first direction X.

[0533] The plurality of contact regions 82 are formed in the surface layer portion of the corresponding body region 80 so as to penetrate the inner portion (the central portion in this embodiment) of the corresponding source region 81. The plurality of contact regions 82 each have a depth greater than the depth of the source region 81, and are directly connected to the corresponding body region 80.

[0534] The plurality of contact regions 82 are formed at intervals from the bottoms of the corresponding body regions 80 toward the first main surface 3, and face the second semiconductor layer 7 in the thickness direction with a part of the corresponding body region 80 sandwiched therebetween. The plurality of contact regions 82 are exposed from the first main surface 3.

[0535] The semiconductor device 1C includes a plurality of p-type well regions 60 formed in the chip 2 (second semiconductor layer 7). The plurality of well regions 60 are formed in the second semiconductor layer 7 in regions below (specifically, directly below) the plurality of body regions 80, spaced apart from one another in the horizontal direction (first direction X).

[0536] The multiple well regions 60 are each formed in a thickness range between the bottom of the second semiconductor layer 7 and the bottoms of the multiple body regions 80, and overlap the multiple body regions 80 in a one-to-one correspondence in the thickness direction.

[0537] The multiple well regions 60 extend in a strip-like manner in the second direction Y in a plan view, following the extension direction of the corresponding body regions 80. That is, the multiple well regions 60 are arranged in a stripe-like manner extending in the second direction Y in a plan view. The extension direction of the multiple well regions 60 coincides with the off-direction of the SiC single crystal. The multiple well regions 60 may extend in the first direction X in accordance with the extension direction of the multiple body regions 80. In this case, the multiple body regions 80 intersect (specifically, are perpendicular to) the off-direction.

[0538] The multiple well regions 60 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first major surface 3, and face the first semiconductor layer 6 across a part of the second semiconductor layer 7. Each of the multiple well regions 60 has an upper end located on the first major surface 3 side, and a bottom (lower end) located on the bottom side of the second semiconductor layer 7.

[0539] In this embodiment, the upper ends of the multiple well regions 60 are connected to the corresponding body regions 80. The bottoms of the multiple well regions 60 may be located on the bottom side of the second semiconductor layer 7 (closer to the second main surface 4) with respect to the depth position of the intermediate portion of the second semiconductor layer 7, or may be located on the first main surface 3 side with respect to the depth position of the intermediate portion of the second semiconductor layer 7. The bottoms of the multiple well regions 60 are directly connected to the second semiconductor layer 7. The multiple well regions 60 form a JFET region Tj together with the second semiconductor layer 7 in a region below the body region 80.

[0540] The semiconductor device 1C includes a plurality of n-type high concentration regions 70 formed in the chip 2 (second semiconductor layer 7). The plurality of high concentration regions 70 are formed in the second semiconductor layer 7 in regions between the plurality of well regions 60 at intervals in the horizontal direction (first direction X). The plurality of high concentration regions 70 are each formed in a thickness range between the bottom of the second semiconductor layer 7 and the bottoms of the plurality of body regions 80.

[0541] The multiple high-concentration regions 70 extend in a strip-like manner in the second direction Y in a plan view, following the extension direction of the multiple well regions 60. That is, the multiple high-concentration regions 70 are arranged in a stripe-like manner extending in the second direction Y in a plan view. The extension direction of the multiple high-concentration regions 70 coincides with the off-direction of the SiC single crystal. The multiple high-concentration regions 70 may extend in the first direction X in accordance with the extension direction of the multiple well regions 60. In this case, the multiple high-concentration regions 70 intersect (specifically, are perpendicular to) the off-direction.

[0542] The multiple high-concentration regions 70 are electrically connected to the multiple well regions 60 located on both sides thereof. The multiple high-concentration regions 70 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first major surface 3, and face the first semiconductor layer 6 with a part of the second semiconductor layer 7 in between. Each of the multiple high-concentration regions 70 has an upper end located on the first major surface 3 side, and a bottom (lower end) located on the bottom side of the second semiconductor layer 7.

[0543] In this embodiment, the upper ends of the multiple high concentration regions 70 are formed at intervals from the first major surface 3 toward the bottom of the second semiconductor layer 7. The upper ends of the multiple high concentration regions 70 may be located on the first major surface 3 side with respect to the depth positions of the bottoms of the multiple body regions 80, or may be located on the bottom side of the second semiconductor layer 7 with respect to the depth positions of the bottoms of the multiple body regions 80. The upper ends of the multiple high concentration regions 70 may be exposed from the first major surface 3.

[0544] The bottoms of the multiple high-concentration regions 70 may be located on the bottom side of the second semiconductor layer 7 (the second major surface 4 side) relative to the depth position of the intermediate part of the second semiconductor layer 7, or may be located on the first major surface 3 side relative to the depth position of the intermediate part of the second semiconductor layer 7.

[0545] In this embodiment, the bottoms of the multiple high-concentration regions 70 are located closer to the first main surface 3 than the depth positions of the bottoms of the multiple well regions 60. In other words, the bottoms of the multiple high-concentration regions 70 are formed at intervals from the bottoms of the well regions 60 toward the first main surface 3, maintaining a configuration in which the well regions 60 are directly connected to the second semiconductor layer 7. The bottoms of the multiple high-concentration regions 70 are connected to the well regions 60 in regions on the bottom side relative to the depth positions of the intermediate portions of the multiple well regions 60.

[0546] The multiple high-concentration regions 70 may be formed deeper than the multiple well regions 60 (see also FIG. 16 ). That is, the bottoms of the multiple high-concentration regions 70 may be located closer to the bottom of the second semiconductor layer 7 than the depth positions of the bottoms of the multiple well regions 60. In this case, the bottoms of the multiple high-concentration regions 70 may overlap the bottoms of the multiple well regions 60. It is preferable that the bottoms of the multiple high-concentration regions 70 partially overlap the bottoms of the multiple well regions 60.

[0547] That is, it is preferable that the bottoms of the multiple high-concentration regions 70 are formed at intervals from one another in a region below the bottoms of the multiple well regions 60, and are opposed to one another in the horizontal direction across a part of the second semiconductor layer 7. In other words, it is preferable that the bottoms of the multiple high-concentration regions 70 do not entirely overlap the bottoms of the multiple well regions 60, leaving direct connection portions of the multiple well regions 60 to the second semiconductor layer 7.

[0548] The plurality of high-concentration regions 70 respectively form pn junctions with the plurality of well regions 60. The bottoms of the plurality of high-concentration regions 70 form a JFET region Tj together with the plurality of well regions 60. The plurality of high-concentration regions 70 may form a charge balance with the plurality of well regions 60.

[0549] According to this configuration, the multiple high concentration regions 70 form a super junction structure together with the multiple well regions 60. The multiple high concentration regions 70 do not necessarily have to form a super junction structure together with the multiple well regions 60, and may simply form a body diode structure.

[0550] The semiconductor device 1C includes a plurality of p-type channel regions 83 defined in surface layer portions of a plurality of body regions 80. The plurality of channel regions 83 are defined in regions between a plurality of source regions 81 and the second semiconductor layer 7 (high concentration region 70) in the surface layer portions of the plurality of body regions 80. The plurality of channel regions 83 form a current path extending horizontally along the first main surface 3.

[0551] The semiconductor device 1C includes a plurality of planar gate structures 85 arranged on the first main surface 3 in the active region 8. The plurality of gate structures 85 are arranged on both sides of the plurality of body regions 80 on the first main surface 3, and face the plurality of high-concentration regions 70 in the thickness direction.

[0552] The multiple gate structures 85 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the multiple gate structures 85 are arranged in a strip shape extending in the second direction Y. The extending direction of the multiple gate structures 85 also coincides with the off-direction of the SiC single crystal. Of course, when the extending direction of the multiple body regions 80 is the first direction X, the multiple gate structures 85 may each extend in a strip shape in the first direction X.

[0553] The plurality of gate structures 85 each cover at least one channel region 83 (periphery of the body region 80). The plurality of gate structures 85 are positioned on the at least one channel region 83, and each cover at least one peripheral portion of the body region 80, at least one source region 81, and one heavily doped region 70.

[0554] In this embodiment, the multiple gate structures 85 cross one high-concentration region 70 in the first direction X and extend across the peripheral portions of two adjacent body regions 80. Specifically, the multiple gate structures 85 extend across the peripheral portion of the source region 81 of one body region 80 and the peripheral portion of the source region 81 of the other body region 80, respectively covering the two source regions 81, one high-concentration region 70, and two channel regions 83. The multiple gate structures 85 expose the multiple source regions 81 and the multiple contact regions 82.

[0555] Each of the plurality of gate structures 85 has a laminated structure including an insulating film 86 and a planar electrode 87. The insulating film 86 may be referred to as a "gate insulating film," and the planar electrode 87 may be referred to as a "gate electrode."

[0556] The insulating films 86 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating films 86 have a single-layer structure made of a silicon oxide film. The insulating films 86 preferably include a silicon oxide film made of an oxide of the chip 2.

[0557] The insulating films 86 are arranged on both sides of the body regions 80 on the first main surface 3, respectively, and cover the first main surface 3 in a film-like manner. The insulating films 86 are arranged at intervals in the first direction X, and are each formed in a strip-like shape extending in the second direction Y along the body region 80. In other words, the insulating films 86 are arranged in a strip-like shape extending in the second direction Y. The extending direction of the insulating films 86 also coincides with the off-direction of the SiC single crystal.

[0558] The insulating films 86 each cover at least one channel region 83 (periphery of the body region 80). The insulating films 86 are located on at least one channel region 83, and each cover at least one peripheral portion of the body region 80, at least one source region 81, and one high-concentration region 70.

[0559] In this embodiment, the multiple insulating films 86 cross one high-concentration region 70 and extend across the peripheral portions of two adjacent body regions 80. Specifically, the multiple insulating films 86 extend across the peripheral portion of the source region 81 in one body region 80 and the peripheral portion of the source region 81 in the other body region 80, respectively covering the two source regions 81, one high-concentration region 70, and two channel regions 83. The multiple insulating films 86 expose the multiple source regions 81 and the multiple contact regions 82.

[0560] The plurality of planar electrodes 87 are respectively arranged in the form of a film on the plurality of insulating films 86. The plurality of planar electrodes 87 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0561] The multiple planar electrodes 87 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y along the body region 80. That is, the multiple planar electrodes 87 are arranged in stripes extending in the second direction Y. The extending direction of the multiple planar electrodes 87 coincides with the off-direction of the SiC single crystal. In this embodiment, the multiple planar electrodes 87 are formed at intervals inward from both ends of the corresponding insulating film 86 in the first direction X, exposing both ends of the corresponding insulating film 86.

[0562] The plurality of planar electrodes 87 each face at least one channel region 83 (periphery of the body region 80) with a corresponding insulating film 86 sandwiched therebetween. The plurality of planar electrodes 87 each cover at least one peripheral portion of the body region 80, at least one source region 81, and one high-concentration region 70 with a corresponding insulating film 86 sandwiched therebetween so as to face at least one channel region 83.

[0563] In this embodiment, the plurality of planar electrodes 87 cross one heavily doped region 70 and extend over the peripheral portions of two adjacent body regions 80. Specifically, the plurality of planar electrodes 87 extend over the peripheral portion of the source region 81 of one body region 80 and the peripheral portion of the source region 81 of the other body region 80, and face the two source regions 81, one heavily doped region 70, and two channel regions 83, respectively, with the corresponding insulating film 86 sandwiched therebetween.

[0564] Similar to the semiconductor device 1A, the semiconductor device 1C includes an interlayer film 43 covering the first main surface 3. The interlayer film 43 covers a plurality of gate structures 85 in the active region 8. The semiconductor device 1C includes a plurality of source openings 44 formed in the interlayer film 43 in the active region 8.

[0565] The source openings 44 are formed in regions between the planar electrodes 87 at intervals from each other, exposing the first main surface 3 (chip 2). Specifically, the source openings 44 penetrate the insulating film 86 and the interlayer film 43 in the regions between the planar electrodes 87, exposing the corresponding source regions 81 and contact regions 82.

[0566] In this embodiment, the source openings 44 are formed at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. That is, the source openings 44 are formed in stripes extending in the second direction Y. The source openings 44 have opening ends defined by arc corners of the interlayer film 43.

[0567] A plurality of source openings 44 may be formed in a region between two gate structures 85 adjacent to each other in the first direction X. In this case, the plurality of source openings 44 may be formed in a line at intervals in the second direction Y. Furthermore, in this case, each source opening 44 may be formed in a quadrilateral shape (square shape) in a plan view, a rectangular shape extending in the first direction X, a rectangular shape extending in the second direction Y, a hexagonal shape, a circular shape, or the like.

[0568] Similar to the semiconductor device 1A, the semiconductor device 1C includes a source electrode 45. Similar to the semiconductor device 1A, the source electrode 45 is disposed in the active region 8 and has a first pad portion 45a, a second pad portion 45b, and a third pad portion 45c. The source electrode 45 extends from above the interlayer film 43 into the plurality of source openings 44 and is electrically connected to the plurality of source regions 81 and the plurality of contact regions 82 within the plurality of source openings 44.

[0569] As in the case of the semiconductor device 1A, the source electrode 45 has a laminated structure including a lower electrode film 46 and a main electrode film 47, which are laminated in this order from the chip 2 side. In this embodiment, the lower electrode film 46 has a laminated structure including a first electrode film 48 and a second electrode film 49.

[0570] The first electrode film 48 collectively covers the region of the interlayer film 43 where the multiple source openings 44 are formed, and extends into the multiple source openings 44 from above the interlayer film 43. The first electrode film 48 has a portion that covers the insulating main surface of the interlayer film 43 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 44 in a film-like manner, and a portion that covers the first main surface 3 within the multiple source openings 44. The first electrode film 48 covers the first main surface 3 in the source openings 44 in a film-like manner, and is mechanically and electrically connected to the multiple source regions 81 and the multiple contact regions 82.

[0571] The second electrode film 49 directly covers the first electrode film 48. The second electrode film 49 collectively covers the region of the interlayer film 43 where the multiple source openings 44 are formed, sandwiching the first electrode film 48 therebetween, and extends from above the interlayer film 43 into the multiple source openings 44.

[0572] The second electrode film 49 has a portion that covers the interlayer film 43 in a film state with the first electrode film 48 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of source openings 44 in a film state with the first electrode film 48 sandwiched therebetween, and a portion that covers the first main surface 3 in a film state with the first electrode film 48 sandwiched therebetween within the plurality of source openings 44. The second electrode film 49 covers the first main surface 3 in a film state with the first electrode film 48 sandwiched therebetween within the source openings 44, and is electrically connected to the plurality of source regions 81 and the plurality of contact regions 82 via the first electrode film 48.

[0573] The main electrode film 47 directly covers the lower electrode film 46 (second electrode film 49). The main electrode film 47 backfills the source openings 44 and collectively covers the region of the interlayer film 43 where the source openings 44 are formed.

[0574] The main electrode film 47 has a portion that covers the interlayer film 43 with the lower electrode film 46 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of source openings 44 with the lower electrode film 46 sandwiched therebetween, and a portion that covers the first main surface 3 with the lower electrode film 46 sandwiched therebetween. The main electrode film 47 is electrically connected to the plurality of source regions 81 and the plurality of contact regions 82 via the lower electrode film 46 within the plurality of source openings 44.

[0575] Similar to the semiconductor device 1A, the semiconductor device 1C includes a gate electrode 51 disposed on the first main surface 3. Similar to the source electrode 45, the gate electrode 51 includes a lower electrode film 46 and a main electrode film 47 laminated in this order from the chip 2 side.

[0576] The gate finger electrode 52 extends from the gate electrode 51 onto a portion of the interlayer film 43 that covers the gate structure 85. The gate finger electrode 52 is routed in a strip shape over the gate structure 85. The gate finger electrode 52 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view. In this embodiment, the gate finger electrode 52 is formed in a strip shape with ends having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 45.

[0577] The gate finger electrode 52 penetrates into the plurality of gate openings 50 (not shown) from above the interlayer film 43, and is mechanically and electrically connected to the gate structures 85 within the plurality of gate openings 50. As a result, the gate potential applied to the gate electrode 51 is applied to the plurality of gate structures 85 via the gate structure 85.

[0578] Similar to the semiconductor device 1A, the semiconductor device 1C includes a drain electrode 53 covering the second main surface 4. The drain electrode 53 is electrically connected to the first semiconductor layer 6. The drain electrode 53 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain electrode 53 may also partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.

[0579] A breakdown voltage that can be applied between the source electrode 45 and the drain electrode 53 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, 2500 V or more and 2750 V or less, and 2750 V or more and 3000 V or less.

[0580] Fig. 38 is a plan view showing a semiconductor device 1D according to the fourth embodiment. Fig. 39 is a cross-sectional view taken along line XXXIX-XXXIX shown in Fig. 38. Fig. 40 is an enlarged cross-sectional view showing a main part of the active region 8 shown in Fig. 39.

[0581] The semiconductor device 1D has a configuration in which the configuration of the semiconductor device 1B (well region 60 and high-concentration region 70) is combined with a Schottky barrier diode structure Di, which is an example of a device structure. The semiconductor device 1D includes a chip 2, a first semiconductor layer 6, a second semiconductor layer 7, an active region 8, and a peripheral region 9, similar to the semiconductor device 1A.

[0582] The semiconductor device 1D includes a p-type guard region 90 formed in the outer periphery region 9 in a surface layer portion of the first main surface 3. The guard region 90 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7.

[0583] The guard region 90 is formed in a surface layer portion of the second semiconductor layer 7. The guard region 90 extends in a layered manner along the first main surface 3. The guard region 90 is formed at an interval from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) to the inward side of the first main surface 3 (toward the active region 8). The guard region 90 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 8) in a plan view.

[0584] In this embodiment, the guard region 90 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 8) of the first main surface 3. The guard region 90 has an inner edge portion that defines the active region 8 and an outer edge portion that defines the outer peripheral region 9. The guard region 90 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0585] The semiconductor device 1D includes a plurality of p-type well regions 60 formed in the surface layer portion of the first main surface 3 in the active region 8. The description of the well regions 60 in the semiconductor device 1B applies to the well regions 60. The semiconductor device 1D includes a plurality of p-type high-concentration regions 70 formed in the surface layer portion of the first main surface 3 in the active region 8. The description of the high-concentration regions 70 in the semiconductor device 1B applies to the high-concentration regions 70.

[0586] The semiconductor device 1D includes an insulating interlayer film 43 that selectively covers the first main surface 3 in the active region 8 and the peripheral region 9. The interlayer film 43 may have a single layer structure or a multilayer structure including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer film 43 has a single layer structure including a silicon oxide film.

[0587] The interlayer film 43 covers the guard region 90 in the outer periphery region 9. In this embodiment, the interlayer film 43 is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the interlayer film 43 may be formed at a distance inward from the periphery of the first main surface 3, exposing the second semiconductor layer 7 from the periphery of the first main surface 3.

[0588] The interlayer film 43 has an opening 91 that exposes the first main surface 3 in the active region 8. In this embodiment, the opening 91 has an opening wall surface positioned above the guard region 90, exposing the inner edge of the guard region 90.

[0589] The semiconductor device 1D includes an anode electrode 92 covering the first main surface 3 in the active region 8. The anode electrode 92 may also be referred to as a "first main surface electrode," a "first terminal (electrode)," a "first pad (electrode)," or the like. The anode electrode 92 is disposed inward from the periphery of the chip 2 with a space therebetween. The anode electrode 92 is formed in a polygonal shape (a quadrangular shape in this embodiment) that follows the periphery of the chip 2 in a plan view.

[0590] The anode electrode 92 extends into the opening 91 from above the interlayer film 43, and is electrically connected to the first main surface 3 and the guard region 90 within the opening 91. The anode electrode 92 forms a Schottky junction with the first main surface 3. This forms a Schottky barrier diode structure Di.

[0591] In this embodiment, both the well region 60 and the high concentration region 70 are formed at an interval from the first major surface 3 toward the bottom side of the second semiconductor layer 7. Therefore, the anode region forms a Schottky junction with the second semiconductor layer 7. When the well region 60 is exposed from the first major surface 3, the anode electrode 92 is mechanically and electrically connected to the well region 60. When the high concentration region 70 is exposed from the first major surface 3, the anode electrode 92 forms a Schottky junction with the high concentration region 70.

[0592] The semiconductor device 1D includes a cathode electrode 93 covering the second main surface 4. The cathode electrode 93 may also be referred to as a "second main surface electrode," a "second terminal (electrode)," a "second pad (electrode)," or the like. The cathode electrode 93 is electrically connected to the first semiconductor layer 6. The cathode electrode 93 forms ohmic contact with the first semiconductor layer 6.

[0593] The cathode electrode 93 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The cathode electrode 93 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0594] The breakdown voltage that can be applied between the anode electrode 92 and the cathode electrode 93 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0595] The above-described embodiments (including variations) can be implemented in other forms. For example, the first to fourth embodiments can be appropriately combined. Furthermore, semiconductor devices 1A to 1D may be employed that simultaneously include at least two of the first to fourth embodiments.

[0596] In the above-described embodiments, the chip 2 includes a SiC single crystal. However, the chip 2 may include a silicon single crystal. The first semiconductor layer 6 may include a silicon single crystal. The second semiconductor layer 7 may include a silicon single crystal.

[0597] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0598] In each of the above-described embodiments, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0599] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," "semiconductor rectifier device," etc., as necessary.

[0600] [A1] A semiconductor device (1A) including: a semiconductor layer (2, 7) of a first conductivity type (n-type) having a main surface (3); a body region (10) of a second conductivity type (p-type) formed in a surface layer portion of the main surface (3); a trench-type gate structure (15) formed in the main surface (3) so as to penetrate the body region (10); and a well region (25) of the second conductivity type (p-type) formed in a region below the gate structure (15) within the semiconductor layer (2, 7), the well region (25) having bulge regions (26, 26A, 26B, 28, 29) that bulge out horizontally along the main surface (3) relative to a sidewall of the gate structure (15).

[0601] [A2] The semiconductor device (1A) according to A1, wherein the semiconductor layer (2, 7) contains SiC.

[0602] [A3] The semiconductor device (1A) according to A1 or A2, wherein the bulging region (26, 26A, 26B, 28, 29) has an impurity concentration higher than the impurity concentration of the body region (10).

[0603] [A4] The semiconductor device (1A) according to any one of A1 to A3, wherein the bulging region (26, 26A, 26B, 28, 29) is connected to the bottom wall of the gate structure (15).

[0604] [A5] The semiconductor device (1A) according to any one of A1 to A4, wherein the bulging region (26, 26A, 26B, 28, 29) bulges out in an arc shape.

[0605] [A6] The semiconductor device (1A) described in any one of A1 to A5, wherein the well region (25) has a constricted region (27) that is recessed horizontally along the main surface (3) relative to the bulging region (26, 26A, 26B, 28, 29) below the bulging region (26, 26A, 26B, 28, 29).

[0606] [A7] The semiconductor device (1A) according to A6, wherein the constricted region (27) has a portion positioned inside the sidewall of the gate structure (15).

[0607] [A8] A semiconductor device (1A) according to any one of A1 to A7, wherein the bulging region (26, 26A, 26B, 28, 29) protrudes horizontally along the main surface (3) from both side walls of the gate structure (15).

[0608] [A9] The semiconductor device (1A) according to any one of A1 to A8, wherein the well region (25) includes a plurality of the bulging regions (26, 26A, 26B, 28, 29) formed at different depth positions.

[0609] [A10] The well region (25) includes a first well region (28) of a second conductivity type (p-type) formed below the gate structure (15), and a second well region (29) of the second conductivity type (p-type) formed below the first well region (28), and the bulge region (26, 26A, 26B, 28, 29) is formed by the first well region (28). A semiconductor device (1A) described in any one of A1 to A9.

[0610] [A11] The semiconductor device (1A) according to A10, wherein the second well region (29) has an impurity concentration lower than the impurity concentration of the first well region (28).

[0611] [A12] The semiconductor device (1A) according to A10 or A11, wherein the second well region (29) has a thickness greater than a thickness of the first well region (28).

[0612] [A13] The semiconductor device (1A) according to any one of A1 to A12, wherein the gate structure (15) includes a trench (16) formed in the main surface (3), an insulating film (17) covering the wall surface of the trench (16), and a buried electrode (18) buried in the trench (16) via the insulating film (17).

[0613] [A14] The semiconductor device (1A) according to A13, wherein the buried electrode (18) is buried at a distance from the height position of the main surface (3) toward the bottom wall of the trench (16).

[0614] [A15] The semiconductor device (1A) described in A14, wherein the gate structure (15) includes a buried insulator (19) buried in the trench (16) at a distance from a height position of the main surface (3) toward the bottom wall of the trench (16) so as to cover the buried electrode (18).

[0615] [A16] A semiconductor device (1A) according to any one of A1 to A15, further comprising a second conductivity type (p-type) contact region (37) extending along a sidewall of the gate structure (15) and electrically connecting the bulge region (26, 26A, 26B, 28, 29) to the body region (10).

[0616] [A17] The semiconductor device (1A) according to A16, wherein the contact region (37) has an impurity concentration higher than an impurity concentration of the body region (10).

[0617] [A18] The semiconductor device (1A) according to any one of A1 to A17, further comprising a first conductivity type (n-type) source region (35) formed in a surface layer portion of the body region (10).

[0618] [A19] A semiconductor device (1A) according to any one of A1 to A18, further comprising a first conductivity type (n-type) high concentration region (30) formed in the semiconductor layer (2, 7) within the thickness range of the bottom of the body region (10) and the bottom wall of the gate structure (15), and having an impurity concentration higher than the impurity concentration of the semiconductor layer (2, 7).

[0619] [A20] The semiconductor device (1A) according to any one of A1 to A19, further including a main surface electrode (45) electrically connected to the body region (10) on the main surface (3) and electrically isolated from the gate structure (15).

[0620] [B1] A semiconductor device (1A) including: a semiconductor layer (2, 7) of a first conductivity type (n-type) having a main surface (3); a body region (10) of a second conductivity type (p-type) formed in a surface layer portion of the main surface (3); a trench-type gate structure (15) formed in the main surface (3) so as to penetrate the body region (10); and a high-concentration body region (36) formed at the bottom of the body region (10) and having an impurity concentration higher than the impurity concentration of the body region (10).

[0621] [B2] The semiconductor device (1A) according to B1, wherein the semiconductor layer (2, 7) contains SiC.

[0622] [B3] The semiconductor device (1A) according to B1 or B2, wherein the high-concentration body region (36) is partially formed in the bottom of the body region (10).

[0623] [B4] The semiconductor device (1A) according to B3, wherein the body high concentration region (36) is formed at a distance from the gate structure (15) and faces the gate structure (15) across a portion of the body region (10).

[0624] [B5] The semiconductor device (1A) according to any one of B1 to B4, wherein the high-concentration body region (36) extends along the extension direction of the gate structure (15).

[0625] [B6] The semiconductor device (1A) according to any one of B1 to B5, wherein a plurality of the high-concentration body regions (36) are formed at intervals along the gate structure (15).

[0626] [B7] The semiconductor device (1A) according to any one of B1 to B6, wherein the gate structure (15) includes a trench (16) formed in the main surface (3), an insulating film (17) covering the wall surface of the trench (16), and a buried electrode (18) buried in the trench (16) via the insulating film (17).

[0627] [B8] The semiconductor device (1A) according to B7, wherein the buried electrode (18) is buried at a distance from the height position of the main surface (3) toward the bottom wall of the trench (16).

[0628] [B9] The semiconductor device (1A) described in B8, wherein the gate structure (15) includes a buried insulator (19) buried in the trench (16) at a distance from a height position of the main surface (3) toward the bottom wall of the trench (16) so as to cover the buried electrode (18).

[0629] [B10] A semiconductor device (1A) according to any one of B1 to B9, further comprising a first conductivity type (n-type) source region (35) formed in a surface layer portion of the body region (10), and the body high concentration region (36) is formed in a thickness range between the bottom of the body region (10) and the bottom of the source region (35).

[0630] [B11] The semiconductor device (1A) according to any one of B1 to B10, further comprising a second conductivity type (p-type) contact region (37) formed along the gate structure (15) in a surface layer portion of the body region (10) and having an impurity concentration higher than the impurity concentration of the body region (10).

[0631] [B12] The semiconductor device (1A) according to B11, wherein the contact region (37) is electrically connected to the high-concentration body region (36) in the body region (10).

[0632] [B13] The semiconductor device (1A) according to B11 or B12, wherein the contact region (37) has a portion connected to the high-concentration body region (36) within the body region (10).

[0633] [B14] A semiconductor device (1A) according to any one of B1 to B10, further comprising a second conductivity type (p-type) well region (25) formed in the semiconductor layer (2, 7) in a region below the gate structure (15) and spaced apart from the bottom of the body high concentration region (36).

[0634] [B15] The semiconductor device (1A) according to B14, wherein the well region (25) is formed at a distance from the bottom of the body region (10).

[0635] [B16] The semiconductor device (1A) described in B14 or B15, wherein the well region (25) includes a first well region (28) of a second conductivity type (p-type) formed below the gate structure (15), and a second well region (29) of the second conductivity type (p-type) formed below the first well region (28) and having an impurity concentration lower than the impurity concentration of the first well region (28).

[0636] [B17] The semiconductor device (1A) according to B16, wherein the second well region (29) has a thickness greater than a thickness of the first well region (28).

[0637] [B18] A semiconductor device (1A) according to any one of B14 to B17, further comprising a second conductivity type (p-type) contact region (37) extending along a sidewall of the gate structure (15) and electrically connecting the well region (25) to the body region (10).

[0638] [B19] A semiconductor device (1A) according to any one of B1 to B18, further comprising a first conductivity type (n-type) high concentration region (30) formed in the semiconductor layer (2, 7) within the thickness range of the bottom of the body region (10) and the bottom wall of the gate structure (15), and having an impurity concentration higher than the impurity concentration of the semiconductor layer (2, 7).

[0639] [B20] The semiconductor device (1A) according to any one of B1 to B19, further comprising a main surface electrode (45) electrically connected to the body region (10) on the main surface (3) and electrically isolated from the gate structure (15).

[0640] [C1] A semiconductor device (1A) including a first conductivity type (n-type) semiconductor layer (2, 7) including a SiC single crystal and having a main surface (3), a trench-type gate structure (15) formed in the main surface (3), and a second conductivity type (p-type) well region (25, 29) formed in the semiconductor layer (2, 7) in a region below the gate structure (15) and extending along an axial channel of the SiC single crystal.

[0641] [C2] A semiconductor device (1A) according to C1, wherein the well region (25, 29) has an impurity concentration higher than the impurity concentration of the semiconductor layer (2, 7), and the conductivity type of the semiconductor layer (2, 7) is changed from a first conductivity type (n-type) to a second conductivity type (p-type).

[0642] [C3] The semiconductor device (1A) according to C1 or C2, wherein the well region (25, 29) has a concentration gradient that monotonically decreases in the depth direction.

[0643] [C4] A semiconductor device (1A) according to any one of C1 to C3, wherein the well region (25, 29) has a depth of 0.5 μm or more and 5 μm or less when the bottom wall of the gate structure (15) is used as the reference.

[0644] [C5] A semiconductor device (1A) according to any one of C1 to C4, wherein the well region (25, 29) has a depth, when the bottom wall of the gate structure (15) is used as a reference, that is smaller than the depth of the gate structure (15) when the main surface (3) is used as a reference.

[0645] [C6] The semiconductor device (1A) according to any one of C1 to C5, wherein the well region (25, 29) is formed in a shape tapering toward the bottom in a cross-sectional view.

[0646] [C7] A semiconductor device (1A) according to any one of C1 to C6, further comprising a first conductivity type (n-type) high concentration region (30) formed in the semiconductor layer (2, 7) in a region to the side of the well region (25, 29) and having an impurity concentration higher than the impurity concentration of the semiconductor layer (2, 7).

[0647] [C8] The semiconductor device (1A) according to C7, wherein the high concentration region (30) extends along the axial channel of the SiC single crystal.

[0648] [C9] The semiconductor device (1A) according to C7 or C8, wherein the high concentration region (30) has a bottom located closer to the main surface (3) than the bottom of the well region (25, 29).

[0649] [C10] The semiconductor device (1A) according to any one of C7 to C9, wherein the high concentration region (30) has a concentration gradient that decreases in the thickness direction.

[0650] [C11] A semiconductor device (1A) according to any one of C7 to C10, wherein the high concentration region (30) has a first region (31) positioned above the depth position of the bottom wall of the gate structure (15), and a second region (32) positioned below the depth position of the bottom wall of the gate structure (15).

[0651] [C12] The semiconductor device (1A) according to C11, wherein the second region (32) has a concentration gradient that monotonically decreases in the thickness direction.

[0652] [C13] The semiconductor device (1A) according to C11 or C12, wherein the second region (32) has a depth of 0.5 μm or more and 5 μm or less, based on the depth position of the bottom wall of the gate structure (15).

[0653] [C14] A semiconductor device (1A) according to any one of C1 to C13, further comprising a second conductivity type (p-type) high concentration well region (25, 28) formed below the gate structure (15) in the semiconductor layer (2, 7), the well region (25, 29) having an impurity concentration lower than the impurity concentration of the well high concentration region (25, 28) and formed below the well high concentration region (25, 28).

[0654] [C15] The semiconductor device (1A) according to C14, wherein the well region (25, 29) has a thickness greater than a thickness of the high concentration well region (25, 28).

[0655] [C16] The semiconductor device (1A) according to C14 or C15, wherein the well high concentration region (25, 28) has a concentration gradient that increases and decreases downward from the bottom wall side of the gate structure (15).

[0656] [C17] A semiconductor device (1A) according to any one of C1 to C16, further comprising a body region (10) of a second conductivity type (p-type) formed in a surface layer portion of the main surface (3), and the gate structure (15) penetrates the body region (10).

[0657] [C18] A semiconductor device (1A) according to C17, further comprising a second conductivity type (p-type) contact region (37) extending along a sidewall of the gate structure (15) and electrically connecting the well region (25, 29) to the body region (10).

[0658] [C19] The semiconductor device (1A) according to C17 or C18, further comprising a first conductivity type (n-type) source region (35) formed in a surface layer portion of the body region (10).

[0659] [C20] The semiconductor device (1A) according to any one of C1 to C19, further comprising a main surface electrode (45) arranged on the main surface (3).

[0660] [D1] A semiconductor device (1A-1D) including: an n-type semiconductor layer (2, 7); a p-type well region (25, 29, 60) formed in the semiconductor layer (2, 7) to have a higher concentration than the semiconductor layer (2, 7); and an n-type high concentration region (30, 32, 70) formed in the semiconductor layer (2, 7) to have a higher concentration than the semiconductor layer (2, 7) and forming a p-n junction with the well region (25, 29, 60).

[0661] [D2] The semiconductor device (1A to 1D) according to D1, wherein the semiconductor layer (2, 7) contains SiC.

[0662] [D3] The well region (25, 29, 60) has an impurity concentration that is decoupled from the impurity concentration of the high concentration region (30, 32, 70), and the high concentration region (30, 32, 70) has an impurity concentration that is decoupled from the impurity concentration of the well region (25, 29, 60). A semiconductor device (1A-1D) described in D1 or D2.

[0663] [D4] A semiconductor device (1A to 1D) described in any one of D1 to D3, wherein the semiconductor layer (2, 7) has a concentration adjusted by a first element consisting of a pentavalent element, the well region (25, 29, 60) has a concentration adjusted by a second element consisting of a trivalent element in addition to the first element, and the high concentration region (30, 32, 70) has a concentration adjusted by a third element consisting of a pentavalent element in addition to the first element.

[0664] [D5] The semiconductor device (1A to 1D) according to D4, wherein the concentration of the third element in the well region (25, 29, 60) is less than the concentration of the third element in the high concentration region (30, 32, 70).

[0665] [D6] The semiconductor device (1A to 1D) according to D4 or D5, wherein the inner part of the well region (25, 29, 60) does not contain the third element.

[0666] [D7] A semiconductor device (1A to 1D) described in any one of D4 to D6, wherein the concentration of the second element in the high concentration region (30, 32, 70) is less than the concentration of the second element in the well region (25, 29, 60).

[0667] [D8] The semiconductor device (1A to 1D) according to any one of D4 to D7, wherein the inner part of the high concentration region (30, 32, 70) does not contain the second element.

[0668] [D9] A semiconductor device (1A to 1D) according to any one of D4 to D8, wherein the first element includes at least one of nitrogen, phosphorus, and arsenic, the second element includes at least one of boron and aluminum, and the third element includes at least one of nitrogen, phosphorus, and arsenic.

[0669] [D10] The semiconductor device (1A to 1D) according to any one of D4 to D9, wherein the semiconductor layer (2, 7) has a concentration adjusted by the first element.

[0670] [D11] The semiconductor device (1A to 1D) according to any one of D4 to D10, wherein the third element is different from the first element.

[0671] [D12] A semiconductor device (1A to 1D) described in any one of D1 to D11, wherein the high concentration region (30, 32, 70) has a bottom positioned above the depth position of the bottom of the well region (25, 29, 60).

[0672] [D13] The semiconductor device (1A to 1D) according to any one of D1 to D12, wherein the high concentration region (30, 32, 70) forms a super junction structure with the well region (25, 29, 60).

[0673] [D14] A semiconductor device (1A to 1D) according to any one of D1 to D13, further comprising a trench-type gate structure (15) formed in the semiconductor layer (2, 7), the well region (25, 29, 60) being formed below the gate structure (15), and the high concentration region (30, 32, 70) being formed below the depth position of the bottom wall of the gate structure (15).

[0674] [D15] The semiconductor device (1A to 1D) described in D14 further includes a p-type high concentration well region (28) formed below the gate structure (15), and the well region (25, 29, 60) is formed to have a lower concentration than the high concentration well region (28) in the region below the high concentration well region (28).

[0675] [D16] The semiconductor device (1A to 1D) described in D14 or D15 further includes an n-type upper high concentration region (31) formed above the depth position of the bottom wall of the gate structure (15), and the high concentration region (30, 32, 70) is formed to have a lower concentration than the upper high concentration regio...

Claims

1. An n-type semiconductor layer, a p-type well region formed in the semiconductor layer at a higher concentration than the semiconductor layer, and an n-type high-concentration region formed in the semiconductor layer at a higher concentration than the semiconductor layer and forming a pn junction with the well region, a semiconductor device comprising the same.

2. The semiconductor device according to claim 1, wherein the semiconductor layer contains SiC.

3. The well region has an impurity concentration separated from the impurity concentration of the high-concentration region, and the high-concentration region has an impurity concentration separated from the impurity concentration of the well region. The semiconductor device according to claim 1 or 2.

4. The semiconductor layer is concentration-adjusted by a first element composed of a pentavalent element, the well region is concentration-adjusted by a second element composed of a trivalent element in addition to the first element, and the high-concentration region is concentration-adjusted by a third element composed of a pentavalent element in addition to the first element. The semiconductor device according to any one of claims 1 to 3.

5. The semiconductor device according to claim 4, wherein the concentration of the third element in the well region is less than the concentration of the third element in the high-concentration region.

6. The semiconductor device according to claim 4 or 5, wherein the inner part of the well region does not contain the third element.

7. The semiconductor device according to any one of claims 4 to 6, wherein the concentration of the second element in the high-concentration region is less than the concentration of the second element in the well region.

8. The semiconductor device according to any one of claims 4 to 7, wherein the inner part of the high-concentration region does not contain the second element.

9. The first element contains at least one of nitrogen, phosphorus, and arsenic, the second element contains at least one of boron and aluminum, and the third element contains at least one of nitrogen, phosphorus, and arsenic. The semiconductor device according to any one of claims 4 to 8.

10. The semiconductor device according to any one of claims 4 to 9, wherein the semiconductor layer is concentration-adjusted by a single first element.

11. The semiconductor device according to any one of claims 4 to 10, wherein the third element is different from the first element.

12. The semiconductor device according to any one of claims 1 to 11, wherein the high-concentration region has a bottom located above the depth position of the bottom of the well region.

13. The semiconductor device according to any one of claims 1 to 12, wherein the high-concentration region forms a superjunction structure with the well region.

14. The semiconductor device according to any one of claims 1 to 13, further comprising a trench-type gate structure formed in the semiconductor layer, wherein the well region is formed below the gate structure, and the high-concentration region is formed below the depth position of the bottom wall of the gate structure.

15. The semiconductor device according to claim 14, further comprising a p-type well high-concentration region formed below the bottom wall of the gate structure, wherein the well region is formed with a lower concentration than the well high-concentration region in a region below the well high-concentration region.

16. The semiconductor device according to claim 14 or 15, further comprising an n-type upper high-concentration region formed above the depth position of the bottom wall of the gate structure, wherein the high-concentration region is formed with a lower concentration than the upper high-concentration region in a region below the upper high-concentration region.

17. The semiconductor device according to any one of claims 14 to 16, further comprising a p-type body region formed in the semiconductor layer, wherein the gate structure penetrates the body region.

18. The semiconductor device according to claim 17, further comprising a p-type contact region extending along the side wall of the gate structure.

19. The semiconductor device according to claim 17 or 18, further comprising an n-type source region formed in the surface layer portion of the body region.

20. The semiconductor device according to any one of claims 1 to 19, further comprising a main surface electrode disposed on the semiconductor layer.

Images