Circuit board and semiconductor package

Abstract

This circuit board comprises: a first insulating layer including a cavity; and a second insulating layer disposed on the first insulating layer, wherein the first insulating layer includes a resin and glass fibers dispersed in the resin, and at least a portion of the second insulating layer passes through the glass fibers.

Description

Circuit boards and semiconductor packages

[0001] This embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, electronic product technology has been moving toward multifunctionality and high-speed operation, and to respond to this trend, semiconductor chip manufacturing technology is also developing at a rapid pace.

[0004] In particular, the thickness of circuit boards applied for miniaturization of finished electronic products is also decreasing, and technologies related to multilayer circuit boards that configure more circuit layers within a circuit board of the same thickness are being actively researched.

[0005] Typically, a multilayer circuit board can be formed by laminating a plurality of prepregs (insulators) formed by impregnating glass fibers with epoxy resin, and circuit boards including copper (Cu) circuits formed on the surface thereof.

[0006] According to the structure described above, there is a risk of warpage occurring due to the asymmetrical structure of both surfaces of the circuit board and the difference in physical properties, such as the coefficient of thermal expansion, between the different materials constituting the circuit board.

[0007]

[0008] The present embodiment provides a circuit board and semiconductor package capable of minimizing warpage by forming a processing area within an insulating layer forming a circuit board.

[0009]

[0010] A circuit board according to the present embodiment comprises: a first insulating layer including a cavity; and a second insulating layer disposed on the first insulating layer, wherein the first insulating layer includes a resin and glass fibers dispersed within the resin, and at least a portion of the second insulating layer is disposed to penetrate the glass fibers.

[0011] The second insulating layer may include a body portion disposed on the first insulating layer, and a protrusion portion protruding downward from the lower surface of the body portion and coupled to the cavity.

[0012] The second insulating layer includes a resin and a filler dispersed within the resin, and at least a portion of the filler can overlap horizontally with the glass fiber of the first insulating layer.

[0013] It includes a first circuit pattern arranged on the lower surface of the first insulating layer, and the upper surface of the first circuit pattern may include a first upper surface facing the first insulating layer and a second upper surface facing the cavity.

[0014] A groove having a more concave shape than other areas may be arranged on the second upper surface.

[0015] At least a portion of the second insulating layer may be bonded to the groove.

[0016] A second circuit pattern may be included between the first insulating layer and the second insulating layer, and the second circuit pattern may include a separation portion facing the cavity in the vertical direction.

[0017] At least a portion of the second insulating layer may be disposed in the separation portion.

[0018] The above cavities may be provided in multiple numbers and arranged to be spaced apart from each other within the first insulating layer.

[0019] A semiconductor package according to the present embodiment comprises: a first insulating layer including a cavity; a third insulating layer disposed on the first insulating layer; and an electronic component disposed on the third insulating layer, wherein the first insulating layer includes a resin and glass fibers dispersed within the resin, and at least a portion of the second insulating layer is disposed to penetrate the glass fibers.

[0020]

[0021] In this embodiment, the glass fibers in the first insulating layer can have elasticity against bending by having a region separated by a cavity in the first insulating layer.

[0022] In addition, since the support force is improved by the bonding structure with the third insulating layer through the cavity, warping or sagging can be prevented.

[0023]

[0024] Figure 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0025] Figure 2 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0026] Figures 3 to 6 are drawings illustrating a manufacturing process of a circuit board according to an embodiment of the present invention.

[0027] Figure 7 is a plan view of the upper surface of a circuit board according to an embodiment of the present invention.

[0028] Figure 8 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0029]

[0030] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0031] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0032] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0033] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as "A and / or at least one (or more) of B, C," it may include one or more of all combinations that can be combined with A, B, and C.

[0034] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0035] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0036] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0037] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0038] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIGS. 3 to 6 are drawings illustrating a manufacturing process of a circuit board according to an embodiment of the present invention, and FIG. 7 is a plan view of the upper surface of a circuit board according to an embodiment of the present invention.

[0039] Referring to FIGS. 1 to 7, a circuit board (10) according to an embodiment of the present invention may include a first insulating layer (110), a third insulating layer (120), a second insulating layer (150), a first circuit pattern (130), and a second circuit pattern (140).

[0040] Based on the first insulating layer (110), the third insulating layer (120) may be disposed on one surface of the first insulating layer (110), and the second insulating layer (150) may be disposed on the other surface of the first insulating layer (110). The third insulating layer (120) may be disposed on the lower surface of the first insulating layer (110), and the second insulating layer (150) may be disposed on the upper surface of the first insulating layer (110).

[0041] The first insulating layer (110) may be a single layer or multiple layers. The first insulating layer (110) is a substrate on which an electric circuit capable of changing wiring is formed, and may include a print, wiring board, and insulating substrate made of an insulating material capable of forming circuit patterns on a surface.

[0042] The first insulating layer (110) may include any insulator such as a photocurable and / or thermocurable insulator. The first insulating layer (110) may include a prepreg (PPG) including glass fibers (115) in a resin. The resin of the first insulating layer (110) may include at least one of an epoxy resin, a bismaleimide triazine resin (BT resin), and a phenol resin. When the resin of the first insulating layer (110) is used as an insulating layer resin, it may include a reinforcing material such as glass fibers or aramid fibers.

[0043] The first insulating layer (110) may include a cavity (170). The cavity (170) may be in the shape of a through hole penetrating from the upper surface to the lower surface of the first insulating layer (110). A portion of the upper surface of the first circuit pattern (130) disposed on the lower surface of the first insulating layer (110) may form the bottom surface of the cavity (170).

[0044] The above cavity (170) can be formed by a laser processing method. The laser processing can be a UV or CO2 laser method.

[0045] The bending prevention structure of the circuit board (10) through the cavity (170) will be described later.

[0046] The third insulating layer (120) may be arranged below the first insulating layer (110). The third insulating layer (120) may be a single layer or multiple layers. The third insulating layer (120) may be a substrate on which an electric circuit capable of changing wiring is formed, and may include a print, wiring board, and insulating substrate made of an insulating material capable of forming circuit patterns on a surface.

[0047] The third insulating layer (120) is formed of any insulator, such as a photocurable and / or thermosetting insulator. As a thermosetting insulator, an insulator in which inorganic and / or organic fillers are dispersed in a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a prepreg (PPG) including glass fibers in a resin can be used. In addition, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and the inorganic and / or organic filler may be formed of a material such as silica or plastic. When an insulating resin is used as a core, a reinforcing material formed of glass fibers or aramid fibers can be included.

[0048] The first circuit pattern (130) may be arranged on one surface of the first insulating layer (110). The first circuit pattern (130) may be arranged on the lower surface of the first insulating layer (110). The first circuit pattern (130) may be arranged on the upper surface of the third insulating layer (120). The material of the first circuit pattern (130) may be copper (Cu). A via (not shown) penetrating from the upper surface to the lower surface of the first insulating layer (110) may be formed in the first insulating layer (110), and the first circuit pattern (130) may be electrically connected to the second circuit pattern (140) through the via.

[0049] Before the formation of the second insulating layer (150) described later, a portion of the upper surface of the first circuit pattern (130) may be exposed upward through the cavity (170).

[0050] A portion of the upper surface of the first circuit pattern (130) may form a bottom surface of the cavity (170). In detail, the upper surface of the first circuit pattern (130) may include a first upper surface facing the first insulating layer (110) and a second upper surface facing the cavity (170). The second upper surface may form a bottom surface of the cavity (170). The roughness of the second upper surface may be different from the roughness of the first upper surface. The surface roughness of the second upper surface may be greater than the surface roughness of the first upper surface. A groove (132) having a concave shape downward compared to other regions may be formed on the second upper surface. The grooves (132) may be provided in plurality and may be arranged in a horizontal direction on the second upper surface. The above home (132) can be formed during the process of forming the cavity (170) in the first insulating layer (110).

[0051] The second circuit pattern (140) may be arranged on the other surface of the first insulating layer (110). The second circuit pattern (140) may be arranged on the upper surface of the first insulating layer (110). The material of the second circuit pattern (140) may be copper (Cu). The second circuit pattern (140) may be electrically connected to the first circuit pattern (130) through a via of the first insulating layer (110).

[0052] The second circuit pattern (140) may include a separation portion (147). The second circuit pattern (140) may be divided into two or more regions by the separation portion (147). The separation portion (147) may be arranged in a region that overlaps the cavity (170) in a vertical direction. The cross-sectional shape of the separation portion (147) may be formed to correspond to the cross-sectional shape of the cavity (170).

[0053] The second insulating layer (150) may be disposed on top of the first insulating layer (110). At least a portion of the second insulating layer (150) may be disposed on the second circuit pattern (140).

[0054] The second insulating layer (150) may be formed of any insulator, such as a curable and / or thermosetting insulator. As a thermosetting insulator, an insulator in which inorganic and / or organic fillers are dispersed in a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, may be used, and a prepreg (PPG) including glass fibers in a resin may be used. When the second insulating layer (150) is ABF, the filler in the second insulating layer (150) may be a different material from the filler in the first insulating layer (110). In addition, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and the inorganic and / or organic filler may be formed of a material such as silica or plastic. When an insulating resin is used as a core, a reinforcing material such as glass fiber or aramid fiber may be included. In contrast, the second insulating layer (150) may be a solder resist layer.

[0055] The second insulating layer (150) may include a plate-shaped body portion (152) disposed on the second circuit pattern (140), and a protrusion (154) that protrudes downward from the lower surface of the body portion (152) more than other areas. The protrusion (154) may be coupled within the cavity (170). The protrusion (154) may be disposed to penetrate the spaced portion (147) of the second circuit pattern (140) and the cavity (170). The lower surface of the protrusion (154) may be disposed to face the second upper surface of the first circuit pattern (130). The lower surface of the protrusion (154) may be in contact with the second upper surface of the first circuit pattern (130). The above protrusion (154) can be positioned to fill the groove (132) formed on the second upper surface of the first circuit pattern (130).

[0056] The above protrusion (154) can be formed by introducing pre-cured resin for forming the second insulating layer (150) into the separation portion (147) and the cavity (170) during the process of forming the second insulating layer (150) on the first insulating layer (110).

[0057] Regarding the bending prevention structure of the circuit board (10) according to the present embodiment, due to the rigid material properties of the glass fiber (115) in the first insulating layer (110), there is a risk of bending between the third insulating layer (120) and the third insulating layer (130). However, according to the present embodiment, since the glass fiber (115) in the first insulating layer (110) has a region that is separated from each other in the horizontal direction by the cavity (170) in the first insulating layer (110), it can have elasticity against bending. In addition, since the supporting force is improved by the bonding structure with the protrusion (154) in the second insulating layer (150) through the cavity (170), bending or sagging can be prevented. Here, the meaning that the glass fibers (115) are separated from each other does not mean that a plurality of split glass fibers are arranged in the entire area of ​​the first insulating layer (110), but may mean that a part of the glass fibers (115) is broken by the cavity (170) in the area where the cavity (170) is formed. This may mean that, as illustrated in FIG. 1, when the glass fibers (115) arranged in the left area with respect to the cavity (170) in the first insulating layer (110) are called first glass fibers, and the glass fibers (115) arranged in the right area are called second glass fibers, the right end of the first glass fiber and the left end of the second glass fiber are spaced apart in the horizontal direction. The glass fibers (115) in the first insulating layer (110) may have an area that is separated in the horizontal direction by the cavity (170). The filler in the second insulating layer (150) and the filler in the first insulating layer (110) can be arranged to overlap in the horizontal direction by the protrusion (154) of the second insulating layer (150) coupled to the cavity (170). As described above, the materials of the filler in the second insulating layer (150) and the filler in the first insulating layer (110) can be different from each other.However, this is an example, and the material of the filler in the second insulating layer (150) and the filler in the first insulating layer (110) may be the same.

[0058] Specifically, the second insulating layer (150) may be ABF (Ajinomoto Build-up Film) or prepreg (PPG).

[0059] When the second insulating layer (150) is ABF (Ajinomoto Build-up Film), the filler in the second insulating layer (150) can be arranged to overlap horizontally with the filler in the first insulating layer (110) in the formation area of ​​the cavity (170).

[0060] When the second insulating layer (150) is a prepreg (PPG), the second insulating layer (150) may also include glass fibers. In this case, the glass fibers in the second insulating layer (150) may be arranged in the protrusion (154) to overlap horizontally with the glass fibers or fillers in the first insulating layer (110). Meanwhile, when the second insulating layer (150) is a prepreg (PPG), the glass fibers in the second insulating layer (150) may be arranged only in the body portion (152) and not in the protrusion (154). In this case, the glass fibers in the second insulating layer (150) may not be arranged to overlap horizontally with the glass fibers in the first insulating layer (110).

[0061] As illustrated in FIG. 7, the cavity (170) may be formed in an edge region within the circuit board (10). The cavity (170) may be formed in a corner region within the first insulating layer (110) forming the circuit board (10). When the first insulating layer (110) has a rectangular cross-sectional shape, the cavity (170) may be formed in each of the four corner regions. The cavity (170) may be provided in multiple numbers and arranged in multiple rows in the edge region of the first insulating layer (110). For example, based on one corner region of the first insulating layer (110), the cavities (170) may be arranged in two rows.

[0062] Alternatively, the cavities (170) may be provided in multiple numbers and arranged to have a closed-loop shape along the edge area of ​​the first insulating layer (110). In this case, the plurality of cavities (170) may be interconnected along the edge of the first insulating layer (110). The plurality of cavities (170) being interconnected may mean that adjacent cavities (170) are formed to overlap each other. When the plurality of cavities (170) are arranged to form a closed-loop shape, assuming that the second insulating layer (150) is a prepreg (PPG), the glass fiber of the second insulating layer (150) arranged inside the cavity (170) and the glass fiber of the second insulating layer (150) arranged outside the cavity (170) may not be connected.

[0063] Referring to FIGS. 3 to 6, the manufacturing process of the circuit board (10) will be described. First, as shown in FIG. 3, the second circuit pattern (140) is formed on the first insulating layer (110). At this time, the formation area of ​​the cavity (170) of the circuit pattern (140) can be primarily set by the separation portion (147).

[0064] Next, as illustrated in FIGS. 4 and 5, a cavity (170) may be formed in the first insulating layer (110) through laser processing. In this case, a portion of the upper surface of the first circuit pattern (130) may be exposed upward through the cavity (170) and the separation portion (147). During the process of forming the cavity (170), a groove (132) may be formed on the upper surface of the first circuit pattern (130).

[0065] Next, as shown in FIG. 6, a resin for forming the second insulating layer (150) is applied on the first insulating layer (110) and the second circuit pattern (140) in which the cavity (170) is formed, and accordingly, a body portion (152) and a protrusion portion (154) of the second insulating layer (150) can be formed by curing through a process in which some of the resin fills the cavity (170).

[0066] Figure 8 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0067] Referring to FIG. 8, a semiconductor package according to an embodiment of the present invention may include a circuit board (10) and an electronic component (200) mounted on the circuit board (10). A protective layer (not shown) may be formed on the circuit board (10), and a pad (210) for electrical connection of the electronic component (200) may be disposed on the protective layer. The pad (210) may be disposed on the second insulating layer (150).

[0068] The above electronic component (200) may include an active component or a passive component, and thus may include a transistor, an IC semiconductor chip, a capacitor, a resistor, an inductor, and the like.

[0069] Although all components constituting the embodiments of the present invention have been described above as being combined or operating in combination, the present invention is not necessarily limited to these embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined and operated one or more times. In addition, terms such as "include," "comprise," or "have" described above, unless specifically stated to the contrary, mean that the corresponding component may be inherent, and therefore should be interpreted as including other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in a dictionary, should be interpreted as being consistent with the contextual meaning of the related technology, and shall not be interpreted in an ideal or excessively formal sense, unless explicitly defined in the present invention.

[0070] The above description is merely an illustrative description of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

[0071] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0072] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. A first insulating layer including a cavity; and Including a second insulating layer disposed on the first insulating layer, The above first insulating layer comprises a resin and glass fibers dispersed within the resin, A circuit board wherein at least a portion of the second insulating layer is arranged to penetrate the glass fiber.

2. In paragraph 1, A circuit board including a body portion arranged on the first insulating layer and a protrusion portion protruding downward from a lower surface of the body portion and coupled to the cavity, wherein the second insulating layer is formed on the first insulating layer.

3. In paragraph 2, The second insulating layer comprises a resin and a filler dispersed within the resin, A circuit board wherein at least a portion of the filler horizontally overlaps the glass fiber of the first insulating layer.

4. In paragraph 1, Including a first circuit pattern arranged on the lower surface of the first insulating layer, A circuit board having a first upper surface of the first circuit pattern including a first upper surface facing the first insulating layer and a second upper surface facing the cavity.

5. In paragraph 4, A circuit board having a groove having a more concave shape than other areas on the second upper surface.

6. In paragraph 5, A circuit board wherein at least a portion of the second insulating layer is bonded to the groove.

7. In paragraph 1, Including a second circuit pattern arranged between the first insulating layer and the second insulating layer, The above second circuit pattern is a circuit board including a gap portion facing the cavity in the vertical direction.

8. In paragraph 7, A circuit board wherein at least a portion of the second insulating layer is disposed on the separation portion.

9. In paragraph 1, A circuit board having a plurality of the above cavities and arranged spaced apart from each other within the first insulating layer.

10. A first insulating layer including a cavity; A third insulating layer disposed on the first insulating layer; and Including an electronic component arranged on the third insulating layer, The above first insulating layer comprises a resin and glass fibers dispersed within the resin, A semiconductor package wherein at least a portion of the second insulating layer is arranged to penetrate the glass fiber.

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