Circuit board and semiconductor package

Abstract

This circuit board includes: a first insulation layer; a first resin layer arranged on the top surface of the first insulating layer; a second insulating layer arranged on the top surface of the first resin layer; a cavity passing through the second insulating layer; a first circuit pattern arranged on the bottom surface of the first insulating layer; a second circuit pattern arranged on the bottom surface of the cavity which is the top surface of the first resin layer; and a via hole passing through the first resin layer and the first insulating layer and connecting the first circuit pattern with the second circuit pattern.

Description

Circuit boards and semiconductor packages

[0001] This embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, electronic product technology has been moving toward multifunctionality and high-speed operation, and to respond to this trend, semiconductor chip manufacturing technology is also developing at a rapid pace.

[0004] In particular, the thickness of circuit boards applied for miniaturization of finished electronic products is also decreasing, and technologies related to multilayer circuit boards that configure more circuit layers within a circuit board of the same thickness are being actively researched.

[0005] A circuit board is a substrate made by printing a circuit line pattern with a conductive material, such as copper, onto an electrically insulating substrate. It generally refers to a board immediately before electronic components are mounted. To densely mount numerous electronic components on a flat surface, the mounting locations of each component are determined, and the circuit patterns connecting the components are printed and secured onto the flat surface.

[0006] These circuit boards are generally single-layer PCBs and build-up boards, or multilayer PCB boards, which are formed by forming PCBs in multiple layers. Build-up boards, or multilayer PCB boards, can increase the yield of the overall multilayer PCB board by manufacturing the board layer by layer and evaluating its quality, and by precisely connecting the wiring between layers, it is possible to manufacture high-density, small PCBs. This build-up process forms wiring connection lines between layers, and connects them through via holes. In order to form these via holes, a laser can be used instead of the existing mechanical drilling work, allowing for extremely fine diameters to be implemented.

[0007] The circuit board manufacturing process involves a desmear process to remove foreign matter and impart a rough surface to the board. In this case, the desmear process can damage the surface of the insulating layer through via holes due to the chemicals used in the process, exposing internal areas, such as glass fibers, within the insulating layer.

[0008]

[0009] The present embodiment provides a circuit board and semiconductor package capable of improving appearance characteristics by protecting the surface of an insulating layer during a surface treatment process such as desmear.

[0010]

[0011] A circuit board according to the present embodiment includes: a first insulating layer; a first resin layer disposed on an upper surface of the first insulating layer; a second insulating layer disposed on an upper surface of the first resin layer; a cavity penetrating the second insulating layer; a first circuit pattern disposed on a lower surface of the first insulating layer; a second circuit pattern disposed on a bottom surface of the cavity, which is an upper surface of the first resin layer; and a via hole penetrating the first resin layer and the first insulating layer and connecting the first circuit pattern and the second circuit pattern.

[0012] The material of the first insulating layer may be different from the material of the first resin layer.

[0013] The above first insulating layer is a prepreg (PPG) including glass fiber in resin, and the first resin layer may be made of a resin material.

[0014] The above second insulating layer may be a PID (Photo-Imageable Dielectric).

[0015] The second insulating layer includes a first through hole penetrating from one side to the other side,

[0016] At least a portion of the upper surface of the first resin layer may be exposed above the second insulating layer through the first through hole.

[0017] At least a portion of the second circuit pattern may be arranged on the upper surface of the first resin layer exposed through the first through hole.

[0018] A groove having a more concave shape than other regions may be formed on the upper surface of the second insulating layer.

[0019] A groove having a more concave shape than other regions may be formed on the upper surface of the first resin layer exposed upward through the first through hole.

[0020] It may include a protective layer disposed on the upper surface of the second insulating layer.

[0021] A semiconductor package according to the present embodiment includes: a first insulating layer; a first resin layer disposed on an upper surface of the first insulating layer; a second insulating layer disposed on an upper surface of the first resin layer; a cavity penetrating the second insulating layer; an electronic component disposed within the cavity; a first circuit pattern disposed on a lower surface of the first insulating layer; a second circuit pattern disposed on a bottom surface of the cavity, which is an upper surface of the first resin layer; and a via hole penetrating the first resin layer and the first insulating layer and connecting the first circuit pattern and the second circuit pattern.

[0022]

[0023] In this embodiment, by covering the surface of the first insulating layer exposed upward through the cavity with the first resin layer, the surface of the first insulating layer can be prevented from being damaged by contact with a chemical during the desmear process, thereby preventing the glass fibers in the first insulating layer from being exposed to the outside.

[0024]

[0025] Figure 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0026] Figures 2 to 11 are drawings illustrating a manufacturing process of a circuit board according to an embodiment of the present invention.

[0027]

[0028] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0029] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0030] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0031] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as "A and / or at least one (or more) of B, C," it may include one or more of all combinations that can be combined with A, B, and C.

[0032] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0033] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0034] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0035] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0036] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, and FIGS. 2 to 11 are drawings illustrating a manufacturing process of a circuit board according to an embodiment of the present invention.

[0037] Referring to FIGS. 1 to 11, a circuit board (10) according to an embodiment of the present invention may include a core layer (110), a first build-up layer (112) disposed on one surface of the core layer (110), and a second build-up layer (114) disposed on the other surface of the core layer (110). Here, the meaning of being disposed on one surface and the other surface is not only understood as a configuration in direct contact with the one surface and the other surface, but may also be understood as another configuration between the one surface and the first build-up layer (112), and between the other surface and the second build-up layer (114).

[0038] The core layer (110) may be a member forming the basis of the circuit board (10). The core layer (110) may be an insulating layer with embedded glass fibers or a metallic material.

[0039] For example, the core layer (110) may be any insulator such as photocurable and / or thermosetting. As a thermosetting insulator, it may be an insulator in which inorganic and / or organic fillers are dispersed in a resin such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, or a prepreg (PPG) including glass fibers in a resin. In addition, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and the inorganic and / or organic fillers may be provided with a material such as silica or plastic. When an insulating resin is used as the core, it may include a reinforcing material provided with glass fibers or aramid fibers.

[0040] As another example, when the core layer (110) is composed of a metallic material, the rigidity of the circuit board (10) increases, thereby improving the bending characteristics and enhancing the heat dissipation characteristics. In this case, the material of the first insulating layer (102) may include at least one of copper (Cu), aluminum (Al), magnesium (Mg), titanium (Ti), hafnium (Hf), and zinc (Zn). The material of the core layer (110) may also be composed of a metal including tungsten (W), molybdenum (Mo), and aluminum (Al), or any one of an alloy including invar, kovar, nickel (Ni) and iron (Fe), and ceramics.

[0041] The core layer (110) may include a via hole (not shown) penetrating from one surface to the other surface, and a circuit pattern disposed on one surface of the core layer (110) and a circuit pattern disposed on the other surface may be electrically connected through the via hole.

[0042] A first build-up layer (112) may be arranged on one side of the core layer (110). The first build-up layer (112) may include a first insulating layer (120), a first resin layer (130), and a second insulating layer (140). The first insulating layer (120), the first resin layer (130), and the second insulating layer (140) may be arranged in a vertical direction, which is a vertical direction of the core layer (110).

[0043] The first insulating layer (120) may be disposed on the upper surface of the core layer (110). The first insulating layer (120) may include any insulator, such as a photocurable and / or a thermocurable insulator. The first insulating layer (120) may include a prepreg (PPG) containing glass fibers in a resin. The resin of the first insulating layer (120) may include at least one of an epoxy resin, a bismaleimide triazine resin (BT resin), and a phenol resin. When the resin of the first insulating layer (120) is used as an insulating layer resin, it may include a reinforcing material made of glass fibers, aramid fibers, or the like.

[0044] A first circuit pattern (161) may be embedded in the lower surface of the first insulating layer (120). The first insulating layer (120) includes a first via hole (171), and the first via hole (171) may be formed to penetrate the first insulating layer (120) in a vertical direction. The lower end of the first via hole (171) may be electrically connected to the first circuit pattern (161).

[0045] The second insulating layer (140) may be disposed on top of the first insulating layer (120). The second insulating layer (140) may be a thermosetting insulator. The second insulating layer (140) may be a photosensitive insulating material. The second insulating layer (140) may be a PID (Photo-Imageable Dielectric).

[0046] The second insulating layer (140) may include a first through hole (152) to form a region of a cavity (150) disposed on one surface of the circuit board (10). The first through hole (152) is formed to penetrate from the upper surface to the lower surface of the second insulating layer (140), and a portion of the upper surface of the first resin layer (130) may be exposed upward through the first through hole (152).

[0047] A second circuit pattern (162) may be embedded in the lower surface of the second insulating layer (140). The second circuit pattern (162) may be electrically connected to the upper end of the first via hole (171). The second insulating layer (140) includes a second via hole (173), and the second via hole (173) may be formed to penetrate the second insulating layer (140) in a vertical direction. The lower end of the second via hole (173) may be electrically connected to the second circuit pattern (162).

[0048] A third circuit pattern (163) may be arranged on the upper surface of the second insulating layer (140). The third circuit pattern (163) may be electrically connected to the upper end of the second via hole (173).

[0049] A groove (142) having a concave shape downward compared to other regions may be formed on the upper surface of the second insulating layer (140). A plurality of grooves (142) may be provided, and a plurality of grooves may be provided along the upper surface of the second insulating layer (140). The groove (142) may be covered by a first protective layer (190) to be described later. A portion of the first protective layer (190) may be embedded in the groove (142). The groove (142) may be formed during a desmear process of the circuit board (10) to be described later.

[0050] A first resin layer (130) may be formed between the first insulating layer (120) and the second insulating layer (140). The first resin layer (130) may be interposed between the upper surface of the first insulating layer (120) and the lower surface of the second insulating layer (140). The thickness of the first resin layer (130) may be thinner than the thickness of the first insulating layer (120) or the thickness of the second insulating layer (140). For example, the thickness of the first resin layer (130) may be 1 um or more and 3 um or less. The first resin layer (130) may be formed of a resin material. The first resin layer (130) may include a resin and an adhesive applied to the surface of the resin.

[0051] The material of the above resin layer (130) may be resin. The above resin layer (130) may not include a filler, but alternatively, the above resin layer (103) may include a filler.

[0052] More specifically, the resin layer (130) may be formed of a primer containing isopropyl alcohol (IPA) or an acrylic silane. In addition, the first resin layer (130) may be formed of MPS (3-(trimethoxysilyl) propylmethacrylate), and a silane additive may be added.

[0053] The first resin layer (130) may include a third via hole (172). The third via hole (172) may be connected to the upper end of the first via hole (171). The third via hole (172) may be formed integrally with the first via hole (171). Since the first via hole (171) and the third via hole (172) connecting the first circuit pattern (161) and the second circuit pattern (162) are formed integrally, the combined configuration of the first via hole (171) and the third via hole (172) may be referred to as a single via hole. The upper end of the third via hole (172) may be electrically connected to the second circuit pattern (162).

[0054] A portion of the upper surface of the first resin layer (130) may form the bottom surface of the cavity (150). A portion of the upper surface of the first resin layer (130) may be exposed above the first build-up layer (112) through the first through hole (152). A portion of the second circuit pattern (162) may be arranged on the upper surface of the first resin layer (130) exposed through the first through hole (152). In this case, the second circuit pattern (162) may also be understood as being formed on the upper surface of the first resin layer (130).

[0055] The first resin layer (130) is arranged to cover the upper surface of the first insulating layer (120), and the upper surface of the first insulating layer (120) can be protected by the arrangement of the first resin layer (130). Specifically, a part of the upper surface of the first resin layer (130) can be exposed upward through the cavity (150). In this case, since the upper surface of the first insulating layer (120) is covered by the first resin layer (130) before the formation of the first protective layer (190), the first insulating layer (120) can be prevented from being damaged by the chemical sprayed according to the desmear process. Since the first insulating layer (120) includes resin and glass fiber, there is a risk that the glass fiber may be exposed to the outside of the first insulating layer (120) due to damage to the resin within the first insulating layer (120) when the chemical is sprayed. However, according to the present embodiment, the glass fiber within the first insulating layer (120) can be prevented from being exposed to the outside by the cover structure of the first insulating layer (120) through the first resin layer (130).

[0056] Meanwhile, although not shown, one or more concave grooves may be formed on the upper surface of the first resin layer (130) exposed upward through the cavity (150) according to the desmear process.

[0057] A first protective layer (190) may be formed on the upper surface of the first build-up layer (112). The first protective layer (190) may protect the third circuit pattern (163) from external moisture or contaminants. In addition, when a semiconductor element is arranged on the circuit board (10) using a material such as solder, the first protective layer (190) may perform a function of preventing a short circuit between solders due to low wettability with the solder. The first protective layer (190) may use a photocurable insulating material, and for example, the first protective layer (190) may use a solder resist.

[0058] The first protective layer (190) may include a second through hole (154). The second through hole (154) may be arranged to face the first through hole (152) in a vertical direction. A cavity (150) may be formed on the upper surface of the circuit board (10) by the first through hole (152) and the second through hole (154). The second circuit pattern (162) may be formed on the bottom surface of the cavity (150). An electronic component (not shown) electrically connected to the second circuit pattern (162) may be arranged in the cavity (150), and a semiconductor package may be implemented by combining the electronic component and the circuit board (10). At least a portion of the electronic component may be arranged within the second through hole (154).

[0059] A second build-up layer (114) may be arranged on the other surface of the core layer (110). The second build-up layer (114) may include a third insulating layer (125), a second resin layer (135), and a fourth insulating layer (145). The third insulating layer (125), the second resin layer (135), and the fourth insulating layer (145) may be arranged in a vertical direction, which is a vertical direction of the core layer (110).

[0060] The third insulating layer (125) may be disposed on the lower surface of the core layer (110). The third insulating layer (125) may include any insulator, such as a photocurable and / or thermocurable insulator. The third insulating layer (125) may include a prepreg (PPG) containing glass fibers in a resin. The resin of the third insulating layer (125) may include at least one of an epoxy resin, a bismaleimide triazine resin (BT resin), and a phenol resin. When the resin of the third insulating layer (125) is used as an insulating layer resin, it may include a reinforcing material made of glass fibers, aramid fibers, or the like.

[0061] A fourth circuit pattern (164) may be embedded in the upper surface of the third insulating layer (125). The third insulating layer (125) includes a fourth via hole (174), and the fourth via hole (174) may be formed to penetrate the third insulating layer (125) in a vertical direction. The upper end of the fourth via hole (174) may be electrically connected to the fourth circuit pattern (164).

[0062] The fourth insulating layer (145) may be disposed below the third insulating layer (125). The fourth insulating layer (145) may be a thermosetting insulator. The fourth insulating layer (145) may be a photosensitive insulating material. The fourth insulating layer (145) may be a PID (Photo-Imageable Dielectric).

[0063] A fifth circuit pattern (165) may be embedded in the upper surface of the fourth insulating layer (145). The fifth circuit pattern (165) may be electrically connected to the lower end of the fourth via hole (174). The fourth insulating layer (145) includes a fifth via hole (176), and the fifth via hole (176) may be formed to penetrate the fourth insulating layer (145) in a vertical direction. The upper end of the fifth via hole (176) may be electrically connected to the fifth circuit pattern (165).

[0064] A sixth circuit pattern (166) may be arranged on the lower surface of the fourth insulating layer (145). The sixth circuit pattern (166) may be electrically connected to the lower end of the fifth via hole (176).

[0065] A second resin layer (135) may be formed between the third insulating layer (125) and the fourth insulating layer (145). The second resin layer (135) may be interposed between the lower surface of the third insulating layer (125) and the upper surface of the fourth insulating layer (145). The thickness of the second resin layer (135) may be thinner than the thickness of the third insulating layer (125) or the thickness of the fourth insulating layer (145). For example, the thickness of the second resin layer (135) may be 1 um or more and 3 um or less. The second resin layer (135) may be formed of a resin material. The second resin layer (135) may include a resin and an adhesive applied to the surface of the resin.

[0066] More specifically, the second resin layer (135) may be formed of a primer containing isopropyl alcohol (IPA) or an acrylic silane. In addition, the second resin layer (135) may be formed of MPS (3-(trimethoxysilyl) propylmethacrylate), and a silane additive may be added.

[0067] The second resin layer (135) may include a sixth via hole (175). The sixth via hole (174) may be connected to the lower end of the fourth via hole (174). The sixth via hole (175) may be formed integrally with the fourth via hole (174). Since the fourth via hole (174) and the sixth via hole (175), which connect the fourth circuit pattern (164) and the fifth circuit pattern (165), are formed integrally, the combined configuration of the fourth via hole (174) and the fifth via hole (175) may be referred to as a single via hole. The upper end of the sixth via hole (174) may be electrically connected to the fifth circuit pattern (165).

[0068] A second protective layer (195) may be formed on the lower surface of the second build-up layer (114). The second protective layer (195) may protect the sixth circuit pattern (166) from external moisture or contaminants. In addition, when a semiconductor element is arranged on the lower surface of the circuit board (10) using a material such as solder, the second protective layer (195) may perform a function of preventing a short circuit between solders due to low wettability with the solder. The second protective layer (195) may use a photocurable insulating material, and for example, the second protective layer (195) may use a solder resist.

[0069] According to the structure as described above, since the surface of the first insulating layer (120) exposed upward through the cavity (150) is covered with the first resin layer (130), the surface of the first insulating layer (120) can be prevented from being damaged by contact with a chemical during the desmear process, and thus the glass fibers in the first insulating layer (120) can be prevented from being exposed to the outside.

[0070] Referring to FIGS. 2 to 11, a manufacturing process of a circuit board (10) according to an embodiment of the present invention will be described.

[0071] First, as illustrated in FIGS. 2 and 3, a first circuit pattern (161) and a fourth circuit pattern (164) can be formed on the surface of the core layer (110) through a metal foil (160). For example, the first circuit pattern (161) and the fourth circuit pattern (164) can be implemented by etching.

[0072] Next, as illustrated in Fig. 4, a first insulating layer (120) and a first resin layer (130), and a third insulating layer (125) and a second resin layer (135) are laminated on one side and the other side of the core layer (110) to implement a first build-up layer (112) and a second build-up layer (114), respectively. In this case, a copper foil (200) may be disposed on the upper surface of the first resin layer (130) and the lower surface of the second resin layer (135), respectively.

[0073] Next, as illustrated in FIG. 5, a via hole (210) is formed in the first insulating layer (120) and the first resin layer (130) on which the copper foil (200) is arranged, and in the third insulating layer (125) and the second resin layer (135). Accordingly, among the configurations of the circuit board (10) described above, the first via hole (171) and the third via hole (172) can be formed simultaneously, and the fourth via hole (174) and the sixth via hole (175) can be formed simultaneously.

[0074] Next, as illustrated in FIG. 6, the copper foil (200) disposed on the upper surface of the first resin layer (130) and the lower surface of the second resin layer (135) can be removed through etching. Thereafter, as illustrated in FIGS. 7 and 8, chemical copper (Cu, 220) for implementing the metal patterns in the first via hole (171) and the third via hole (172), the metal patterns in the second circuit pattern (162), the fourth via hole (174) and the sixth via hole (175), and the fifth circuit pattern (165) can be processed on the upper surface of the first resin layer (130) and the lower surface of the second primer layer (135), respectively.

[0075] Next, as illustrated in Fig. 9, the second insulating layer (140) and the fourth insulating layer (145) may be attached to the upper surface of the first resin layer (130) on which the second circuit pattern (162) is formed and the lower surface of the second resin layer (135) on which the fifth circuit pattern (165) is formed. The second insulating layer (140) and the fourth insulating layer (145) may be implemented by a process of vacuum-sealing the PID to the upper surface of the first resin layer (130) and the lower surface of the second primer layer (135), respectively.

[0076] Next, as illustrated in FIG. 10, a cavity (230) for forming the first through hole (152) and a via hole (240) for forming the second via hole (173) and the fifth via hole (176) can be formed on the upper surface of the second insulating layer (140) and the lower surface of the fourth insulating layer (145).

[0077] Thereafter, as illustrated in FIG. 11, a desmear process may be performed to remove foreign substances on the surfaces of the first build-up layer (112) and the second build-up layer (114). As described above, during the desmear process, the surfaces of the first insulating layer (120) and the third insulating layer (125) are covered by the first resin layer (130) and the second resin layer (135), respectively, so that damage to the surfaces of the first insulating layer (120) and the third insulating layer (125) due to chemicals for the desmear process can be prevented.

[0078] As described above, during the desmear process, a groove (142) can be formed on the upper surface of the second insulating layer (140) exposed upward and on the upper surface of the first resin layer (130) exposed upward through the cavity (230) by contact between the resin constituting the second insulating layer (140) and the resin constituting the first resin layer (130) with a chemical for the desmear process.

[0079] After the desmear process, a patterning process for forming a third circuit pattern (163), a second via hole (173), a sixth circuit pattern (166), and a fifth via hole (176) on the upper surface of the first build-up layer (112) and the lower surface of the second build-up layer (114), respectively, and a process for forming the first protective layer (190) and the second protective layer (195) are performed, so that a circuit board (10) as in FIG. 1 can be manufactured.

[0080] Although all components constituting the embodiments of the present invention have been described above as being combined or operating in combination, the present invention is not necessarily limited to these embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined and operated one or more times. In addition, terms such as "include," "comprise," or "have" described above, unless specifically stated to the contrary, mean that the corresponding component may be inherent, and therefore should be interpreted as including other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in a dictionary, should be interpreted as being consistent with the contextual meaning of the related technology, and shall not be interpreted in an ideal or excessively formal sense, unless explicitly defined in the present invention.

[0081] The above description is merely an illustrative description of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. First insulating layer; A first resin layer disposed on the upper surface of the first insulating layer; A second insulating layer disposed on the upper surface of the first resin layer; A cavity penetrating the second insulating layer; A first circuit pattern arranged on the lower surface of the first insulating layer; A second circuit pattern arranged on the bottom surface of the cavity, which is the upper surface of the first resin layer; and A circuit board including a via hole penetrating the first resin layer and the first insulating layer and connecting the first circuit pattern and the second circuit pattern.

2. In paragraph 1, A circuit board in which the material of the first insulating layer is different from the material of the first resin layer.

3. In paragraph 2, The above first insulating layer is a prepreg (PPG) containing glass fibers in resin, The above first resin layer is a circuit board made of resin material.

4. In paragraph 1, A circuit board in which the second insulating layer is a PID (Photo-Imageable Dielectric).

5. In paragraph 1, The second insulating layer includes a first through hole penetrating from one side to the other side, A circuit board in which at least a portion of the upper surface of the first resin layer is exposed above the second insulating layer through the first through hole.

6. In paragraph 5, A circuit board in which at least a portion of the second circuit pattern is arranged on the upper surface of the first resin layer exposed through the first through hole.

7. In paragraph 1, A circuit board in which a groove having a more concave shape than other areas is formed on the upper surface of the second insulating layer.

8. In paragraph 5, A circuit board in which a groove having a more concave shape than other regions is formed on the upper surface of the first resin layer exposed upward through the first through hole.

9. In paragraph 1, A circuit board including a protective layer disposed on an upper surface of the second insulating layer.

10. First insulating layer; A first resin layer disposed on the upper surface of the first insulating layer; A second insulating layer disposed on the upper surface of the first resin layer; A cavity penetrating the second insulating layer; Electronic components arranged within the cavity; A first circuit pattern arranged on the lower surface of the first insulating layer; A second circuit pattern arranged on the bottom surface of the cavity, which is the upper surface of the first resin layer; and A semiconductor package including a via hole penetrating the first resin layer and the first insulating layer and connecting the first circuit pattern and the second circuit pattern.

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