Method for manufacturing LED device

Abstract

Disclosed is a method for manufacturing an LED device having a uniform surface, by using at least one of SiO2 and Si3N4 as an etch stop layer and using etch rates of the etch stop layer and an insulating layer in a dry etching step after wet etching, so that a current spreading layer on the LED device and the insulating layer on the side of the LED device have upper surfaces on the same plane.

Description

Method for manufacturing LED elements

[0001] The present invention relates to a method for manufacturing an LED device having a uniform surface by using at least one of SiO2 and Si3N4 as an etching stop layer and utilizing the etching speed of the etching stop layer and the insulating layer in a dry etching step after wet etching, thereby allowing a current dispersing layer on the upper side of the LED device and an insulating layer on the side of the LED device to have upper surfaces on the same plane.

[0002] The research subject information of the present invention is as follows.

[0003] Project No.: 00470058, Ministry of SMEs and Startups, Project Management Agency: Korea Technology Information Promotion Agency for Small and Medium Businesses, Research Project Name: Small and Medium Business Technology Innovation Development Project (Export-Oriented_Tech-Bridge), Research Project Name: Development of High-Efficiency Nano-LED Devices with a Diameter of 650nm for Next-Generation Displays, Project Implementing Organization: Advanced View Technology Co., Ltd., Research Period: 2024.10.01-2026.09.30

[0004] LED elements are semiconductor light-emitting elements that convert electric current into light. They are widely used as light sources for displays due to their high light conversion efficiency.

[0005] Recently, research is being conducted to apply ultra-small LED elements manufactured in nanometer or micrometer units to lighting, displays, etc.

[0006] To manufacture these LED devices, there is a top-down manufacturing method that involves cutting or etching a bulk structure to create the desired shape. A SiO2 layer, which acts as a current-dispersing layer and mask, is deposited on a GaN wafer, and then dry etching is used to create column- or rod-shaped LED devices in a top-down manner. The remaining SiO2 layer is then removed before subsequent processes can begin.

[0007] However, when the SiO2 layer is removed, there is a problem that the surface uniformity is reduced due to wet etching when the upper surface of the p-type semiconductor layer is exposed after passivation in the subsequent process.

[0008] As another example, a wafer made of group III / V material layers can be bonded to a silicon wafer, and the wafer made of group III / V material layers can be selectively etched to manufacture an LED device. In the case of etching, the wafer made of group III / V material layers can be etched, but it may be difficult to obtain an LED device with a precise shape due to undercutting phenomena, etc.

[0009] If the surface condition of the device is uneven, the luminescence characteristics of each individual device are all different, which can be the main cause of a decrease in the overall luminescence yield characteristics.

[0010] In this way, since the surface condition of the LED element has a great influence on the light-emitting characteristics of the LED element, it is important that the LED element after etching has a uniform surface.

[0011] Therefore, research is needed on a method for manufacturing LED devices with a uniform surface after etching.

[0012] An object of the present invention is to provide a method for manufacturing an LED element having a uniform surface such that a current dispersing layer on the upper side of the LED element and an insulating layer on the side of the LED element have an upper surface on the same plane.

[0013] The objectives of the present invention are not limited to those mentioned above. Other objectives and advantages of the present invention not mentioned above can be understood through the following description and will be more clearly understood through the embodiments of the present invention. Furthermore, it will be readily apparent that the objectives and advantages of the present invention can be realized by the means and combinations thereof set forth in the claims.

[0014] A method for manufacturing an LED device according to the present invention comprises the steps of: (a) preparing a semiconductor structure having a current dispersing layer and an etching stop layer disposed on the current dispersing layer; (b) depositing an insulating layer on an outer surface of the semiconductor structure having the etching stop layer deposited thereon; (c) coating the semiconductor structure having the insulating layer deposited thereon with a photoresist; (d) wet-etching the coated semiconductor structure to etch the insulating layer so as to expose an upper surface of the etching stop layer; (e) dry-etching the wet-etched semiconductor structure to etch the etching stop layer and the insulating layer so as to expose an upper surface of the current dispersing layer; and (f) removing the photoresist coated on the etched semiconductor structure.

[0015] In the above step (e), the current dissipation layer and the insulating layer may have upper surfaces on the same plane.

[0016] The above etching stop layer may include at least one of SiO2 and Si3N4.

[0017] The semiconductor structure may include an n-type semiconductor layer, an active layer disposed on the n-type semiconductor layer, and a p-type semiconductor layer disposed on the active layer.

[0018] In the above step (a), the thickness of the etching stop layer may be 0.5 to 2 μm.

[0019] In the above step (b), the thickness of the insulating layer may be 30 to 90 nm.

[0020] The etching speed of the above etching stop layer may be faster than the etching speed of the insulating layer.

[0021] In the above step (c), a step of descumming the photoresist so that the insulating layer of the semiconductor structure is exposed may be further included.

[0022] In the above step (d), an aqueous solution containing hydrogen fluoride (HF) and ammonium fluoride (NH4F) can be used.

[0023] In the above step (e), reactive ion etching (RIE) can be used.

[0024] An LED device according to the present invention comprises a semiconductor structure including an n-type semiconductor layer, an active layer disposed on the n-type semiconductor layer, and a p-type semiconductor layer disposed on the active layer; a current dispersing layer disposed on the semiconductor structure; and an insulating layer surrounding an outer circumferential surface of the semiconductor structure and the current dispersing layer; characterized in that a surface of the current dispersing layer is exposed.

[0025] According to the method for manufacturing an LED element of the present invention, by applying at least one of SiO2 and Si3N4 as an etching stop layer, the current dispersing layer on the upper side of the LED element and the insulating layer on the side of the LED element after etching can have an upper surface on the same plane, thereby exhibiting a uniform surface.

[0026] Accordingly, ultimately, after aligning the LED elements, the arranged LED elements are put into a display through a FAB (Fabrication Facility) process, and current is ultimately injected into the LED elements. During this process, if the upper surface is uniformly exposed with a current dispersing layer, it can function as a single light-emitting element. In particular, uniform light-emitting characteristics can be secured between individual elements.

[0027] In addition to the effects described above, specific effects of the present invention are described below while explaining specific details for carrying out the invention.

[0028] Figure 1 is a schematic diagram showing a method for manufacturing a semiconductor structure according to the present invention.

[0029] Figure 2 is a flowchart showing a method for manufacturing an LED element according to the present invention.

[0030] Figure 3 is a schematic diagram showing a method for manufacturing an LED element according to the present invention.

[0031] Figure 4 is an image photograph of the upper part of an LED element after the wet etching step according to the present invention.

[0032] Figure 5 is a photograph of the top of an LED element after a dry etching step according to the present invention.

[0033] Figure 6 is a photograph of the top of an LED device that was wet etched after dry etching.

[0034] Figure 7 is a photograph of the top of an LED element that has been dry etched only.

[0035] [Explanation of symbols]

[0036] 1: Substrate

[0037] 2: n-type semiconductor layer

[0038] 3: Active layer

[0039] 4: p-type semiconductor layer

[0040] 5: Chrome layer

[0041] 6: Pattern layer

[0042] 10: Current distribution layer

[0043] 20: Etch stop layer

[0044] 30: Photoresist

[0045] 40: Semiconductor structure

[0046] 50: Insulating layer

[0047] 100: LED element

[0048]

[0049] The above-described objects, features, and advantages will be described in detail below with reference to the accompanying drawings, so that those skilled in the art can easily practice the technical idea of ​​the present invention. In describing the present invention, if it is determined that a detailed description of known technologies related to the present invention may unnecessarily obscure the gist of the present invention, a detailed description thereof will be omitted. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar components.

[0050] Hereinafter, the phrase "any configuration is placed on (or below)" a component or "on (or below)" a component may mean that any configuration is placed in contact with the upper surface (or lower surface) of said component, and that other configurations may be interposed between said component and any configuration placed on (or below) said component.

[0051] Additionally, when it is described that a component is "connected," "coupled," or "connected" to another component, it should be understood that the components may be directly connected or connected to one another, but that other components may also be "interposed" between the components, or that each component may be "connected," "coupled," or "connected" through another component.

[0052] Hereinafter, a method for manufacturing an LED device according to some embodiments of the present invention will be described.

[0053] Previously, when exposing the p-type semiconductor layer located on top of the LED element after passivation of the LED element, there was a problem that the uniformity of the exposed surface was reduced due to wet etching.

[0054] Meanwhile, a column or rod-shaped LED element is manufactured by etching in a top-down manner while at least one layer of SiO2 and Si3N4, which serves as a current spreading layer and mask, is deposited on a GaN wafer, and the remaining SiO2 layer is removed. However, in this process, the inventor left at least one layer of SiO2 and Si3N4 without removing it and applied it as an etching stop layer.

[0055] Accordingly, by applying at least one of SiO2 and Si3N4 as an etch stop layer on the top of the LED element, performing dry etching after wet etching, and performing etching of the insulating layer, it was confirmed that the current dispersing layer on the top of the LED element and the insulating layer on the side of the LED element have an upper surface on the same plane and exhibit a uniform surface.

[0056] These LED elements have a rod shape, and light emitted from the active layer can travel toward the front of the display device through the n-type semiconductor layer, thereby forming a light source in the pixel area.

[0057] First, before performing the step (S110) of preparing a semiconductor structure on which a current dispersing layer and an etching stop layer are deposited, a semiconductor structure including an n-type semiconductor layer, an active layer disposed on the n-type semiconductor layer, and a p-type semiconductor layer disposed on the active layer can be manufactured.

[0058] Figure 1 is a schematic diagram showing a method for manufacturing a semiconductor structure according to the present invention.

[0059] As shown in Fig. 1, after growing an n-type semiconductor layer (2), an active layer (3), and a p-type semiconductor layer (4) on a sapphire substrate (1), a current spreading layer (10) can be deposited on the p-type semiconductor layer (4).

[0060] Next, after depositing at least one of SiO2 and Si3N4, Cr is deposited, and a nano-sized pattern layer (6) can be formed on the top layer.

[0061] The Cr layer (5) acts as a mask when etching one or more layers (20) of SiO2 and Si3N4 at the bottom.

[0062] The pattern layer (6) acts as a mask for etching the Cr layer at the bottom.

[0063] The pattern layer (6) is made of a polymer material and is also called imprinting.

[0064] The thickness of the semiconductor structure including the n-type semiconductor layer, the active layer, and the p-type semiconductor layer may be 1 to 10 μm, and the thickness of the current spreading layer may be 0.2 to 0.5 μm.

[0065] In addition, the thickness of at least one layer (20) of SiO2 and Si3N4 serves as a mask for etching, and the thickness may be 0.5 to 2 μm.

[0066] The layer deposited with Cr can have a thickness of 10 to 100 nm and can serve as a mask for etching. The thickness of the pattern layer can be 500 to 1500 μm.

[0067] Next, ICP-RIE dry etching can be performed to etch the side surface of the Cr layer (5) in a direction perpendicular to the substrate plane.

[0068] Inductively coupled plasma (ICP)-reactive ion etching (RIE) can be used, which can etch specific areas through chemical and physical reactions using activated ions.

[0069] For example, dry etching uses CFx gas and can be performed in the range of 500 to 900 seconds, and preferably in the range of 600 to 800 seconds.

[0070] The etched Cr layer has a patterned shape, and the surface of one or more layers (20) of SiO2 and Si3N4 can be exposed.

[0071] Next, ICP-RIE dry etching may be performed to etch the side surface of at least one layer (20) of SiO2 and Si3N4 in a direction perpendicular to the substrate plane. The etched at least one layer of SiO2 and Si3N4 may have a patterned shape, and the surface of the current spreading layer may be exposed.

[0072] Next, ICP-RIE dry etching can be performed to etch the current spreading layer (10) and the side surface of the semiconductor structure in a direction perpendicular to the plane of the substrate (1) so that they have an inclined surface.

[0073] As illustrated in FIG. 1, the vertical direction at this stage may include a shape in which the side surfaces of the current spreading layer and the semiconductor structure have inclined surfaces.

[0074] A current dissipation layer remains and can be used as an etch stop layer.

[0075] The semiconductor structure can be etched to have a top layer with a thickness of 3 to 3.5 μm.

[0076] Next, through side etching of the semiconductor structure (40), the shape of the semiconductor structure can be formed into a rod shape. Wet etching can be performed by dipping for 10 minutes to 2 hours using KOH (potassium hydroxide) at a concentration of 20 to 30 wt%.

[0077] The semiconductor structure illustrated in (E) of Fig. 1 is the semiconductor structure of step S100 of Fig. 3.

[0078] Fig. 2 is a flowchart showing a method for manufacturing an LED element according to the present invention, and Fig. 3 is a schematic diagram showing a method for manufacturing an LED element according to the present invention.

[0079] As shown in FIGS. 2 and 3, the method for manufacturing an LED element according to the present invention

[0080] It may include a step of preparing a semiconductor structure having a current dispersing layer and an etching stop layer disposed on the current dispersing layer (S110), a step of depositing an insulating layer on an outer surface of the semiconductor structure (S120), a step of coating the semiconductor structure with a photoresist (S130), a step of wet-etching the semiconductor structure to etch the insulating layer so that an upper surface of the etching stop layer is exposed (S140), a step of dry-etching the semiconductor structure to etch the etching stop layer and the insulating layer so that an upper surface of the current dispersing layer is exposed (S150), and a step of removing the photoresist (S160).

[0081] Step (S110) of preparing a semiconductor structure in which a current dispersing layer and an etching stop layer disposed on the current dispersing layer are deposited

[0082] A semiconductor structure (40) is grown on a substrate, a current dispersing layer (10) is deposited on the semiconductor structure, and an etching stop layer (20) serving as a mask is sequentially deposited. Then, the semiconductor structure (40) and the current dispersing layer (10) are etched in a top-down manner through dry etching, thereby manufacturing a semiconductor structure in the form of a column or rod.

[0083] In the manufactured column or rod-shaped semiconductor structure, it is desirable to maintain the etching stop layer (20) that acts as a mask, and by maintaining the etching stop layer on top of the semiconductor structure (40), the surfaces of the current dispersing layer (10) and the insulating layer (50) can be formed at the same position.

[0084] The substrate (1) can be selected from a sapphire substrate, a gallium nitride (GaN) substrate, etc.

[0085] A semiconductor structure (40) may include an n-type semiconductor layer (2), an active layer (3) disposed on the n-type semiconductor layer, and a p-type semiconductor layer (4) disposed on the active layer.

[0086] For example, n-GaN can be used as the n-type semiconductor layer, GaN / InGaN as the active layer, and p-GaN as the p-type semiconductor layer. The active layer generates light through the recombination of electrons supplied from the n-type semiconductor layer and holes supplied from the p-type semiconductor layer. The p-type semiconductor layer has relatively high resistance.

[0087] The thickness of the semiconductor structure may be 1 to 10 μm, preferably 2 to 4 μm.

[0088] Looking at the thickness of each layer of the semiconductor structure, the n-type semiconductor layer may be 5㎛ or less, the active layer may be 100nm or less, and the p-type semiconductor layer may be 120nm or less, but is not limited thereto.

[0089] In order to distribute current in the p-type semiconductor layer, a current dispersing layer including a metal such as Al, Cu, Cr, Ni, etc., and / or a transparent conductive oxide (TCO) material such as ITO (Indium Tin Oxide) or FTO (Fluorine-doped Tin Oxide) can be placed on one surface of the p-type semiconductor layer.

[0090] The thickness of the current dissipation layer may be, but is not limited to, 0.2 to 0.5 μm.

[0091] The etch stop layer (20) is a layer generated during the manufacturing process of a semiconductor structure and can be used to protect the underlying semiconductor structure from the etching solution. From this perspective, the etch stop layer is preferably resistant to the etching solution and is preferably sealed to completely cover the upper surface of the semiconductor structure.

[0092] Additionally, it is desirable that the etching rate of the etch stop layer for the etching solution be faster than the etching rate of the insulating layer, which is important in that the insulating layer on the side must be maintained while the etch stop layer is etched to expose the current dispersing layer.

[0093] Since the insulating layer (50) is deposited by stacking atomic layers using ALD (Atomic Layer Deposition), the deposition density is high, and the etching speed is relatively slow compared to the etching stop layer.

[0094] The etching stop layer (20) preferably includes at least one of SiO2 and Si3N4, and serves as a mask for etching the semiconductor structure and current dispersion layer.

[0095] The type of etch stop layer may differ from the type of insulating layer because the etch stop layer and the insulating layer have different etching rates.

[0096] The thickness of the etch stop layer may be 0.5 to 2 μm, and preferably 0.6 to 1 μm. If the thickness of the etch stop layer is less than 0.5 μm, there is a risk that the current dispersing layer may be exposed during the wet etching step. Conversely, if the thickness of the etch stop layer exceeds 2 μm, there may be a disadvantage that the etching time takes a long time during the dry etching step.

[0097] Step of depositing an insulating layer on the outer surface of a semiconductor structure (S120)

[0098] In order to protect the semiconductor structure (40) on which the etching stop layer (20) is deposited, an insulating layer (50) such as a protective film can be deposited on the outer surface of the semiconductor structure, and preferably, the insulating layer (50) can be deposited on the entire surface of the semiconductor structure.

[0099] The insulating layer (50) can be arranged to surround the side of the n-type semiconductor layer, the active layer, and the p-type semiconductor layer together with the side of the active layer.

[0100] Additionally, the insulating layer prevents electrical short circuits that may occur when the active layer comes into contact with conductive materials other than the n-type semiconductor layer and the p-type semiconductor layer.

[0101] Additionally, by placing an insulating layer on the outer surface of the active layer, surface defects of the LED element can be minimized, thereby improving the lifespan and efficiency.

[0102] After manufacturing the LED element, it is separated or dispersed from the substrate using ultrasonic waves for use. At this time, the thickness of the insulating layer can be adjusted to facilitate separation by ultrasonic waves.

[0103] From this perspective, the thickness of the insulating layer may be 30 to 90 nm, and preferably 30 to 50 nm. If the thickness of the insulating layer exceeds 90 nm, separation by ultrasonic waves may be insufficient.

[0104] The insulating layer (50) can be deposited using an ALD (Atomic Layer Deposition) device.

[0105] The insulating layer may include a transparent insulating material. For example, the insulating layer may include, but is not limited to, one or more insulating materials selected from the group consisting of SiO2, Si3N4, Al2O3, AlN, and TiO2.

[0106] Step of coating a semiconductor structure with photoresist (S130)

[0107] A semiconductor structure on which an insulating layer (50) is deposited can be coated with photoresist (PR), and the photoresist can be applied (filled) to the height of the upper surface of the semiconductor structure to prevent etching of the lower part of the semiconductor structure.

[0108] In steps S130 and S140 of Fig. 3, a photoresist (30) that is easy to coat and remove is used to fill the gaps between the rod-shaped semiconductor structures. Without a UV irradiation process, a viscous photoresist (30) is spin-coated to fill the gaps between the rod-shaped semiconductor structures, and a coating process of the photoresist is performed. To harden the photoresist, a heat treatment (baking) is performed, followed by wet or dry etching.

[0109] For example, photoresist is a light-sensitive material that contains an organic solvent and a polymer. After spin-coating the photoresist, the organic solvent within the photoresist can be removed. Photoresists use light to form patterns and are classified as negative and positive. Negative photoresists cause particles to clump together when exposed to light, so when exposed to light, the unexposed portion is removed. Positive photoresists react to the light-exposed area, and when exposed to light, the polymer bonds are broken, so when exposed to light, only the exposed portion is removed.

[0110] A photoresist (30) exists on the upper surface of the exposed insulating layer (50), and the photoresist can be etched.

[0111] As shown in steps S130 and S140, after coating with photoresist, a step of descumming the photoresist so that the insulating layer of the semiconductor structure is exposed may be further included.

[0112] The descum process uses an oxygen plasma etching process (O2 gas) to etch the photoresist so that the insulating layer is exposed.

[0113] Even if the descum process is performed, the photoresist may not be completely removed. Photoresist not removed during the descum process may be removed simultaneously with the insulating layer during the insulating layer etching process.

[0114] Additionally, the photoresist can be selectively etched, but is not limited thereto.

[0115] Selective etching can be performed using dry etching such as sputter etching using inert gases, ions, etc., plasma etching, or wet etching using a chemical reaction using a solution.

[0116] Step (S140) of wet etching the semiconductor structure to etch the insulating layer so that the upper surface of the etching stop layer is exposed.

[0117] The upper region of the coated semiconductor structure (40) can be wet-etched to etch the insulating layer (50) so that the upper surface of the etch stop layer (20) is exposed.

[0118] Etching processes can remove part or all of a thin film using physical or chemical methods. Etching can be categorized into wet and dry etching, depending on the method. In the step of etching the insulating layer, wet etching can be performed by exposing the thin film to an etching solution. However, due to the difficulty in achieving directionality due to the use of an etching solution, it can result in an isotropic etching pattern.

[0119] Here, isotropic etching means that when the etching solution touches the thin film, it etches at the same rate in all directions from the moment of contact.

[0120] At this time, only the insulating layer on the upper surface of the etching stop layer may be etched, or a portion of the etching stop layer may be etched together with the insulating layer, or a portion of the etching stop layer and a portion of the photoresist may be etched together with the insulating layer.

[0121] In the wet etching step, an aqueous solution (buffered oxide etch, BOE) containing hydrogen fluoride (HF) and ammonium fluoride (NH4F) can be used, and preferably, an aqueous solution containing hydrogen fluoride (HF) and ammonium fluoride (NH4F) mixed in a weight ratio of 0.5 to 3:10 can be used.

[0122] Preferably, wet etching can be performed by dipping at room temperature (25°C) for up to 90 to 100 seconds when using BOE (NH4F:10, HF:1 weight ratio).

[0123] When immersed in a wet etching solution for up to 90 to 100 seconds, the solution can penetrate between the photoresist and the rod-shaped semiconductor structure, etching away the insulating layer on the side.

[0124] By using an aqueous solution containing hydrogen fluoride (HF) and ammonium fluoride (NH4F), the wet etching speed can be controlled to achieve excellent uniformity of the etched surface.

[0125] A step (S150) of dry etching a semiconductor structure to etch the etch stop layer and the insulating layer so that the upper surface of the current distribution layer is exposed.

[0126] The semiconductor structure (40) that was wet-etched in the first stage can be dry-etched in the second stage to etch the etching stop layer (20) and the insulating layer (50) so that the upper surface of the current dispersing layer is exposed.

[0127] In the dry etching step, the etching stop layer with a fast etching rate and the insulating layer with a slow etching rate can be etched so that the surface of the etching stop layer initially has a well shape, i.e. a concave shape, and ultimately the current dispersing layer and the insulating layer have upper surfaces on the same plane.

[0128] Through dry etching, the upper surface of the photoresist can also be positioned at the same level as the surface of the current-dispersing layer and the surface of the insulating layer. Furthermore, since the upper etch-stop layer is completely removed when the current-dispersing layer is exposed, the side surfaces remain surrounded by an insulating layer.

[0129] In the dry etching step, reactive ion etching (RIE) can be used, which can etch specific areas on the wafer through chemical and physical reactions using activated ions.

[0130] For example, dry etching uses CFx gas and can be performed in the range of 500 to 900 seconds, and preferably in the range of 600 to 800 seconds.

[0131] If the etching time exceeds 900 seconds, burning may occur in the photoresist layer.

[0132] Meanwhile, if wet etching is performed twice after dry etching once, burning of the photoresist may occur before the etch stop layer is removed, and the etch stop layer and insulating layer of the semiconductor structure tend to be etched unevenly.

[0133] If only dry etching is performed in the first stage, the photoresist may not be maintained and may be etched until the etch stop layer and insulating layer on top of the semiconductor structure are completely etched, the photoresist around the semiconductor structure may be etched first, and if the etching degree is severe, burning of the photoresist may occur.

[0134] From this point of view, it is preferable that the method for manufacturing the LED element of the present invention performs dry etching after wet etching.

[0135] Step for removing photoresist (S160)

[0136] Finally, the photoresist (30) coated on the etched semiconductor structure can be removed to manufacture an LED element.

[0137] Any remaining photoresist can be removed using a PR stripper, which may contain organic solvents.

[0138] An LED device manufactured by a manufacturing method according to the present invention comprises a semiconductor structure including an n-type semiconductor layer, an active layer disposed on the n-type semiconductor layer, and a p-type semiconductor layer disposed on the active layer, a current dispersing layer disposed on the semiconductor structure, and an insulating layer surrounding an outer circumferential surface of the semiconductor structure and the current dispersing layer, characterized in that a surface of the current dispersing layer is exposed.

[0139] Since the details regarding the semiconductor structure, current distribution layer, and insulating layer are the same as those described above, they will be omitted.

[0140] In this way, the present invention utilizes at least one of SiO2 and Si3N4, which serve as a mask function, used when manufacturing a semiconductor structure, as an etching stop layer in a method for manufacturing an LED device, and utilizes the etching speed of the etching stop layer and the insulating layer when dry etching is performed after wet etching, thereby manufacturing the LED device so that the current distribution layer and the insulating layer have the same plane.

[0141] The manufactured LED element may be a nano LED element or a micro LED element with a side size of 100㎛ or less, and may be in the form of a rod, a bar, or a nanowire.

[0142] Preferably, the manufactured LED element is in the form of a rod including GaN of 3.0 to 3.5 μm and a current spreading layer of 0.2 to 0.4 μm, and the sides except the top are surrounded by an insulating layer. The LED element can be separated from the wafer using ultrasonic waves and then aligned for use.

[0143] After aligning the LED elements, a FAB (Fabrication Facility) process can be performed as a production process to display the arranged LED elements for light emission. The FAB process is a post-process for light emission, and refers to a layer formation process for applying a current dispersing layer such as ITO to inject current.

[0144] After going through this FAB process, current is finally injected into the LED element. If the upper surface is uniformly exposed with a current dispersing layer during this process, it can function as a single light-emitting element.

[0145] If the current dissipation layer is uneven, there is a risk that it will act as a resistor. In addition, if the upper surface of the p-type semiconductor layer is uneven, the upper surface of the p-type semiconductor layer may not be exposed during the post-process (fab process) when the ITO layer is deposited and current is injected into the LED device, so no current is injected. Or, if it is overexposed, the MQW layer at the bottom of the p-type semiconductor layer may be exposed, which may act as a leakage.

[0146] Therefore, it is desirable to form a uniform surface so that the current dispersing layer on the upper side of the LED element and the insulating layer on the side of the LED element have upper surfaces on the same plane, and to uniformly expose the upper surface of the p-type semiconductor layer.

[0147] In addition, the manufactured LED element has the advantage of generating less heat and consuming less power due to its small size, and thus can be applied to mobile display devices, ultra-high definition large display devices, and flexible display devices.

[0148] Here, a specific example of a method for manufacturing an LED element is as follows.

[0149] Figures 4 to 7 were observed using FE-SEM (HITACHI S-4700).

[0150] Fig. 4 is a SEM photograph showing the upper part of the LED element after step S140 of the present invention, in which the upper surface of the etching stop layer (SiO2) is exposed, and the heights of the upper surfaces of the etching stop layer, the insulating layer (Al2O3), and the photoresist are the same, and show the same plane.

[0151] Fig. 5 is an SEM photograph showing the upper part of the LED element after step S140 of the present invention.

[0152] In Fig. 5, the top layer in the form of a ball is a current dispersing layer (ITO), its outer peripheral surface is an insulating layer (Al2O3) that serves as a side passivation, and the round shape at the bottom is a photoresist layer remaining after dry etching.

[0153] Figure 6 is a photograph of the top of an LED device that was wet etched after dry etching.

[0154] From Fig. 6, it can be confirmed that the insulating layer (Al2O3) and the etching stop layer (SiO2) of the LED element are etched unevenly.

[0155] Figure 7 is a photograph of the top of an LED element that has been subjected to only dry etching.

[0156] As in examples 1 and 2 from Fig. 7, if the photoresist is etched first, the surface may be uneven, and if the etching degree is severe, a burning phenomenon of the photoresist may be observed.

[0157]

[0158] Although the present invention has been described with reference to the drawings exemplified above, it is to be understood that the present invention is not limited to the embodiments and drawings disclosed herein, and that various modifications may be made by those skilled in the art within the scope of the technical idea of ​​the present invention. Furthermore, even if the operational effects according to the configuration of the present invention have not been explicitly described while describing the embodiments of the present invention, it is natural that the effects predictable by the corresponding configuration should also be acknowledged.

Claims

1. (a) A step of preparing a semiconductor structure in which a current dispersing layer and an etching stop layer disposed on the current dispersing layer are deposited; (b) a step of depositing an insulating layer on the outer surface of a semiconductor structure on which the etching stop layer is deposited; (c) a step of coating the semiconductor structure on which the insulating layer is deposited with a photoresist; (d) a step of wet etching the coated semiconductor structure to etch the insulating layer so that the upper surface of the etch stop layer is exposed; (e) a step of dry etching the wet-etched semiconductor structure to etch the etch stop layer and the insulating layer so that the upper surface of the current dispersing layer is exposed; and (f) a step of removing a photoresist coated on the etched semiconductor structure; a method for manufacturing an LED device, comprising:

2. In paragraph 1, A method for manufacturing an LED element, wherein in step (e) above, the current dispersing layer and the insulating layer have upper surfaces on the same plane.

3. In paragraph 1, A method for manufacturing an LED device, wherein the etching stop layer comprises at least one of SiO2 and Si3N4.

4. In paragraph 1, A method for manufacturing an LED device, wherein the semiconductor structure includes an n-type semiconductor layer, an active layer disposed on the n-type semiconductor layer, and a p-type semiconductor layer disposed on the active layer.

5. In paragraph 1, A method for manufacturing an LED element, wherein in the step (a) above, the thickness of the etching stop layer is 0.5 to 2 μm.

6. In paragraph 1, A method for manufacturing an LED element in which, in the step (b) above, the thickness of the insulating layer is 30 to 90 nm.

7. In paragraph 1, A method for manufacturing an LED device, wherein the etching speed of the etching stop layer is faster than the etching speed of the insulating layer.

8. In paragraph 1, A method for manufacturing an LED device, further comprising: in step (c) above, a step of descumming a photoresist so as to expose an insulating layer of a semiconductor structure.

9. In paragraph 1, A method for manufacturing an LED device using an aqueous solution containing hydrogen fluoride (HF) and ammonium fluoride (NH4F) in the step (d) above.

10. In paragraph 1, In the step (e) above, a method for manufacturing an LED device using reactive ion etching (RIE).

11. A semiconductor structure including an n-type semiconductor layer, an active layer disposed on the n-type semiconductor layer, and a p-type semiconductor layer disposed on the active layer; A current dispersing layer disposed on the semiconductor structure; and An insulating layer surrounding the outer surface of the semiconductor structure and the current dissipation layer; An LED element in which the surface of the current dissipation layer is exposed.

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