Shift register, gate driving circuit, and display panel

Abstract

A shift register, a gate driving circuit, and a display panel, which belong to the technical field of display. The shift register comprises a second control module, which comprises a fourth sub-circuit, a fifth sub-circuit and a third capacitor, wherein a first end of the third capacitor and a control end of the fourth sub-circuit are electrically connected to a second control node; a second end of the fifth sub-circuit, a second end of the fourth sub-circuit and a second end of the third capacitor are electrically connected to a seventh control node; a first end of the fourth sub-circuit is electrically connected to a first auxiliary clock signal end; a control end of the fifth sub-circuit is electrically connected to a first control node, and a first end of the fifth sub-circuit is electrically connected to a first power-supply voltage end; and the gating level of a first auxiliary clock signal is later than the gating level of a first clock signal for a first preset time, which is shorter than a half of a clock period of the first clock signal. The shift register can increase the output speed of scanning signals.

Description

Shift register, gate drive circuit and display panel Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, and a display panel. Background Art

[0002] Display panels typically use gate drive circuits to generate scan signals. If the rising or falling edge of the scan signal is long, the pixel lighting time or pixel charging time may vary, resulting in the risk of uneven display brightness.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a shift register, a gate drive circuit and a display panel to increase the output speed of the scanning signal.

[0006] According to a first aspect of the present disclosure, a shift register is provided, comprising a first output sub-circuit, a second output sub-circuit, a first input sub-circuit and a second control module.

[0007] The control terminal of the first output sub-circuit is electrically connected to the first control node, the first terminal of the first output sub-circuit is electrically connected to the first power supply voltage terminal, and the first output sub-circuit is configured to output the first power supply voltage to the output terminal in response to a gating level on the first control node;

[0008] The control terminal of the second output sub-circuit is electrically connected to the second control node, the first terminal of the second output sub-circuit is electrically connected to the second power supply voltage terminal, and the second output sub-circuit is configured to output the second power supply voltage to the output terminal in response to a gating level on the second control node;

[0009] A first terminal of the first input sub-circuit is electrically connected to an input signal terminal, a control terminal of the first input sub-circuit is electrically connected to a first clock signal terminal, and a second terminal of the first input sub-circuit is electrically connected to the second control node. The first input sub-circuit is configured to cause a voltage on the input signal terminal to be applied to the second control node in response to a gating level of the first clock signal.

[0010] The second control module includes a fourth subcircuit, a fifth subcircuit, and a third capacitor, wherein a first end of the third capacitor and a control end of the fourth subcircuit are electrically connected to the second control node; a second end of the fifth subcircuit, a second end of the fourth subcircuit, and a second end of the third capacitor are electrically connected to the seventh control node; a first end of the fourth subcircuit is electrically connected to the first auxiliary clock signal terminal, and the control end of the fifth subcircuit is electrically connected to the first control node; and a first end of the fifth subcircuit is electrically connected to the first power supply voltage terminal.

[0011] The fourth sub-circuit is configured to, in response to the gating level on the second control node, load the voltage on the first auxiliary clock signal terminal to the seventh control node;

[0012] The fifth sub-circuit is configured to, in response to a gating level on the first control node, load the voltage on the first power supply voltage terminal to the seventh control node;

[0013] The gating level of the first auxiliary clock signal is later than the gating level of the first clock signal by a first preset time, and the first preset time is less than half of a clock period of the first clock signal.

[0014] According to one embodiment of the present disclosure, the fourth sub-circuit includes a fourth transistor, a first terminal of the fourth transistor is electrically connected to the first auxiliary clock signal terminal, a control terminal of the fourth transistor is electrically connected to the first terminal of the third capacitor, and a second terminal of the fourth transistor is electrically connected to the seventh control node;

[0015] The fifth sub-circuit includes a fifth transistor, a first terminal of the fifth transistor is electrically connected to the first power supply voltage terminal, a control terminal of the fifth transistor is electrically connected to the first control node, and a second terminal of the fifth transistor is electrically connected to the seventh control node.

[0016] According to an embodiment of the present disclosure, the first input sub-circuit includes a first transistor, a first terminal of the first transistor is electrically connected to the input signal terminal, a control terminal of the first transistor is electrically connected to the first clock signal terminal, and a second terminal of the first transistor is electrically connected to the second control node;

[0017] The first output sub-circuit includes a ninth transistor and a second capacitor; a first terminal of the ninth transistor and a first terminal of the second capacitor are electrically connected to the first power supply voltage terminal, a second terminal of the ninth transistor is electrically connected to the output terminal, and a control terminal of the ninth transistor and a second terminal of the second capacitor are electrically connected to the first control node;

[0018] The second output sub-circuit includes a tenth transistor, a first terminal of the tenth transistor is electrically connected to the second power supply voltage terminal, a control terminal of the tenth transistor is electrically connected to the second control node, and a second terminal of the tenth transistor is electrically connected to the output terminal.

[0019] According to an embodiment of the present disclosure, the shift register further includes a first control module, the first control module including a second sub-circuit, a third sub-circuit, a sixth sub-circuit, a seventh sub-circuit and a first capacitor;

[0020] The control terminal of the second sub-circuit is electrically connected to the second terminal of the first input sub-circuit, the first terminal of the second sub-circuit is electrically connected to the first clock signal terminal, and the second terminal of the second sub-circuit and the second terminal of the third sub-circuit are electrically connected to the third control node; the second sub-circuit is configured to apply the voltage on the first clock signal terminal to the third control node in response to the gating level on the second control node;

[0021] The first terminal of the third sub-circuit is electrically connected to the second power supply voltage terminal, and the control terminal of the third sub-circuit is electrically connected to the first clock signal terminal; the third sub-circuit is configured to apply the second power supply voltage to the third control node in response to the gating level of the first clock signal;

[0022] The first terminal of the sixth sub-circuit is electrically connected to the second clock signal terminal, the control terminal of the sixth sub-circuit and the second terminal of the first capacitor are electrically connected to the fifth control node, and the second terminal of the sixth sub-circuit, the first terminal of the first capacitor, and the first terminal of the seventh transistor are electrically connected to the sixth control node. The sixth sub-circuit is configured to, in response to a gating level on the fifth control node, cause the voltage on the second clock signal terminal to be applied to the sixth control node. The fifth control node is electrically connected to the third control node.

[0023] The control end of the seventh sub-circuit is electrically connected to the sixth control node, the first end of the seventh sub-circuit is electrically connected to the first control node, the control end of the seventh sub-circuit is electrically connected to the second clock signal end, and the seventh sub-circuit is configured to be electrically turned on in response to the selection level of the second clock signal.

[0024] According to one embodiment of the present disclosure, the second sub-circuit includes a second transistor, a first terminal of the second transistor is electrically connected to the first clock signal terminal, a control terminal of the second transistor is electrically connected to the second control node, and a second terminal of the second transistor is electrically connected to the third control node;

[0025] The third sub-circuit includes a third transistor, a first terminal of the third transistor is electrically connected to the second power supply voltage terminal, a control terminal of the third transistor is electrically connected to the first clock signal terminal, and a second terminal of the third transistor is electrically connected to the third control node;

[0026] The sixth sub-circuit includes a sixth transistor, a first terminal of the sixth transistor is electrically connected to the second clock signal terminal, a control terminal of the sixth transistor is electrically connected to the fifth control node, and a second terminal of the sixth transistor is electrically connected to the sixth control node;

[0027] The seventh sub-circuit includes a seventh transistor, a first terminal of the seventh transistor is electrically connected to the sixth control node, a second terminal of the seventh sub-circuit is electrically connected to the second clock signal terminal, and a first terminal of the seventh sub-circuit is electrically connected to the first control node.

[0028] According to one embodiment of the present disclosure, the first control module also includes an eleventh transistor, the first end of the eleventh transistor is electrically connected to the third control node, the second end of the eleventh transistor is electrically connected to the fifth control node, and the control end of the eleventh transistor is electrically connected to the second power supply voltage end to make the eleventh transistor conductive.

[0029] According to an embodiment of the present disclosure, the clock period of the second clock signal is the same as the clock period of the first clock signal;

[0030] The gating level of the second clock signal has the same duration as the gating level of the first clock signal;

[0031] The gating level of the second clock signal is later than the gating level of the first clock signal by a second preset time, and the second preset time is half of a clock cycle of the first clock signal.

[0032] According to an embodiment of the present disclosure, the duration of the gating level of the first clock signal is less than half of the clock period of the first clock signal.

[0033] According to an embodiment of the present disclosure, the shift register further includes an eighth sub-circuit, wherein a control terminal of the eighth sub-circuit is electrically connected to the second control node, a first terminal of the eighth sub-circuit is electrically connected to the first power supply voltage terminal, and a second terminal of the eighth sub-circuit is electrically connected to the first control node;

[0034] The eighth sub-circuit is configured to apply the first power supply voltage to the first control node in response to a gating level on the second control node.

[0035] According to one embodiment of the present disclosure, the eighth sub-circuit includes an eighth transistor, the control end of the eighth transistor is electrically connected to the second control node, the first end of the eighth transistor is electrically connected to the first power supply voltage end, and the second end of the eighth transistor is electrically connected to the first control node.

[0036] According to an embodiment of the present disclosure, the shift register further includes an eighth sub-circuit, wherein a control terminal of the eighth sub-circuit is electrically connected to the input signal terminal, a first terminal of the eighth sub-circuit is electrically connected to the first power supply voltage terminal, and a second terminal of the eighth sub-circuit is electrically connected to the first control node;

[0037] The eighth sub-circuit is configured to apply the first power supply voltage to the first control node in response to a strobe level on the input signal terminal.

[0038] According to one embodiment of the present disclosure, the eighth sub-circuit includes an eighth transistor, the control end of the eighth transistor is connected to the input signal end, the first end of the eighth transistor is electrically connected to the first power supply voltage end, and the second end of the eighth transistor is electrically connected to the first control node.

[0039] According to one embodiment of the present disclosure, the shift register also includes a twelfth transistor, the first end of the twelfth transistor and the second end of the first input sub-circuit are electrically connected to the fourth control node, and the second end of the twelfth transistor is electrically connected to the second control node; the control end of the twelfth transistor is electrically connected to the second power supply voltage end to make the twelfth transistor conductive.

[0040] According to one embodiment of the present disclosure, the shift register also includes a thirteenth transistor, a first end of the thirteenth transistor is electrically connected to the first power supply voltage end, a second end of the thirteenth transistor is electrically connected to the second control node, and a control end of the thirteenth transistor is electrically connected to the control signal; the thirteenth transistor is configured to load the first power supply voltage to the second control node in response to the control voltage.

[0041] According to an embodiment of the present disclosure, each transistor of the shift register is a P-type transistor;

[0042] The first power supply voltage is a high-level power supply voltage; the second power supply voltage is a low-level power supply voltage.

[0043] According to an embodiment of the present disclosure, the clock period of the first auxiliary clock signal is the same as the clock period of the first clock signal, and the time length of the gating level of the first auxiliary clock signal is the same as the time length of the gating level of the first clock signal.

[0044] According to an embodiment of the present disclosure, the sum of the first preset time and the duration of the gating level of the first clock signal is less than half of a clock period of the first clock signal.

[0045] According to an embodiment of the present disclosure, the first preset time is no greater than 2 microseconds.

[0046] According to an embodiment of the present disclosure, the shift register further includes a second input sub-circuit, a fifteenth transistor, and a sixteenth sub-circuit;

[0047] a first terminal of the second input sub-circuit electrically connected to the input signal terminal, a control terminal of the second input sub-circuit electrically connected to the first clock signal terminal, a second terminal of the second input sub-circuit electrically connected to the first terminal of the fifteenth transistor; a control terminal of the fifteenth transistor electrically connected to a second power supply voltage terminal to turn on the fifteenth transistor; a second terminal of the fifteenth transistor, a control terminal of the fourth sub-circuit, a control terminal of the sixteenth sub-circuit, and a first terminal of the sixteenth sub-circuit electrically connected, and a second terminal of the sixteenth sub-circuit electrically connected to the second control node;

[0048] The second input sub-circuit is configured to load the voltage on the input signal terminal to the control terminal of the sixteenth sub-circuit in response to the gating level of the first clock signal.

[0049] According to one embodiment of the present disclosure, the second input sub-circuit includes a fourteenth transistor; a first terminal of the fourteenth transistor is electrically connected to the input signal terminal, a control terminal of the fourteenth transistor is electrically connected to the first clock signal terminal, and a second terminal of the fourteenth transistor is electrically connected to the first terminal of the fifteenth transistor;

[0050] The sixteenth sub-circuit includes a sixteenth transistor, a first terminal of the sixteenth transistor and a control terminal of the sixteenth transistor are electrically connected to the second terminal of the fifteenth transistor, and the second terminal of the sixteenth transistor is electrically connected to the second control node.

[0051] According to an embodiment of the present disclosure, a starting time of the gating level of the first clock signal is the same as a starting time of the gating level of the first auxiliary clock signal.

[0052] According to an embodiment of the present disclosure, the shift register is not provided with the first auxiliary clock signal terminal; the first terminal of the fourth sub-circuit is electrically connected to the first clock signal terminal.

[0053] According to a second aspect of the present disclosure, a gate drive circuit is provided, comprising a plurality of the above-mentioned shift registers cascaded in sequence; the output end of the shift register of the previous stage is electrically connected to the input signal end of the shift register of the next stage.

[0054] According to a third aspect of the present disclosure, there is provided a display panel, comprising a gate drive circuit and a first clock trace, a second clock trace, a first auxiliary clock trace, and a second auxiliary clock trace for driving the gate drive circuit;

[0055] The gate drive circuit includes a plurality of the above-mentioned shift registers cascaded in sequence; the output end of the shift register of the previous stage is electrically connected to the input signal end of the shift register of the next stage;

[0056] The first clock trace is electrically connected to the first clock signal terminal of the odd-numbered shift register, and is electrically connected to the second clock signal terminal of the even-numbered shift register;

[0057] The second clock trace is electrically connected to the second clock signal terminal of the odd-numbered shift register, and is electrically connected to the first clock signal terminal of the even-numbered shift register;

[0058] The first auxiliary clock trace is electrically connected to the first auxiliary clock signal terminal of the odd-numbered shift register;

[0059] The second auxiliary clock trace is electrically connected to the first auxiliary clock signal terminal of the even-numbered shift register.

[0060] According to a fourth aspect of the present disclosure, there is provided a display panel, comprising a gate driving circuit and a first clock trace and a second clock trace for driving the gate driving circuit;

[0061] The gate drive circuit includes a plurality of the above-mentioned shift registers cascaded in sequence; the output end of the shift register of the previous stage is electrically connected to the input signal end of the shift register of the next stage;

[0062] The first clock trace is electrically connected to the first clock signal terminal of the odd-numbered shift register, and is electrically connected to the second clock signal terminal of the even-numbered shift register;

[0063] The second clock trace is electrically connected to the second clock signal terminal of the odd-numbered shift register, and is electrically connected to the first clock signal terminal of the even-numbered shift register.

[0064] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0066] FIG1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0067] FIG2 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0068] FIG3 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0069] FIG4 is a schematic structural diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0070] FIG5 is a schematic diagram of the principle of a shift register in one embodiment of the present disclosure.

[0071] FIG6 is a schematic structural diagram of a shift register in one embodiment of the present disclosure.

[0072] FIG7 is a schematic structural diagram of a shift register in one embodiment of the present disclosure.

[0073] FIG8 is a schematic structural diagram of a gate drive circuit in one embodiment of the present disclosure.

[0074] FIG9 is a driving timing diagram of a gate driving circuit in one embodiment of the present disclosure.

[0075] FIG10 is a schematic structural diagram of a shift register in one embodiment of the present disclosure.

[0076] FIG11 is a schematic structural diagram of a shift register in one embodiment of the present disclosure.

[0077] FIG12 is a schematic structural diagram of a shift register in one embodiment of the present disclosure.

[0078] FIG13 is a schematic structural diagram of a gate drive circuit in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0079] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0080] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0081] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0082] In the embodiments of the present disclosure, a transistor refers to an element comprising at least three terminals: a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the source, the channel region, and the drain. The channel region refers to the region through which current mainly flows. In the embodiments of the present disclosure, in the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "source" and the "drain" can be interchanged. In the embodiments of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor, and the gate is referred to as the control terminal of the transistor.

[0083] An embodiment of the present disclosure provides a display panel PNL. Referring to FIG. 1 , the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. In the display area AA, the display panel PNL is provided with an array of display units UU, each of which includes a sub-pixel PIX and a pixel driving circuit PDC for driving the sub-pixel PIX. The display panel PNL does not have a display unit in the peripheral area BB, or the display unit provided is not used to display an image. Referring to FIG. 1 , the display panel PNL is provided with a plurality of scan lines GL extending along a row direction DH in the display area AA, each scan line GL being provided in a one-to-one correspondence with each display unit row. The pixel driving circuit PDC of each display unit in the display unit row is electrically connected to the corresponding scan line GL. The display panel PNL is also provided with a plurality of data lines DL extending along a column direction DV in the display area AA, each data line DL being provided in a one-to-one correspondence with each display unit column. The pixel driving circuit PDC of each display unit in the display unit column is electrically connected to the corresponding data line DL. In this way, the pixel driving circuit PDC of each display unit is connected to the scan line GL and the data line DL. The scan line GL is loaded with a scan signal to control the state of the pixel driving circuit PDC. It will be understood that in the example of Figure 1, only one scan line GL corresponding to the display unit row is illustrated; as needed, the display panel PNL can be provided with a plurality of different scan lines GL corresponding to the display unit row. The data line DL can be loaded with a data voltage Vdata for driving the pixel driving circuit PDC. The pixel driving circuit PDC can drive the sub-pixel PIX according to the written data voltage Vdata, thereby controlling the brightness of the sub-pixel PIX. It will be understood that the pixel driving circuit PDC can also control the brightness of the sub-pixel PIX according to other signals.

[0084] Optionally, the pixel drive circuit PDC includes at least a data write transistor, a drive transistor and a storage capacitor, and the gate of the drive transistor can be electrically connected to an electrode plate of the storage capacitor. The source of the data write transistor can be electrically connected to the data line DL, and the gate of the data write transistor can be electrically connected to a write control line for loading a data write signal (a scan signal). The pixel drive circuit PDC is configured so that when the gating level of the data write signal is loaded on the write control line, the data write transistor is turned on, thereby causing the drive voltage on the data line DL to be written to the gate of the drive transistor and the storage capacitor. When the data write transistor is turned off, the drive voltage can be maintained by the storage capacitor. The drive transistor can output a drive current to drive the sub-pixel PIX to emit light under the control of the voltage on its gate. It is understandable that the pixel drive circuit PDC of the embodiment of the present disclosure may also include other transistors or capacitors so that the pixel drive circuit PDC has better driving performance. For example, the pixel drive circuit PDC can be a pixel drive circuit of 7T1C (7 thin film transistors and a storage capacitor), 8T1C (8 thin film transistors and a storage capacitor) or other architectures.

[0085] Optionally, the sub-pixel PIX can be a current-driven self-luminous element, for example, it can be any one of the light-emitting elements such as OLED, PLED, QLED, Micro LED, MiNi LED, etc. In this embodiment, the sub-pixel PIX can include sub-pixels PIX of multiple different colors, for example, a red sub-pixel RPIX for emitting red light, a blue sub-pixel BPIX for emitting green light, and a green sub-pixel GPIX for emitting green light. It is understood that in other embodiments of the present disclosure, the sub-pixels PIX in the display area AA may also have sub-pixels PIX of other colors (for example, a yellow sub-pixel for emitting yellow light, a cyan sub-pixel for emitting cyan light, a white sub-pixel for emitting white light, etc.).

[0086] In one embodiment of the present disclosure, referring to FIG2 , the display panel PNL may include a base substrate SBT, a drive layer DRL, and a pixel layer PIXL, which are stacked in sequence. The pixel layer PIXL includes subpixels PIX, and the drive layer DRL includes a pixel drive circuit PDC for driving the subpixels PIX. Each subpixel PIX can emit light to display an image under the drive of the pixel drive circuit PDC. Furthermore, the display panel PNL also includes a thin film encapsulation layer TFE located on the side of the pixel layer PIXL away from the drive backplane DBP. The thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.

[0087] Optionally, the substrate SBT can be a substrate of an inorganic material, or a substrate of an organic material; of course, it can also be a composite substrate formed by stacking a substrate of an inorganic material and a substrate of an organic material. For example, in some embodiments of the present disclosure, the material of the substrate SBT can be a glass material such as soda-lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can include polyimide.

[0088] Optionally, in the drive layer DRL, any pixel drive circuit PDC may include a thin film transistor TFT and a storage capacitor. Furthermore, the thin film transistor TFT may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; and the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0089] It is understandable that, among the transistors in the pixel driving circuit, the types of any two transistors may be the same or different. For example, in some embodiments, in a pixel driving circuit, some transistors may be N-type transistors and some transistors may be P-type transistors. Again for example, in other embodiments, in a pixel driving circuit, the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistors are low-temperature polysilicon transistors. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors, and some thin film transistors are metal oxide transistors.

[0090] Optionally, the drive layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, a planarization layer PLN, etc. stacked between the substrate SBT and the pixel layer PIXL. Each thin film transistor and storage capacitor may be formed by film layers such as the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, and the source / drain metal layer SD. The positional relationship of each film layer may be determined according to the film layer structure of the thin film transistor. Furthermore, the semiconductor layer SCL may be used to form the channel region of the transistor, and may also be used to form partial wiring or conductive structures by conductorization when necessary. The gate layer may be used to form one or more scan wirings, such as one or more gate layer wirings such as a write control wiring, a reset control wiring, and a light emitting control wiring, and may also be used to form the gate of a transistor, and may also be used to form part or all of the electrode plates of a storage capacitor. The source / drain metal layer may be used to form source / drain metal layer wirings such as a data line DL and a drive power supply voltage wiring, and may also be used to form part of the electrode plates of a storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL may further include other film layers as needed, for example, it may further include a light shielding layer located between the semiconductor layer SCL and the substrate SBT. As needed, any of the above-mentioned film layers such as the semiconductor layer SCL, the gate layer GT, the source / drain metal layer SD, etc. may also be multi-layered. For example, the driving layer DRL may include two different semiconductor layers SCL, or two or three source / drain metal layers SD, or two or three gate layers GT. Accordingly, the insulating film layers in the driving layer DRL (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) may be adaptively increased or decreased, or new insulating film layers may be added as needed.

[0091] Optionally, the driving layer DRL may further include a passivation layer. The passivation layer may be provided on a surface of the source / drain metal layer SD away from the substrate SBT, so as to protect the source / drain metal layer SD.

[0092] As an example, referring to FIG2 , the driving layer DRL may include an inorganic buffer layer BUF, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, and a planarization layer PLN stacked in sequence, and the thin film transistor formed in this way is a top-gate thin film transistor.

[0093] In one embodiment of the present disclosure, referring to FIG2 , the sub-pixel PIX in the pixel layer PIXL is a thin-film light-emitting element, which may include two stacked electrodes and a light-emitting functional layer sandwiched between the two electrodes. For example, referring to FIG2 , the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EFL, and a common electrode layer COML stacked in sequence. The pixel electrode layer PEL includes a plurality of pixel electrodes PE in the display area of ​​the display panel; the portion of the light-emitting functional layer EFL connected to the pixel electrode PE serves as the light-emitting functional unit of the sub-pixel PIX, and the common electrode layer COML serves as a common electrode electrically connected to the light-emitting functional units of each sub-pixel PIX.

[0094] Furthermore, the pixel layer PIXL may also include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting function layer EFL. The pixel definition layer PDL has a plurality of through pixel openings arranged in a one-to-one correspondence with the plurality of pixel electrodes PE, and any pixel opening exposes at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode PE and exposes at least a portion of the internal area of ​​the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode PE (the area directly connected to the light-emitting function layer EFL), thereby defining the light-emitting area and light-emitting area of ​​the sub-pixel PIX. The light-emitting function layer EFL at least covers the pixel electrode PE exposed by the pixel definition layer PDL. The common electrode layer COML can cover the light-emitting function layer EFL in the display area. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting function layer EFL, so that the light-emitting function layer EFL emits light. The portion of the light-emitting function layer EFL located between the pixel electrode PE and the common electrode layer COML can serve as a light-emitting function unit. The pixel electrode PE, the common electrode layer COML, and the light emitting functional unit form a light emitting element LD as a sub-pixel, wherein one of the pixel electrode PE and the common electrode layer COML serves as an anode of the sub-pixel PIX, and the other serves as a cathode of the sub-pixel PIX.

[0095] In one example, the pixel electrode PE serves as an anode of the sub-pixel PIX, and the common electrode layer COML serves as a cathode of the sub-pixel PIX.

[0096] It is understandable that the types of light-emitting elements are different, and the materials and film layers of the light-emitting functional layer EFL are different.

[0097] For example, when the light-emitting element is an OLED, the light-emitting functional layer (EFL) may include an organic light-emitting layer (EML), and may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). Furthermore, the organic light-emitting layer (EML) may include a light-emitting layer host material and a light-emitting layer guest material. The light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, and in particular, may be a thermally activated delayed fluorescent material. It is understood that when the OLED adopts a stacked structure, a charge generation layer (CGL) may also be provided in the light-emitting functional layer (EFL).

[0098] For another example, when the light-emitting element is a QLED, the light-emitting functional layer (EFL) may include a quantum dot layer (QDL), and may include one or more of a hole injection layer (HIL), an electron transport layer (ETL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). Furthermore, the quantum dot layer (QDL) may include quantum dot particles, which may be interconnected via surface modification groups. It is understood that when the QLED adopts a stacked structure, a charge generation layer (CGL) may also be provided in the light-emitting functional layer (EFL).

[0099] 3 , in the display panel PNL, a gate drive circuit GOA is provided in the peripheral area BB to provide scan signals to the pixel drive circuit PDC. Depending on the needs of the pixel drive circuit PDC, multiple gate drive circuits GOA may be provided in the peripheral area BB to provide different scan signals. Alternatively, some scan signals may share a single gate drive circuit GOA.

[0100] Optionally, according to the needs of the pixel driving circuit PDC, the scanning signal may include but is not limited to one or more of the following signals: a write control signal for controlling the writing of the data voltage into the pixel driving circuit PDC, a light emitting control signal for controlling the output driving current of the pixel driving circuit PDC, a reset control signal for controlling the resetting of the pixel driving circuit PDC, etc.

[0101] Taking the pixel drive circuit PDC shown in FIG4 as an example, the pixel drive circuit PDC includes first to ninth transistors T1X to T9X, and a storage capacitor CSTX. The first terminal of the fifth transistor T5 is used to apply a driving power supply voltage VDD, and the control terminal of the fifth transistor T5 is used to apply a light emission control signal EM, which serves as a scanning signal. The second terminal of the fifth transistor T5, the second terminal of the ninth transistor T9, the second terminal of the fourth transistor T4, and the first terminal of the third transistor T3 are electrically connected to the second node N2. The second terminal of the third transistor T3, the first terminal of the second transistor T2, and the first terminal of the sixth transistor T6 are electrically connected to the third node N3. The control terminal of the sixth transistor T6 is used to apply the light emission control signal EM, and the second terminal of the sixth transistor T6 and the second terminal of the seventh transistor T7 are electrically connected to the subpixel. The first terminal of the seventh transistor T7 is used to apply a second initialization voltage ViNit2, and the control terminal of the seventh transistor T7 is used to apply a reset control signal RST, which serves as a scanning signal. The first terminal of the ninth transistor T9 is used to apply a reference voltage Vref, and the control terminal of the ninth transistor T9 is used to apply the reset control signal RST. The first end of the fourth transistor T4 is used to apply the data voltage Vdata, and the control end of the fourth transistor T4 is used to apply the second scan signal GSP, which is a scan signal. The second end of the storage capacitor CSTX is used to apply the driving power supply voltage VDD. The first end of the storage capacitor CSTX, the control end of the third transistor T3, and the second end of the eighth transistor T8 are electrically connected to the first node N1. The second end of the second transistor T2, the first end of the eighth transistor T8, and the second end of the first transistor T1 are electrically connected to each other. The control end of the second transistor T2 is used to apply the second scan signal GSP; the control end of the eighth transistor T8 is used to apply the first scan signal GSN, which is a scan signal; the control end of the first transistor T1 is used to apply the reset control signal RST; and the first end of the first transistor T1 is used to apply the first initialization voltage ViNit1.

[0102] In this example, the pixel driving circuit PDC can first be supplied with the gate level of the reset control signal RST and the gate level of the first scan signal GSN. This causes the ninth transistor T9X to turn on and reset the second node N2, the seventh transistor T7X to turn on and reset the pixel electrode of the subpixel, the first transistor T1X and the eighth transistor T8X to turn on and reset the first node N1, and thus the third transistor T3X to be in a conductive state. Then, the pixel driving circuit PDC can be supplied with the gate level of the first scan signal GSN and the gate level of the second scan signal GSP. This causes the fourth transistor T4X to turn on and load the data voltage Vdata to the second node N2. The second transistor T2X and the eighth transistor T8X are turned on, causing the second node N2 to charge the first node N1 through the third transistor T3X, the second transistor T2X, and the eighth transistor T8X until the third transistor T3X is turned off. This allows the data voltage Vdata and the threshold voltage of the third transistor T3X to be written to the first node N1. Then, the pixel driving circuit PDC may be provided with a strobe level of the light emitting control signal EM, thereby turning on the fifth transistor T5X and the sixth transistor T6X, and the third transistor T3X outputs a driving current to the sub-pixel under the control of the first node N1, thereby controlling the light emitting brightness of the sub-pixel.

[0103] In this example, the pixel driving circuit PDC requires four different scanning signals, namely, a second scanning signal GSP, a first scanning signal GSN, a reset control signal RST, and an emission control signal EM. It is understood that different pixel driving circuits PDC may require different numbers and types of scanning signals.

[0104] In the example of FIG. 4 , the eighth transistor T8X may be a metal oxide transistor to reduce leakage current at the first node N1 and improve the voltage holding capability of the first node N1, thereby enabling variable frequency drive and low refresh rate drive of the display panel PNL, thereby reducing power consumption of the display panel PNL. Accordingly, the gate level of the first scan signal GSN is high. The remaining transistors may be P-type transistors, and the gate levels of the second scan signal GSP, the reset control signal RST, and the emission control signal EM may be low.

[0105] In this example, the duration of the strobe level of some scanning signals may exceed the time it takes to drive a row of sub-pixels. For example, the duration of the strobe level of scanning signals such as the reset control signal RST, the emission control signal EM, and the first scanning signal GSN may exceed the time it takes to drive a row of sub-pixels.

[0106] In the embodiment of the present disclosure, the scan signal includes at least two different levels. One of the levels can turn on the driven thin film transistor TFT, and this level is the gating level of the scan signal; the other level can turn off the driven thin film transistor TFT, and this level is the cut-off level of the scan signal. For example, in the above example, the eighth transistor T8 is a metal oxide thin film transistor, the gating level of the first scan signal GSN is a high level, and the cut-off level of the first scan signal GSN is a low level. For another example, in the above example, the fifth transistor T5 and the sixth transistor T6 are P-type low-temperature polysilicon thin film transistors, the gating level of the light-emitting control signal EM is a low level, and the cut-off level of the light-emitting control signal EM is a high level. It can be understood that when one scan signal is multiplexed into another scan signal, the gating levels of the two scan signals can be the same or different.

[0107] The speed at which a scanning signal transitions from a low level to a high level, or vice versa, can sometimes significantly impact the driving performance of the pixel driver circuit (PDC). For example, if the second scanning signal GSP transitions from the cutoff level to the enable level too slowly, the pixel driver circuit (PDC) may not have sufficient charging time, impacting display performance, such as uneven brightness. For another example, if the emission control signal EM transitions from the cutoff level to the enable level too slowly, the sub-pixels may experience uneven lighting times, impacting display performance, such as uneven brightness.

[0108] In an embodiment of the present disclosure, a gate drive circuit GOA is provided in the peripheral area BB of the display panel PNL to provide scan signals to the display area AA of the display panel PNL. The gate drive circuit GOA includes a cascaded shift register SR. Referring to Figure 5 , the shift register SR includes a first output sub-circuit Mout1, a second output sub-circuit Mout2, a first control node PU_out, a second control node PD_out, and an output terminal EO. The output terminal EO is electrically connected to a scan trace for applying scan signals to the display area AA. Under the control of the first control node PU_out, the first output sub-circuit Mout1 can apply a first power supply voltage V1 to the output terminal EO. Under the control of the second control node PD_out, the second output sub-circuit Mout2 can apply a second power supply voltage V2 to the output terminal EO. In this way, the voltage of the scan signal switches between the first power supply voltage V1 and the second power supply voltage V2. In related art, the level switching of the second control node PD_out is often not rapid enough, resulting in a relatively long time for the scan signal level to switch from the first power supply voltage V1 to the second power supply voltage V2, which in turn affects the display quality.

[0109] In the disclosed embodiments, the shift register SR can be optimized to increase the voltage switching speed of the second control node PD_out, thereby increasing the voltage switching speed of the output terminal EO. For example, when the transistors of the second output sub-circuit Mout2 are P-type transistors and the second power supply voltage V2 is at a low voltage level, the shift register SR can quickly pull down the second control node PD_out, thereby quickly and fully opening the second output sub-circuit Mout2, thereby enabling the output terminal EO to quickly switch from a high level to a low level.

[0110] 6 , the shift register SR of this embodiment includes a first output sub-circuit Mout1 , a second output sub-circuit Mout2 , a first input sub-circuit Min1 , and a second control module MPDC.

[0111] The control terminal of the first output sub-circuit Mout1 is electrically connected to the first control node PU_out, and the first terminal of the first output sub-circuit Mout1 is electrically connected to the first power supply voltage terminal. The first output sub-circuit Mout1 is configured to output the first power supply voltage V1 to the output terminal EO in response to a gating level on the first control node PU_out. In this embodiment, the gating level on the first control node PU_out refers to a level that can turn on the first output sub-circuit Mout1 to output the first power supply voltage V1.

[0112] The control end of the second output sub-circuit Mout2 is electrically connected to the second control node PD_out, the first end of the second output sub-circuit Mout2 is electrically connected to the second power supply voltage end, and the second output sub-circuit Mout2 is configured to output the second power supply voltage V2 to the output end EO in response to the selection level on the second control node PD_out; in this embodiment, the selection level on the second control node PD_out refers to the level that can cause the second output sub-circuit Mout2 to be turned on to output the second power supply voltage V2.

[0113] The first end of the first input sub-circuit Min1 is electrically connected to the input signal end, the control end of the first input sub-circuit Min1 is electrically connected to the first clock signal end, and the second end of the first input sub-circuit Min1 is electrically connected to the second control node PD_out. The first input sub-circuit Min1 is configured to load the voltage at the input signal end to the second control node PD_out in response to the gating level of the first clock signal CK. The gating level of the first clock signal CK refers to the level, between the high and low levels of the first clock signal CK, that can turn on the driven transistor or module. In this embodiment, the second end of the first input sub-circuit Min1 and the second control node PD_out can be directly connected or indirectly connected through other transistors, modules, or nodes.

[0114] The second control module MPDC includes a fourth sub-circuit M4, a fifth sub-circuit M5 and a third capacitor C3, the first end of the third capacitor C3 and the control end of the fourth sub-circuit M4 are electrically connected to the second control node PD_out; the second end of the fifth sub-circuit M5, the second end of the fourth sub-circuit M4, and the second end of the third capacitor C3 are electrically connected to the seventh control node PD_c; the first end of the fourth sub-circuit M4 is electrically connected to the first auxiliary clock signal end, and the control end of the fifth sub-circuit M5 is electrically connected to the first control node PU_out; the first end of the fifth sub-circuit M5 is electrically connected to the first power supply voltage end.

[0115] The fourth sub-circuit M4 is configured to, in response to the gating level on the second control node PD_out, load the voltage on the first auxiliary clock signal terminal to the seventh control node PD_c;

[0116] The fifth sub-circuit M5 is configured to, in response to a gating level on the first control node PU_out, load the voltage on the first power voltage terminal to the seventh control node PD_c.

[0117] 9 , the gating level of the first auxiliary clock signal CK2 is later than the gating level of the first clock signal CK by a first preset time, and the first preset time is less than half the clock period of the first clock signal CK. The gating level of the first auxiliary clock signal CK2 and the gating level of the first clock signal CK are the same level, for example, both are low.

[0118] In the shift register SR provided in this embodiment, when the first input sub-circuit Min1 applies a gating level to the second control node PD_out, the second output sub-circuit Mout2 is turned on, thereby gradually switching the voltage level of the output terminal EO to the second power supply voltage V2. At this point, the level of the first clock signal CK is the gating level of the first clock signal CK, the voltage of the seventh control node PD_c is the first power supply voltage V1, and the fourth sub-circuit M4 is turned on, electrically connecting the seventh control node PD_c to the first auxiliary clock signal terminal. The selection level of the first auxiliary clock signal CK2 is slightly later than the selection level of the first clock signal CK. Therefore, when the level of the first auxiliary clock signal CK2 is switched to the selection level of the first auxiliary clock signal CK2, the level of the seventh control node PD_c will be adjusted to the selection level of the first auxiliary clock signal CK2; this adjustment will affect the level of the second control node PD_out through capacitive coupling, thereby further increasing the conduction degree of the second output sub-circuit Mout2, accelerating the driving force of the second output sub-circuit Mout2, and making the level of the output terminal EO switch from the first power supply voltage V1 to the second power supply voltage V2 faster.

[0119] For example, in one embodiment, each transistor in the shift register SR is a P-type transistor, the first power supply voltage V1 is a high-level power supply voltage VGH, and the second power supply voltage V2 is a low-level power supply voltage VGL. The gating level of the first clock signal CK, the gating level of the first auxiliary clock signal CK2, and the gating level of the second control node PD_out are all low. Before the first input sub-circuit Min1 writes the low-level voltage (e.g., the low-level power supply voltage VGL) of the input signal terminal to the second control node PD_out in response to the gating level of the first clock signal CK, the second control node PD_out is high (e.g., the high-level power supply voltage VGH). At this time, the second output sub-circuit Mout2 and the fourth sub-circuit M4 are turned off. The first control node PU_out is low (e.g., the low-level power supply voltage VGL), which causes the first output sub-circuit Mout1 to conduct and write the high-level power supply voltage VGH to the output terminal EO. The fifth sub-circuit M5 is also turned on, causing the high-level power supply voltage VGH to be written to the seventh control node PD_c. When a low level (e.g., the low-level power supply voltage VGL) is applied to the input signal terminal and the first clock signal CK is at its gate level, the low level applied to the input signal terminal can be applied to the second control node PD_out, thereby turning on the second output sub-circuit Mout2 and the fourth sub-circuit M4. This causes the low-level power supply voltage VGL to be applied to the output terminal EO, and the voltage applied to the first auxiliary clock signal terminal to be applied to the seventh control node PD_c. At this moment, the level of the first control node PU_out switches to a high level, turning off the first output sub-circuit Mout1 and the fifth sub-circuit M5. At this point, although the second output sub-circuit Mout2 is writing the low-level power supply voltage VGL to the output terminal EO, the driving force of the second output sub-circuit Mout2 may be insufficient, causing the voltage at the output terminal EO to drop too slowly. Subsequently, the level of the first auxiliary clock signal CK2 at the first auxiliary clock signal terminal can switch to its gate level, causing the level of the seventh control node PD_c to drop from a high level to a low level. The coupling effect of the third capacitor C3 pulls down the voltage at the second control node PD_out, thereby increasing the conductivity of the second output sub-circuit Mout2 and strengthening the driving force of the second output sub-circuit Mout2, accelerating the voltage drop of the output terminal EO to the low-level power supply voltage VGL. This shortens the time it takes for the output terminal EO to switch from the high-level power supply voltage VGH to the low-level power supply voltage VGL, speeding up the switching speed of the scan signal output by the shift register SR and reducing problems such as insufficient charging time and inconsistent light emission time that can result from insufficient signal switching speed.

[0120] 8 , the gate drive circuit GOA includes multiple shift registers SR connected in cascade. The output terminal EO of the previous shift register SR is electrically connected to the input signal terminal of the next shift register SR. The input signal terminal of the first shift register SR is used to load the column start signal ESTV.

[0121] Optionally, the display panel PNL may be provided with four clock lines in the peripheral area BB, namely, a first clock line CL1, a second clock line CL2, a first auxiliary clock line CL1X, and a second auxiliary clock line CL2X, which cooperate with the gate drive circuit GOA. The first clock line CL1 and the first auxiliary clock line CL1X are grouped together, and the clock signal loaded on the first auxiliary clock line CL1X is slightly later than the clock signal loaded on the first clock line CL1, so that when the clock signal on the first clock line CL1 serves as the first clock signal CK, the clock signal on the first auxiliary clock line CL1X can serve as the first auxiliary clock signal CK2. The second clock line CL2 and the second auxiliary clock line CL2X are grouped together, and the clock signal loaded on the second auxiliary clock line CL2X is slightly later than the clock signal loaded on the second clock line CL2, so that when the clock signal on the second clock line CL2 serves as the first clock signal CK, the clock signal on the second auxiliary clock line CL2X can serve as the first auxiliary clock signal CK2.

[0122] In this gate drive circuit GOA, the first clock line CL1 is electrically connected to the first clock signal terminal of the odd-numbered shift register SR and to the second clock signal terminal of the even-numbered shift register SR; the second clock line CL2 is electrically connected to the second clock signal terminal of the odd-numbered shift register SR and to the first clock signal terminal of the even-numbered shift register SR; the first auxiliary clock line CL1X is electrically connected to the first auxiliary clock signal terminal of the odd-numbered shift register SR; and the second auxiliary clock line CL2X is electrically connected to the first auxiliary clock signal terminal of the even-numbered shift register SR. Thus, for the odd-numbered shift register SR, the clock signal on the first clock line CL1 serves as the first clock signal CK, the clock signal on the first auxiliary clock line CL1X serves as the first auxiliary clock signal CK2, and the clock signal on the second clock line CL2 serves as the second clock signal CB. For the even-stage shift register SR, the clock signal on the second clock line CL2 serves as the first clock signal CK, the clock signal on the second auxiliary clock line CL2X serves as the first auxiliary clock signal CK2, and the clock signal on the first clock line CL1 serves as the second clock signal CB.

[0123] In one example of this embodiment, referring to FIG. 9 , the clock cycle of the first auxiliary clock signal CK2 is the same as the clock cycle of the first clock signal CK, and the duration of the gate level of the first auxiliary clock signal CK2 is the same as the duration of the gate level of the first clock signal CK. In other words, the waveform of the first auxiliary clock signal CK2 is the same as that of the first clock signal CK, but is delayed by a first predetermined time compared to the first clock signal CK.

[0124] In one example of this embodiment, referring to FIG9 , the sum of the first preset time and the duration of the gate level of the first clock signal CK is less than half the clock cycle of the first clock signal CK. This ensures that the voltage of the seventh control node PD_c is changed before half the clock cycle of the first clock signal CK, thereby changing the voltage of the second control node PD_out (e.g., further lowering the low level on the second control node PD_out), thereby promptly enhancing the driving force of the second output sub-circuit Mout2 and accelerating the level switching of the output terminal EO.

[0125] In one example of this embodiment, the first preset time is no greater than 2 microseconds. The first preset time can be reasonably set according to the specific requirements of the gate drive circuit GOA, for example, the first preset time can be 0.1 microseconds, 0.4 microseconds, 0.7 microseconds, 1.1 microseconds, 1.5 microseconds, 1.8 microseconds, 2.0 microseconds, etc.

[0126] In another embodiment of the present disclosure, the start time of the gating level of the first clock signal CK is the same as the start time of the gating level of the first auxiliary clock signal CK2. This makes the first preset time equal to 0. Furthermore, the first clock signal CK and the first auxiliary clock signal CK2 can be the same signal, that is, there is no time delay between the first clock signal CK and the first auxiliary clock signal CK2. In this embodiment, the gating level of the first clock signal CK at the first clock signal terminal causes the level at the first auxiliary clock signal terminal to switch to the gating level of the first auxiliary clock signal CK2 when the first input sub-circuit Min1 applies the gating level (e.g., the low-level power supply voltage VGL) to the second control node PD_out, but the fourth sub-circuit M4 remains turned off, leaving the seventh control node PD_c unchanged. As the level of the second control node PD_out changes to the point where the fourth sub-circuit M4 is turned on (for example, as the level of the second control node PD_out is pulled down to the point where the fourth sub-circuit M4 is turned on), the fourth sub-circuit M4 is turned on, causing the level of the seventh control node PD_c to change, and this change will be superimposed on the second control node PD_out through the coupling effect of the third capacitor C3; that is, the level change of the second control node PD_out caused by the level change of the seventh control node PD_c and the level change of the second control node PD_out caused by the first input sub-circuit Min1 have the same change trend, for example, the seventh control node PD_c and the first input sub-circuit Min1 simultaneously pull down the second control node PD_out, thereby causing the second control node PD_out to be quickly pulled down to a lower level, so that the second output sub-circuit Mout2 obtains a larger driving force as soon as possible.

[0127] In an example of this embodiment, four clock lines, namely the first clock line CL1, the second clock line CL2, the first auxiliary clock line CL1X and the second auxiliary clock line CL2X, can still be set on the display panel PNL, and the clock signals on the first clock line CL1 and the first auxiliary clock line CL1X are kept consistent, and the clock signals on the second clock line CL2 and the second auxiliary clock line CL2X are kept consistent.

[0128] In another embodiment of the present disclosure, referring to Figures 13 and 12 , the first auxiliary clock signal terminal may not be provided, and instead the first terminal of the fourth sub-circuit M4 may be directly electrically connected to the first clock signal terminal. This is equivalent to the first clock signal CK and the first auxiliary clock signal CK2 being consistent. In this embodiment, there is no need to additionally provide a first auxiliary clock trace CL1X and a second auxiliary clock trace CL2X. The display panel PNL may be provided with a first clock trace CL1 and a second clock trace CL2 in the peripheral area BB that cooperate with the gate drive circuit GOA. The first clock trace CL1 is electrically connected to the first clock signal terminal of the shift register SR of the odd-numbered stages and to the second clock signal terminal of the shift register SR of the even-numbered stages; the second clock trace CL2 is electrically connected to the second clock signal terminal of the shift register SR of the odd-numbered stages and to the first clock signal terminal of the shift register SR of the even-numbered stages. This facilitates achieving a narrow bezel for the display panel PNL.

[0129] In one embodiment of the present disclosure, referring to Figures 6 and 7, the first input sub-circuit Min1 includes a first transistor T1, a first end of the first transistor T1 is electrically connected to the input signal end, a control end of the first transistor T1 is electrically connected to the first clock signal end, and a second end of the first transistor T1 is electrically connected to the second control node PD_out.

[0130] In one embodiment of the present disclosure, the first output sub-circuit Mout1 includes a ninth transistor T9 and a second capacitor C2; the first end of the ninth transistor T9 and the first end of the second capacitor C2 are electrically connected to the first power supply voltage end, the second end of the ninth transistor T9 is electrically connected to the output end EO, and the control end of the ninth transistor T9 and the second end of the second capacitor C2 are electrically connected to the first control node PU_out.

[0131] In one embodiment of the present disclosure, the second output sub-circuit Mout2 includes a tenth transistor T10, a first end of the tenth transistor T10 is electrically connected to the second power supply voltage end, a control end of the tenth transistor T10 is electrically connected to the second control node PD_out, and a second end of the tenth transistor T10 is electrically connected to the output end EO.

[0132] In one embodiment of the present disclosure, the fourth sub-circuit M4 includes a fourth transistor T4, a first end of the fourth transistor T4 is electrically connected to the first auxiliary clock signal end, a control end of the fourth transistor T4 is electrically connected to the first end of the third capacitor C3, and a second end of the fourth transistor T4 is electrically connected to the seventh control node PD_c.

[0133] In one embodiment of the present disclosure, the fifth sub-circuit M5 includes a fifth transistor T5, a first end of the fifth transistor T5 is electrically connected to the first power supply voltage end, a control end of the fifth transistor T5 is electrically connected to the first control node PU_out, and a second end of the fifth transistor T5 is electrically connected to the seventh control node PD_c.

[0134] In one embodiment of the present disclosure, the shift register SR further includes a first control module MPUC, the first control module MPUC including a second sub-circuit M2, a third sub-circuit M3, a sixth sub-circuit M6, a seventh sub-circuit M7 and a first capacitor C1;

[0135] In which, the control end of the second sub-circuit M2 is electrically connected to the second end of the first input sub-circuit Min1, the first end of the second sub-circuit M2 is electrically connected to the first clock signal end, and the second end of the second sub-circuit M2 and the second end of the third sub-circuit M3 are electrically connected to the third control node PU_in; the second sub-circuit M2 is configured to load the voltage on the first clock signal end to the third control node PU_in in response to the selection level on the second control node PD_out.

[0136] A first terminal of the third sub-circuit M3 is electrically connected to the second power supply voltage terminal, and a control terminal of the third sub-circuit M3 is electrically connected to the first clock signal terminal; the third sub-circuit M3 is configured to load the second power supply voltage V2 to the third control node PU_in in response to the selection level of the first clock signal CK.

[0137] A first terminal of the sixth sub-circuit M6 is electrically connected to the second clock signal terminal, a control terminal of the sixth sub-circuit M6 and the second terminal of the first capacitor C1 are electrically connected to the fifth control node PU_c, and a second terminal of the sixth sub-circuit M6, a first terminal of the first capacitor C1, and a first terminal of the seventh transistor T7 are electrically connected to the sixth control node PU_c2. The sixth sub-circuit M6 is configured to, in response to a gating level on the fifth control node PU_c, apply a voltage on the second clock signal terminal to the sixth control node PU_c2. The fifth control node PU_c is electrically connected to the third control node PU_in.

[0138] A first end of the seventh sub-circuit M7 is electrically connected to the first control node PU_out, a second end of the seventh sub-circuit M7 is electrically connected to the second clock signal end, and the seventh sub-circuit M7 is configured to be electrically conductive in response to a gating level of the second clock signal CB.

[0139] In an example of this embodiment, the second sub-circuit M2 includes a second transistor T2, a first end of the second transistor T2 is electrically connected to the first clock signal end, a control end of the second transistor T2 is electrically connected to the second control node PD_out, and a second end of the second transistor T2 is electrically connected to the third control node PU_in.

[0140] The third sub-circuit M3 includes a third transistor T3, a first end of the third transistor T3 is electrically connected to the second power supply voltage end, a control end of the third transistor T3 is electrically connected to the first clock signal end, and a second end of the third transistor T3 is electrically connected to the third control node PU_in.

[0141] The sixth sub-circuit M6 includes a sixth transistor T6, a first end of the sixth transistor T6 is electrically connected to the second clock signal end, a control end of the sixth transistor T6 is electrically connected to the fifth control node PU_c, and a second end of the sixth transistor T6 is electrically connected to the sixth control node PU_c2.

[0142] The seventh sub-circuit M7 includes a seventh transistor T7, a first end of the seventh transistor T7 is electrically connected to the sixth control node PU_c2, a second end of the seventh sub-circuit M7 is electrically connected to the second clock signal end, and a first end of the seventh sub-circuit M7 is electrically connected to the first control node PU_out.

[0143] In one example of this embodiment, the first control module MPUC further includes an eleventh transistor T11, wherein a first end of the eleventh transistor T11 is electrically connected to the third control node PU_in, a second end of the eleventh transistor T11 is electrically connected to the fifth control node PU_c, and a control end of the eleventh transistor T11 is electrically connected to the second power supply voltage terminal to turn on the eleventh transistor T11. For example, if the eleventh transistor T11 is a P-type transistor, the control end of the eleventh transistor T11 is electrically connected to the low-level power supply voltage terminal PVGL to keep the eleventh transistor T11 electrically conductive.

[0144] In one example of this embodiment, the clock cycle of the second clock signal CB is the same as the clock cycle of the first clock signal CK; the gating level of the second clock signal CB is the same duration as the gating level of the first clock signal CK; the gating level of the second clock signal CB is delayed by a second preset time relative to the gating level of the first clock signal CK, where the second preset time is half the clock cycle of the first clock signal CK. In other words, the second clock signal CB and the first clock signal CK have the same waveform, but the second clock signal CB is delayed by half a clock cycle relative to the first clock signal CK. Accordingly, the clock signals loaded on the first clock line CL1 and the second clock line CL2 have the same waveform, but their phases differ by half a clock cycle.

[0145] In an example of this embodiment, the time length of the selection level of the first clock signal CK is less than half of the clock period of the first clock signal CK. For example, the clock length of the selection level of the first clock signal CK is 1 / 3 clock period, 1 / 4 clock period, 1 / 5 clock period or 1 / 6 clock period.

[0146] In one embodiment of the present disclosure, referring to Figures 6 and 7 , the shift register SR further includes an eighth sub-circuit MC, wherein a control terminal of the eighth sub-circuit MC is electrically connected to the second control node PD_out, a first terminal of the eighth sub-circuit MC is electrically connected to the first power supply voltage terminal, and a second terminal of the eighth sub-circuit MC is electrically connected to the first control node PU_out. The eighth sub-circuit MC is configured to apply the first power supply voltage V1 to the first control node PU_out in response to a strobe level on the second control node PD_out. In this embodiment, the strobe level on the first control node PU_out is low. When the strobe level is applied to the second control node PD_out, turning on the second output sub-circuit Mout2, the first power supply voltage V1 is applied to the first control node PU_out, turning off the first output sub-circuit Mout1. It will be appreciated that if the strobe level on the first control node PU_out is high, the control terminal of the eighth sub-circuit MC may be electrically connected to the second power supply voltage terminal. In this way, it can be ensured that when the second output sub-circuit Mout2 outputs the second power supply voltage V2 to the output end EO, the first output sub-circuit Mout1 remains cut off.

[0147] In an example of this embodiment, the eighth sub-circuit MC includes an eighth transistor T8, the control end of the eighth transistor T8 is electrically connected to the second control node PD_out, the first end of the eighth transistor T8 is electrically connected to the first power supply voltage end, and the second end of the eighth transistor T8 is electrically connected to the first control node PU_out.

[0148] In another embodiment of the present disclosure, referring to FIG11 , the shift register SR further includes an eighth sub-circuit MC, wherein a control terminal of the eighth sub-circuit MC is electrically connected to the input signal terminal, a first terminal of the eighth sub-circuit MC is electrically connected to the first power supply voltage terminal, and a second terminal of the eighth sub-circuit MC is electrically connected to the first control node PU_out. The eighth sub-circuit MC is configured to apply the first power supply voltage V1 to the first control node PU_out in response to a strobe level at the input signal terminal. In this embodiment, when the level at the input signal terminal is the strobe level, the eighth sub-circuit MC can be turned on to apply the first power supply voltage V1 to the first control node PU_out, thereby causing the first output sub-circuit Mout1 to be prematurely terminated. When the first input sub-circuit Min1 is turned on to apply the strobe level at the input signal terminal to the second control node PD_out, the second output sub-circuit Mout2 can be turned on to apply the second power supply voltage terminal to the output terminal EO. At this time, the first output sub-circuit Mout1 has been cut off in advance, which can prevent a current path from being formed between the first power supply voltage terminal and the second power supply voltage terminal, thereby facilitating a rapid level conversion at the output terminal EO (faster conversion from the first power supply voltage V1 to the second power supply voltage V2), and avoiding power consumption caused by direct connection between the first power supply voltage terminal and the second power supply voltage terminal.

[0149] In an example of this embodiment, the eighth sub-circuit MC includes an eighth transistor T8, the control end of the eighth transistor T8 is connected to the input signal end, the first end of the eighth transistor T8 is electrically connected to the first power supply voltage end, and the second end of the eighth transistor T8 is electrically connected to the first control node PU_out.

[0150] In one embodiment of the present disclosure, the shift register SR further includes a twelfth transistor T12, a first end of the twelfth transistor T12 and a second end of the first input sub-circuit Min1 are electrically connected to the fourth control node PD_in, and a second end of the twelfth transistor T12 is electrically connected to the second control node PD_out; and the control end of the twelfth transistor T12 is electrically connected to the second power supply voltage end so that the twelfth transistor T12 is turned on.

[0151] In one embodiment of the present disclosure, the shift register SR further includes a thirteenth transistor T13, a first end of the thirteenth transistor T13 being electrically connected to the first power supply voltage end, a second end of the thirteenth transistor T13 being electrically connected to the second control node PD_out, and a control end of the thirteenth transistor T13 being electrically connected to the control signal Tot_R; the thirteenth transistor T13 is configured to load the first power supply voltage V1 to the second control node PD_out in response to the control voltage Tot_R.

[0152] In one embodiment of the present disclosure, referring to FIG. 10 , the shift register SR further includes a second input sub-circuit Min2 , a fifteenth transistor T15 , and a sixteenth sub-circuit M16 .

[0153] A first end of the second input sub-circuit Min2 is electrically connected to the input signal end, a control end of the second input sub-circuit Min2 is electrically connected to the first clock signal end, a second end of the second input sub-circuit Min2 is electrically connected to the first end of the fifteenth transistor T15; the control end of the fifteenth transistor T15 is electrically connected to the second power supply voltage end so that the fifteenth transistor T15 is turned on; a second end of the fifteenth transistor T15, the control end of the fourth sub-circuit M4, the control end of the sixteenth sub-circuit M16, and a first end of the sixteenth sub-circuit M16 are electrically connected, and a second end of the sixteenth sub-circuit M16 is electrically connected to the second control node PD_out.

[0154] The second input sub-circuit Min2 is configured to apply the voltage at the input signal terminal to the control terminal of the sixteenth sub-circuit M16 in response to the gate level of the first clock signal CK. Thus, when the input signal terminal writes a voltage to the second control node PD_out, this can be done simultaneously through both the first input sub-circuit Min1 and the second input sub-circuit Min2. This improves the overall driving force and facilitates rapid changes in the voltage at the second control node PD_out. For example, when the voltage at the input signal terminal is the second power supply voltage V2 and the voltage at the first clock signal terminal is the gate level of the first clock signal CK, the first input sub-circuit Min1 and the second input sub-circuit Min2 simultaneously write the second power supply voltage V2 to the second control node PD_out, allowing the voltage at the second control node PD_out to quickly transition to the second power supply voltage V2.

[0155] In one example, the second input sub-circuit Min2 includes a fourteenth transistor T14; a first end of the fourteenth transistor T14 is electrically connected to the input signal end, a control end of the fourteenth transistor T14 is electrically connected to the first clock signal end, and a second end of the fourteenth transistor T14 is electrically connected to the first end of the fifteenth transistor T15;

[0156] The sixteenth sub-circuit M16 includes a sixteenth transistor T16 , a first terminal of the sixteenth transistor T16 and a control terminal of the sixteenth transistor T16 are electrically connected to the second terminal of the fifteenth transistor T15 , and a second terminal of the sixteenth transistor T16 is electrically connected to the second control node PD_out.

[0157] In one example, each transistor of the shift register SR is a P-type transistor, the first power supply voltage V1 is a high-level power supply voltage VGH, and the second power supply voltage V2 is a low-level power supply voltage VGL. In this example, the gating level of the second control node PD_out is low; the gating level of the first control node PU_out is low. The first power supply voltage V1 is the high-level power supply voltage VGH, and the second power supply voltage V2 is the low-level power supply voltage VGL. The gating level of the first clock signal CK is low, and the gating level of the second clock signal CB is low. The gating level of the first auxiliary clock signal CK2 is low.

[0158] The embodiments of the present disclosure also conducted simulation tests on the shift register SR illustrated in Figures 7 and 10. During the simulation test of the shift register SR illustrated in Figure 7, it was found that when the first end of the fourth transistor T4 was loaded with the second clock signal CB, the reset time (pull-down time) of the output terminal EO was 5.82 microseconds; when the first end of the fourth transistor T4 was loaded with the first auxiliary clock signal CK2, the reset time of the output terminal EO was 0.311 microseconds. During the simulation test of the shift register SR illustrated in Figure 10, it was found that when the first end of the fourth transistor T4 was loaded with the second clock signal CB, the reset time (pull-down time) of the output terminal EO was 1.02 microseconds; when the first end of the fourth transistor T4 was loaded with the first auxiliary clock signal CK2, the reset time of the output terminal EO was 0.432 microseconds. Therefore, in the shift register SR provided by the present disclosure, by causing the first end of the fourth transistor T4 to be loaded with the first auxiliary clock signal CK2 or the first clock signal CK instead of the second clock signal CB, the reset time of the output terminal EO can be significantly improved, thereby avoiding display abnormalities caused by untimely reset of the output terminal EO.

[0159] As follows, the working principle and process of the shift register SR shown in FIG7 are exemplarily described by taking the case where all transistors of the shift register SR shown in FIG7 are P-type transistors as an example.

[0160] Referring to Figure 7 , the shift register SR includes first to thirteenth transistors T1 to T13, and first to third capacitors C1 to C3. Each of the transistors is a P-type transistor. In this example, the first power supply voltage V1 is a high-level power supply voltage VGH, and the second power supply voltage V2 is a low-level power supply voltage VGL. The gating levels of the first clock signal CK, the first auxiliary clock signal CK2, and the second clock signal CB are all low.

[0161] Referring to FIG. 9 , at a first moment P1, the input signal (the column start signal ESTV) is applied to the input signal (the input signal of the first-stage shift register SR) and the gate level of the first clock signal CK is high. Therefore, the input signal cannot be applied to the second control node PD_out. The second control node PD_out is at a level and the first control node PU_out is at a high level, which turns on the tenth transistor T10 and turns off the ninth transistor T9. Consequently, the output terminal EO outputs a low level.

[0162] At the second moment P2, the input signal is high, and the first clock signal CK is low. The input signal is applied to the second control node PD_out, causing it to remain high. The eighth transistor T8 remains off, causing the first control node PU_out to be high. The ninth transistor T9 remains off, and the output terminal EO remains low. The third and eleventh transistors T3 and T11 are turned on, causing the low-level power supply voltage VGL to be applied to the fifth control node PU_c, thereby causing the sixth transistor T6 to remain on.

[0163] At the third moment P3, the first clock signal CK is at a high level, which causes the level of the second control node PD_out to be locked at a high level. The tenth transistor T10 remains off, and the low-level power supply voltage VGL cannot be applied to the output terminal EO. The second clock signal CB is at a low level, and the sixth transistor T6 and the seventh transistor T7 are turned on, thereby causing the first control node PU_out to be at a low level. The ninth transistor T9 is turned on, causing the high-level power supply voltage VGH to be applied to the output terminal EO, and the output terminal EO outputs a high level.

[0164] At the fourth moment P4, the first clock signal CK is at a low level and the input signal remains at a high level, which causes the second control node PD_out to remain at a high level, and the tenth transistor T10 and the eighth transistor T8 to remain off. The second clock signal CB is at a high level, which causes the first control node PU_out to remain at a low level, and the ninth transistor T9 remains on, causing the output terminal EO to output a high level.

[0165] At a fifth moment P5, the first clock signal CK is at a high level, the input signal switches to a low level, the first transistor T1 is turned off, causing the second control node PD_out to remain at a high level, and the tenth transistor T10 and the eighth transistor T8 remain turned off. The second clock signal CB is at a low level, and the sixth transistor T6 and the seventh transistor T7 are turned on, causing the first control node PU_out to remain at a low level. The ninth transistor T9 remains turned on, causing the output terminal EO to output a high level.

[0166] At the beginning of the sixth moment P6, the second clock signal CB is at a high level, the first clock signal CK switches to a low level, and the first auxiliary clock signal CK2 also switches to a high level immediately after the first clock signal CK. The high level of the second clock signal CB turns off the seventh transistor T7. After the first clock signal CK switches to a low level, the first transistor T1 turns on, causing the second control node PD_out to be at a low level. The tenth transistor T10 turns on and outputs a low level to the output terminal EO. The eighth transistor T8 turns on and outputs a high level to the first control node PU_out, turning off the ninth transistor T9. This causes the output terminal EO to begin to drop. When the first auxiliary clock signal CK2 begins to switch to a low level, the seventh control node PD_c drops from a high level to a low level. Through the coupling effect of the third capacitor C3, the second control node PD_out is further pulled down, increasing the conductivity of the tenth transistor T10 and thus the driving force of the tenth transistor T10, accelerating the drop in the output terminal EO.

[0167] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A shift register comprising a first output subcircuit, a second output subcircuit, a first input subcircuit, and a second control module; in, The control terminal of the first output sub-circuit is electrically connected to the first control node, the first terminal of the first output sub-circuit is electrically connected to the first power supply voltage terminal, and the first output sub-circuit is configured to output the first power supply voltage to the output terminal in response to a gating level on the first control node; The control terminal of the second output sub-circuit is electrically connected to the second control node, the first terminal of the second output sub-circuit is electrically connected to the second power supply voltage terminal, and the second output sub-circuit is configured to output the second power supply voltage to the output terminal in response to a gating level on the second control node; A first terminal of the first input sub-circuit is electrically connected to an input signal terminal, a control terminal of the first input sub-circuit is electrically connected to a first clock signal terminal, and a second terminal of the first input sub-circuit is electrically connected to the second control node. The first input sub-circuit is configured to cause a voltage on the input signal terminal to be applied to the second control node in response to a gating level of the first clock signal. The second control module includes a fourth subcircuit, a fifth subcircuit, and a third capacitor, wherein a first end of the third capacitor and a control end of the fourth subcircuit are electrically connected to the second control node; a second end of the fifth subcircuit, a second end of the fourth subcircuit, and a second end of the third capacitor are electrically connected to the seventh control node; a first end of the fourth subcircuit is electrically connected to the first auxiliary clock signal terminal, and the control end of the fifth subcircuit is electrically connected to the first control node; and a first end of the fifth subcircuit is electrically connected to the first power supply voltage terminal. The fourth sub-circuit is configured to, in response to the gating level on the second control node, load the voltage on the first auxiliary clock signal terminal to the seventh control node; The fifth sub-circuit is configured to, in response to a gating level on the first control node, load the voltage on the first power supply voltage terminal to the seventh control node; The gating level of the first auxiliary clock signal is higher than the gating level of the first clock signal. The clock signal is delayed by a first preset time, where the first preset time is less than half of a clock period of the first clock signal.

2. The shift register according to claim 1, wherein: a fourth sub-circuit comprising a fourth transistor, a first terminal of the fourth transistor being electrically connected to the first auxiliary clock signal terminal, a control terminal of the fourth transistor being electrically connected to the first terminal of the third capacitor, and a second terminal of the fourth transistor being electrically connected to the seventh control node; The fifth sub-circuit includes a fifth transistor, a first terminal of the fifth transistor is electrically connected to the first power supply voltage terminal, a control terminal of the fifth transistor is electrically connected to the first control node, and a second terminal of the fifth transistor is electrically connected to the seventh control node.

3. The shift register according to claim 1, wherein: The first input sub-circuit includes a first transistor, a first terminal of the first transistor is electrically connected to the input signal terminal, a control terminal of the first transistor is electrically connected to the first clock signal terminal, and a second terminal of the first transistor is electrically connected to the second control node; The first output sub-circuit includes a ninth transistor and a second capacitor; a first terminal of the ninth transistor and a first terminal of the second capacitor are electrically connected to the first power supply voltage terminal, a second terminal of the ninth transistor is electrically connected to the output terminal, and a control terminal of the ninth transistor and a second terminal of the second capacitor are electrically connected to the first control node; The second output sub-circuit includes a tenth transistor, a first terminal of the tenth transistor is electrically connected to the second power supply voltage terminal, a control terminal of the tenth transistor is electrically connected to the second control node, and a second terminal of the tenth transistor is electrically connected to the output terminal.

4. The shift register according to claim 1, wherein: The shift register further includes a first control module, which includes a second sub-circuit, a third sub-circuit, a sixth sub-circuit, a seventh sub-circuit and a first capacitor; The control terminal of the second sub-circuit is electrically connected to the second terminal of the first input sub-circuit, the first terminal of the second sub-circuit is electrically connected to the first clock signal terminal, and the second terminal of the second sub-circuit and the second terminal of the third sub-circuit are electrically connected to the third control node; The second sub-circuit is configured to load the voltage on the first clock signal terminal to the third control node in response to the gating level on the second control node; The first terminal of the third sub-circuit is electrically connected to the second power supply voltage terminal, and the control terminal of the third sub-circuit is electrically connected to the first clock signal terminal; the third sub-circuit is configured to apply the second power supply voltage to the third control node in response to the gating level of the first clock signal; The first terminal of the sixth sub-circuit is electrically connected to the second clock signal terminal, the control terminal of the sixth sub-circuit and the second terminal of the first capacitor are electrically connected to the fifth control node, and the second terminal of the sixth sub-circuit, the first terminal of the first capacitor, and the first terminal of the seventh transistor are electrically connected to the sixth control node. The sixth sub-circuit is configured to, in response to a gating level on the fifth control node, cause the voltage on the second clock signal terminal to be applied to the sixth control node. The fifth control node is electrically connected to the third control node. The control end of the seventh sub-circuit is electrically connected to the sixth control node, the first end of the seventh sub-circuit is electrically connected to the first control node, the control end of the seventh sub-circuit is electrically connected to the second clock signal end, and the seventh sub-circuit is configured to be electrically turned on in response to the selection level of the second clock signal.

5. The shift register according to claim 4, wherein: The second sub-circuit includes a second transistor, a first terminal of the second transistor is electrically connected to the first clock signal terminal, a control terminal of the second transistor is electrically connected to the second control node, and a second terminal of the second transistor is electrically connected to the third control node; The third sub-circuit includes a third transistor, a first terminal of the third transistor is electrically connected to the second power supply voltage terminal, a control terminal of the third transistor is electrically connected to the first clock signal terminal, and a second terminal of the third transistor is electrically connected to the third control node; The sixth sub-circuit includes a sixth transistor, a first terminal of the sixth transistor is electrically connected to the second clock signal terminal, a control terminal of the sixth transistor is electrically connected to the fifth control node, and a second terminal of the sixth transistor is electrically connected to the sixth control node; The seventh sub-circuit includes a seventh transistor, a first terminal of the seventh transistor is electrically connected to the sixth control node, a second terminal of the seventh sub-circuit is electrically connected to the second clock signal terminal, and a first terminal of the seventh sub-circuit is electrically connected to the first control node.

6. The shift register according to claim 4, wherein: The first control module also includes an eleventh transistor, the first end of the eleventh transistor is electrically connected to the third control node, the second end of the eleventh transistor is electrically connected to the fifth control node, and the control end of the eleventh transistor is electrically connected to the second power supply voltage end to make the eleventh transistor conductive.

7. The shift register according to claim 4, wherein: A clock period of the second clock signal is the same as a clock period of the first clock signal; The gating level of the second clock signal has the same duration as the gating level of the first clock signal; The gating level of the second clock signal is later than the gating level of the first clock signal by a second preset time, and the second preset time is half of a clock cycle of the first clock signal.

8. The shift register according to claim 4, wherein: The duration of the gating level of the first clock signal is less than half of a clock period of the first clock signal.

9. The shift register according to claim 1, wherein: The shift register further includes an eighth sub-circuit, wherein a control terminal of the eighth sub-circuit is electrically connected to the second control node, a first terminal of the eighth sub-circuit is electrically connected to the first power supply voltage terminal, and a second terminal of the eighth sub-circuit is electrically connected to the first control node; The eighth sub-circuit is configured to apply the first power supply voltage to the first control node in response to a gating level on the second control node.

10. The shift register according to claim 9, wherein: The eighth sub-circuit includes an eighth transistor, a control terminal of the eighth transistor is electrically connected to the second control node, a first terminal of the eighth transistor is electrically connected to the first power supply voltage terminal, and a second terminal of the eighth transistor is electrically connected to the first control node.

11. The shift register according to claim 1, wherein: The shift register further includes an eighth sub-circuit, wherein a control terminal of the eighth sub-circuit is electrically connected to the input signal terminal, a first terminal of the eighth sub-circuit is electrically connected to the first power supply voltage terminal, and a second terminal of the eighth sub-circuit is electrically connected to the first control node; The eighth sub-circuit is configured to apply the first power supply voltage to the first control node in response to a strobe level on the input signal terminal.

12. The shift register according to claim 11, wherein: The eighth sub-circuit includes an eighth transistor, a control terminal of the eighth transistor is connected to the input signal terminal, a first terminal of the eighth transistor is electrically connected to the first power supply voltage terminal, and a second terminal of the eighth transistor is electrically connected to the first control node.

13. The shift register according to claim 1, wherein: The shift register also includes a twelfth transistor, a first end of the twelfth transistor and a second end of the first input sub-circuit are electrically connected to the fourth control node, and a second end of the twelfth transistor is electrically connected to the second control node; the control end of the twelfth transistor is electrically connected to the second power supply voltage end to turn on the twelfth transistor.

14. The shift register according to claim 1, wherein: The shift register also includes a thirteenth transistor, a first end of the thirteenth transistor is electrically connected to the first power supply voltage end, a second end of the thirteenth transistor is electrically connected to the second control node, and a control end of the thirteenth transistor is electrically connected to the control signal; the thirteenth transistor is configured to load the first power supply voltage to the second control node in response to the control voltage.

15. The shift register according to claim 1, wherein: Each transistor of the shift register is a P-type transistor; The first power supply voltage is a high-level power supply voltage; the second power supply voltage is a low-level power supply voltage.

16. The shift register according to claim 1, wherein: A clock cycle of the first auxiliary clock signal is the same as a clock cycle of the first clock signal, and a time length of a gating level of the first auxiliary clock signal is the same as a time length of a gating level of the first clock signal.

17. The shift register according to claim 16, wherein: The sum of the first preset time and the duration of the gating level of the first clock signal is less than half of a clock period of the first clock signal.

18. The shift register according to claim 1, wherein: The first preset time is no greater than 2 microseconds.

19. The shift register according to any one of claims 1 to 18, wherein: The shift register further includes a second input sub-circuit, a fifteenth transistor, and a sixteenth sub-circuit; a first terminal of the second input sub-circuit electrically connected to the input signal terminal, a control terminal of the second input sub-circuit electrically connected to the first clock signal terminal, a second terminal of the second input sub-circuit electrically connected to the first terminal of the fifteenth transistor; a control terminal of the fifteenth transistor electrically connected to a second power supply voltage terminal to turn on the fifteenth transistor; a second terminal of the fifteenth transistor, a control terminal of the fourth sub-circuit, a control terminal of the sixteenth sub-circuit, and a first terminal of the sixteenth sub-circuit electrically connected, and a second terminal of the sixteenth sub-circuit electrically connected to the second control node; The second input sub-circuit is configured to load the voltage on the input signal terminal to the control terminal of the sixteenth sub-circuit in response to the gating level of the first clock signal.

20. The shift register according to claim 19, wherein: The second input sub-circuit includes a fourteenth transistor; a first terminal of the fourteenth transistor is electrically connected to the input signal terminal, a control terminal of the fourteenth transistor is electrically connected to the first clock signal terminal, and a second terminal of the fourteenth transistor is electrically connected to the first terminal of the fifteenth transistor; The sixteenth sub-circuit includes a sixteenth transistor, a first terminal of the sixteenth transistor and a control terminal of the sixteenth transistor are electrically connected to the second terminal of the fifteenth transistor, and the second terminal of the sixteenth transistor is electrically connected to the second control node.

21. The shift register according to any one of claims 1 to 16, wherein: A starting time point of the gating level of the first clock signal is the same as a starting time point of the gating level of the first auxiliary clock signal.

22. The shift register according to any one of claims 1 to 15, wherein: The shift register is not provided with the first auxiliary clock signal terminal; the first terminal of the fourth sub-circuit is electrically connected to the first clock signal terminal.

23. A gate drive circuit, comprising a plurality of shift registers according to any one of claims 1 to 22 connected in cascade sequence, wherein the output terminal of the shift register of the previous stage is electrically connected to the input signal terminal of the shift register of the next stage.

24. A display panel comprising a gate driving circuit and a first clock line, a second clock line, a first auxiliary clock line, and a second auxiliary clock line for driving the gate driving circuit; The gate drive circuit comprises a plurality of shift registers according to any one of claims 1 to 21 that are cascaded in sequence; the output terminal of the shift register of the previous stage is electrically connected to the input signal terminal of the shift register of the next stage; The first clock trace is electrically connected to the first clock signal terminal of the odd-numbered shift register, and is electrically connected to the second clock signal terminal of the even-numbered shift register; The second clock trace is electrically connected to the second clock signal terminal of the odd-numbered shift register, and is electrically connected to the first clock signal terminal of the even-numbered shift register; The first auxiliary clock trace is electrically connected to the first auxiliary clock signal terminal of the odd-numbered shift register; The second auxiliary clock trace is electrically connected to the first auxiliary clock signal terminal of the even-numbered shift register.

25. A display panel comprising a gate driving circuit and a first clock line and a second clock line for driving the gate driving circuit; The gate drive circuit comprises a plurality of shift registers according to claim 22 that are cascaded in sequence; the output terminal of the shift register of the previous stage is electrically connected to the input signal terminal of the shift register of the next stage; The first clock line is electrically connected to the first clock signal terminal of the odd-numbered shift register. connected to, and electrically connected to the second clock signal end of the shift register of the even-numbered stage; The second clock trace is electrically connected to the second clock signal terminal of the odd-numbered shift register, and is electrically connected to the first clock signal terminal of the even-numbered shift register.

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