Display apparatus and electronic device

Abstract

A display apparatus and an electronic device. The display apparatus comprises an LCD display module, a backlight module and a display driving chip. The display driving chip comprises a pixel positioning circuit, N data channels arranged in sequence, an LCD control module and a backlight control module; and the backlight module comprises J*K backlight zones, and each backlight zone is configured to provide backlight for pixel units corresponding to physical positions on the LCD display module, the pixel positioning circuit being configured to determine pixel positioning information for a current clock cycle on the basis of the number of pieces of pixel data transmitted by the N data channels and an ID sequence respectively in each clock cycle, wherein the pixel positioning information comprises the size of the backlight zone, a zone boundary signal and backlight zone information; the size of the backlight zone is the maximum number of pieces of pixel data which can be mapped by one row or one column in a backlight zone; and the ID sequence is obtained by means of sequentially encoding the sizes of J backlight zones or the sizes of K backlight zones, J, K and N being natural numbers.

Description

Display device and electronic device Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and particularly to a display device and an electronic device. Background Art

[0002] The pixel positioning circuit is an important circuit module with image processing function used in display devices. The pixel positioning circuit is used to realize the positioning of the backlight partition mapped by the current pixel, so as to provide accurate pixel position information for subsequent other modules for corresponding calculations.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, an embodiment of the present disclosure provides a display device, comprising an LCD display module, a backlight module, and a display driver chip; the display driver chip comprises a pixel positioning circuit, N data channels arranged in sequence, an LCD control module, and a backlight control module;

[0006] The LCD display module is arranged on the light-emitting side of the backlight module and includes W×H pixel units;

[0007] The backlight module includes J×K backlight partitions, each backlight partition being configured to provide backlight for a pixel unit corresponding to a physical position on the LCD display module; wherein the total number of pixel units corresponding to all J backlight partitions in each row is equal to the total number W of pixel units in each row of the LCD display module, and the total number of pixel units corresponding to all K backlight partitions in each column is equal to the total number H of pixel units in each column of the LCD display module;

[0008] The N data channels are configured to sequentially transmit pixel data to the pixel positioning circuit in each clock cycle; the clock cycle is determined according to the refresh frequency of the display device;

[0009] The backlight control module is configured to generate backlight data according to the pixel data, the pixel positioning information output by the pixel positioning circuit and a preset backlight operation algorithm and provide the backlight data to the backlight module;

[0010] The LCD control module is configured to generate LCD display grayscale data based on the pixel data, the pixel positioning information output by the pixel positioning circuit and a preset grayscale compensation algorithm and provide the data to the LCD display module;

[0011] in:

[0012] The pixel positioning circuit is configured to determine, in each clock cycle, pixel positioning information for the current clock cycle based on the number of pixel data transmitted by the N data channels and an ID sequence; wherein the pixel positioning information includes a backlight partition size, a partition boundary signal, and backlight partition information; the backlight partition size is the maximum number of pixel data that can be mapped to a row or a column in a backlight partition; the ID sequence is obtained by sequentially encoding the sizes of the J backlight partitions or the sizes of the K backlight partitions, the ID sequence comprising J sequentially arranged IDs or K sequentially arranged IDs corresponding one-to-one to the sizes of the J backlight partitions or the sizes of the K backlight partitions; the partition boundary signal is used to indicate whether pixel data transmitted via the N data channels in the next clock cycle is at least partially mapped to a new backlight partition, the new backlight partition being the next backlight partition located in the same row or column as the current backlight partition and adjacent to the current backlight partition; and the backlight partition information is configured to indicate the backlight partition to which the pixel data transmitted by the N data channels in the current clock cycle is mapped;

[0013] Among them, W, H, J, K and N are natural numbers.

[0014] In an exemplary embodiment, the pixel positioning circuit includes: a partition mark generation module, a partition ID control module, a partition size control module, a counting control module and a backlight partition information generation module;

[0015] The partition flag generating module is configured to output a partition boundary signal and determine, in each clock cycle, whether pixel data transmitted through the N data channels in the next clock cycle is partially or completely mapped to a new backlight partition; when the determination result is yes, the partition boundary signal is set to be valid; when the determination result is no, the partition boundary signal is set to be invalid;

[0016] The partition ID control module is configured to store the ID sequence and output a current ID in each clock cycle, and to set the current ID to the first ID in the ID sequence in the first clock cycle when the system is powered on or pixel data is mapped to a new row or column; the partition ID control module is further configured to set the next ID in the ID sequence after the current ID in the ID sequence as the new current ID at the beginning of each clock cycle if the partition boundary signal is valid;

[0017] The partition size control module is configured to output the size of the backlight partition corresponding to the current ID according to the current ID output by the partition ID control module at the beginning of each clock cycle;

[0018] The counting control module is configured to determine, in each clock cycle, position information of the first pixel data in the current clock cycle based on the size of the backlight partition corresponding to the current ID and the number N of the data channels, and output the position information to the backlight partition information generation module; the first pixel data is pixel data transmitted by the last channel in the data channels; the position information is used to indicate the row or column of the backlight partition to which the first pixel data is mapped, the first pixel data being the Xth pixel data mapped in the row or column, where X is a natural number; wherein the pixel data mapped to a row or column of each backlight partition are sorted respectively;

[0019] The backlight partition information generation module is configured to output the backlight partition information whenever it receives the position information of the first pixel output by the counting control module; wherein, when the partition boundary signal is invalid, the backlight partition information is a value used to indicate that all N pixel data transmitted by the N data channels in the current clock cycle are mapped to one backlight partition; when the partition boundary signal is valid, the backlight partition information is a value used to indicate the mapping relationship between the N pixel data transmitted by the N data channels in the current clock cycle and the current backlight partition and the new backlight partition.

[0020] In an exemplary embodiment, the partition ID control module includes a synchronous shift register chain, and the synchronous shift register chain includes J synchronous shift registers or K synchronous shift registers arranged in sequence;

[0021] The J synchronous shift registers are sequentially set to the J IDs in the ID sequence; or the initial values ​​of the K synchronous shift registers are sequentially set to the K IDs in the ID sequence; wherein the output end of the Jth synchronous shift register or the output end of the Kth synchronous shift register is configured to output the current ID;

[0022] The synchronous shift register chain is configured to trigger a shift at the beginning of each clock cycle when the partition boundary signal is valid; wherein each shift uses the ID in the i-th synchronous shift register to replace the ID in the i+1-th synchronous shift register; i is each integer from 1 to J-1 or each integer from 1 to K-1.

[0023] In an exemplary embodiment, the synchronous shift register is a D flip-flop; in the synchronous shift register chain, the Q output terminal of the i-th D flip-flop is connected to the D input terminal of the i+1-th D flip-flop when the partition boundary signal is valid; i is each integer from 1 to M-1;

[0024] The output value of the Q output terminal of the D flip-flop changes to the value of the D input terminal at the beginning of each clock cycle.

[0025] In an exemplary embodiment, the partition ID control module further includes:

[0026] J-1 first multiplexers, corresponding one-to-one to the first to the J-1th D flip-flops; or K-1 first multiplexers, corresponding one-to-one to the first to the K-1th D flip-flops;

[0027] The positive output terminal of the i-th D flip-flop is connected to the first input terminal of the i-th first multiplexer, the output terminal of the i-th first multiplexer is connected to the D input terminal of the (i+1)-th D flip-flop; the Q output terminal of the J-th D flip-flop or the Q output terminal of the K-th D flip-flop is connected to the partition size control module;

[0028] The first multiplexer is configured to enable the first input terminal when the partition boundary signal is valid.

[0029] In an exemplary embodiment, wherein:

[0030] The bit width of the synchronous shift register chain is determined according to the number of specifications of the J backlight partitions or the number of specifications of the K backlight partitions; wherein the number of specifications refers to the number of types formed by the sizes of the backlight partitions according to different sizes.

[0031] In an exemplary embodiment, the partition size control module includes:

[0032] a first register module and a second multiplexer;

[0033] Different input terminals of the second multiplexer are configured to receive the size of each backlight partition respectively, and the output terminal is configured to be connected to the first register module; the second multiplexer is configured to select the corresponding input terminal according to the current ID output by the partition ID control module;

[0034] The output end of the first register module is electrically connected to the counting control module, and is configured to change the output to the size of the backlight partition corresponding to the current ID at the beginning of each clock cycle.

[0035] In an exemplary embodiment, the counting control module includes an adding unit, a first comparing unit, a subtracting unit, a third multiplexer, and a remainder unit;

[0036] The adding unit is configured to, in each clock cycle, add N to the position information of the first pixel in the previous clock cycle to obtain an accumulated value in the current clock cycle when the partition boundary signal is invalid; and add N to the output value of the subtracting unit in the previous clock cycle to obtain an accumulated value in the current clock cycle when the partition boundary signal is valid;

[0037] The subtraction unit is configured to calculate a first difference value; the first difference value is the absolute value of the difference obtained by subtracting the output value of the partition size control module from the accumulated value of the current clock cycle;

[0038] The first comparing unit is configured to perform a first comparison between the accumulated value of the current clock cycle obtained by the adding unit and the output value of the partition size control module to obtain a first comparison result of the current clock cycle;

[0039] The first input terminal of the third multiplexer is connected to the output terminal of the adding unit, and the second input terminal is connected to the output terminal of the subtracting unit, and is configured to select one from the first difference and the accumulated value of the current clock cycle as the position information of the first pixel in the current clock cycle according to the first comparison result;

[0040] The remainder unit is configured to calculate a remainder obtained by dividing the first difference by N.

[0041] In an exemplary embodiment, wherein:

[0042] The third multiplexer is configured to connect the second input terminal when the first comparison result is that the accumulated value of the current clock cycle is greater than the output value of the partition size control module; and to connect the first input terminal when the first comparison result is that the accumulated value of the current clock cycle is less than or equal to the value output by the partition size control module.

[0043] In an exemplary embodiment, the backlight partition information generation module includes a fourth multiplexer and a fifth multiplexer;

[0044] The two input terminals of the fourth multiplexer are respectively configured to be connected to the output terminal of the fifth multiplexer and to receive a first preset value; the output terminal is configured to output the output of the fifth multiplexer as the pixel location information when the partition boundary signal is valid; and to output the first preset value as the pixel location information when the partition boundary signal is invalid; wherein the first preset value is used to indicate that the N pixel data transmitted through the data channel in the current clock cycle all correspond to one partition;

[0045] The fifth multiplexer has N input terminals configured to be connected to N second preset values, respectively; an output terminal configured to select one of the N input terminals based on the remainder output by the counting control module; the N second preset values ​​respectively represent N situations in which the N pixel data transmitted through the data channel in the current clock cycle correspond to two partitions.

[0046] In an exemplary embodiment, the partition mark generation module includes a second comparison unit, a third comparison unit, a boundary signal generation unit and a storage unit;

[0047] The storage unit is configured to store the size output by the partition size control module in the previous clock cycle;

[0048] The second comparison unit is configured to perform a second comparison between the first sum value and the size output by the partition size control module to obtain a second comparison result, wherein the first sum value is the sum of the position information of the first pixel in the current clock cycle output by the counting control module and N;

[0049] The third comparison unit is configured to perform a third comparison between the position information of the first pixel in the current clock cycle output by the counting control module and the size stored in the storage unit to obtain a third comparison result;

[0050] The boundary signal generating unit is configured to output a valid or invalid partition boundary signal according to the second comparison result and the third comparison result.

[0051] In an exemplary embodiment, when the first sum value is greater than or equal to the size output by the partition control module, the second comparison result is a preset first logic value; when the first sum value is less than the size output by the partition control module, the second comparison result is a preset second logic value;

[0052] When the size stored in the storage unit is equal to the position information of the first pixel data in the current clock cycle, the third comparison result is a preset first logic value; when the size stored in the storage unit is not equal to the position information of the first pixel data in the current clock cycle, the third comparison result is a preset second logic value;

[0053] The boundary signal generating unit outputs the valid partition boundary signal when and only when the third comparison result is the preset second logic value and the second comparison result is the preset first logic value; and outputs an invalid partition boundary signal when the third comparison result is the first logic value, or when the third comparison result is the preset second logic value and the second comparison result is the preset second logic value.

[0054] On the other hand, an embodiment of the present disclosure further provides an electronic device, comprising any of the aforementioned display devices.

[0055] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0056] Summary of the Figures

[0057] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0058] FIG1 is a schematic diagram of the corresponding relationship between clock signals, data channels and partitions;

[0059] FIG2 is a schematic diagram of another correspondence relationship between clock signals, data channels and partitions;

[0060] FIG3 is a schematic diagram showing a corresponding relationship between a partition sequence number and a partition width;

[0061] FIG4 is a schematic diagram of a display device according to an embodiment of the present disclosure;

[0062] FIG5 is a schematic diagram of a pixel positioning circuit according to an embodiment of the present disclosure;

[0063] FIG6 is a schematic diagram of a partition ID control module according to an embodiment of the present disclosure;

[0064] FIG7 is a schematic diagram of a partition size control module according to an embodiment of the present disclosure;

[0065] FIG8 is a schematic diagram of a counting control module according to an embodiment of the present disclosure;

[0066] FIG9 is a schematic diagram of a backlight partition information generation module according to an embodiment of the present disclosure;

[0067] FIG10 is a schematic diagram of a partition mark generation module according to an embodiment of the present disclosure;

[0068] FIG11 is a schematic diagram of another partition mark generation module according to an embodiment of the present disclosure.

[0069] Details

[0070] The present disclosure describes a plurality of embodiments, but the description is exemplary rather than restrictive, and it is apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0071] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other limitations except for the limitations set forth in the appended claims and their equivalents. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0072] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation on the claims. In addition, the claims to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.

[0073] Unless otherwise defined, the technical or scientific terms used in this disclosure have the usual meanings understood by persons of ordinary skill in the art to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, number of channels or importance, but are merely used to distinguish different components. In this disclosure, "plurality" may refer to a number of two or more. Words such as "include" or "comprising" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0074] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and components. The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures can refer to the general design.

[0075] The display device includes an LCD display module, a backlight module and a display driver chip; the display driver chip includes a pixel positioning circuit, N data channels arranged in sequence, an LCD control module and a backlight control module;

[0076] The LCD display module is arranged on the light-emitting side of the backlight module and includes W×H pixel units;

[0077] The backlight module includes J×K backlight sub-areas, each of which is configured to provide backlight for a corresponding pixel unit on an LCD display module directly above the backlight sub-area; wherein the total number of pixel units corresponding to all J backlight sub-areas in each row is equal to the total number W of pixel units in each row of the LCD display module, and the total number of pixel units corresponding to all K backlight sub-areas in each column is equal to the total number H of pixel units in each column of the LCD display module;

[0078] The N data channels are configured to sequentially transmit pixel data to the pixel positioning circuit in each clock cycle; the clock cycle is determined according to the refresh frequency of the display device;

[0079] The pixel positioning circuit is configured to determine, in each clock cycle, pixel positioning information for the current clock cycle based on the number of pixel data transmitted by the N data channels, the sizes of the J backlight partitions, or the sizes of the K backlight partitions; wherein the pixel positioning information includes the size of the backlight partition, a partition boundary signal, and backlight partition information; the size of the backlight partition is the maximum number of pixel data that can be mapped to a row or a column in a backlight partition; the partition boundary signal is used to indicate whether pixel data transmitted via the N data channels in the next clock cycle is at least partially mapped to another backlight partition, the other backlight partition being the next backlight partition located in the same row or column as the current backlight partition and adjacent to the current backlight partition; and the backlight partition information is configured to indicate the backlight partition to which the pixel data transmitted via the N data channels in the current clock cycle is mapped;

[0080] The backlight control module is configured to generate backlight data according to the pixel data, the pixel positioning information output by the pixel positioning circuit and a preset backlight operation algorithm;

[0081] The LCD control module is configured to generate LCD display grayscale data according to the pixel data, the pixel positioning information output by the pixel positioning circuit and a preset grayscale compensation algorithm;

[0082] Among them, W, H, J, K and N are natural numbers.

[0083] The pixel data corresponds to the pixel, that is, one pixel corresponds to one pixel data.

[0084] The above-mentioned pixel positioning circuit, N data channels arranged in sequence, LCD control module and backlight control module can be integrated into a circuit function module. In this circuit function module, N pixel data are simultaneously transmitted to the pixel positioning circuit through N (N can be 1, 2, 4, 8, 16, etc.) data channels (lanes) in each clock cycle. The pixel positioning circuit needs to transmit the mapping information of the backlight partition corresponding to the pixel data transmitted in each clock cycle to the backlight control module and LCD control module to generate backlight data and LCD display grayscale data respectively.

[0085] When N is divisible by the size of any backlight partition, the pixel data transmitted in each clock cycle can be mapped to the same backlight partition; when N is not divisible by the backlight partition size, the pixel data transmitted in the same clock cycle will be mapped to different backlight partitions.

[0086] Taking an LCD display module with progressive scanning as an example, any pixel corresponds to only one backlight zone, and 17 adjacent pixels in the same row correspond to one backlight zone. Refer to Figure 1. The horizontal column header, clk_t (t is a positive integer), represents the tth clock cycle; for example, clk_1 represents the first clock cycle. The vertical column header, lane_n, represents the nth data channel among N data channels (n = 1, 2, 3, ..., N-1, N = 8). Specifically, in the first clock cycle clk_0, the first data channel lane_0 through the eighth data channel lane_7 respectively transmit the first to eighth pixel data corresponding to the current backlight subarea. In the second clock cycle clk_2, the first data channel lane_0 through the eighth data channel lane_7 respectively transmit the ninth to sixteenth pixel data corresponding to the current backlight subarea. In the third clock cycle clk_3, the first data channel lane_0 transmits the seventeenth pixel data corresponding to the current backlight subarea, and the second data channel lane_1 through the eighth data channel lane_7 respectively transmit the first to seventh pixel data corresponding to the next backlight subarea. And so on. It can be seen that in the third clock cycle clk_3, the fifth clock cycle clk_5, the seventh clock cycle clk_7, and the ninth clock cycle clk_9, within the same clock cycle, the pixel data transmitted by the first data channel lane_0 through the eighth data channel lane_7 do not correspond to the same backlight subarea.

[0087] Still taking the LCD display module with row-by-row scanning as an example, any pixel corresponds to only one backlight partition. Two adjacent backlight partitions among multiple backlight partitions located in the same row correspond to different numbers of pixels located in the same row and adjacent to each other. For example, some backlight partitions among multiple backlight partitions located in the same row correspond to 17 adjacent pixels located in the same row, and another part of the backlight partitions corresponds to 18 adjacent pixels located in the same row. Please refer to Figure 2. clk_t (t is a positive integer) in the horizontal header represents the t-th clock cycle, for example, clk_1 represents the first clock cycle; lane_n in the vertical header represents the n-th data channel among N data channels (n=1, 2, 3, ... N-1, N=8); the current backlight partition corresponds to 17 pixels, the next backlight partition corresponds to 18 pixels, and so on; in the first clock cycle clk_0, the first data channel lane_0 to the eighth data channel lane_7 respectively transmit the first pixel data to the eighth pixel data corresponding to the current backlight partition; in the second clock cycle clk_2, the first data channel lane_0 to the eighth data channel lane_7 respectively transmit the ninth pixel data to the sixteenth pixel data corresponding to the current backlight partition; in the third clock cycle clk_3, the first data channel lane_4 to the eighth data channel lane_5 respectively transmit the ninth pixel data to the sixteenth pixel data corresponding to the current backlight partition; In the fourth clock cycle clk_4, the first data channel lane_0 to the eighth data channel lane_7 transmit the eighth pixel data to the fifteenth pixel data corresponding to the next backlight partition respectively; in the fifth clock cycle clk_5, the first data channel lane_0 to the third data channel lane_2 transmit the sixteenth pixel data to the eighteenth pixel data corresponding to the next backlight partition respectively, and the fourth data channel lane_3 to the eighth data channel lane_7 transmit the first pixel data to the fifth pixel data corresponding to the next backlight partition respectively; and so on. It can be found that in the 3rd clock cycle clk_3, the 4th clock cycle clk_4, the 5th clock cycle clk_5, the 7th clock cycle clk_7, the 8th clock cycle clk_8, the 9th clock cycle clk_9, the 11th clock cycle clk_11, the 12th clock cycle clk_12, the 13th clock cycle clk_13, and the 14th clock cycle clk_14, within the same clock cycle, the pixel data transmitted by the 1st data channel lane_0 to the 8th data channel lane_7 do not correspond to the same backlight partition.

[0088] If pixel data transmitted through N data channels in the same clock cycle is mapped to different backlight partitions, it will inevitably lead to increased design complexity of the pixel positioning circuit and occupy too many resources.

[0089] For example, 26 backlight partitions are arranged along rows or columns, and in FIG3 , partition numbers 1 to 26 are used to represent each backlight partition. The partition sizes (i.e., the number of pixels physically located in the same row and adjacent to each other) of the backlight partitions include two specifications: 78 pixels and 79 pixels. The two sizes of backlight partitions are arranged irregularly. When M registers are used to store the M backlight partition sizes one by one, the circuit function module needs to provide a large amount of storage resources to store the partition parameter information. If an 8-bit binary number is used to store the backlight partition size, the total storage capacity is (J + K) × 8 bits. Converted into a two-input NAND gate count for an ASIC (Application Specific Integrated Circuit), this is estimated to be on the order of several thousand bits. A complete display driver circuit functional module typically consumes approximately 200kb to 500kb of resources. The pixel positioning circuit, a lightweight module within the circuit functional module, consumes several thousand bits of resources just to store the partition parameters. This far exceeds the expected kilobits, directly increasing the cost of the ASIC and severely impacting the widespread adoption of such display devices. Therefore, there is an urgent need for display devices that can reduce resource consumption.

[0090] In view of this, an embodiment of the present disclosure provides a display device.

[0091] FIG4 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG4 , the display device includes an LCD display module, a backlight module, and a display driver chip; the display driver chip includes a pixel positioning circuit, N data channels arranged in sequence, an LCD control module, and a backlight control module;

[0092] The LCD display module is arranged on the light-emitting side of the backlight module and includes W×H pixel units;

[0093] The backlight module includes J×K backlight partitions, each backlight partition physically corresponding to a plurality of pixel units in the LCD display module and providing backlight therefor; wherein the total number of pixel units corresponding to all J backlight partitions in each row is equal to the total number W of pixel units in each row of the LCD display module, and the total number of pixel units corresponding to all K backlight partitions in each column is equal to the total number H of pixel units in each column of the LCD display module;

[0094] The N data channels are configured to sequentially transmit pixel data to the pixel positioning circuit in each clock cycle; the clock cycle is determined according to the refresh frequency of the display device;

[0095] The backlight control module is configured to generate backlight data according to the pixel data, the pixel positioning information output by the pixel positioning circuit and a preset backlight operation algorithm;

[0096] The LCD control module is configured to generate LCD display grayscale data according to the pixel data, the pixel positioning information output by the pixel positioning circuit and a preset grayscale compensation algorithm;

[0097] in:

[0098] The pixel positioning circuit is configured to determine, in each clock cycle, pixel positioning information for the current clock cycle based on the number of pixel data transmitted by the N data channels and an ID sequence; wherein the pixel positioning information includes a backlight partition size, a partition boundary signal, and backlight partition information; the backlight partition size is the maximum number of pixel data that can be mapped to a row or a column in a backlight partition; the ID sequence is obtained by sequentially encoding the sizes of the J backlight partitions or the sizes of the K backlight partitions, the ID sequence comprising J sequentially arranged IDs or K sequentially arranged IDs corresponding one-to-one to the sizes of the J backlight partitions or the sizes of the K backlight partitions; the partition boundary signal is used to indicate whether pixel data transmitted via the N data channels in the next clock cycle is at least partially mapped to a new backlight partition, the new backlight partition being the next backlight partition located in the same row or column as the current backlight partition and adjacent to the current backlight partition; and the backlight partition information is configured to indicate the backlight partition to which the pixel data transmitted by the N data channels in the current clock cycle is mapped;

[0099] Among them, W, H, J, K and N are natural numbers.

[0100] The pixel data corresponds to the pixel, that is, one pixel corresponds to one pixel data.

[0101] In the embodiment of the present disclosure, the sizes of the J backlight partitions or the sizes of the K backlight partitions are sequentially encoded to obtain an ID sequence. In each clock cycle, the pixel positioning information of the current clock cycle is determined according to the number of pixel data transmitted by the N data channels and the ID sequence. This can solve the problem of a large amount of backlight partition information storage resources in some pixel positioning circuits, thereby reducing resource consumption.

[0102] For example, assume that the LCD display module includes 1920×1080 pixel units and the backlight module includes 24×54 backlight partitions. A row of the backlight module has 24 backlight partitions. For example, if the size of a backlight partition represents the maximum number of pixel data that can be mapped to a row of a backlight partition, and if the backlight partition size can be 37 pixels or 43 pixels, then a size of 37 pixels can be encoded as 0, and a size of 43 pixels can be encoded as 1. Assuming that the horizontal sizes of the backlight partitions from left to right are 37 pixels, 43 pixels, 37 pixels, 43 pixels…37 pixels, the ID sequence can be 0101…0.

[0103] For example, the number of data channels can be 8, meaning that 8 pixels of data are transmitted per clock cycle. The number of data channels can also be 1, 2, 4, or 16. Assuming that the size of a backlight partition represents the maximum number of pixel data that can be mapped to a row in a backlight partition, and assuming that the sizes of the backlight partitions are 16 pixels and 17 pixels, and the sizes of the backlight partitions from left to right are 16 pixels, 17 pixels, 16 pixels, 17 pixels... 16 pixels, 17 pixels, respectively, the ID sequence can be 0101...01. In the first clock cycle, the eight pixel data are mapped to the first backlight partition, and the partition boundary signal of the first clock cycle indicates that the pixel data transmitted through the N data channels in the next clock cycle will not be at least partially mapped to the new backlight partition. In the second clock cycle, the eight pixel data transmitted through the data channels are mapped to the first backlight partition. Since in the third clock cycle, the eight pixel data transmitted through the data channels can only be partially mapped to the first backlight partition, the partition boundary signal of the second clock cycle indicates that the pixel data transmitted through the N data channels in the next clock cycle will be at least partially mapped to the new backlight partition. In the third clock cycle, the number of pixel data transmitted through the data channels reaches 24, exceeding the maximum number of pixel data that can be mapped to a row of the first backlight partition. Therefore, the pixel data transmitted in the third clock cycle is mapped to the second backlight partition, and the partition boundary signal of the third clock cycle indicates that the pixel data transmitted through the N data channels in the next clock cycle will not be at least partially mapped to the new backlight partition.

[0104] FIG5 is a schematic diagram of a pixel positioning circuit according to an embodiment of the present disclosure. As shown in FIG5 , the pixel positioning circuit includes: a partition mark generation module, a partition ID control module, a partition size control module, a counting control module, and a backlight partition information generation module;

[0105] The partition flag generating module is configured to output a partition boundary signal and determine, in each clock cycle, whether pixel data transmitted through the N data channels in the next clock cycle is partially or completely mapped to a new backlight partition; when the determination result is yes, the partition boundary signal is set to be valid; when the determination result is no, the partition boundary signal is set to be invalid;

[0106] The partition ID control module is configured to store the ID sequence and output a current ID in each clock cycle, and to set the current ID to the first ID in the ID sequence in the first clock cycle when the system is powered on or pixel data is mapped to a new row or column; the partition ID control module is further configured to set the next ID in the ID sequence after the current ID in the ID sequence as the new current ID at the beginning of each clock cycle if the partition boundary signal is valid;

[0107] The partition size control module is configured to output the size of the backlight partition corresponding to the current ID according to the current ID output by the partition ID control module at the beginning of each clock cycle;

[0108] The counting control module is configured to determine, in each clock cycle, position information of the first pixel data in the current clock cycle based on the size of the backlight partition corresponding to the current ID and the number N of the data channels, and output the position information to the backlight partition information generation module; the first pixel data is pixel data transmitted by the last channel in the data channels; the position information is used to indicate the row or column of the backlight partition to which the first pixel data is mapped, the first pixel data being the Xth pixel data mapped in the row or column, where X is a natural number; wherein the pixel data mapped to a row or column of each backlight partition are sorted respectively;

[0109] The backlight partition information generation module is configured to output the backlight partition information whenever it receives the position information of the first pixel output by the counting control module; wherein, when the partition boundary signal is invalid, the backlight partition information is a value used to indicate that all N pixel data transmitted by the N data channels in the current clock cycle are mapped to one backlight partition; when the partition boundary signal is valid, the backlight partition information is a value used to indicate the mapping relationship between the N pixel data transmitted by the N data channels in the current clock cycle and the current backlight partition and the new backlight partition.

[0110] FIG6 is a schematic diagram of a partition ID control module according to an embodiment of the present disclosure. As shown in FIG6 , the partition ID control module includes a synchronous shift register chain, and the synchronous shift register chain includes J synchronous shift registers or K synchronous shift registers arranged in sequence.

[0111] The J synchronous shift registers are sequentially set to the J IDs stored in the ID sequence when the system is powered on or when pixel data is mapped to a new row or column; or the initial values ​​of the K synchronous shift registers are sequentially set to the K IDs stored in the ID sequence when the system is powered on or when pixel data is mapped to a new row or column; wherein the output end of the Jth synchronous shift register or the output end of the Kth synchronous shift register is configured to output the current ID;

[0112] The synchronous shift register chain is further configured to trigger a shift at the beginning of each clock cycle when the partition boundary signal is valid; wherein each shift uses the ID in the i-th synchronous shift register to replace the ID in the i+1-th synchronous shift register; i is each integer from 1 to J-1 or each integer from 1 to K-1.

[0113] Each synchronous shift register can store an ID.

[0114] In an exemplary embodiment, the synchronous shift register is a D flip-flop; in the synchronous shift register chain, the Q output terminal of the i-th D flip-flop is connected to the D input terminal of the i+1-th D flip-flop when the partition boundary signal is valid;

[0115] The output value of the Q output terminal of the D flip-flop changes to the value of the D input terminal at the beginning of each clock cycle.

[0116] In an exemplary embodiment, the partition ID control module further includes:

[0117] J-1 first multiplexers, corresponding one-to-one to the first to the J-1th D flip-flops; or K-1 first multiplexers, corresponding one-to-one to the first to the K-1th D flip-flops;

[0118] The positive output terminal of the i-th D flip-flop is connected to the first input terminal of the i-th first multiplexer, the output terminal of the i-th first multiplexer is connected to the D input terminal of the (i+1)-th D flip-flop; the Q output terminal of the J-th D flip-flop or the Q output terminal of the K-th D flip-flop is connected to the partition size control module;

[0119] The first multiplexer is configured to enable the first input terminal when the partition boundary signal is valid.

[0120] In an exemplary embodiment, the bit width of the synchronous shift register chain is determined according to the number of specifications of the J backlight partitions or the number of specifications of the K backlight partitions; wherein the number of specifications refers to the number of types formed by the sizes of the backlight partitions according to different sizes.

[0121] For example, J backlight sub-areas have only two sizes: A1 and A2. Assuming A1 = 16 pixels and A2 = 17 pixels, the bit width of the synchronous shift register chain is 1. Because a bit width of 1 can represent two cases, for example, 0 and 1 represent A1 and A2, respectively. K backlight sub-areas have four sizes: B1, B2, B3, and B4. Therefore, the bit width of the synchronous shift register chain is 2. Because a bit width of 2 can represent four cases, for example, 00, 01, 10, and 11 represent B1, B2, B3, and B4, respectively.

[0122] FIG7 is a schematic diagram of a partition size control module according to an embodiment of the present disclosure. As shown in FIG7 , the partition size control module includes: a first register module and a second multiplexer;

[0123] Different input terminals of the second multiplexer are configured to receive the size of each backlight partition respectively, and the output terminal is configured to be connected to the first register module; the second multiplexer is configured to select the corresponding input terminal according to the current ID output by the partition ID control module;

[0124] The output end of the first register module is electrically connected to the counting control module, and is configured to change the output to the size of the backlight partition corresponding to the current ID at the beginning of each clock cycle.

[0125] In an exemplary embodiment, the first register module may include a plurality of D flip-flops.

[0126] FIG8 is a schematic diagram of a counting control module according to an embodiment of the present disclosure. As shown in FIG8 , the counting control module includes an adding unit, a first comparing unit, a subtracting unit, a third multiplexer, and a remainder unit.

[0127] The adding unit is configured to, in each clock cycle, add N to the position information of the first pixel in the previous clock cycle to obtain an accumulated value in the current clock cycle when the partition boundary signal is invalid; and add N to the output value of the subtracting unit in the previous clock cycle to obtain an accumulated value in the current clock cycle when the partition boundary signal is valid;

[0128] The subtraction unit is configured to calculate a first difference value; the first difference value is the absolute value of the difference obtained by subtracting the output value of the partition size control module from the accumulated value of the current clock cycle;

[0129] The first comparing unit is configured to perform a first comparison between the accumulated value of the current clock cycle obtained by the adding unit and the size of the backlight partition corresponding to the current ID output by the partition size control module to obtain a first comparison result of the current clock cycle;

[0130] The first input terminal of the third multiplexer is connected to the output terminal of the adding unit, and the second input terminal is connected to the output terminal of the subtracting unit, and is configured to select one from the first difference and the accumulated value of the current clock cycle as the position information of the first pixel in the current clock cycle according to the first comparison result;

[0131] The remainder unit is configured to calculate a remainder obtained by dividing the first difference by N.

[0132] In an exemplary embodiment, the third multiplexer is configured to connect the second input terminal when the first comparison result indicates that the accumulated value of the current clock cycle is greater than the value output by the partition size control module; and is configured to connect the first input terminal when the first comparison result indicates that the accumulated value of the current clock cycle is less than or equal to the value output by the partition size control module.

[0133] FIG9 is a schematic diagram of a backlight partition information generation module according to an embodiment of the present disclosure. As shown in FIG9 , the backlight partition information generation module includes a fourth multiplexer and a fifth multiplexer;

[0134] One of the two input terminals of the fourth multiplexer is configured to be connected to the output terminal of the fifth multiplexer, and the other of the two input terminals of the fourth multiplexer is configured to receive a first preset value; the output terminal is configured to output the output of the fifth multiplexer as the backlight partition information when the partition boundary signal is valid; and to output the first preset value as the backlight partition information when the partition boundary signal is invalid; wherein the first preset value is used to indicate that all N pixels transmitted through the data channel in the current clock cycle correspond to one partition;

[0135] The N input terminals of the fifth multiplexer are configured to be connected to N second preset values, respectively; the output terminal is configured to select one input terminal among the N input terminals according to the remainder output by the counting control module; the N second preset values ​​respectively represent N situations in which the N pixels transmitted through the data channel in the current clock cycle correspond to two partitions.

[0136] Exemplarily, the first preset value may be 00000000, indicating that all N pixels transmitted through the data channel in the current cycle correspond to one partition. Taking the data channel as 8 channels (channel 0 to channel 7) as an example, the 8 second preset values ​​may include: 11111111 (indicating that 8 pixels transmitted through the preset pixel transmission channel in the current cycle are located in the old partition), 11111110 (indicating that 7 pixels transmitted through the preset pixel transmission channel in the current cycle are located in the old partition, and 1 pixel is located in the new partition), 11111100 (indicating that 6 pixels transmitted through the preset pixel transmission channel in the current cycle are located in the old partition, and 2 pixels are located in the new partition), 11111000 (indicating that 5 pixels transmitted through the preset pixel transmission channel in the current cycle are located in the old partition), and 11111000 (indicating that 5 pixels transmitted through the preset pixel transmission channel in the current cycle are located in the old partition). , 3 pixels are located in the new partition), 11110000 (indicating that 4 pixels transmitted through the preset pixel transmission channel in the current cycle are located in the old partition, and 4 pixels are located in the new partition), 11100000 (indicating that 3 pixels transmitted through the preset pixel transmission channel in the current cycle are located in the old partition, and 5 pixels are located in the new partition), 11000000 (indicating that 2 pixels transmitted through the preset pixel transmission channel in the current cycle are located in the old partition, and 6 pixels are located in the new partition), 10000000 (indicating that 1 pixel transmitted through the preset pixel transmission channel in the current cycle is located in the old partition, and 7 pixels are located in the new partition). The correspondence between the remainder and the output value of the fifth multiplexer is shown in Table 1.

[0137] Table 1 Correspondence between remainder and output value of the fifth multiplexer

[0138] FIG10 is a schematic diagram of a partition mark generation module according to an embodiment of the present disclosure. As shown in FIG10 , the partition mark generation module includes a second comparison unit, a third comparison unit, a boundary signal generation unit, and a storage unit;

[0139] The storage unit is configured to store the size output by the partition size control module in the previous clock cycle;

[0140] The second comparison unit is configured to perform a second comparison between the first sum value and the size output by the partition size control module to obtain a second comparison result, wherein the first sum value is the sum of the position information of the first pixel in the current clock cycle output by the counting control module and N;

[0141] The third comparison unit is configured to perform a third comparison between the position information of the first pixel in the current clock cycle output by the counting control module and the size stored in the storage unit to obtain a third comparison result;

[0142] The boundary signal generating unit is configured to output a valid or invalid partition boundary signal according to the second comparison result and the third comparison result.

[0143] In an exemplary embodiment, when the first sum value is greater than or equal to the size output by the partition control module, the second comparison result is a preset first logic value; when the first sum value is less than the size output by the partition control module, the second comparison result is a preset second logic value;

[0144] When the size stored in the storage unit is equal to the position information of the first pixel data in the current clock cycle, the third comparison result is a preset first logic value; when the size stored in the storage unit is not equal to the position information of the first pixel data in the current clock cycle, the third comparison result is a preset second logic value;

[0145] The boundary signal generating unit outputs the valid partition boundary signal when and only when the third comparison result is the preset second logic value and the second comparison result is the preset first logic value; and outputs an invalid partition boundary signal when the third comparison result is the first logic value, or when the third comparison result is the preset second logic value and the second comparison result is the preset second logic value.

[0146] [Corrected 26.02.2024 in accordance with Rule 91] Figure 11 is a schematic diagram of another partition mark generation module of an embodiment of the present disclosure. As shown in Figure 11, the partition mark generation module includes a second comparison unit 110, a third comparison unit 130, a boundary signal generation unit 140, and a storage unit 120. The second comparison unit 110 includes an adder and a first comparator, the output of the adder is connected to one input of the first comparator, and the position information of the first pixel and N serve as inputs of the adder. The other input of the first comparator is the partition size of the current cycle. The storage unit 120 includes a register. The third comparison unit 130 includes a second comparator. The boundary signal generation unit 140 includes a third comparator and a fourth comparator. 1'b1 in Figure 11 represents a binary number 1, and 1'b0 represents a binary number 0. The clock signal represents a clock cycle signal.

[0147] The working process of the pixel positioning circuit is explained using the overall circuit as an example.

[0148] The number of data channels is preset to 8. Assume that the backlight partition size represents the maximum number of pixel data that can be mapped into a row within a backlight partition. Assume that the backlight partition sizes are 16 pixels and 17 pixels, and the horizontal backlight partition sizes from left to right are 16 pixels, 17 pixels, 16 pixels, 17 pixels, ... 16 pixels, respectively. The ID sequence can be 0101 ... 0. Assume that flag represents a partition boundary signal. Flag = 0 indicates that the partition boundary signal is invalid, and flag = 1 indicates that the partition boundary signal is valid.

[0149] When the system is powered on, the ID sequence is assigned to the synchronous shift register chain.

[0150] The first clock cycle: not a partition boundary, flag = 0.

[0151] The partition ID control module outputs the ID of the first backlight partition. The partition size control module outputs the size of the first backlight partition.

[0152] For the counting control module, the output value of the addition unit is 8, the output value of the subtraction unit is 8, the output value of the remainder unit is 0, and the output of the first comparison unit is 0 (assuming that the output value of the addition unit is less than or equal to the size of the current backlight partition, the output of the first comparison unit is 0, and the output value of the addition unit is greater than the size of the current backlight partition, the output of the first comparison unit is 1), and the third multiplexer outputs the output value of the addition unit 8. 8 is the position information of the first pixel in the current cycle.

[0153] For the backlight partition information generation module, since flag = 0 (the output value of the fifth selection unit is not considered, only the output value of the fourth selection unit is output), the output value of the fourth selection unit is a first preset value. The first preset value can be 00000000, indicating that all pixel data transmitted through the preset pixel transmission channel in the current cycle are mapped to the same partition.

[0154] For the partition mark generation module, since the position of the first pixel is 8, the value after adding 8 is 16 (i.e., the first sum value), 16 is compared with the size of the current backlight partition 16, and the second comparison unit outputs a logic 1 (based on the fact that when the first sum value is greater than or equal to the size output by the partition control module, the second comparison result is a preset first logic value), the third comparison unit outputs a logic 0 (8 is compared with the size of the current backlight partition 16, and the two are not equal, so a logic 0 is output), and the boundary signal generation unit outputs a valid partition boundary signal; that is, the output of the partition mark generation module is 1, indicating that the next cycle is a partition boundary.

[0155] The second clock cycle: is the partition boundary, flag = 1.

[0156] For the partition ID control module, synchronous shifting is performed to shift the ID corresponding to the second backlight partition to the output end of the synchronous shift register chain. The partition size control module still outputs the size of the first backlight partition.

[0157] For the counting control module, the output value of the addition unit is 16, the output value of the subtraction unit is 0, the output value of the remainder unit is 0, the output of the first comparison unit is logic 0, and the output of the third multiplexer is 16, which is the position information of the first pixel in the current cycle.

[0158] For the backlight partition information generation module, since flag = 1 (the output value of the fourth selection unit is not considered, only the output value of the fifth selection unit is output), the fifth selection unit outputs 11111111 among the N second preset values ​​according to the output value 0 of the remainder unit of the current cycle, indicating that all pixel data transmitted through the preset pixel transmission channel in the current cycle are mapped to the old partition.

[0159] For the partition mark generation module, the second comparison unit outputs logic 1 (when the first summation value is greater than or equal to the size output by the partition control module, the second comparison result is a preset first logic value. Since the position of the first pixel is 16, adding 8 equals 24 (i.e., the first summation value), and 24 is greater than the size of the current backlight partition 16, so logic 1 is output). The third comparison unit outputs logic 1 (when the size stored in the storage unit is equal to the position information of the first pixel data of the current clock cycle, the third comparison result is the preset first logic value. 16 is compared with the size of the current backlight partition 16 and the two are equal, so logic 1 is output). When the third comparison result is the first logic value, or when the third comparison result is the preset second logic value and the second comparison result is the preset second logic value, an invalid partition boundary signal is output; that is, the output of the partition mark generation module is 0, indicating that the next cycle is not a partition boundary.

[0160] The third clock cycle: not a partition boundary, flag = 0.

[0161] The partition size control module outputs the value of the output terminal of the synchronous shift register chain, which is the size of the next backlight partition, 17 pixels. It is a partition adjacent to the partition corresponding to the first clock cycle, and the partition corresponding to the third clock cycle is the next partition of the partition corresponding to the first clock cycle.

[0162] For the counting control module, the output value of the addition unit is 0+8=8 (the output value of the subtraction unit in the previous cycle is added to data channel 8), the output value of the subtraction unit is 9, the output value of the remainder unit is 1, the output value of the first comparison unit is logic 0, and the third multiplexer outputs the output value of the addition unit 8. 8 is the position of the first pixel in the current cycle.

[0163] For the backlight partition information generation module, since flag = 0 (the output value of the fifth selection unit is not considered, only the output value of the fourth selection unit is output), the output value of the fourth selection unit is a first preset value. The first preset value can be 00000000, indicating that all pixel data transmitted through the preset pixel transmission channel in the current cycle are mapped to the same partition.

[0164] For the partition mark generation module, the second comparison unit outputs logic 0 (according to the second comparison result being the preset second logic value when the first sum value is smaller than the size output by the partition control module, since the position of the first pixel is 8, the sum after adding 8 is 16 (i.e., the first sum value), and 16 is smaller than the size of the current backlight partition 17, so logic 0 is output), and the third comparison unit outputs logic 1 (according to the third comparison result being the preset first logic value when the size stored in the storage unit is equal to the position information of the first pixel data of the current clock cycle, 8 is compared with the size of the current backlight partition 17, and the two are not equal, so logic 0 is output), and when the third comparison result is the preset second logic value (0) and the second comparison result is the preset second logic value (0), an invalid partition boundary signal is output; that is, the output of the partition mark generation module is 0, indicating that the next cycle is not a partition boundary.

[0165] The fourth clock cycle: not a partition boundary, the partition signal flag=0.

[0166] The output values ​​of the partition size control module and the partition ID control module remain unchanged.

[0167] For the counting control module, the output value of the addition unit is 8+8=16 (determined based on the position information of the first pixel in the previous cycle and data channel 8), the output value of the subtraction unit is 1, the output value of the remainder unit is 1, the output value of the first comparison unit is logic 0, and the third multiplexer outputs the output value of the addition unit 16. 16 is the position of the first pixel in the current cycle.

[0168] For the backlight partition information generation module, since flag = 0 (the output value of the fifth selection unit is not considered, only the output value of the fourth selection unit is output), the output value of the fourth selection unit is a first preset value. The first preset value can be 00000000, indicating that all pixel data transmitted through the preset pixel transmission channel in the current cycle are mapped to the same partition.

[0169] For the partition boundary signal generation module, the second comparison unit outputs 1 (when the first summation value is greater than or equal to the size output by the partition control module, the second comparison result is a preset first logic value. Since the position of the first pixel is 16, adding 8 is 24 (i.e., the first summation value), and 24 is greater than the size of the current backlight partition 17, so logic 1 is output), and the third comparison unit outputs logic 0 (when the size stored in the storage unit is not equal to the position information of the first pixel data of the current clock cycle, the third comparison result is a preset second logic value. Compared with the size of the current backlight partition 17, the two are not equal, so logic 0 is output). When the third comparison result is the preset second logic value and the second comparison result is the preset first logic value, the valid partition boundary signal is output; the boundary signal generation unit outputs a valid partition boundary signal; that is, the output of the partition mark generation module is 1, indicating that the next cycle is a partition boundary.

[0170] The fifth clock cycle: is the partition boundary, the partition signal flag=1.

[0171] The partition ID control module performs synchronous shifting to shift the ID corresponding to the third backlight partition to the output end of the synchronous shift register chain. The partition size control module still outputs the size of the second backlight partition.

[0172] For the counting control module, the output value of the addition unit is 24, the output value of the subtraction unit is 7 (24-17=7), the output value of the remainder unit is 7, the output value of the first comparison unit is 1, and the third multiplexer outputs the output value of the subtraction unit 7. 7 is the position of the first pixel in the current cycle.

[0173] For the backlight partition information generation module, since flag = 1 (the output value of the fourth selection unit is not considered, and only the output value of the fifth selection unit is output), the output value of the fifth selection unit is one of N second preset values. The second preset value determined based on the position information of the first pixel in the current cycle is 1000000, indicating that one pixel transmitted through the preset pixel transmission channel in the current cycle is located in the old partition and seven pixels are located in the new partition. The fourth selection unit selects the output value of the fifth selection unit for output.

[0174] For the partition mark generation module, the second comparison unit outputs a logic 0 (based on the fact that when the first summed value is smaller than the size output by the partition control module, the second comparison result is a preset second logic value. Since the position of the first pixel is 7, adding 8 equals 15 (i.e., the first summed value), and 15 is smaller than the size of the current backlight partition, 17, so a logic 0 is output). The third comparison unit outputs a logic 0 (based on the fact that when the size stored in the storage unit is equal to the position information of the first pixel data of the current clock cycle, the third comparison result is a preset first logic value. Compared with 7, the size of the current backlight partition, 17, they are not equal, so a logic 0 is output). When the third comparison result is the preset second logic value and the second comparison result is the preset second logic value, an invalid partition boundary signal is output; that is, the output of the partition mark generation module is 0, indicating that the next cycle is not a partition boundary.

[0175] The pixel positioning circuit described in the embodiment of the present disclosure uses less than 8 bits (which can be 1 bit or 2 bits) of ID information for each backlight partition instead of the 8-bit backlight partition size, which greatly reduces the amount of resources occupied by partition parameter configuration.

[0176] In some exemplary embodiments, N in N data channels may include 1, 2, 4, 8, 16, etc., and thus the pixel positioning circuit may be configured to support the above-mentioned N data channels, where N may include 1, 2, 4, 8, 16, etc.

[0177] In some exemplary embodiments, the partitions supported in the H and V directions may be E types (E≥1) of specifications: that is, the same backlight (H direction or V direction) may also support one or more partition specifications, and the arrangement may be customized.

[0178] In some exemplary embodiments, since the circuit architecture of the pixel positioning circuit is mainly composed of a shift register chain, a counter, and a multiplexer, and does not involve complex arithmetic circuits, the operation speed is very fast. The main clock frequency thereof can reach over 250 MHz when simulated using the Vivado tool.

[0179] In some exemplary embodiments, the pixel positioning circuit can achieve a 0clk delay, that is, the positioning information of the pixel data can be directly provided in the current clock cycle without storing the original pixel information.

[0180] An embodiment of the present disclosure further provides an electronic device, including any of the display devices described above.

[0181] The electronic devices include but are not limited to displays, mobile communication devices, and wearable devices.

[0182] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the functional modules / units mentioned in the above description are not divided equally; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0183] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display device, the display device includes an LCD display module, a backlight module, and a display driver chip; the display driver chip includes a pixel positioning circuit, N data channels arranged in sequence, an LCD control module, and a backlight control module; The LCD display module is disposed on the light-emitting side of the backlight module and includes W×H pixel units; The backlight module includes J×K backlight zones, and each backlight zone is configured to provide backlight for pixel units corresponding to physical positions on the LCD display module; wherein, The total number of pixel units corresponding to all J backlight zones in each row is equal to the total number of pixel units W in each row of the LCD display module, and the total number of pixel units corresponding to all K backlight zones in each column is equal to the total number of pixel units H in each column of the LCD display module; The N data channels are configured to sequentially transmit pixel data to the pixel positioning circuit in each clock cycle; the clock cycle is determined according to the refresh frequency of the display device; The backlight control module is configured to generate backlight data according to the pixel data, the pixel positioning information output by the pixel positioning circuit, and a preset backlight operation algorithm and provide the backlight data to the backlight module; The LCD control module is configured to generate LCD display gray-scale data according to the pixel data, the pixel positioning information output by the pixel positioning circuit, and a preset gray-scale compensation algorithm and provide the LCD display gray-scale data to the LCD display module; Wherein: The pixel positioning circuit is configured to respectively determine the pixel positioning information of the current clock cycle according to the number of pixel data transmitted by the N data channels and the ID sequence in each clock cycle; wherein, the pixel positioning information includes the size of the backlight zone, the partition boundary signal, and the backlight zone information; the size of the backlight zone is the maximum number of pixel data that can be mapped by one row or one column in a backlight zone; the ID sequence is obtained by sequentially encoding the sizes of the J backlight zones or the sizes of the K backlight zones, and the ID sequence contains J IDs arranged in sequence or K IDs arranged in sequence, which correspond one-to-one to the sizes of the J backlight zones or the sizes of the K backlight zones arranged in sequence; the partition boundary signal is used to indicate whether at least part of the pixel data transmitted through the N data channels in the next clock cycle is mapped to a new backlight zone, and the new backlight zone refers to the next backlight zone that is in the same row or the same column as the current backlight zone and is adjacent to the current backlight zone; the backlight zone information is set to indicate the backlight zone to which the pixel data transmitted by the N data channels in the current clock cycle is mapped; Wherein, W, H, J, K, and N are natural numbers.

2. The display device according to claim 1, wherein, The pixel positioning circuit includes: a partition flag generation module, a partition ID control module, a partition size control module, a counting control module, and a backlight zone information generation module; The partition flag generation module is configured to output a partition boundary signal and respectively determine in each clock cycle whether part or all of the pixel data transmitted through the N data channels in the next clock cycle is mapped to a new backlight zone; when the determination result is yes, set the partition boundary signal to be valid; when the determination result is no, set the partition boundary signal to be invalid; The partition ID control module is configured to store the ID sequence and output the current ID in each clock cycle. Whenever in the first clock cycle after the system is powered on or pixel data is mapped to a new row or column, the current ID is set to the first ID in the ID sequence; the partition ID control module is further configured to, at the beginning of each clock cycle, if the partition boundary signal is valid, take the next ID after the current ID in the ID sequence as the new current ID according to the arrangement order of the IDs in the ID sequence; The partition size control module is configured to, at the beginning of each clock cycle, output the size of the backlight partition corresponding to the current ID according to the current ID output by the partition ID control module; The counting control module is configured to determine the position information of the first pixel data in the current clock cycle according to the size of the backlight partition corresponding to the current ID and the number N of channels of the data channel respectively in each clock cycle and output it to the backlight partition information generation module; the first pixel data is the pixel data transmitted by the last channel in the data channel; the position information is used to indicate that for the row or column of the backlight partition mapped by the first pixel data, the first pixel data is the Xth pixel data mapped in that row or column, where X is a natural number; among them, the pixel data mapped to one row or one column of each backlight partition is sorted separately; The backlight partition information generation module is configured to output the backlight partition information whenever receiving the position information of the first pixel output by the counting control module; among them, when the partition boundary signal is invalid, the backlight partition information is a value used to indicate that the N pixel data transmitted by the N data channels in the current clock cycle are all mapped to one backlight partition; when the partition boundary signal is valid, the backlight partition information is a value used to indicate the mapping relationship between the N pixel data transmitted by the N data channels in the current clock cycle and the current backlight partition and the new backlight partition.

3. The display device according to claim 2, wherein, The partition ID control module includes a synchronous shift register chain, and the synchronous shift register chain includes J synchronous shift registers arranged in sequence or K synchronous shift registers; The J synchronous shift registers are sequentially set to J IDs in the ID sequence; or the initial values of the K synchronous shift registers are sequentially set to K IDs in the ID sequence; among them, the output end of the Jth synchronous shift register or the output end of the Kth synchronous shift register is configured to output the current ID; The synchronous shift register chain is configured to trigger a shift once at the beginning of each clock cycle when the partition boundary signal is valid; among them, each shift is to use the ID in the ith synchronous shift register to replace the ID in the (i + 1)th synchronous shift register; i is each integer from 1 to J - 1 or i is each integer from 1 to K - 1 respectively.

4. The display device according to claim 3, wherein, The synchronous shift register is a D flip-flop; in the synchronous shift register chain, the Q output terminal of the i-th D flip-flop is connected to the D input terminal of the (i + 1)-th D flip-flop when the partition boundary signal is valid; i is each integer from 1 to M - 1; The output value of the Q output terminal of the D flip-flop changes to the value of the D input terminal at the beginning of each clock cycle.

5. The display device according to claim 4, wherein, The partition ID control module further includes: J - 1 first multiplexers, corresponding to the first to the (J - 1)-th D flip-flops one by one; or K - 1 first multiplexers, corresponding to the first to the (K - 1)-th D flip-flops one by one; The positive output terminal of the i-th D flip-flop is connected to the first input terminal of the i-th first multiplexer, and the output terminal of the i-th first multiplexer is connected to the D input terminal of the (i + 1)-th D flip-flop; the Q output terminal of the J-th D flip-flop or the Q output terminal of the K-th D flip-flop is connected to the partition size control module; The first multiplexer is set to select the first input terminal when the partition boundary signal is valid.

6. The display device according to any one of claims 3-5, wherein: The bit width of the synchronous shift register chain is determined according to the number of specifications of the J backlight partitions or the number of specifications of the K backlight partitions; wherein the number of specifications refers to the number of types formed by the sizes of the backlight partitions in different sizes.

7. The display device according to claim 2, wherein, The partition size control module includes: A first register module and a second multiplexer; Different input terminals of the second multiplexer are set to receive the sizes of each backlight partition respectively, and the output terminal is set to be connected to the first register module; the second multiplexer is set to select the corresponding input terminal according to the current ID output by the partition ID control module; The output terminal of the first register module is electrically connected to the counting control module, and is set to change to output the size of the backlight partition corresponding to the current ID at the beginning of each clock cycle.

8. The display device according to claim 2, The counting control module includes an addition unit, a first comparison unit, a subtraction unit, a third multiplexer and a remainder unit; The addition unit is configured to, in each clock cycle, when the partition boundary signal is invalid, add N to the position information of the first pixel in the previous clock cycle to obtain the accumulated value in the current clock cycle; When the partition boundary signal is valid, add N to the output value of the subtraction unit in the previous clock cycle to obtain the accumulated value in the current clock cycle; The subtraction unit is set to calculate a first difference; The first difference is the absolute value of the difference obtained by subtracting the output value of the partition size control module from the accumulated value in the current clock cycle; The first comparison unit is set to perform a first comparison between the accumulated value in the current clock cycle obtained by the addition unit and the output value of the partition size control module to obtain the first comparison result in the current clock cycle; The first input terminal of the third multiplexer is connected to the output terminal of the addition unit, and the second input terminal is connected to the output terminal of the subtraction unit, and is set to select one of the first difference and the accumulated value in the current clock cycle as the position information of the first pixel in the current clock cycle according to the first comparison result; The remainder unit is set to calculate the remainder obtained by dividing the first difference by N.

9. The display device according to claim 8, wherein: When the first comparison result is that the accumulated value of the current clock cycle is greater than the output value of the partition size control module, the third multiplexer gates and connects to the second input terminal; when the first comparison result is that the accumulated value of the current clock cycle is less than or equal to the value output by the partition size control module, the third multiplexer gates and connects to the first input terminal.

10. The display device according to claim 2, wherein, The backlight partition information generation module includes a fourth multiplexer and a fifth multiplexer; The two input terminals of the fourth multiplexer are respectively set to connect to the output terminal of the fifth multiplexer and receive a first preset value; the output terminal is set to use the output of the fifth multiplexer as the pixel positioning information output when the partition boundary signal is valid; and use the first preset value as the pixel positioning information output when the partition boundary signal is invalid; wherein, the first preset value is used to indicate that all N pixel data transmitted through the data channel in the current clock cycle correspond to one partition; The fifth multiplexer has N input terminals set to respectively connect to N second preset values; the output terminal is set to gate and connect to one of the N input terminals according to the remainder output by the counting control module; the N second preset values respectively represent N cases where the N pixel data transmitted through the data channel in the current clock cycle correspond to two partitions.

11. The display device according to claim 2, wherein, The partition flag generation module includes a second comparison unit, a third comparison unit, a boundary signal generation unit, and a storage unit; The storage unit is set to save the size output by the partition size control module in the previous clock cycle; The second comparison unit is set to perform a second comparison between the first summation value and the size output by the partition size control module to obtain a second comparison result, wherein the first summation value is the sum of the position information of the first pixel in the current clock cycle output by the counting control module and N; The third comparison unit is set to perform a third comparison between the position information of the first pixel in the current clock cycle output by the counting control module and the size saved in the storage unit to obtain a third comparison result; The boundary signal generation unit is set to output the valid or invalid partition boundary signal according to the second comparison result and the third comparison result.

12. The display device according to claim 11, wherein, When the first summation value is greater than or equal to the size output by the partition control module, the second comparison result is a preset first logic value; when the first summation value is less than the size output by the partition control module, the second comparison result is a preset second logic value; When the size saved in the storage unit is equal to the position information of the first pixel data in the current clock cycle, the third comparison result is a preset first logic value; When the size saved in the storage unit is not equal to the position information of the first pixel data in the current clock cycle, the third comparison result is a preset second logic value; The boundary signal generating unit outputs the valid partition boundary signal if and only if the third comparison result is the preset second logical value and the second comparison result is the preset first logical value; when the third comparison result is the first logical value, or when the third comparison result is the preset second logical value and the second comparison result is the preset second logical value, an invalid partition boundary signal is output.

13. An electronic device, comprising the display device according to any one of claims 1 to 12.

Images