Semiconductor structure forming method

Abstract

A semiconductor structure forming method, comprising: providing a substrate having a first conductivity type, wherein the substrate has a first surface; forming in the substrate an initial trench recessed relative to the first surface; forming a storage doped region in the substrate on two sides of the bottom of the initial trench, wherein the storage doped region is of the first conductivity type, and the doping concentration of the storage doped region is greater than the doping concentration of the substrate; and after the storage doped region is formed, etching the bottom of the initial trench, and forming a trench in the substrate, wherein the bottom of the trench is lower than the bottom of the storage doped region. By means of the forming method provided in the present technical solution, a storage doped region can be formed at an expected depth of a substrate.

Description

Method for forming semiconductor structure Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] The insulated gate bipolar transistor (IGBT) is one of the most important devices in power semiconductors today. It has the advantages of MOSFET, such as easy driving, simple control, and high switching frequency, as well as the advantages of power transistor, such as low on-state voltage, large on-state current, and low loss. Therefore, it has been widely used in power grids, rail transportation, electric vehicles, industrial frequency conversion, and home appliances.

[0003] The future development of IGBT products will primarily follow two paths: ultra-thin wafer IGBT process technology and IGBT surface structure design. Surface structure design primarily improves performance by increasing the carrier concentration on the emitter side. This is achieved by implanting a high-energy N-type region beneath the IGBT's P-substrate and then diffusing it to form a storage doping region. This allows holes to accumulate beneath the P-substrate when the device is turned on, thereby increasing the carrier concentration on the emitter side during forward conduction, enhancing the device's conductivity modulation effect and reducing the device's forward conduction voltage drop. The storage doping region must reach a predetermined depth within the substrate. Traditional methods for forming this region require ultra-high-energy ion implantation and an extremely long thermal process to achieve this depth. However, ultra-high-energy ion implantation often exceeds the operating capacity of the ion implantation equipment, and the extremely long thermal process often results in irreversible impacts on product performance.

[0004] Therefore, there is an urgent need to provide a method for forming a semiconductor structure, which can form a storage doping region within a predetermined depth of a substrate without requiring high energy and a long thermal process.

[0005] Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can form a storage doping region at a desired depth of a substrate.

[0007] To solve the above technical problems, an embodiment of the present invention provides a substrate having a first conductive type, the substrate having a first surface; an initial trench recessed relative to the first surface is formed in the substrate; a storage doping region is formed in the substrate on both sides of the bottom of the initial trench, the storage doping region is of the first conductive type, and the doping concentration of the storage doping region is greater than the doping concentration of the substrate; after forming the storage doping region, the bottom of the initial trench is etched to form a trench in the substrate, and the bottom of the trench is lower than the bottom of the storage doping region.

[0008] Optionally, the ratio of the depth of the initial groove to the depth of the groove is in a range of 0.2 to 0.99.

[0009] Optionally, the depth of the initial groove is 1 micron to 5 microns; the depth of the groove is 3 microns to 7 microns.

[0010] Optionally, the distance from the top of the storage doping region to the substrate surface is 0.5 microns to 5 microns.

[0011] Optionally, the method for forming storage doping regions in the substrate on both sides of the bottom of the initial trench includes: injecting first conductive type ions into the bottom of the initial trench, and annealing the substrate to form storage doping regions in the substrate on both sides of the bottom of the initial trench.

[0012] Optionally, the ion implantation dose of the first conductive type ions is 5E11atom / cm 2 ~5E14atom / cm 2 The implantation energy is 0 KeV to 2 MeV, and the angle between the implantation direction of the first conductive type ions and the substrate normal is 0° to 50°.

[0013] Optionally, the annealing treatment is performed at a temperature of 800° C. to 1200° C. and for a time of 5 min to 300 min.

[0014] Optionally, the first conductivity type is N-type.

[0015] Optionally, before forming the initial trench, the method further includes forming a mask layer on the substrate to expose a portion of the surface of the substrate, and etching the substrate to form the initial trench using the mask layer as a mask.

[0016] Optionally, the material of the mask layer includes one or more combinations of oxides or nitrides.

[0017] Optionally, it also includes: forming a base doping region in contact with the storage doping region in the substrate, the base doping region is located on the top of the storage doping region, the base doping region is of the second conductivity type, and the second conductivity type is opposite to the first conductivity type; forming an emitter doping region in the substrate on both sides of the trench, the emitter doping region is located on the top of the base doping region, the emitter doping region is of the first conductivity type, and the doping concentration of the emitter doping region is greater than the doping concentration of the substrate; forming a gate structure in the trench; forming a collector doping region in the second surface of the substrate, the collector doping region is of the second conductivity type, the second surface is opposite to the first surface, and a buffer layer is provided between the collector doping region and the storage doping region.

[0018] Optionally, it also includes: forming a contact region in the substrate, the contact region is of the second conductivity type, and the contact region is located on the top of the base doping region, and the doping concentration of the contact region is greater than the doping concentration of the base doping region.

[0019] Optionally, the gate structure includes a gate dielectric layer located on the sidewalls and bottom surface of the trench, and a gate layer located on the gate dielectric layer.

[0020] Optionally, the method further includes: forming an emitter conductive layer on the top of the emitter doping region; and forming a collector conductive layer on a side of the collector doping region away from the substrate.

[0021] Optionally, the second conductivity type is P type.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0023] The method for forming a semiconductor structure provided by the present technical solution forms an initial trench in a substrate, and then forms a storage doping region in the substrate on both sides of the bottom of the initial trench. The bottom of the initial trench can be used as a depth positioning for forming the storage doping region, and the depth of the formed storage doping region in the substrate can be easily controlled, thereby forming the storage doping region within the expected depth of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] 1 to 11 are schematic structural diagrams corresponding to steps in a process of forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0025] As described in the background technology, IGBT semiconductor devices require the formation of a storage doping region within the desired depth of the substrate. The currently commonly used method for forming the storage doping region is to directly implant high-energy ions into the substrate and then propel the ions through annealing. This method requires a great deal of heat and is difficult to propel the ions to the desired depth, resulting in poor process results.

[0026] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising providing a substrate of a first conductivity type, the substrate having a first surface; forming an initial trench recessed relative to the first surface in the substrate; forming storage doping regions in the substrate on both sides of the bottom of the initial trench, the storage doping regions being of the first conductivity type and having a doping concentration greater than the doping concentration of the substrate; after forming the storage doping regions, etching the bottom of the initial trench to form a trench in the substrate, the bottom of the trench being lower than the bottom of the storage doping region. First, an initial trench is formed in the substrate, the bottom of the initial trench is used as the depth positioning of the storage doping region in the substrate, and storage doping regions are formed in the substrate on both sides of the bottom of the initial trench, ensuring that the formed storage doping regions are at the expected depth of the substrate, so that the formation position of the storage doping regions is accurate and the energy required is small.

[0027] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] 1 to 11 are schematic structural diagrams corresponding to steps in a process of forming a semiconductor structure in one embodiment of the present invention.

[0029] 1 , a substrate 100 having a first conductivity type is provided. The substrate 100 has a first face 101 .

[0030] In this embodiment, the substrate 100 has a first surface 101 and a second surface 102 that are opposite to each other.

[0031] In this embodiment, the first conductivity type is N-type.

[0032] In this embodiment, the substrate 100 is a silicon substrate.

[0033] An initial trench recessed relative to the first surface 101 is formed in the substrate 100 .

[0034] 2 , before forming the initial trench, a mask layer 103 is formed on the first surface 101 of the substrate 100 to expose a portion of the surface of the substrate 100 .

[0035] The material of the mask layer 103 includes one or more combinations of oxides and nitrides. In this embodiment, the material of the mask layer 103 is ethyl silicate.

[0036] In this embodiment, the method for forming the mask layer 103 includes: forming a mask material layer (not shown) on the first surface 101 of the substrate 100; forming a photoresist layer (not shown) on the mask material layer; developing and exposing the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask, etching the mask material layer to form the mask layer 103; and removing the patterned photoresist layer.

[0037] 3 , the substrate 100 is etched using the mask layer 103 as a mask to form an initial trench 104 in the substrate 100 .

[0038] In this embodiment, the substrate 100 is etched using a dry etching process to form the initial trench 104 in the substrate 100 .

[0039] The depth of the initial trench 104 ranges from 1 micron to 5 microns. The bottom of the initial trench 104 provides depth positioning for the subsequent formation of a storage doping region. The depth of the initial trench 104 is a predetermined depth range of the storage doping region to be formed in the substrate 100 .

[0040] 4 and 5 , storage doped regions 105 are formed in the substrate 100 on both sides of the initial trench 104 .

[0041] The arrow direction in FIG4 indicates the ion implantation direction.

[0042] In this embodiment, the method for forming the storage doping region 105 includes: implanting first conductive type ions into the bottom of the initial trench 104 , and performing annealing on the substrate 100 .

[0043] In this embodiment, the first conductive type ions are N-type ions, and the N-type ions include phosphorus ions, arsenic ions, and the like.

[0044] Specifically, the implantation dose of the first conductive type ions is 5E11atom / cm 2 ~5E14atom / cm 2 , the injection energy is 0KeV~2MeV.

[0045] In this embodiment, the ion doping concentration of the storage doping region 105 is greater than the ion doping concentration of the substrate 100 .

[0046] It should be further explained that when the first conductive type ions are injected into the bottom of the initial trench 104, due to the presence of the mask layer 103, the first conductive type ions will not be directly injected into the substrate 100 covered by the mask layer 103; the injection angle of the first conductive type ions is 0°~50°, and the injection angle is the angle between the injection direction and the normal of the substrate 100. Ion injection at a certain angle can better inject the ions into the substrate 100 on both sides of the bottom of the initial trench 104, saving energy for subsequent annealing treatment.

[0047] In this embodiment, the implantation angle of the first conductive type ions is 0°, that is, the ions are implanted in a direction perpendicular to the surface of the substrate 100 .

[0048] After implanting the first conductive type ions, an annealing process is performed to diffuse the first conductive type ions into the substrate on both sides of the initial trench 104. Specifically, the annealing process is performed at a temperature of 800°C to 1200°C for a time of 5 minutes to 300 minutes. If the annealing temperature is too high, material properties will be degraded, while if the annealing temperature is too low, it will be difficult to repair lattice defects caused by the ion implantation. If the annealing time is too long, energy will be wasted, while if the annealing time is too short, the implanted ions may not be able to diffuse to the desired locations.

[0049] 6 , the bottom of the initial trench 104 is etched to form a trench 106 in the substrate 100 . The bottom of the trench 106 is lower than the bottom of the storage doped region 105 .

[0050] In this embodiment, a wet etching process is used to etch the bottom of the initial trench 104 .

[0051] In this embodiment, the depth of the groove 106 is 3 microns to 7 microns, and the depth of the groove 106 can be determined according to actual process requirements.

[0052] The ratio of the depth of the initial groove 104 to the depth of the groove 106 is in a range of 0.2 to 0.99.

[0053] After the trench 106 is formed, the mask layer 103 is removed.

[0054] 7 , a base doping region 107 in contact with the storage doping region 105 is formed in the substrate 100 . The base doping region 107 is located on top of the storage doping region 105 . The doping type of the base doping region 107 is a second conductive type, which is opposite to the first conductive type.

[0055] In this embodiment, the second conductivity type is P type.

[0056] Continuing to refer to Figure 7, it also includes forming an emitter doping region 108 in the substrate 100 on both sides of the groove 106, the emitter doping region 108 is located on the top of the base doping region 107, the emitter doping region 108 is of the first conductivity type, and the doping concentration of the emitter doping region 108 is greater than the doping concentration of the substrate 100.

[0057] In this embodiment, the doping concentration of the emitter doping region 108 is 1E14 atom / cm 2 ~1E16atom / cm 2 .

[0058] 8 , it also includes: forming a contact region 109 in the substrate 100 , the contact region 109 being of the second conductivity type, and the contact region 109 being located on top of the base doping region 107 , and the doping concentration of the contact region 109 being greater than the doping concentration of the base doping region 107 .

[0059] In this embodiment, the doping concentration of the contact region 109 is 1E14 atom / cm 2 ~1E16atom / cm 2 The doping concentration of the base doping region 107 is 1E2atom / cm 2 ~1E14atom / cm 2 .

[0060] 9 , a gate structure 112 is formed in the trench 106 , and a top surface of the gate structure 112 is flush with a top surface of the emitter doping region 108 .

[0061] In this embodiment, the gate structure 112 includes a gate dielectric layer 110 located at the bottom and sidewall surfaces of the trench 106 , and a gate layer 111 located on the gate dielectric layer 110 .

[0062] The material of the gate dielectric layer 110 includes a high-k dielectric layer or silicon oxide, and the material of the gate layer 111 is polysilicon.

[0063] 10 , the method further includes forming a collector doping region 113 in the second surface 102 of the substrate 100 , wherein the collector doping region 113 is of the second conductivity type, and a buffer layer 114 is provided between the collector doping region 113 and the storage doping region 105 .

[0064] In this embodiment, the buffer layer 114 is of the first conductivity type.

[0065] 11 , the method further includes forming an emitter conductive layer 115 on the top of the emitter doping region 108 , and forming a collector conductive layer 116 on a side of the collector doping region 113 away from the substrate 100 .

[0066] In this embodiment, specifically, the emitter conductive layer 115 is located on top of the emitter doping region 108 and the contact region 109 .

[0067] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate of a first conductivity type, the substrate having a first surface; Forming an initial trench recessed with respect to the first surface within the substrate; Forming storage doping regions within the substrate on both sides of the bottom of the initial trench, the storage doping regions being of the first conductivity type and having a doping concentration greater than that of the substrate; After forming the storage doping regions, etching the bottom of the initial trench to form a trench within the substrate, the bottom of the trench being lower than the bottom of the storage doping regions.

2. The method for forming a semiconductor structure according to claim 1, wherein, The ratio range of the depth of the initial trench to the depth of the trench is 0.2 to 0.

99.

3. The method for forming a semiconductor structure according to claim 1, wherein The depth of the initial trench is 1 micrometer to 5 micrometers; the depth of the trench is 3 micrometers to 7 micrometers.

4. The method for forming a semiconductor structure according to claim 1, wherein, The distance from the top of the storage doping region to the surface of the substrate is 0.5 micrometer to 5 micrometers.

5. The method for forming a semiconductor structure according to claim 1, wherein The method of forming storage doping regions within the substrate on both sides of the bottom of the initial trench includes: injecting ions of the first conductivity type into the bottom of the initial trench and annealing the substrate to form storage doping regions within the substrate on both sides of the bottom of the initial trench.

6. The method for forming a semiconductor structure according to claim 5, wherein, The ion implantation dose of ions of the first conduction type is 5E11 atom / cm 2 ~5E14 atom / cm 2 , the implantation energy is 0 keV to 2 MeV, and the angle between the implantation direction of the ions of the first conduction type and the substrate normal is 0° to 50°.

7. The method for forming a semiconductor structure as claimed in claim 5, wherein The temperature of the annealing treatment is 800°C to 1200°C, and the time is 5 min to 300 min.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The first conductivity type is N-type.

9. The method for forming a semiconductor structure according to claim 1, wherein, Before forming the initial trench, it further includes forming a mask layer on the substrate that exposes a part of the substrate surface, and using the mask layer as a mask to etch the substrate to form the initial trench.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The material of the mask layer includes one or a combination of oxides or nitrides.

11. The method for forming a semiconductor structure according to claim 1, wherein, Also comprising: Forming a base doping region in the substrate that is in contact with the storage doping region, the base doping region being located on top of the storage doping region, the base doping region being of a second conductivity type, the second conductivity type being opposite to the first conductivity type; forming emitter doping regions in the substrate on both sides of the trench, the emitter doping regions being located on top of the base doping region, the emitter doping regions being of the first conductivity type and having a doping concentration greater than that of the substrate; forming a gate structure within the trench; forming a collector doping region within the second surface of the substrate, the collector doping region being of the second conductivity type, the second surface being opposite to the first surface, and there being a buffer layer between the collector doping region and the storage doping region.

12. The method for forming a semiconductor structure according to claim 11, wherein, Also comprising: Forming a contact region in the substrate, the contact region being of the second conductivity type and being located on top of the base doping region, and the doping concentration of the contact region being greater than that of the base doping region.

13. The method for forming a semiconductor structure according to claim 11, wherein, The gate structure includes a gate dielectric layer on the sidewalls and bottom surface of the trench, and a gate layer on the gate dielectric layer.

14. The method for forming a semiconductor structure according to claim 11, wherein, Also comprising: Forming an emitter conductive layer on top of the emitter doping region; Forming a collector conductive layer on the side of the collector doping region away from the substrate.

15. The method for forming a semiconductor structure according to claim 11, wherein The second conductivity type is P-type.

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