Semiconductor structure and manufacturing method therefor, and electronic device

Abstract

The present invention relates to the technical field of integrated circuits. Provided are a semiconductor structure and a manufacturing method therefor, and an electronic device. In the manufacturing method, by means of optimizing a process, after a first trench (141) is formed, a groove (142) extending in a direction parallel to a substrate (100) is formed on a side wall of the first trench (141); then, isolation trenches (121) are formed to expose part of a dummy gate structure (400) in the groove (142); during the process of etching to remove the dummy gate structure (400), the dummy gate structure which covers a side wall of the groove (142) is retained, such that after a semiconductor layer (510), a gate dielectric layer and a word line are formed, the semiconductor layer (510) in the groove (142) can be etched and removed on the basis of the isolation trenches (121), thereby preventing the semiconductor layer (510) remaining in the groove (142) from forming a parasitic device.

Description

Semiconductor structure and manufacturing method thereof, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to Chinese patent application number 202410002413.7, filed on January 2, 2024, entitled “Semiconductor structure, manufacturing method thereof, and electronic device”. The entire contents of the patent application are incorporated by reference into this disclosure. Technical Field

[0003] The present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a manufacturing method thereof, and an electronic device. Background Art

[0004] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0005] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0006] Summary of the Invention

[0007] The present disclosure provides a semiconductor structure, a manufacturing method thereof, and an electronic device.

[0008] In a first aspect, the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0009] Providing a substrate, forming a stacked structure on the substrate, the stacked structure comprising first dielectric layers and second dielectric layers alternately arranged in a direction away from the substrate;

[0010] forming a first trench, wherein the first trench penetrates the stacked structure in a direction perpendicular to the substrate;

[0011] Etching the first dielectric layer based on the first trench to form a recess;

[0012] forming a dummy gate structure, wherein the dummy gate structure fills the first trench and the recess;

[0013] forming isolation trenches, the isolation trenches extending along a first direction and spaced apart along a second direction, the first direction and the second direction both being parallel to the substrate and intersecting the first direction and the second direction;

[0014] etching and removing a portion of the dummy gate structure, and retaining the dummy gate structure covering the groove wall;

[0015] forming a semiconductor layer, a gate dielectric layer and a word line in sequence in the first trench and the recess;

[0016] A portion of the dummy gate structure and a portion of the semiconductor layer in the groove are removed by etching.

[0017] Optionally, forming a dummy gate structure includes:

[0018] forming a protective layer, wherein the protective layer covers the groove wall of the first trench and the groove wall of the recess;

[0019] A dummy gate layer is formed, where the dummy gate layer covers the protection layer and fills the first trench and the recess.

[0020] Optionally, etching and removing a portion of the dummy gate structure includes:

[0021] Etching and removing the dummy gate layer in the first trench to expose the protection layer covering the trench wall of the first trench;

[0022] Etching and removing the protection layer covering the wall of the first trench;

[0023] The dummy gate layer in the groove is removed by etching.

[0024] Optionally, the protection layer has a high etching selectivity ratio relative to the first dielectric layer and the second dielectric layer.

[0025] Optionally, forming a dummy gate structure includes:

[0026] A first material is deposited to fill the first trench and the recess to form the dummy gate structure, wherein the first material has a high etching selectivity with respect to the first dielectric layer and the second dielectric layer.

[0027] Optionally, after forming the isolation trench, the following steps are further included:

[0028] etching and removing the second dielectric layer, and forming an active material layer at a position where the second dielectric layer is removed;

[0029] The active material layer on both sides of the dummy gate structure along the second direction is etched away to form an active layer. Along the first direction, the active layer includes a first segment and a second segment independently arranged on both sides of the dummy gate structure, and along the second direction, the size of the active layer is smaller than the size of the first dielectric layer.

[0030] Optionally, before forming the active material layer, the method further includes: forming a diffusion barrier layer, wherein the diffusion barrier layer covers the exposed surface of the dummy gate structure and the exposed surface of the first dielectric layer;

[0031] After the active layer is formed, the diffusion barrier layer located on both sides of the dummy gate structure along the second direction is removed by etching.

[0032] Optionally, before etching away part of the dummy gate structure, the method further includes:

[0033] forming a first barrier layer, wherein the first barrier layer covers the exposed surface of the active layer;

[0034] A first isolation layer is formed, where the first isolation layer covers the first barrier layer and fills the isolation trench.

[0035] Optionally, after forming the semiconductor layer, the gate dielectric layer, and the word line, the first isolation layer in the isolation trench is removed by etching to expose the dummy gate structure in the groove.

[0036] Optionally, the dummy gate structure has a high etching selectivity with respect to the first isolation layer.

[0037] In a second aspect, the present disclosure provides a semiconductor structure, comprising:

[0038] substrate;

[0039] At least one memory cell layer is provided on the substrate, wherein the memory cell layer includes at least one memory cell; the memory cell includes at least one transistor, and the transistor includes:

[0040] A gate and a gate dielectric layer are connected to each other, and a semiconductor channel is arranged on the side of the gate dielectric layer away from the gate; the semiconductor channel includes a bottom close to the substrate, a top away from the substrate, and a middle part connecting the bottom and the top, and the size of the middle part in the direction parallel to the substrate is smaller than the sizes of the bottom and the top in the direction parallel to the substrate.

[0041] Optionally, it also includes:

[0042] A word line perpendicular to the substrate: a plurality of the gates serve as part of the word line, and two adjacent gates are connected by a connecting portion along a direction perpendicular to the substrate, and a size of the connecting portion in a direction parallel to the substrate is larger than a size of the gate in the direction parallel to the substrate.

[0043] Optionally, it also includes:

[0044] An active layer includes a first segment and a second segment separated and arranged along a first direction parallel to the substrate, the first segment and the second segment are respectively connected to the semiconductor channel, and a protective layer is provided between the first segment and the top, and between the first segment and the bottom.

[0045] Optionally, the bottom and the top of the semiconductor channel extend in a direction away from the word line, and the bottom, the top and the middle portion constitute a groove structure, the end of the first segment close to the word line extends into the groove structure, and the end of the second segment close to the word line extends into the groove structure.

[0046] Optionally, it also includes:

[0047] Along a direction perpendicular to the substrate, a first dielectric layer is provided between two adjacent memory cell layers, and the protection layer has a high etching selectivity ratio relative to the first dielectric layer.

[0048] Optionally, it also includes:

[0049] A second isolation layer is provided between two adjacent storage unit layers, and the second isolation layer is located between the first dielectric layer and the connecting portion.

[0050] Optionally, it also includes:

[0051] The material of the second isolation layer is different from that of the first dielectric layer, and the material of the second isolation layer includes at least one of silicon nitride and silicon oxynitride.

[0052] Optionally, it also includes:

[0053] A diffusion barrier layer is provided on a top surface of the active layer away from the substrate, a bottom surface close to the substrate, and a side surface of the active layer close to the semiconductor channel.

[0054] Optionally, at the gate, the gate dielectric layer, the semiconductor channel, the diffusion barrier layer and the active layer are sequentially arranged in a direction away from the gate.

[0055] In a third aspect, the present disclosure provides an electronic device comprising the semiconductor structure as described in the second aspect.

[0056] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0058] FIG1 is a process flow chart of a method for manufacturing a semiconductor structure provided in some embodiments.

[0059] FIG. 2 is a top view of a stacked structure in some embodiments.

[0060] FIG3 is a cross-sectional view perpendicular to the substrate along line AA in FIG2 .

[0061] FIG. 4 is a cross-sectional view perpendicular to the substrate along line AA in FIG. 3 after forming a first trench in some embodiments.

[0062] FIG. 5 is a cross-sectional view perpendicular to the substrate along line AA in FIG. 3 after a groove is formed on the sidewall of the first trench in some embodiments.

[0063] FIG. 6 is a cross-sectional view perpendicular to the substrate along line AA in FIG. 3 after forming a protection layer in some embodiments.

[0064] FIG. 7 is a cross-sectional view perpendicular to the substrate along line AA in FIG. 3 after a dummy gate structure is formed in some embodiments.

[0065] FIG8 is a cross-sectional view parallel to the substrate along line BB in FIG7 after forming a dummy gate structure in some embodiments.

[0066] FIG. 9 is a cross-sectional view parallel to the substrate along line CC in FIG. 7 after forming a dummy gate structure in some embodiments.

[0067] FIG. 10 is a cross-sectional view perpendicular to the substrate along line AA in FIG. 3 after a dummy gate structure is formed in some embodiments.

[0068] FIG. 11 is a cross-sectional view parallel to the substrate along line BB in FIG. 7 after isolation trenches are formed in some embodiments.

[0069] FIG. 12 is a cross-sectional view parallel to the substrate along line CC in FIG. 7 after isolation trenches are formed in some embodiments.

[0070] FIG. 13 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after isolation trenches are formed in some embodiments.

[0071] FIG. 14 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after the second dielectric layer is removed in some embodiments.

[0072] FIG. 15 is a cross-sectional view perpendicular to the substrate along line EE in FIG. 12 after the second dielectric layer is removed in some embodiments.

[0073] FIG. 16 is a cross-sectional view parallel to the substrate along line CC in FIG. 7 after forming an active material layer in some embodiments.

[0074] FIG. 17 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after forming an active material layer in some embodiments.

[0075] FIG. 18 is a cross-sectional view parallel to the substrate along line CC in FIG. 7 after an active layer is formed in some embodiments.

[0076] FIG. 19 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after an active layer is formed in some embodiments.

[0077] FIG. 20 is a cross-sectional view perpendicular to the substrate along line EE in FIG. 12 after an active layer is formed in some embodiments.

[0078] FIG. 21 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after forming a first barrier layer in some embodiments.

[0079] FIG. 22 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after forming a first isolation layer in some embodiments.

[0080] FIG. 23 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after forming a first isolation layer in some embodiments.

[0081] FIG. 24 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after the dummy gate layer in the first trench is removed in some embodiments.

[0082] FIG. 25 is a cross-sectional view perpendicular to the substrate along line EE in FIG. 12 after the dummy gate layer in the first trench is removed in some embodiments.

[0083] FIG. 26 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after the protection layer in the first trench is removed in some embodiments.

[0084] FIG. 27 is a cross-sectional view perpendicular to the substrate along line EE in FIG. 12 after the protection layer in the first trench is removed in some embodiments.

[0085] FIG. 28 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after the dummy gate layer in the groove is removed in some embodiments.

[0086] FIG. 29 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after a portion of the dummy gate structure is removed in some embodiments.

[0087] FIG30 is a cross-sectional view perpendicular to the substrate along line EE in FIG12 after a portion of the dummy gate structure is removed in some embodiments.

[0088] FIG31 is a cross-sectional view parallel to the substrate along line BB in FIG7 after forming a semiconductor layer, a gate dielectric layer, and a word line in some embodiments.

[0089] FIG32 is a cross-sectional view parallel to the substrate along line CC in FIG7 after forming a semiconductor layer, a gate dielectric layer, and a word line in some embodiments.

[0090] FIG33 is a cross-sectional view perpendicular to the substrate along line DD in FIG12 after forming a semiconductor layer, a gate dielectric layer, and a word line in some embodiments.

[0091] FIG. 34 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after the first isolation layer in the isolation trench is removed in some embodiments.

[0092] FIG. 35 is a cross-sectional view perpendicular to the substrate along line EE in FIG. 12 after the first isolation layer in the isolation trench is removed in some embodiments.

[0093] FIG. 36 is a cross-sectional view parallel to the substrate along line BB in FIG. 7 after the dummy gate structure in the groove is removed in some embodiments.

[0094] FIG. 37 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after the dummy gate structure in the groove is removed in some embodiments.

[0095] FIG38 is a cross-sectional view perpendicular to the substrate along line EE in FIG12 after the dummy gate structure in the groove is removed in some embodiments.

[0096] FIG. 39 is a cross-sectional view parallel to the substrate along line BB in FIG. 7 after the semiconductor layer in the groove is removed in some embodiments.

[0097] FIG. 40 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 12 after the semiconductor layer in the groove is removed in some embodiments.

[0098] FIG. 41 is a cross-sectional view perpendicular to the substrate along line EE in FIG. 12 after the semiconductor layer in the groove is removed in some embodiments.

[0099] FIG. 42 is a cross-sectional view of the semiconductor structure provided in some embodiments, taken along line BB in FIG. 7 and parallel to the substrate.

[0100] FIG. 43 is a cross-sectional view of the semiconductor structure provided in some embodiments, taken along line CC in FIG. 7 and parallel to the substrate.

[0101] FIG. 44 is a cross-sectional view of the semiconductor structure provided in some embodiments, taken along line DD in FIG. 12 and perpendicular to the substrate.

[0102] FIG. 45 is a cross-sectional view perpendicular to the substrate along line EE in FIG. 12 of the semiconductor structure provided in some embodiments.

[0103] FIG. 46 is a cross-sectional view of the semiconductor structure provided in some embodiments, taken along line DD in FIG. 12 and perpendicular to the substrate.

[0104] Description of reference numerals:

[0105] 100, substrate; 101, oxide layer; 121, isolation trench; 131, connection portion; 140, channel groove; 141, first trench; 142, recess; 200, stacked structure; 210, first dielectric layer; 220, second dielectric layer; 230, diffusion barrier layer; 240, active material layer; 250, active layer; 250a, first segment; 250b, second segment; 260, first barrier layer; 310, first isolation layer; 320, second isolation layer; 400, dummy gate structure; 410, protection layer; 420, dummy gate layer; 500, semiconductor channel; 500a, bottom portion; 500b, top portion; 500c, middle portion; 510, semiconductor layer;

[0106] Z1, memory cell area; Z2, bit line area; BL, bit line; WL, word line; GM, gate dielectric layer; SU, memory cell; MCT, transistor; G1, gate; S / D1, first source / drain; S / D2, second source / drain; D1, first direction; D2, second direction; D3, third direction. DETAILED DESCRIPTION

[0107] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0108] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0109] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0110] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0111] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0112] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0113] The present disclosure provides a semiconductor structure, a manufacturing method thereof, and an electronic device. The manufacturing method of the semiconductor structure optimizes the process flow. After forming a first trench, a groove extending in a direction parallel to the substrate is formed on the sidewall of the first trench to form an isolation trench to expose a portion of the pseudo-gate structure in the groove. During the process of etching and removing the pseudo-gate structure, the pseudo-gate structure covering the sidewall of the groove is retained. In this way, after forming a semiconductor layer, a gate dielectric layer, and a word line, the semiconductor layer in the groove can be etched and removed based on the isolation trench, thereby avoiding the formation of parasitic devices by the residual semiconductor layer in the groove, and improving the performance of the semiconductor structure.

[0114] Some exemplary embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, as shown in Figure 1. Figure 1 shows a flow chart of a method for manufacturing a semiconductor structure provided according to an exemplary embodiment of the present disclosure. This embodiment does not limit the semiconductor structure. The semiconductor structure will be introduced below as a dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. The semiconductor structure in this embodiment can also be other types of memory, such as static random access memory (SRAM), flash EPROM, ferroelectric random access memory (FRAM), and magnetic random access memory (MRAM).

[0115] FIG1 shows a flow chart of a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure, and FIG2 to FIG46 are schematic diagrams of various stages of the method for fabricating a semiconductor structure. The method for fabricating a semiconductor structure of this embodiment will be described below in conjunction with FIG2 to FIG46. As shown in FIG1, a method for fabricating a semiconductor structure of this embodiment includes the following steps:

[0116] Step S110: providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure includes a first dielectric layer and a second dielectric layer alternately arranged in a direction away from the substrate.

[0117] Step S120: forming a first trench, wherein the first trench penetrates the stacked structure in a direction perpendicular to the substrate.

[0118] Step S130: etching the first dielectric layer based on the first trench to form a recess.

[0119] Step S140 : forming a dummy gate structure, wherein the dummy gate structure fills the first trench and the recess.

[0120] Step S150 : forming isolation trenches, wherein the isolation trenches extend along a first direction and are arranged at intervals along a second direction, wherein both the first direction and the second direction are parallel to the substrate and intersect with each other.

[0121] Step S160 : etching and removing a portion of the dummy gate structure, leaving the dummy gate structure covering the groove wall.

[0122] Step S170: forming a semiconductor layer, a gate dielectric layer and a word line in sequence in the first trench and the recess.

[0123] Step S180: etching and removing a portion of the dummy gate structure and a portion of the semiconductor layer in the groove.

[0124] In step S110, FIG2 shows a cross-sectional view of the AA plane (refer to AA in FIG3 ) after forming the stacked structure 200 on the substrate 100, and FIG3 shows a top view of the stacked structure 200. Referring to FIG2 and FIG3 , the substrate 100 may be a semiconductor substrate, and the material of the semiconductor substrate may include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP) or other III / V semiconductor materials or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. The substrate 100 may be a single-layer structure or a multi-layer structure.

[0125] In this embodiment, an oxide layer 101 is formed on the top surface of the substrate 100 . The oxide layer 101 is used to protect the substrate 100 from being exposed to a process environment and contaminated, thereby ensuring that the substrate 100 has good electrical conductivity.

[0126] The stacked structure 200 is formed on the substrate 100, and the following embodiments may be used:

[0127] 2 and 3 , any one of chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering processes may be used to alternately deposit the first dielectric layer 210 and the second dielectric layer 220 , and the cycle may be repeated several times to form the stacked structure 200 .

[0128] The first dielectric layer 210 and the second dielectric layer 220 of the stacked structure 200 may be alternately stacked in 2 to 1024 layers or more. For example, the first dielectric layer 210 and the second dielectric layer 220 may be alternately stacked in 48, 64, 128, 256, or 512 layers. The first dielectric layer 210 is made of silicon oxide, and the second dielectric layer 220 is made of silicon nitride.

[0129] 3 , the stacked structure 200 is laid out according to the semiconductor structure to be formed, and a memory cell region Z1 and a bit line region Z2 are defined on the stacked structure 200 . The memory cell region Z1 and the bit line region Z2 are arranged along a first direction D1 , which is parallel to the top surface of the substrate 100 .

[0130] In step S120, as shown in Figure 4 and referring to Figures 2 and 3, a first mask layer (first mask layer) is formed on the top surface of the stacked structure 200, and the first mask layer defines a pattern of the first trench 141. The stacked structure 200 is etched according to the first mask layer, and the first dielectric layer 210 and the second dielectric layer 220 exposed by the first mask layer are etched away layer by layer to form the first trench 141 that penetrates the stacked structure 200 along a third direction D3 perpendicular to the substrate 100.

[0131] In this embodiment, a plurality of first trenches 141 can be formed in the memory cell area Z1 of the stacked structure 200, and the plurality of first trenches 141 are arranged at intervals in the memory cell area Z1 along the second direction D2, the second direction D2 is parallel to the top surface of the substrate 100, and the second direction D2 intersects with the first direction D1.

[0132] It should be noted that the first trench 141 can penetrate the oxide layer 101 to expose a portion of the top surface of the substrate 100; or, as shown in this embodiment, the first trench 141 can only penetrate the stacked structure 200, and the first trench 141 does not penetrate the oxide layer 101. Since the thickness of the oxide layer 101 is very thin, the oxide layer 101 is easily broken down, and therefore the oxide layer 101 will not affect the electrical connection between the word line WL formed in the subsequent steps and the substrate 100.

[0133] In step S130, as shown in Figure 5 and referring to Figure 4, a wet process can be used to etch and remove the portion of the first dielectric layer 210 exposed by the sidewall of the first trench 141 to form a groove 142. The groove 142 is connected to the first trench 141, and the groove 142 is recessed from the first trench 141 in a direction parallel to the substrate 100 toward a direction away from the first trench 141.

[0134] For example, an etching solution can be injected into the first groove 141. The etching solution has a high etching selectivity ratio relative to the second dielectric layer 220. The amount of the first dielectric layer 210 removed can be precisely controlled by controlling the etching time, thereby precisely controlling the size of the groove 142 along the direction parallel to the substrate 100.

[0135] The first trench 141 and the groove 142 connected thereto together form a trench 140 . Along a plane parallel to the substrate 100 , the size of the trench 140 disposed in the first dielectric layer 210 is larger than that of the trench 140 disposed in the second dielectric layer 220 .

[0136] In step S140, in this embodiment, a dummy gate structure is formed, including the following steps:

[0137] Step S141 : forming a protection layer, where the protection layer covers the groove wall of the first trench and the groove wall of the recess.

[0138] As shown in FIG6 , referring to FIG5 , a protective layer 410 may be deposited using an atomic layer deposition process to cover the walls of the first trench 141 and the walls of the recess 142. The protective layer 410 has a high etching selectivity relative to the first dielectric layer 210 and the second dielectric layer 220. The material of the protective layer 410 may include silicon oxide.

[0139] It is understandable that although the material of the protective layer 410 and the material of the first dielectric layer 210 both include silicon oxide, in the process of forming the protective layer 410, the protective layer 410 and the first dielectric layer 210 can have a high etching selectivity by adjusting the deposition process conditions and process parameters.

[0140] Step S142 : forming a dummy gate layer, where the dummy gate layer covers the protection layer and fills the first trench and the recess.

[0141] As shown in Figures 7, 8, and 9, with reference to Figures 5 and 6, a dummy gate layer 420 can be deposited using any one of chemical vapor deposition, atomic layer deposition, or sputtering processes. The dummy gate layer 420 covers the protective layer 410 and fills the first trench 141 and the recess 142. The material of the dummy gate layer 420 may include at least one of single-crystal silicon and polycrystalline silicon. In this embodiment, the dummy gate layer 420 and the protective layer 410 together form a dummy gate structure 400.

[0142] 8 and 9 , along a plane parallel to the substrate 100 , the size of the dummy gate structure 400 formed in the first dielectric layer 210 is larger than the size of the dummy gate structure 400 formed in the second dielectric layer 220 .

[0143] In some other embodiments, the dummy gate structure 400 can be formed by the following method: As shown in FIG10 , with reference to FIG5 , a first material is deposited to fill the first trench 141 and the recess 142 to form the dummy gate structure 400. The first material has a high etch selectivity with respect to the first dielectric layer 210 and the second dielectric layer 220. For example, the first material can be selected from a spin-on carbon material and aluminum oxide. In this embodiment, only a single deposition process is required to form the dummy gate structure 400, saving process steps and time.

[0144] In step S150 , as shown in FIG. 11 , FIG. 12 , and FIG. 13 , and referring to FIG. 8 , FIG. 9 , and FIG. 10 , a second mask layer (not shown) is formed on the top surface of the stacked structure 200 , and the second mask layer defines a pattern of the isolation trench 121 .

[0145] The stacked structure 200 is etched according to the second mask layer to form isolation trenches 121 in the memory cell area Z1 (refer to FIG. 3 ). The isolation trenches 121 extend along the first direction D1 and are arranged at intervals along the second direction D2. Both the first direction D1 and the second direction D2 are parallel to the substrate 100, and the first direction D1 and the second direction D2 intersect.

[0146] For example, the angle between the first direction D1 and the second direction D2 may be 30°, 45°, 60°, 90°, 120°, or 150°. In some embodiments, the angle between the first direction D1 and the second direction D2 is 90°, and the first direction D1 and the second direction D2 intersect perpendicularly.

[0147] As shown in FIG11 , FIG12 and FIG13 , referring to FIG8 , FIG9 and FIG10 , the isolation trench 121 divides the stacked structure 200 of the memory cell region Z1 into strip structures (not numbered in the figures) extending along the first direction D1 and arranged at intervals along the second direction D2 .

[0148] A dummy gate structure 400 is correspondingly provided in each strip structure, and part of the sidewall of the dummy gate structure 400 located in the groove 142 is exposed in the isolation trench 121. In other words, each isolation trench 121 exposes part of the sidewall of the dummy gate structure 400 located on both sides thereof along the second direction D2.

[0149] After step S150 and before step S160, the following steps are further performed:

[0150] Step S10: etching and removing the second dielectric layer, and forming an active material layer at the position where the second dielectric layer is removed.

[0151] First, the entire second dielectric layer 220 is removed by etching based on the isolation trench 121. As shown in Figures 14 and 15, with reference to Figures 10 and 13, an etchant can be injected into the isolation trench 121. The etchant has a high etching selectivity with respect to the first dielectric layer 210 and the dummy gate structure 400. For example, a phosphoric acid solution can be injected into the isolation trench 121 to dissolve and remove the entire second dielectric layer 220. Referring to Figure 3, the entire second dielectric layer 220 in the memory cell area Z1 and the entire second dielectric layer 220 in the bit line area Z2 are removed, exposing the sidewalls of the dummy gate structure 400 originally covered by the second dielectric layer 220. The first dielectric layer 210 is then supported by the dummy gate structure 400.

[0152] Then, a diffusion barrier layer 230 is formed to cover the exposed surface of the dummy gate structure 400 and the exposed surface of the first dielectric layer 210. As shown in Figures 16 and 17, the diffusion barrier layer 230 can be formed by depositing using any one of an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition (PVD) process. The diffusion barrier layer 230 covers the exposed surface of the dummy gate structure 400 and the surface of the first dielectric layer 210.

[0153] The material of the diffusion barrier layer 230 can be selected from metal titanium or titanium compounds, metal tantalum or tantalum compounds, metal platinum or platinum compounds. In this embodiment, the material of the diffusion barrier layer 230 includes titanium nitride.

[0154] Next, as shown in Figures 16 and 17, any one of an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process can be selected to deposit and form an active material layer 240. The active material layer 240 covers the diffusion barrier layer 230 and fills the position where the second dielectric layer 220 was originally set. The material of the active material layer 240 may include at least one of metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al). In this embodiment, the material of the active material layer 240 includes metallic tungsten.

[0155] Next, the diffusion barrier layer 230 located on both sides of the dummy gate structure 400 along the second direction D2 is removed by etching. A dry process can be selected to etch away the active material layer 240 in the isolation trench 121. Then, a wet process is used to etch away the diffusion barrier layer 230 in the isolation trench 121 to cut the active material layer 240 into multiple layers arranged at intervals along the third direction D3. The multiple active material layers 240 are independently provided.

[0156] In this embodiment, the active material layer 240 in the bit line region Z2 is formed into bit lines BL. The bit lines BL extend along the second direction D2 and are spaced apart along the third direction D3.

[0157] Step S20: etching and removing the active material layer on both sides of the dummy gate structure along the second direction to form an active layer, wherein along the first direction, the active layer includes a first segment and a second segment independently arranged on both sides of the dummy gate structure, and along the second direction, the size of the active layer is smaller than the size of the first dielectric layer.

[0158] As shown in Figures 18, 19 and 20, with reference to Figures 16 and 17, the active material layer 240 is etched based on the isolation trench 121, and the active material layer 240 is etched along the second direction D2 using an anisotropic etching process to remove a portion of the active material layer 240. The active material layer 240 is cut along the first direction D1 to form an active layer 250. The active layer 250 includes a first segment 250a and a second segment 250b that are relatively arranged on both sides of the dummy gate structure 400, and along the second direction D2, the size of the active layer 250 is smaller than the size of the first dielectric layer 210. Both sides of the active layer 250 are recessed relative to the first dielectric layer 210, and the active layer 250 exposes a portion of the diffusion barrier layer 230 covering the dummy gate structure 400.

[0159] Next, as shown in Figures 18, 19 and 20, after the active layer 250 is formed, the diffusion barrier layer 230 exposed by the active layer 250 is etched away. For example, a wet process can be used to etch away the exposed diffusion barrier layer 230, leaving only the diffusion barrier layer 230 located between the active layer 250 and the pseudo gate structure 400, thereby preventing the metal material in the active layer 250 from diffusing into other devices and causing contamination of other devices.

[0160] Step S30: forming a first barrier layer, wherein the first barrier layer covers the exposed surface of the active layer.

[0161] In some embodiments, as shown in FIG21 , an atomic layer deposition process or a chemical vapor deposition process may be used to deposit and form a first barrier layer 260, which covers the exposed surface of the active layer 250, the exposed surface of the first dielectric layer 210, and the exposed surface of the dummy gate structure 400. The material of the first dielectric layer 210 may include at least one of silicon nitride or silicon oxynitride.

[0162] As shown in FIG21 , the first barrier layer 260 covers the exposed surface of the active layer 250 , preventing the active layer 250 from being exposed to the process space and oxidized in subsequent processes, thereby preventing the electrical performance of the active layer 250 from being degraded, thereby improving the electrical performance of the semiconductor structure.

[0163] Step S40 : forming a first isolation layer, where the first isolation layer covers the first barrier layer and fills the isolation trench.

[0164] As shown in Figure 22, referring to Figure 21, the first isolation layer 310 can be formed by a spin coating process or a deposition process. The dummy gate structure 400 has a high etching selectivity relative to the first isolation layer 310. In this embodiment, the material of the first isolation layer 310 may include spin-coated carbon or silicon oxide.

[0165] In other embodiments, as shown in FIG. 23 , the first barrier layer 260 may not be formed, and the active layer 250 may be nitrided to partially nitride the exposed surface of the active layer 250, forming a nitride layer on the exposed surface of the active layer 250. Then, a first isolation layer 310 is formed using a spin coating process or a deposition process. The first isolation layer 310 covers the active layer 240 and fills the isolation trench 121. In subsequent embodiments, this solution will be described assuming that the first barrier layer 260 is not formed.

[0166] In step S160 , in this embodiment, a portion of the dummy gate structure 400 is removed by etching to expose the first trench 141 and a portion of the recess 142 , including:

[0167] Step S161 : etching and removing the dummy gate layer in the first trench to expose the protection layer covering the trench wall of the first trench.

[0168] As shown in Figures 24 and 25 , referring to Figures 20 and 23 , a third mask layer (not shown) is formed on the top surface of the stacked structure 200. The third mask layer exposes the top surface of the dummy gate layer 420. The dummy gate layer 420 is etched according to the third mask layer. An anisotropic etching process is used to remove the dummy gate layer 420 in the first trench 141 (see Figure 5 ) along the third direction D3, exposing the protection layer 410 covering the trench wall of the first trench 141.

[0169] Step S162 : etching and removing the protection layer covering the wall of the first trench.

[0170] As shown in FIG. 26 and FIG. 27 , referring to FIG. 24 and FIG. 25 , the protection layer 410 covering the wall of the first trench 141 is etched using a wet process to expose the diffusion barrier layer 230 that was etched and retained in the previous step.

[0171] Step S163: etching and removing the dummy gate layer in the groove.

[0172] As shown in FIG. 28 and FIG. 30 , referring to FIG. 26 and FIG. 27 , all of the dummy gate layer 420 in the groove 142 is removed by wet etching to expose the protection layer 410 covering the sidewall of the groove 142 .

[0173] In some embodiments, part of the dummy gate structure 400 is etched away to expose the first trench 141 and part of the recess 142 . The following implementation can be adopted: as shown in FIG. 29 , referring to FIG. 11 , first, all of the dummy gate structure 400 in the first trench 141 is etched away.

[0174] Then, based on the first trench 141, the pseudo gate structure 400 in the groove 142 is etched, and plasma can be used to perform an anisotropic etching process on the pseudo gate structure 400 in the groove 142, and part of the pseudo gate structure 400 is etched away in a direction parallel to the substrate 100. By controlling the energy and direction of the plasma, part of the pseudo gate structure 400 in the groove 142 is etched away, and the pseudo gate structure 400 covering the groove wall of the groove 142 is retained.

[0175] In step S170, first, as shown in Figures 31, 32, 33, and 34, with reference to Figures 28 and 30, an atomic layer deposition process can be used to deposit a semiconductor layer 510. The semiconductor layer 510 covers the walls of the first trench 141 (see Figure 5) and the dummy gate structure 400 (see Figures 28 or 29, 30) in the recess 142 (see Figure 5). The material of the semiconductor layer 510 may include indium gallium zinc oxide (IGZO).

[0176] The material of the semiconductor layer 510 may include indium gallium zinc oxide. For example, the material of the semiconductor layer 510 may include at least one of the following materials: zinc tin oxide (ZTO), indium zinc oxide (IZO), indium tin oxide (ITO), tungsten-doped indium oxide (IWO), zinc oxide (ZnOx), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), indium zinc oxide (InSnOx), zinc oxynitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOx), a), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), indium tin zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO).

[0177] Then, as shown in Figures 31, 32, and 33, an atomic layer deposition process is used to deposit a gate dielectric layer GM, which covers the semiconductor layer 510. The material of the gate dielectric layer GM may include at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), hafnium silicate (HfSiO), zirconium silicate (ZrSiO), and strontium silicate (SrSiO); alternatively, the material of the gate dielectric layer GM may include at least one of hafnium silicate nitride (HfSiON), zirconium silicate nitride (ZrSiON), and zirconium silicate nitride (SrSiON). In some embodiments, the material of the gate dielectric layer GM includes aluminum oxide, and the thickness of the gate dielectric layer GM is 10 nm.

[0178] Next, as shown in Figures 31, 32, and 33, word lines WL are formed by atomic layer deposition or chemical vapor deposition. The word lines WL cover the gate dielectric layer GM and fill the unfilled areas of the first trench 141 and the recess 142. The material of the word lines WL can be selected from at least one of tin-doped indium oxide (ITO), aluminum-doped zinc oxide (AZO), and indium-doped zinc oxide thin film (IZO).

[0179] During the deposition process of forming the word lines WL, some material may be deposited on the top surface of the structure. After the word line WL material fills the unfilled areas in the first trench 141 and the recess 142, a chemical mechanical planarization (CMP) process is used to remove the word line WL material deposited on the top surface of the structure.

[0180] In this embodiment, after the semiconductor layer 510, the gate dielectric layer GM and the word line WL are formed, the following steps are further performed:

[0181] Step S1701: etching and removing the first isolation layer in the isolation trench to expose the dummy gate structure in the groove.

[0182] As shown in Figures 34 and 35 , with reference to Figures 31 , 32 , and 33 , a fourth mask layer (not shown) is formed on the top surface of the structure. The fourth mask layer exposes the top surface of the first isolation layer 310 located in the isolation trench 121. The first isolation layer 310 is etched based on the fourth mask layer. A dry process, a wet process, or a combination of dry and wet processes can be used to etch away the first isolation layer 310 in the isolation trench 121, exposing a portion of the dummy gate structure 400 in the recess 142.

[0183] 33 and 34 , along the second direction D2 , the first isolation layer 310 in the recessed areas on both sides of the active layer 250 relative to the first dielectric layer 210 is etched and retained. The etched and retained first isolation layer 310 is used to protect the active layer 250 and the semiconductor layer 510 connected to the active layer 250 .

[0184] In step S180, as shown in Figures 36, 37, and 38, and with reference to Figures 31, 34, and 35, a wet process is used to etch and remove part of the dummy gate structure 400 based on the isolation trench 121 to expose the semiconductor layer 510 in the groove 142. For example, an etching solution can be injected into the isolation trench 121. The dummy gate structure 400 has a high etching selectivity relative to the first isolation layer 310, and the dummy gate structure 400 connected to the first dielectric layer 210 is etched and removed, while preventing the etching solution from damaging the first isolation layer 310, thereby preventing the active layer 250 and the semiconductor layer 510 connected to the active layer 250 from being etched and damaged.

[0185] Then, as shown in FIG39 , FIG40 and FIG41 , the exposed semiconductor layer 510 and the exposed gate dielectric layer GM are removed by wet etching, and the retained semiconductor layer 510 is etched to form semiconductor channels 500 arranged at intervals along the third direction D3 .

[0186] In this embodiment, after removing the semiconductor layer 510 in the groove 142, the following steps are further performed: as shown in Figures 42, 43, 44, 45, and 46, an oxide is deposited in an oxygen atmosphere to form a second isolation layer 320. The second isolation layer 320 covers the gate dielectric layer GM in the groove 142, fills the unfilled area in the groove 142, and isolates the trench 121. The material of the second isolation layer may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0187] Then, a chemical mechanical polishing process is used to polish the top surface of the second isolation layer 320 into a flat surface, so as to facilitate other subsequent processing steps on the semiconductor structure.

[0188] The manufacturing method of the semiconductor structure of this embodiment optimizes the process flow. After forming the first trench, the sidewall of the first trench is directly etched to form a groove extending in a direction parallel to the substrate, so that the size of the dummy gate structure formed in the groove is larger than the size of the dummy gate structure formed in the first trench. Then, an isolation trench is formed to expose part of the dummy gate structure located in the groove, thereby achieving the removal of the semiconductor layer in the groove by etching the isolation trench, avoiding the formation of parasitic devices by the presence of residual semiconductor layers between adjacent active layers, improving the performance of the semiconductor structure, and facilitating the multi-layer stacking and miniaturization of three-dimensional semiconductor structures.

[0189] The method for manufacturing the semiconductor structure of this embodiment reduces the complexity and challenge of the process by optimizing the process, simplifies the process steps, reduces the repeated photo-irradiation-etching process steps of small sizes, and saves process costs and time.

[0190] In some embodiments, a semiconductor structure is provided, as shown in Figures 42, 43, 44, 45, and 46. The semiconductor structure includes a substrate 100 and a multi-layer memory cell layer arranged in a direction perpendicular to the substrate 100 (third direction D3); the memory cell layer includes multiple rows and columns of memory cells SU, the row direction is a first direction D1, and the column direction is a second direction D2, the first direction D1 and the second direction D2 are both parallel to the substrate 100, and the first direction D1 and the second direction D2 intersect; the memory cell SU includes at least one transistor MCT, the transistor MCT includes a gate G1 and a gate dielectric layer GM connected to each other, and a semiconductor channel 500 arranged on a side of the gate dielectric layer GM away from the gate G1; the semiconductor channel 500 includes a bottom 500a close to the substrate, a top 500b away from the substrate 100, and a middle portion 500c connecting the bottom 500a and the top 500b, wherein the size of the middle portion 500c in the direction parallel to the substrate 100 is smaller than the sizes of the bottom 500a and the top 500b in the direction parallel to the substrate 100.

[0191] The angle between the first direction D1 and the second direction D2 may be 30°, 45°, 60°, 90°, 120°, or 150°. In some embodiments, the angle between the first direction D1 and the second direction D2 is 90°, and the first direction D1 and the second direction D2 intersect perpendicularly.

[0192] The semiconductor structure of this embodiment is manufactured using the manufacturing process of the above-mentioned embodiment. The first dielectric layer is etched based on the first trench to form a groove. The groove is recessed from the first trench in a direction parallel to the substrate toward a direction away from the first trench. The semiconductor structure of this embodiment can be formed. The bottom 500a and the top 500b of the semiconductor channel 500 are larger than the size of the middle portion 500c, which facilitates disconnecting the semiconductor layer from both sides to form the semiconductor channel 500.

[0193] The semiconductor structure of this embodiment has no residual conductive film layer between adjacent transistors MCT along the direction perpendicular to the substrate 100, and is free from the trouble of parasitic devices, thereby improving the electrical performance and yield of the semiconductor structure and facilitating multi-layer stacking and miniaturization of the semiconductor structure.

[0194] In some embodiments, as shown in Figures 42, 43, 44, 45, and 46, the semiconductor structure further includes a word line WL along a direction perpendicular to the substrate 100 (third direction D3): multiple gates G1 serve as part of the word line WL, and along the direction perpendicular to the substrate 100 (third direction D3), two adjacent gates G1 are connected by a connecting portion 131, and the size of the connecting portion 131 in the direction parallel to the substrate 100 is larger than the size of the gate G1 in the direction parallel to the substrate 100.

[0195] The size of the connection portion 131 of the word line WL is larger than that of the gate G1, so that the bottom 500a and the top 500b of the semiconductor channel 500 are larger, which facilitates the formation of the semiconductor channel 500 by disconnecting the semiconductor layer from both sides during the manufacturing process of the semiconductor structure.

[0196] In some embodiments, as shown in Figures 42, 43, 44, 45, and 46, the semiconductor structure also includes an active layer 250, the active layer 250 includes a first segment 250a and a second segment 250b separated and arranged along a first direction D1 parallel to the substrate 100, the first segment 250a and the second segment 250b are respectively connected to the semiconductor channel 500, and a protective layer 410 is provided between the first segment 250a and the top 500b, and between the first segment 250a and the bottom 500a.

[0197] In a direction perpendicular to the substrate 100, the residual dummy gate structure 400 is arranged between the bottom 500a of the semiconductor channel 500 and the connecting portion 131 located below it, and between the top 500b of the semiconductor channel 500 and the connecting portion 131 located above it. The residual dummy gate structure 400 can enhance the isolation performance between the two adjacent layers of storage units SU.

[0198] In some embodiments, as shown in Figures 42, 43, 44, 45, and 46, the bottom 500a and top 500b of the semiconductor channel 500 extend in a direction away from the word line WL, and along a direction parallel to the substrate 100, the bottom 500a, the top 500b, and the middle portion 500c form a groove structure, and the end of the first segment 250a close to the word line WL extends into the groove structure, and the end of the second segment 250b close to the word line WL extends into the groove structure.

[0199] Each transistor MCT also includes a first source / drain S / D1 and a second source / drain S / D2 connected to the semiconductor channel 500, the first source / drain S / D1 is arranged in the partial structure connecting the first section 250a and the semiconductor channel 500, and the second source / drain S / D2 is arranged in the partial structure connecting the second section 250b and the semiconductor channel 500.

[0200] The middle portion 500 c of the semiconductor channel 500 surrounds and covers the periphery of the gate G1 .

[0201] The bottom 500a, top 500b, and middle portion 500c of the semiconductor channel 500 form a groove-like structure. The first source / drain S / D1 and the second source / drain S / D2 are arranged in the groove-like structure relative to each other along a first direction D1, and are respectively in contact with the semiconductor channel 500. This increases the contact area between the first source / drain S / D1, the second source / drain S / D2, and the semiconductor channel 500, improves the gate control capability of the transistor MCT, and effectively suppresses the short channel effect.

[0202] In the trench structure formed by the semiconductor channel 500, the first dielectric layer 210 fills the area except for the first source / drain S / D1 and the second source / drain S / D2. That is, as shown in Figures 44 and 46, the first dielectric layer 210 and the semiconductor channel 500 are connected along the second direction D2.

[0203] In some embodiments, as shown in Figures 42, 43, 44, 45, and 46, the semiconductor structure further includes a first dielectric layer 210 between two adjacent memory cell layers along a direction perpendicular to the substrate 100 (third direction D3), and the protective layer 410 has a high etching selectivity ratio relative to the first dielectric layer 210.

[0204] The protection layer 410 prevents the wet solution from damaging the dummy gate layer 420 when etching the second dielectric layer 220 , thereby avoiding affecting the length of the gate G1 of the transistor MCT.

[0205] In some embodiments, as shown in Figures 42, 43, 44, 45, and 46, the semiconductor structure further includes a second isolation layer 320 disposed between two adjacent memory cell layers. The second isolation layer 320 is located between the first dielectric layer 210 and the connecting portion 131. The second isolation layer 320 can further enhance the isolation effect between two adjacent memory cell layers SU.

[0206] In some embodiments, as shown in Figures 42, 43, 44, 45, and 46, the material of the second isolation layer 320 is different from the material of the first dielectric layer 210. The material of the second isolation layer 320 includes at least one of silicon nitride or silicon oxynitride. The presence of an isolation layer made of two materials between two adjacent layers of memory cells SU enhances the isolation between the two layers of memory cells SU.

[0207] In some embodiments, as shown in Figures 42, 43, 44, 45, and 46, the semiconductor structure also includes a diffusion barrier layer 230, which is arranged on the top surface 100 of the active layer 250 away from the substrate, the bottom surface close to the substrate 100, and the side surface of the active layer 250 close to the semiconductor channel 500.

[0208] In some embodiments, as shown in Figures 42, 43, 44, 45, and 46, at the gate G1, the gate dielectric layer GM, the semiconductor channel 500, the diffusion barrier layer 230, and the active layer 250 are sequentially arranged in a direction away from the gate G1.

[0209] In some embodiments, as shown in Figures 42, 43, 45, and 46, the semiconductor structure further includes a first barrier layer 260, which is disposed on side walls of the active layer 250 that are oppositely disposed along the second direction D2. Along the second direction D2, the first barrier layer 260 is also disposed between the first dielectric layer 210 and the semiconductor channel 500.

[0210] In some embodiments, an electronic device is provided, comprising the semiconductor structure of the above embodiments. The electronic device may be a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, or the like.

[0211] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0212] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, comprising the following steps: Providing a substrate, and forming a stacked structure on the substrate, the stacked structure including a first dielectric layer and a second dielectric layer alternately arranged in a direction away from the substrate; Forming a first trench, the first trench penetrating the stacked structure in a direction perpendicular to the substrate; Etching the first dielectric layer based on the first trench to form a groove; Forming a dummy gate structure, the dummy gate structure filling the first trench and the groove; Forming isolation trenches, the isolation trenches extending in a first direction and arranged at intervals in a second direction, the first direction and the second direction both being parallel to the substrate, and the first direction and the second direction intersecting; Etching and removing part of the dummy gate structure, and retaining the dummy gate structure covering the sidewalls of the groove; Sequentially forming a semiconductor layer, a gate dielectric layer, and a word line in the first trench and the groove; Etching and removing part of the dummy gate structure and part of the semiconductor layer in the groove.

2. The manufacturing method of the semiconductor structure according to claim 1, wherein, Forming a dummy gate structure includes: Forming a protective layer, the protective layer covering the sidewalls of the first trench and the sidewalls of the groove; Forming a dummy gate layer, the dummy gate layer covering the protective layer and filling the first trench and the groove.

3. The manufacturing method of the semiconductor structure according to claim 2, wherein, Etching and removing part of the dummy gate structure includes: Etching and removing the dummy gate layer in the first trench to expose the protective layer covering the sidewalls of the first trench; Etching and removing the protective layer covering the sidewalls of the first trench; Etching and removing the dummy gate layer in the groove.

4. The method of fabricating a semiconductor structure according to claim 2, wherein, The protective layer has a high etching selectivity with respect to the first dielectric layer and the second dielectric layer.

5. The manufacturing method of the semiconductor structure according to claim 1, wherein, Forming a dummy gate structure includes: Depositing a first material to fill the first trench and the groove to form the dummy gate structure, the first material having a high etching selectivity with respect to the first dielectric layer and the second dielectric layer.

6. According to the method for manufacturing a semiconductor structure as claimed in claim 1, after forming the isolation trenches, the following steps are further included: Etching and removing the second dielectric layer, and forming an active material layer at a position where the second dielectric layer is removed; Etching and removing the active material layer on both sides of the dummy gate structure along the second direction to form an active layer, along the first direction, the active layer includes a first segment and a second segment independently arranged on both sides of the dummy gate structure, and along the second direction, the size of the active layer is smaller than the size of the first dielectric layer.

7. The method for manufacturing a semiconductor structure according to claim 6, before forming the active material layer, further comprising: Forming a diffusion barrier layer, the diffusion barrier layer covering the exposed surfaces of the dummy gate structure and the exposed surfaces of the first dielectric layer; After forming the active layer, etching and removing the diffusion barrier layer on both sides of the dummy gate structure along the second direction.

8. According to the method for manufacturing a semiconductor structure as claimed in claim 6, before etching and removing part of the dummy gate structure, the following are further included: Forming a first barrier layer, the first barrier layer covering the exposed surface of the active layer; Forming a first isolation layer, the first isolation layer covering the first barrier layer and filling the isolation trenches.

9. The method for manufacturing a semiconductor structure according to claim 8, after forming the semiconductor layer, the gate dielectric layer, and the word line, etch and remove the first isolation layer in the isolation trench to expose the dummy gate structure in the groove.

10. The manufacturing method of the semiconductor structure according to claim 8, wherein, The dummy gate structure has a high etching selectivity relative to the first isolation layer.

11. A semiconductor structure, comprising: A substrate; At least one memory cell layer disposed on the substrate, the memory cell layer including at least one memory cell; The memory cell includes at least one transistor, and the transistor includes: A gate and a gate dielectric layer connected to each other, and a semiconductor channel disposed on a side of the gate dielectric layer away from the gate; The semiconductor channel includes a bottom close to the substrate, a top away from the substrate, and a middle portion connecting the bottom and the top, and a dimension of the middle portion in a direction parallel to the substrate is smaller than dimensions of the bottom and the top in the direction parallel to the substrate.

12. The semiconductor structure according to claim 11, further comprising: Word lines perpendicular to the substrate: A plurality of the gates serve as a part of the word lines. Along a direction perpendicular to the substrate, two adjacent gates are connected by a connecting portion, and a dimension of the connecting portion in a direction parallel to the substrate is larger than a dimension of the gate in the direction parallel to the substrate.

13. The semiconductor structure according to claim 12, further comprising: An active layer, the active layer includes a first segment and a second segment separated and disposed along a first direction parallel to the substrate, the first segment and the second segment are respectively connected to the semiconductor channel, and there are protective layers between the first segment and the top, and between the first segment and the bottom.

14. The semiconductor structure according to claim 13, wherein, The bottom and the top of the semiconductor channel extend in a direction away from the word line, the bottom, the top, and the middle portion form a groove-like structure, one end of the first segment close to the word line extends into the groove-like structure, and one end of the second segment close to the word line extends into the groove-like structure.

15. The semiconductor structure according to claim 13, further comprising: Along a direction perpendicular to the substrate, there is a first dielectric layer between two adjacent memory cell layers, and the protective layer has a high etching selectivity relative to the first dielectric layer.

16. The semiconductor structure according to claim 15, further comprising: A second isolation layer disposed between two adjacent memory cell layers, the second isolation layer is located between the first dielectric layer and the connecting portion.

17. The semiconductor structure according to claim 16, further comprising: The material of the second isolation layer is different from the material of the first dielectric layer, and the material of the second isolation layer includes at least one of silicon nitride or silicon oxynitride.

18. The semiconductor structure according to claim 13, further comprising: A diffusion barrier layer disposed on a top surface of the active layer away from the substrate, a bottom surface close to the substrate, and a side surface of the active layer close to the semiconductor channel.

19. The semiconductor structure according to claim 18, wherein, At the gate, the gate dielectric layer, the semiconductor channel, the diffusion barrier layer, and the active layer are sequentially disposed in a direction away from the gate.

20. An electronic device, comprising the semiconductor structure according to any one of claims 11-19.

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