Chip module, chip module preparation method, and electronic device

Abstract

The embodiments of the present application belong to the technical field of chips. Provided are a chip module, a chip module preparation method, and an electronic device. Chips are provided on two opposite surfaces of a substrate of the chip module, and the chips are packaged by means of a first packaging member and a second packaging member. Heat dissipation is performed on a first chip by means of a first heat dissipation member, and the layout of the first heat dissipation member is not limited by constraints such as preparation processes and short-circuit protection spacing, such that the projection of the first heat dissipation member can at least partially cover the projection of a heat conduction area of the first chip, thereby shortening a heat dissipation path, reducing thermal resistance, and improving the heat dissipation effect. The end surface of a first end of the first heat dissipation member is recessed inwards relative to the surface of the second packaging member that faces away from the substrate, there is a preset distance between the end surface and the surface of the second packaging member that faces away from the substrate, and when a packaging layer is thinned to form the second packaging member, the packaging layer is thinned for removal to a depth that does not reach the first heat dissipation member, so as to avoid problems such as delamination and cracks occurring at the junction of a side wall of the first heat dissipation member and the packaging layer, thus improving the grinding operability and reliability of the packaging layer, and improving the yield.

Description

Chip module, chip module manufacturing method and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 5, 2024, with application number 202410031048.2 and application name “Chip module, chip module preparation method and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip technology, and in particular to a chip module, a chip module preparation method, and an electronic device. Background Art

[0003] With the continuous development of chip packaging technology, chip packaging devices have been widely used in electronic devices such as mobile phones, laptops, smart watches, etc. For example, the RF chip module in the mobile phone can integrate the chip devices that realize the RF function through packaging, which can protect the chip and improve the integration while enhancing the performance of the entire RF module.

[0004] Currently, electronic devices are developing towards the trend of being "light, thin, short and small" and multifunctional. Chip packaging devices are also developing towards high density, miniaturization and high pin count. When the heat dissipation performance of chip packaging devices is poor, it will greatly affect the performance of the chip. Summary of the Invention

[0005] The embodiments of the present application provide a chip module, a chip module preparation method, and an electronic device. The chip module has an outstanding heat dissipation effect, which is beneficial to improving the performance of the chip module.

[0006] A first aspect of an embodiment of the present application provides a chip module, including a substrate, a first package and a second package. The substrate has a first surface and a second surface opposite to each other in a thickness direction. The first package is arranged on the first surface, and the second package is arranged on the second surface.

[0007] The chip module also includes multiple chips, which are respectively arranged on the first surface and the second surface, and the chips are at least partially wrapped in the first package or the second package. The multiple chips include a first chip, and the first chip has a heat-conducting area for achieving thermal contact. The heat generated by the first chip during operation can be transferred to the outside of the first chip through the heat-conducting area to achieve heat dissipation of the first chip.

[0008] The chip module also includes a first heat sink located between the first surface and a surface of the second package facing away from the substrate, with at least a first end of the first heat sink located within the second package. The first heat sink is configured to dissipate heat from the first chip. Compared to related art methods in which chips dissipate heat through a ball grid array (BGA) composed of solder balls, the layout of the first heat sink is not constrained by manufacturing processes or design constraints such as short-circuit prevention, unlike the layout requirements of the BGA. This eliminates the need for maintaining a spacing required to prevent short circuits, ensuring that the first heat sink can be located below the heat transfer area of ​​the first chip. This ensures that the vertical projection (projected along the thickness direction) of the first heat sink on the substrate at least partially covers the vertical projection of the heat transfer area of ​​the first chip on the substrate. Heat generated by the first chip can be transferred to the first heat sink along the thickness direction through the heat transfer area, and then transferred to the outside of the chip module through the first heat sink for dissipation. This effectively shortens the heat dissipation path of the first chip and reduces thermal resistance. Furthermore, the first heat sink does not need to maintain a spacing required to prevent short circuits, allowing for a larger projected coverage area, significantly improving heat dissipation and thereby significantly enhancing the performance of the first chip and the entire chip module.

[0009] The first end surface of the first heat sink is recessed in the thickness direction relative to the surface of the second package facing away from the substrate, that is, the first end surface of the first heat sink is recessed inward relative to the surface of the second package facing away from the substrate. In the thickness direction, a preset distance is provided between the first end surface of the first heat sink and the surface of the second package facing away from the substrate. That is, during the thinning process of the package layer on the second surface of the substrate, the depth of grinding and removal (the thickness in the thickness direction) does not reach the position of the first heat sink (the position of the first end surface). After the thinning process of the package layer, the first end of the first heat sink is located within the unremoved portion of the package layer (the package thin layer). For example, a preset distance can be provided between the first end surface of the first heat sink and the surface of the package thin layer facing away from the substrate. After the second package is formed by the package thin layer so that the first end surface of the first heat sink is recessed inward, the preset distance is still retained between the first end surface of the first heat sink and the surface of the second package facing away from the substrate. By not thinning the first heat sink while thinning the packaging layer, problems such as delamination, cracks or separation at the junction of the circumferential side wall of the first heat sink and the packaging layer are avoided during the thinning process. The polishing workability and reliability of the side of the packaging layer facing away from the substrate during the thinning process can be improved, the yield rate can be improved, and the occurrence of problems such as short circuits can be avoided, thereby having higher reliability.

[0010] In one possible implementation, the preset distance is 10μm to 20μm, which ensures that the position of the first heat sink will not be removed during the thinning process of the packaging layer. After the thinning process of the packaging layer, the first end of the first heat sink is located inside the packaging thin layer that has not been removed, thereby improving the reliability and operability of the thinning process.

[0011] In one possible implementation, the plurality of heat transfer regions includes at least a first region, which has the largest cross-sectional area among the plurality of heat transfer regions. The vertical projection of the first heat sink on the substrate at least partially covers the vertical projection of the first region on the substrate. This facilitates heat dissipation from the first chip through the electrical connector with a larger cross-sectional area and the first heat sink, further reducing thermal resistance and achieving optimal heat dissipation for the first chip.

[0012] In a possible implementation, the vertical projection of the first heat sink on the substrate covers at least 50% of the vertical projection area of ​​the first region on the substrate, which can further improve the heat dissipation effect on the first chip.

[0013] In one possible implementation, the vertical projection of the first heat sink on the substrate covers at least 50% of the vertical projection area of ​​the first chip on the substrate, which is conducive to the vertical projection of the first heat sink covering a larger area of ​​the heat conduction area and achieving good heat dissipation for the first chip.

[0014] In a possible implementation, the vertical projection of the first heat sink on the substrate completely covers the vertical projection of the first chip on the substrate, thereby achieving a better heat dissipation effect for the first chip.

[0015] In one possible implementation, the chip module also includes a plurality of spaced conductive members, which are fixed on the second surface. The conductive members are electrically connected to the corresponding chips through the substrate. Part of the conductive members are located inside the second package, and one end of the conductive member facing away from the substrate is exposed on the surface of the second package facing away from the substrate, so that the end of the conductive member facing away from the substrate can be electrically connected to the circuit board, thereby realizing the electrical connection between the chip of the chip module and the circuit board.

[0016] In one possible implementation, the cross-sectional area of ​​the first heat sink is larger than the cross-sectional area of ​​a conductive member. The vertical projection of the first heat sink on the substrate is larger than the vertical projection of the conductive member on the substrate, allowing the first heat sink to cover a larger area. The vertical projection of the first heat sink can cover a larger heat conduction area. Compared with heat dissipation of the first chip through conductive members such as solder balls, this increases the heat dissipation area and provides better heat dissipation performance.

[0017] In a possible implementation, the cross-sectional area of ​​the first heat sink is greater than π*(D / 2) 2 , wherein the range of D is 200μm to 300μm, ensuring that the first heat sink can cover a larger heat conduction area and achieve better heat dissipation performance.

[0018] In a possible implementation, the thermal conductivity of the first heat sink is greater than 100 W / mK. The first heat sink dissipates heat for the first chip, ensuring low thermal resistance and achieving good heat dissipation effect.

[0019] In a possible implementation, the thickness of the first heat sink is greater than 30 μm, ensuring that the first heat sink has good thermal conductivity, thereby facilitating good heat dissipation for the first chip.

[0020] In one possible implementation, the second package has a groove on the side facing away from the substrate, and the groove extends to the first end of the first heat sink, so that part of the first end of the first heat sink is exposed, so that the heat of the first chip can be transferred to the outside of the chip module through the first heat sink, thereby ensuring the heat dissipation performance of the first heat sink.

[0021] In one possible implementation, the chip module further includes a first connector secured to a first end of the first heat sink, with an end of the first connector facing away from the first heat sink protruding from a surface of the second package facing away from the substrate. The first heat sink can be fixedly assembled to the circuit board via the first connector, thereby improving assembly stability between the chip module and the circuit board and transferring heat to the circuit board for dissipation, resulting in a good heat dissipation effect.

[0022] Among them, the end of the first connector facing away from the first heat sink can protrude from the side of the second package facing away from the substrate, that is, the first connector is protruding from the second package, which facilitates the assembly connection between the first connector and the circuit board.

[0023] In one possible implementation, a gap is provided between the first connector and the second package, allowing the first connector to have a higher degree of interface freedom during the molding process, thereby improving the molding yield of the first connector. A portion of the first heat sink can still be exposed from the side of the second package facing away from the substrate.

[0024] In a possible implementation, one end of the conductive element facing away from the substrate is protruded from a side of the second package facing away from the substrate, so that the conductive element is better exposed outside the second package, facilitating electrical connection between the conductive element and the circuit board.

[0025] In a possible implementation, a gap is provided between the conductive component and the second packaging component, so that the conductive component has a higher interface freedom during the molding process, which is beneficial to improving the molding yield of the conductive component.

[0026] In a possible implementation, the conductive member and the first connecting member are solder balls, respectively, to facilitate assembly of the conductive member, the first connecting member and an external circuit board.

[0027] In one possible implementation, the first chip is disposed on the first surface, and a first electrical connector is provided on a surface of the first chip facing the substrate. The first chip is electrically connected to the substrate via the first electrical connector. An end surface of the first electrical connector connected to the substrate forms a heat conduction region.

[0028] In one possible implementation, the first heat sink further includes a second end, opposite the first end, in the thickness direction. The second end of the first heat sink is secured to the second surface. That is, the first chip and the first heat sink are located on the first and second opposing surfaces of the substrate, respectively, resulting in a relatively simple structural design. When preparing the chip module, the first heat sink can be positioned on the second surface along with the chip. This is fully compatible with the existing chip size ball grid array (CSBGA) chip module manufacturing process, eliminating the need for additional steps and contributing to cost savings.

[0029] In one possible implementation, the substrate has a second heat sink, and the vertical projections of the second heat sink and the first heat sink on the substrate at least partially overlap, thereby reducing the thermal resistance of the heat dissipation path from the first chip to the first heat sink, thereby further improving the heat dissipation effect.

[0030] In one possible implementation, the second heat sink is located within the substrate. That is, the second heat sink is located between the first and second surfaces, and the second heat sink does not protrude from the first and second surfaces of the substrate. This improves heat dissipation while simplifying the structural design and facilitating implementation.

[0031] In one possible implementation, one end of the second heat sink is located inside the substrate, and the other end of the second heat sink extends toward the second package in the thickness direction. The second end of the first heat sink is fixed to the other end of the second heat sink, which is beneficial to increase the thickness of the second heat sink, further reduce thermal resistance, and enrich the fixed assembly method between the first heat sink and the second surface of the substrate, with better structural design flexibility.

[0032] In one possible implementation, the second end of the first heat sink is fixed to the interior of the substrate in the thickness direction. That is, the first heat sink is inserted into the substrate, with a portion of the first heat sink located within the substrate and a portion of the first heat sink located within the second package. This further reduces thermal resistance and improves heat dissipation, thereby reducing the number of heat sinks installed on the substrate, simplifying the structural design and molding process, and reducing costs.

[0033] In a possible implementation, the first chip is disposed on the second surface, a second electrical connector is provided on a surface of the first chip facing the substrate, and the first chip is electrically connected to the substrate through the second electrical connector.

[0034] The first heat sink is fixed on the side of the first chip facing away from the substrate, and the side of the first chip facing the first heat sink forms a heat conduction area, which further shortens the heat dissipation path, reduces thermal resistance, and improves heat dissipation efficiency.

[0035] In a possible implementation, the first chip includes a power amplifier, and the chip module is a radio frequency module.

[0036] A second aspect of an embodiment of the present application provides a chip module manufacturing method, the method comprising:

[0037] A substrate, a first heat sink, and a plurality of chips are provided, wherein the substrate comprises a first surface and a second surface opposite to each other in a thickness direction. The plurality of chips comprises a first chip having a heat conduction area for achieving heat conduction contact.

[0038] Part of the plurality of chips is disposed on the first surface to form a first package on the first surface, and the chips on the first surface are at least partially encapsulated in the first package.

[0039] Another portion of the multiple chips is arranged on the second surface, and at least the first end of the first heat sink is located on the second surface, and the vertical projection of the first heat sink on the substrate at least partially covers the vertical projection of the heat conduction area of ​​the first chip on the substrate.

[0040] A packaging layer is formed on the second surface, and the packaging layer wraps the chip and the first heat sink located on the second surface.

[0041] The packaging layer is thinned to form a packaging thin layer, and the first end of the first heat dissipation element is wrapped inside the packaging thin layer.

[0042] The thin package layer is processed to form a second package so that a first end surface of the first heat sink is recessed in the thickness direction relative to a surface of the second package facing away from the substrate. The chip located on the second surface is at least partially enclosed within the second package. The first heat sink is located between the first surface and a surface of the second package facing away from the substrate. A predetermined distance is maintained in the thickness direction between the first end surface of the first heat sink and the surface of the second package facing away from the substrate.

[0043] This method achieves excellent heat dissipation performance for the first chip by providing a first heat sink, and ensuring that the vertical projection of the first heat sink on the substrate at least partially covers the vertical projection of the heat conduction area of ​​the first chip on the substrate. Furthermore, after thinning the packaging layer, the first end of the first heat sink is ensured to be located within the thin packaging layer formed after thinning. For example, a preset distance can be provided between the first end surface of the first heat sink and the surface of the packaging layer facing away from the substrate, so that the first heat sink is not exposed on the surface of the packaging layer facing away from the substrate. After the packaging layer is processed to form a second packaging element so that the first end surface of the first heat sink is recessed inwardly relative to one surface of the second packaging element, the preset distance is still retained between the first end surface and the surface of the second packaging element facing away from the substrate. That is, in the process of thinning the packaging layer, the depth of grinding and removal (along the thickness direction) does not reach the position of the first heat sink. The first heat sink is not thinned while the packaging layer is thinned. This avoids problems such as delamination, cracks or separation at the junction of the circumferential side wall of the first heat sink and the packaging layer during the grinding and thinning process, improves the workability and reliability of the grinding of the packaging layer, improves the yield, and can also avoid problems such as short circuits.

[0044] In a possible implementation, before forming the packaging layer on the second surface, the method further includes: forming a plurality of spaced solder joints on the second surface, wherein the solder joints are electrically connected to the chips through the substrate.

[0045] Forming the packaging layer on the second surface further includes: wrapping the solder joints with the packaging layer.

[0046] After forming the packaging layer on the second surface, the method further includes thinning the solder joint member to form a conductive member, with the end of the conductive member facing away from the substrate being exposed on the surface of the second packaging member facing away from the substrate. By forming the conductive member on the second surface of the substrate and exposing the conductive member from the second packaging member, this method facilitates electrical connection between the conductive member and an external circuit board.

[0047] In a possible implementation, thinning the solder joint member to form the conductive member includes:

[0048] The weld joint is thinned to form a transition weld joint.

[0049] A notch structure is formed on the side of the packaging thin layer facing away from the substrate, and the notch structure is arranged around the transition welding point.

[0050] A first solder structure is placed on the transition solder joint. After reflowing, the transition solder joint and the first solder structure form a conductive element. The end of the conductive element facing away from the substrate protrudes from the surface of the second package facing away from the substrate. This method allows the conductive element to protrude from the second package. Furthermore, the notch increases the degree of freedom at the interface between the transition solder joint and the first solder structure, facilitating reflow molding of the conductive element, particularly spherical conductive elements.

[0051] In one possible implementation, processing the thin package layer to form the second package includes: forming a groove on a surface of the thin package layer facing away from the substrate to form the second package, the groove extending to the first end of the first heat sink, thereby causing the first end surface of the first heat sink to be recessed in the thickness direction relative to the surface of the second package facing away from the substrate, thereby ensuring a predetermined distance between the first end surface of the first heat sink and the surface of the second package facing away from the substrate. The groove partially exposes the first end of the first heat sink, allowing heat from the first chip to be transferred to the outside of the chip module through the first heat sink.

[0052] In a possible implementation, after forming the groove on the surface of the encapsulation layer facing away from the substrate, the method further includes:

[0053] A second solder structure is disposed on the first end of the first heat sink.

[0054] The second solder structure is reflowed to form a first connector. The end of the first connector facing away from the first heat sink protrudes from a surface of the second package facing away from the substrate. This method forms the first connector on the first heat sink, facilitating connection of the first heat sink to an external circuit board, etc., via the first connector.

[0055] In one possible implementation, the first chip has a first electrical connector on a surface facing the substrate, and arranging some of the multiple chips on the first surface includes: arranging the first chip on the first surface, and electrically connecting the first chip to the substrate through the first electrical connector, and forming a heat conduction area at an end surface where the first electrical connector is connected to the substrate.

[0056] In a possible implementation, in the thickness direction, the first heat dissipation element further includes a second end opposite to the first end.

[0057] Providing the substrate and the first heat sink includes: fixing the second end of the first heat sink on the second surface. This method can obtain a chip module with a layout in which the first chip is located on the first surface and the first heat sink is located on the second surface.

[0058] In a possible implementation, the substrate has a second heat dissipation element.

[0059] Fixing the second end of the first heat sink to the second surface includes: causing the vertical projection of the first heat sink on the substrate to at least partially overlap with the vertical projection of the second heat sink on the substrate. This method provides a chip module with a second heat sink to improve heat dissipation.

[0060] In a possible implementation, one end of the second heat dissipation member is located inside the substrate, and the other end of the second heat dissipation member extends toward the inside of the second package along the thickness direction.

[0061] Securing the second end of the first heat sink to the second surface includes forming a second connector on the other end of the second heat sink, securing the second end of the first heat sink to the other end of the second heat sink via the second connector. This method can yield a chip module with a layout in which the first chip is located on the first surface, the first heat sink is located on the second surface, and one end of the second heat sink is located within the substrate, with the other end secured to the first heat sink.

[0062] In one possible implementation, providing the substrate and the first heat sink includes fixing the second end of the first heat sink inside the substrate. This method can produce a chip module with a layout in which the first chip is located on the first surface and the first heat sink is partially fixed inside the substrate.

[0063] In a possible implementation, the first chip has a second electrical connection on a surface facing the substrate.

[0064] Disposing another portion of the plurality of chips on the second surface includes:

[0065] The first chip is disposed on the second surface, and the first chip is electrically connected to the substrate through the second electrical connection member.

[0066] The first heat sink is fixed to the side of the first chip facing away from the substrate, and a heat conduction area is formed on the side of the first chip facing the first heat sink.

[0067] This method can be used to obtain a chip module with a layout in which the first chip is located on the second surface and the first heat sink is located on the first chip.

[0068] A second aspect of an embodiment of the present application provides an electronic device, comprising a housing, a circuit board, and any of the above-mentioned chip modules, wherein the chip module is arranged on the circuit board, and the chip module is electrically connected to the circuit board, and both the chip module and the circuit board are assembled in the housing. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] FIG1 is a schematic cross-sectional view of an electronic device according to an embodiment of the present application;

[0070] FIG2 is a schematic cross-sectional view of a chip module and a circuit board assembly in the related art;

[0071] FIG2a is a schematic diagram of a chip module in the related art from a bottom view;

[0072] FIG3 is a schematic cross-sectional view of a chip module according to an embodiment of the present application;

[0073] FIG4 is a schematic diagram of the chip module in FIG3 from a bottom view;

[0074] FIG5 is a schematic cross-sectional view of another chip module provided in an embodiment of the present application;

[0075] FIG6 is a schematic diagram of the chip module and the circuit board assembly in FIG5;

[0076] FIG7 is a schematic cross-sectional view of another chip module provided in an embodiment of the present application;

[0077] FIG8 is a schematic diagram of a junction-to-board thermal resistance model of the first chip in the chip module of FIG7 ;

[0078] FIG9 is a schematic diagram of heat conduction simulation of a first chip of a ball grid array chip module in the related art;

[0079] FIG10 is a schematic diagram of heat conduction simulation of the first chip in the chip module of FIG7 ;

[0080] FIG11 is a schematic cross-sectional view of another chip module provided in an embodiment of the present application;

[0081] FIG12 is a schematic cross-sectional view of another chip module provided in an embodiment of the present application;

[0082] FIG13 is a schematic cross-sectional view of another chip module provided in an embodiment of the present application;

[0083] FIG14 is a schematic cross-sectional view of another chip module provided in an embodiment of the present application;

[0084] FIG15 is a schematic flow chart of a chip module manufacturing method provided in an embodiment of the present application;

[0085] FIG15a is a schematic diagram of a chip module provided in an embodiment of the present application after some chips are assembled on a substrate;

[0086] FIG15 b is a schematic diagram of a chip module provided in an embodiment of the present application after a first package is formed on a substrate;

[0087] FIG15c is a schematic diagram of a chip module provided in an embodiment of the present application after chips and solder joints are assembled on a substrate;

[0088] FIG15 d is a schematic diagram of a chip module in an embodiment of the present application after the encapsulation layer is formed on the second surface of the substrate;

[0089] FIG15e is a schematic diagram of a chip module after thinning the packaging layer according to an embodiment of the present application;

[0090] FIG15f is a schematic diagram of a chip module provided in an embodiment of the present application after the second package is formed;

[0091] FIG15g is a schematic diagram of a chip module provided in an embodiment of the present application after a first solder structure and a second solder structure are provided on a first heat sink;

[0092] FIG15h is a bottom view schematically illustrating a chip module provided in an embodiment of the present application after a first solder structure and a second solder structure are disposed on a first heat sink;

[0093] FIG15i is a schematic diagram of a first solder structure after reflow in a chip module provided in an embodiment of the present application.

[0094] Explanation of the accompanying drawings: 100-electronic device; 101-housing; 101a-side frame; 101b-back cover; 102-display screen; 10-chip module; 11-substrate; 11a-first surface; 11b-second surface; 112-second heat sink; 12a-first chip; 12b-second chip; 12c-third chip; 12d-fourth chip; 13-first package; 14-second package; 15-conductive member; 17-first heat sink; 18-groove; 19-second groove; 110-first connecting member; 120-second connecting member; 130-first solder structure; 140-second solder structure; 20-circuit board; 104-antenna module. DETAILED DESCRIPTION

[0095] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0096] An embodiment of the present application provides an electronic device, which may include but is not limited to a mobile phone, a tablet personal computer, a laptop computer, an ultra-mobile personal computer (UMPC), a desktop computer, a walkie-talkie, a netbook, a personal digital assistant (PDA), a wearable device, a virtual reality (VR) device (such as VR glasses, VR helmets, etc.), an augmented reality (AR) device (such as AR glasses, AR helmets, etc.), a vehicle-mounted device, a surveillance camera device, and other electronic devices with wireless communication capabilities.

[0097] In the embodiments of the present application, the electronic device is taken as an example of a mobile phone.

[0098] FIG1 is a schematic diagram of the cross-sectional structure of an electronic device provided in an embodiment of the present application.

[0099] As shown in Figure 1, the electronic device 100 may include a shell 101 and a display screen 102. The shell 101 may include a back cover 101b and a side frame 101a. The back cover 101b and the display screen 102 may be respectively located on opposite sides of the side frame 101a. The back cover 101b, the side frame 101a and the display screen 102 may form a storage space for accommodating the various structural components of the electronic device 100.

[0100] The electronic device 100 may further include an antenna module 104 . For example, in some examples, a portion of the side frame 101 a may be used to form the antenna module 104 .

[0101] The electronic device 100 may also include a circuit board 20 and a chip module 10, which are respectively assembled in the accommodating space, and the chip module 10 is arranged on the circuit board 20, and the chip module 10 is electrically connected to the circuit board 20 to realize signal transmission between the chip module 10 and the circuit board 20.

[0102] Exemplarily, the chip module 10 can be a radio frequency module, which can be used to modulate the frequency of a received electrical signal (such as an electrical signal sent by a processor of the electronic device 100) and amplify the power. For example, in the process of transmitting an electrical signal to the outside of the electronic device 100, the radio frequency module can modulate the electrical signal from a low frequency to a specified high frequency band to become a radio frequency signal that can be transmitted in the air, and amplify the power of the radio frequency signal to meet communication requirements.

[0103] The circuit board 20 may be electrically connected to the antenna module 104 to achieve electrical connection between the chip module 10 and the antenna module 104 .

[0104] The chip module 10 can transmit radio frequency (RF) signals and transmit them to the antenna module 104 via the circuit board 20. The antenna module 104 can then transmit the RF signals. The antenna module 104 can also receive external electromagnetic wave signals and transmit them to the chip module 10.

[0105] Of course, in some other examples, the chip module 10 may also be other chip integrated modules, for example, a memory chip module, etc. In the embodiment of the present application, the chip module 10 is described as a radio frequency module as an example.

[0106] It is understood that the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer structural components than shown, or may combine or separate certain structural components, or may have different structural component arrangements. For example, the electronic device 100 may further include cameras, such as a front-facing camera and a rear-facing camera, sensors, memory, a battery, a flash, and other structural components.

[0107] As electronic devices develop towards becoming thinner and lighter, chip modules are also gradually developing towards high density, miniaturization, and high pin counts. Ball grid array (BGA) packaging technology has become one of the most commonly used chip packaging technologies due to its advantages such as small package size and high density. In particular, chip modules packaged in die-size ball grid array (DSBGA) are widely used and researched.

[0108] FIG2 is a schematic cross-sectional view of a chip module and circuit board assembly in the related art.

[0109] As shown in FIG. 2 , a DABGA packaged chip module 400 may include a substrate 200 and a plurality of chips. The plurality of chips may be electrically connected to connection traces (not shown) within the substrate 200 .

[0110] The substrate 200 may include relative front and back sides, and multiple chips may also be respectively arranged on the front and back sides of the substrate 200, as shown in Figure 2. For example, the multiple chips may include chip 400a, chip 400b, chip 400c and chip 400d, wherein chip 400a, chip 400b and chip 400c may be located on the front side of the substrate 200, and chip 400d may be located on the back side of the substrate 200.

[0111] A plurality of solder balls 500 may be fixed on the back side of the substrate 200 . The plurality of solder balls 500 are arranged in an array to form a ball grid array (see FIG. 2 a ). The chip may be electrically connected to the plurality of solder balls 500 through connection traces of the substrate 200 .

[0112] For example, the chip may have copper bumps on the side facing the substrate 200 for achieving electrical connection. As shown in Figure 2, taking the chip 400c on the front side of the substrate 200 as an example, the chip 400c has copper bumps 401 on the side facing the front side of the substrate 200, and the connecting traces 201 in the substrate 200 can extend to the front side of the substrate 200. The chip 400c can be electrically connected to the connecting traces 201 through the copper bumps 401, thereby achieving electrical connection between the chip 400c and the substrate 200, and then electrically connected to the solder balls 500 located on the back side of the substrate 200 through the connecting traces 201.

[0113] Among them, the molding material of the solder ball 500 is mostly tin ball. For example, the molding material of the solder ball 500 can be an alloy material composed of three metal components: tin (Sn), silver (Ag), and copper (Cu), such as SAC305 material, that is, the mass percentages of Sn, Ag, and Cu are 96.5%, 3.0%, and 0.5% respectively.

[0114] The front side of the substrate 200 may also be covered with a front side package 600, which encapsulates at least a portion of the chip located on the front side. The back side of the substrate 200 may be covered with a back side package 700, which encapsulates at least a portion of the chip located on the back side. A plurality of solder balls 500 are also located in the back side package 700, and each solder ball 500 has one end facing away from the substrate 200 protruding from the back side package 700 to expose the solder ball 500.

[0115] Continuing to refer to FIG. 2 , the chip module 400 can be soldered to the circuit board 300 via a plurality of solder balls 500 to achieve electrical connection, thereby enabling electrical connection between the plurality of chips and the circuit board 300 .

[0116] Heat dissipation for multiple chips can also be achieved through a ball grid array composed of solder balls 500. The heat generated by the chip during operation can be transferred to the substrate 200, and then conducted out of the chip module through the solder balls 500 to achieve heat dissipation. The area where the chip contacts the substrate 200 can be the chip's heat conduction area. For example, taking chip 400c as an example, the copper bump 401 of chip 400c is in contact and electrically connected to the substrate 200. Chip 400c conducts heat to the substrate 200 through the copper bump 401, thereby achieving heat dissipation for chip 400c. The end surface of the copper bump 401 that contacts the substrate 200 can serve as the chip 400c's heat conduction area 402 (see Figure 2a).

[0117] FIG2 a is a bottom view of a chip module in the related art, wherein the dotted line in FIG2 a indicates the vertical projection of the chip 400 c on the back package 700 .

[0118] However, the distribution of the ball grid array (BGA) is relatively fixed and is limited by the BGA manufacturing process. As shown in FIG2a , spacing must be reserved between the multiple solder balls 500 in the BGA to prevent contact between the solder balls 500 and problems such as short circuits. It is difficult to ensure that the solder balls 500 are positioned exactly below the chip's heat conduction area 402. As shown in FIG2a , the vertical projection of the solder balls 500 on the substrate (or backside package 700 ) cannot cover the vertical projection of the chip 400c's heat conduction area 402 on the substrate, increasing the heat dissipation path. Furthermore, the backside package 700 is often made of plastic, which has a lower thermal conductivity (e.g., 1 W / (mK)). This increases thermal resistance and results in poor heat dissipation performance. Moreover, solder balls are mostly made of tin balls, which have a low thermal conductivity (e.g., 58W / (mK)). The small cross-sectional area of ​​each solder ball is also not conducive to heat dissipation, reducing the heat dissipation effect on the chip, thereby affecting the chip performance. This is especially true for heat-sensitive chips, such as the power amplifier (PA) in the RF module. Poor heat dissipation of the PA will greatly affect the function of the PA, thereby affecting the performance of the entire chip module.

[0119] Based on this, an embodiment of the present application provides a chip module and a method for preparing a chip module. The chip in the chip module can be electrically connected to the substrate through a conductive member (such as a ball grid array assembled by multiple conductive solder balls). The chip module is provided with a first heat sink, so that the first heat sink is used to achieve heat dissipation of the first chip that is sensitive to heat or has severe heat generation. Compared with the heat dissipation of the chip through a ball grid array composed of solder balls, the first heat sink will not be limited by the molding process and local demand constraints, nor does it need to retain spacing to prevent short circuits, etc. It can ensure that the first heat sink can be distributed below the heat conduction area of ​​the first chip, that is, it can ensure that the vertical projection of the first heat sink on the substrate at least partially covers the vertical projection of the heat conduction area of ​​the first chip on the substrate, effectively shortening the heat dissipation path of the first chip, having a smaller thermal resistance and a larger coverage area, significantly improving the heat dissipation performance, so that the first chip and the entire chip module can achieve better performance.

[0120] In addition, the first end surface of the first heat sink is recessed in the thickness direction relative to the side of the second package facing away from the substrate, and a preset distance is retained between the first end surface of the first heat sink and the side of the second package facing away from the substrate, that is, in the process of thinning the package layer, the grinding and removal depth does not reach the first heat sink. After the thinning process, the first end of the first heat sink is located inside the part of the package layer (package thin layer) that has not been removed. After the second package is formed, the first end surface of the first heat sink and the side of the second package facing away from the substrate retain a preset distance. The first heat sink is not thinned while the package layer is thinned, which avoids problems such as delamination, cracks or separation at the junction of the circumferential side wall of the first heat sink and the package layer during the thinning process. It can improve the grinding operability and reliability of the side of the package layer facing away from the substrate during the thinning process, improve the yield, and also avoid the occurrence of problems such as short circuit, with higher reliability.

[0121] FIG3 is a schematic diagram of the cross-sectional structure of a chip module provided in an embodiment of the present application.

[0122] 3 , the chip module 10 includes a substrate 11 , which can serve as a supporting structure for the entire chip module 10 . For example, the substrate 11 can be a square plate-shaped structure, with the thickness direction of the substrate 11 being the x direction shown in FIG. 3 .

[0123] The substrate 11 may include a first surface 11 a and a second surface 11 b opposite to each other. For example, two opposite side surfaces of the substrate 11 in the x-direction may be the first surface 11 a and the second surface 11 b , respectively.

[0124] The chip module 10 further includes multiple chips, which may be radio frequency integrated circuits (RFIC), power amplifiers, low noise amplifiers (LNA), surface acoustic wave filters (SAW), switches (SW), and the like.

[0125] Exemplarily, the multiple chips may include a first chip 12a, and the first chip 12a may be a chip that generates more heat among the multiple chips, or the first chip 12a may also be a heat-sensitive chip. For example, the heat dissipation effect of the first chip 12a will have a great impact on the performance of the first chip 12a. For example, in the embodiment of the present application, the first chip 12a is taken as a PA as an example for illustration.

[0126] As shown in FIG3 , the plurality of chips may be a first chip 12 a , a second chip 12 b , a third chip 12 c and a fourth chip 12 d , and the first chip 12 a , the second chip 12 b , the third chip 12 c and the fourth chip 12 d may be a PA, an RFIC, a SWA and an LNA / SW respectively.

[0127] Multiple chips can be respectively arranged on the first surface 11a and the second surface 11b. As shown in FIG3, for example, the first chip 12a, the second chip 12b and the third chip 12c can be respectively arranged on the first surface 11a, and the fourth chip 12d can be arranged on the second surface 11b.

[0128] The chip module 10 further includes a first package 13 and a second package 14. The first package 13 and the second package 14 can provide packaging and protection for the chips. At least a portion of each chip can be encapsulated and packaged within the first package 13 or the second package 14. Exemplarily, the first package 13 is disposed on the first surface 11 a and can cover the first surface 11 a. The chips located on the first surface 11 a are at least partially encapsulated and packaged within the first package 13. For example, the first chip 12 a, the second chip 12 b, and the third chip 12 c are encapsulated and packaged within the first package 13.

[0129] The second package 14 is disposed on the second surface 11 b , and the second package 14 may cover the second surface 11 b . The chip located on the second surface 11 b is at least partially encapsulated in the second package 14 . For example, the fourth chip 12 a may be partially encapsulated in the second package 14 .

[0130] The molding material of the first package 13 may include plastic, ceramic, resin, glass, etc. The molding material of the second package 14 may be the same as the molding material of the first package 13 .

[0131] It should be noted that the chip is at least partially encapsulated in the first package 13 or the second package 14. The chip can be located inside the package and not exposed. For example, the chip located on the first surface 11a (such as the first chip 12a, the second chip 12b, and the third chip 12c) is encapsulated inside the first package 13, and there is a distance between the side of the chip facing away from the substrate 11 and the side of the first package 13 facing away from the substrate 11.

[0132] Alternatively, the chip may be partially wrapped inside the package and partially exposed from the package. For example, the chip located on the second surface 11b (such as the fourth chip 12d) is partially located inside the second package 14 and partially exposed from the side of the second package 14 facing away from the substrate. For example, the side of the chip facing away from the substrate 11 can be flush with the side of the second package 14 facing away from the substrate 11, so that the chip is partially exposed.

[0133] Of course, in some examples, the chip on the first surface 11a can also be exposed from the first package 13. For example, the side of the chip facing away from the substrate 11 can also be flush with the side of the first package 13 facing away from the substrate 11. The chip on the second surface 11b can also be enclosed within the second package 14 and not exposed. The specific placement of the chip within the package can be selected based on the functional requirements of the chip.

[0134] Continuing with FIG3 , the chip module 10 further includes a plurality of conductive members 15 , which are spaced apart. Each conductive member 15 is fixed to the second surface 11 b of the substrate 11 and partially encapsulated within the second package 14 . The conductive members 15 can be electrically connected to the corresponding chip through the substrate 11 , thereby enabling electrical connection between the chip and an external circuit board.

[0135] For example, the substrate 11 may have a plurality of connecting traces, which may be used to achieve electrical connections between the chips. For example, as shown in FIG3 , the substrate 11 may have connecting traces 111 a and 111 b, which may extend to the first surface 11 a. The first chip 12 a and the third chip 12 c may be electrically connected via the connecting traces 111 a, and the second chip 12 b and the third chip 12 c may be electrically connected via the connecting traces 111 b.

[0136] Connecting traces can also be used to achieve electrical connection between the chip and the conductive member. For example, as shown in Figure 3, the substrate 11 can also have a connecting trace 111c, which can extend to the second surface 11b. The connecting trace 111c can be electrically connected to the fourth chip 12d and the conductive member 15, respectively. It should be noted that Figure 3 only shows a portion of the conductive member 15 and a portion of the connecting traces. For example, the substrate 11 can also have a connecting trace 111d, which can extend to the first surface 11a. The first chip 12a can be electrically connected to the conductive member (not shown) located on the second surface 11b via the connecting trace 111d.

[0137] In some examples, the chip may have an electrical connector to achieve electrical connection with the substrate. For example, taking the first chip 12a arranged on the first surface 11a of the substrate 11 as an example, the first chip 12a may have a first electrical connector 121a on the side facing the first surface 11a of the substrate 11. The first chip 12a is arranged on the first surface 11a and is electrically connected to the connecting traces (such as connecting traces 111d and connecting traces 111a) extending to the first surface 11a through the first electrical connector 121a, thereby achieving electrical connection between the chip and the substrate 11.

[0138] The chip may have multiple electrical connectors to meet the chip's electrical connection requirements. For example, referring to FIG3 , taking the first chip 12a having two first electrical connectors 121a as an example, one of the first electrical connectors 121a of the first chip 12a can be electrically connected to a connection trace 111d extending from the substrate 11 to the first surface 11a, so that the first chip 12a can be electrically connected to the conductive member via the first electrical connector 121a and the connection trace 111d. Another of the first electrical connectors 121a of the first chip 12a can be electrically connected to a connection trace 111a extending from the substrate 11 to the first surface 11a, so that the first chip 12a can be electrically connected to the third chip 12c via the first electrical connector 121a and the connection trace 111a.

[0139] Exemplarily, the connecting traces of the electrical connector and the substrate 11 can be fixed by welding to maintain a stable electrical connection. For example, the chip module can also include a welding part 16. Taking the electrical connection between the first electrical connector 121a of the first chip 12a and the connecting trace 111d in Figure 3 as an example, the first electrical connector 121a is welded to the connecting trace 111d through the welding part 16 to achieve reliable assembly and electrical connection between the first electrical connector 121a of the first chip and the substrate 11.

[0140] The welding member 16 can be a welding structure such as a welding spot or a welding pad. Of course, in some other examples, the electrical connector and the substrate 11 can also be assembled, fixed, and electrically connected in other ways. For example, the electrical connector of the chip and the connecting traces of the substrate can be fixed and electrically connected by means of a conductive clip or a fixing member.

[0141] In some other examples, the chip can also be electrically connected to the substrate 11 in other ways. For example, one side of the chip can be attached to the substrate 11, and the side of the chip facing away from the substrate 11 can have leads, and the chip can be electrically connected to the substrate 11 through the leads.

[0142] It is understandable that the type, quantity, and connection method of the chip to the substrate can be selected and set according to the function and actual needs of the chip module 10, and the number and layout of the connecting lines can also be selected and set according to the connection requirements of the chip.

[0143] One end of each conductive member 15 facing away from the substrate 11 is exposed from the second package 14, that is, the end of the conductive member 15 facing away from the substrate 11 can be exposed on the surface of the second package 14 facing away from the substrate 11, so that the end of the conductive member 15 facing away from the substrate 11 can be electrically connected to the circuit board 20 (as shown in Figure 6), thereby realizing the electrical connection between the chip of the chip module 10 and the circuit board.

[0144] For example, the end of the conductive member 15 facing away from the substrate 11 can be arranged to protrude from the side of the second package 14 facing away from the substrate 11, so that the conductive member 15 is better exposed outside the second package 14, facilitating electrical connection between the conductive member 15 and the circuit board 20.

[0145] Exemplarily, the conductive member 15 may be a solder ball, that is, a spherical welding member. For example, the conductive member 15 may be a solder ball formed of SAC305 material. The conductive member 15 may be fixed to the conductive member on the circuit board by welding to achieve electrical connection.

[0146] It should be noted that the conductive member 15 is partially enclosed in the second package 14, and the outer wall surface of the conductive member 15 can extend to the second package 14, and the outer wall surface of the conductive member 15 is in contact with the second package 14. Alternatively, as shown in FIG3 , a gap 19 can be provided between the outer wall surface of the conductive member 15 and the second package, so that the conductive member 15 has a higher degree of interface freedom during the molding process. For example, in the process of preparing a spherical conductive member 15, a gap can be provided between the molding material of the conductive member 15 and the second package to form the gap 19 after the conductive member 15 is molded. This allows the conductive member molding material to have a high degree of interface freedom, facilitates the spherical molding of the conductive member 15, and improves the molding yield of the conductive member 15.

[0147] The chip of the chip module 10 generates heat during operation. To ensure chip performance, the heat generated by the chip needs to be dissipated. The chip can have a heat-conducting area for achieving thermal contact. The heat generated by the chip during operation can be transferred to the outside of the chip through the heat-conducting area, thereby dissipating the heat of the chip. For example, if the chip is disposed on a substrate 11, a heat-conducting contact area is provided between the chip and the substrate 11. The heat of the chip can be transferred to the substrate 11 through the heat-conducting contact area, thereby dissipating the heat of the chip. The heat-conducting contact area between the chip and the substrate 11 can be the heat-conducting area of ​​the chip.

[0148] For example, in an example in which a chip is electrically connected to a substrate 11 through an electrical connector, the end surface at which the electrical connector is connected to the substrate 11 can be a heat-conducting area of ​​the chip. Referring to FIG3 , taking the first chip 12a disposed on the first surface 11a of the substrate 11 as an example, the first electrical connector 121a of the first chip 12a is in contact and electrically connected with the connecting trace 111d of the substrate 11. The heat generated by the first chip 12a can be transferred to the substrate 11 through the first electrical connector 121a, thereby achieving heat dissipation of the first chip 12a. The end surface at which the first electrical connector 121a is connected to the substrate 11 can form a heat-conducting area 121 of the first chip 12a (as shown in FIG4 ).

[0149] Of course, in some other examples, when the chip realizes heat transfer through other means, the heat conduction area can also be other contact areas for the chip to realize heat transfer. For example, in the example where one side of the chip is bonded to the substrate 11, the heat generated by the chip is transferred to the substrate 11 through the side of the chip bonded to the substrate 11, and the side of the chip bonded to the substrate 11 can form the heat conduction area of ​​the chip. Alternatively, in some other examples, the chip is set on the substrate 11, and when the chip can be bonded to a heat sink (such as a first heat sink) with a higher thermal conductivity than that of the substrate 11, the heat generated by the chip is transferred to the heat sink through the side of the chip bonded to the heat sink, thereby realizing heat dissipation of the chip, and the side of the chip bonded to the heat sink can form the heat conduction area of ​​the chip.

[0150] In order to improve the heat dissipation effect of the first chip 12a, referring to Figure 3, the chip module 10 also includes a first heat sink 17. The first heat sink 17 can be located between the first surface 11a of the substrate 11 and the side of the second package 14 facing away from the substrate 11, that is, the first heat sink 17 will not be exposed from the first surface 11a.

[0151] Furthermore, the first heat sink 17 is at least partially encapsulated within the second package 14. For example, the first heat sink 17 may include a first end 17a and a second end 17b that are opposite in the thickness direction (x direction). The second end 17b may be disposed relatively close to the first surface 11a, while the first end 17a may be disposed relatively far from the first surface 11a. At least the first end 17a of the first heat sink 17 is located within the second package 14. The second end 17b may extend into the substrate 11, such that the first heat sink 17 is partially located within the substrate 11 and partially located within the second package 14. Alternatively, the second end 17b may be fixed to the second surface 11b of the substrate 11.

[0152] FIG4 is a bottom view of the chip module in FIG3 , wherein the dotted line in FIG4 illustrates the vertical projection of the first chip 12 a on the second package 14 .

[0153] The first heat sink 17 can be used to dissipate heat for the first chip 12a. It is understood that, unlike the related art where chips dissipate heat through a ball grid array (BGA) composed of solder balls, the layout of the first heat sink 17 is not limited by manufacturing processes and short-circuit prevention design constraints, as shown in FIG3 . This ensures that the first heat sink 17 is located below the heat conduction region (i.e., the first electrical connector 121a) of the first chip 12a. As shown in FIG4 , the vertical projection (projection along the x-direction) of the first heat sink 17 on the substrate (or second package 14) can at least partially cover the vertical projection (projection along the x-direction) of the heat conduction region 121 of the first chip 12a on the substrate (or second package 14). This allows heat generated by the first chip 12a to be transferred along the x-direction to the first heat sink 17 via the heat conduction region 121, and then to the outside of the chip module 10 through the first heat sink 17, achieving heat dissipation. This effectively shortens the heat dissipation path and reduces thermal resistance. Furthermore, the first heat sink 17 does not need to maintain a spacing to prevent short circuits, and can achieve a larger projected coverage area, significantly improving the heat dissipation effect, thereby greatly improving the performance of the first chip 12 a and the entire chip module 10 .

[0154] It should be noted that the conductive member 15 can also be used to achieve heat dissipation of the chip. For example, part of the conductive member 15 is made to coincide with the vertical projection of the heat-conducting area of ​​the chip on the substrate 11. The heat generated by the chip during operation can also be transferred to the outside of the chip module 10 through the conductive member 15.

[0155] The molding material of the first heat dissipation member 17 may be a material with high thermal conductivity, for example, the thermal conductivity of the first heat dissipation member 17 is greater than the thermal conductivity of the conductive member 15 .

[0156] For example, the thermal conductivity of the first heat sink 17 may be greater than 100 W / mK. The first heat sink 17 can dissipate heat for the first chip 12 a , ensuring a low thermal resistance and achieving a good heat dissipation effect.

[0157] For example, in some examples, the thermal conductivity of the first heat sink 17 may be 200 W / mK to 600 W / mK, which can further reduce thermal resistance, improve heat dissipation effect, and achieve better heat dissipation effect for the first chip 12 a.

[0158] In some examples, the thermal conductivity of the first heat sink 17 may be approximately 400 W / mK. For example, the molding material of the first heat sink 17 may include metallic copper, which can achieve better heat dissipation effect, lower cost, and facilitate production.

[0159] Of course, in some other examples, the first heat sink 17 may also be made of other types of metal materials, such as aluminum, silver, and the like.

[0160] For example, the thickness of the first heat sink 17 may be greater than 30 μm to ensure that the first heat sink 17 has good thermal conductivity, thereby facilitating good heat dissipation for the first chip 12 a.

[0161] For example, in some examples, the thickness of the first heat sink 17 can be 40 μm to 50 μm, which is conducive to achieving better heat dissipation effect. For example, the thickness of the first heat sink 17 can be about 40 μm or 50 μm, so that the first heat sink 17 can achieve better heat dissipation effect.

[0162] The first heat sink 17 may be a structural member. For example, the first heat sink 17 may be a whole heat sink block. The shape of the first heat sink 17 may be a regular or irregular shape such as a cylinder or a cube.

[0163] Alternatively, the first heat sink 17 may also include a plurality of sub-heat sinks. For example, each sub-heat sink may be a heat sink block, and the shape of each sub-heat sink may be a regular or irregular shape such as a cylinder or a cube.

[0164] The cross-sectional area of ​​the first heat sink 17 can be larger than that of one of the conductive members 15. In this embodiment, the cross-sectional area refers to the area of ​​a cross section formed by cutting a component (e.g., the first heat sink or conductive member) along a plane perpendicular to the thickness direction (x-direction). Specifically, the vertical projection of the first heat sink 17 on the substrate is larger than the vertical projection of one of the conductive members 15 on the substrate. This allows the first heat sink 17 to cover a larger area, and the vertical projection of the first heat sink 17 can cover a larger heat conduction area. Compared to heat dissipation of the first chip through conductive members such as solder balls, this increases the heat dissipation area and provides better heat dissipation performance.

[0165] For example, the cross-sectional area of ​​the first heat sink 17 may be greater than π*(D / 2) 2 , where D can be the diameter of a spherical conductive member 15, for example, the range of D can be 200μm to 300μm, ensuring that the first heat dissipation member 17 can cover a larger area of ​​heat conduction area and achieve better heat dissipation performance.

[0166] It should be noted that the heat conduction area 121 of the first chip 12a may include multiple ones. For example, taking the example of the first chip 12a being electrically connected to the substrate through an electrical connector, multiple electrical connectors may be provided on the surface of the first chip 12a facing the substrate, as shown in Figure 4. For example, if the first chip 12a has a first electrical connector 121a and a third electrical connector 121b, the first chip 12a is electrically connected to the substrate through the first electrical connector 121a and the third electrical connector 121b respectively, and the end surface of the first electrical connector 121a connected to the substrate and the end surface of the third electrical connector 121b connected to the substrate can respectively form the heat conduction area 121 of the first chip 12a.

[0167] In some examples, the vertical projection of the first heat dissipation member 17 on the substrate can completely cover the vertical projections of the plurality of heat conduction regions 121 on the substrate, thereby achieving a better heat dissipation effect.

[0168] Alternatively, in some examples, the vertical projection of the first heat sink 17 on the substrate may also only cover part of the vertical projection of the heat conducting area 121 on the substrate, thereby achieving a good heat dissipation effect, reducing the area of ​​the first heat sink 17, and helping to reduce the difficulty of structural design and production costs.

[0169] Exemplarily, the multiple heat-conducting regions may include at least a first region, where the first region is the region with the largest cross-sectional area among the multiple heat-conducting regions. For example, the end surface of the first electrical connector 121a connected to the substrate forms a heat-conducting region 1211, and the end surface of the third electrical connector 121b connected to the substrate forms a heat-conducting region 1212. The cross-sectional area of ​​the first electrical connector 121a may be the largest among the multiple electrical connectors, so that the heat-conducting region 1211 may be the region with the largest cross-sectional area among the multiple heat-conducting regions 121, that is, the heat-conducting region 1211 may be the first region.

[0170] The vertical projection of the first heat sink 17 on the substrate can at least partially cover the vertical projection of the first area on the substrate, which is conducive to dissipating the heat generated by the first chip 12a through the electrical connector with a larger cross-sectional area and the first heat sink 17, further reducing the thermal resistance and achieving good heat dissipation for the first chip 12a.

[0171] For example, the vertical projection of the first heat sink 17 on the substrate covers at least 50% of the vertical projection area of ​​the first region on the substrate, which can further improve the heat dissipation effect on the first chip 12 a.

[0172] In some examples, the vertical projection of the first heat sink 17 on the substrate may cover 80% to 90% of the vertical projection area of ​​the first region on the substrate, thereby achieving a better heat dissipation effect on the first chip 12 a.

[0173] For example, the vertical projection of the first heat sink 17 on the substrate can cover at least 50% of the vertical projection area of ​​the first chip 12a on the substrate, which is conducive to the vertical projection of the first heat sink 17 covering a larger area of ​​the heat conduction area 121, thereby achieving good heat dissipation for the first chip 12a.

[0174] For example, the vertical projection of the first heat sink 17 on the substrate may cover 80% to 90% of the vertical projection area of ​​the first chip 12 a on the substrate, which may further improve the heat dissipation effect on the first chip 12 a.

[0175] In some examples, the vertical projection of the first heat sink 17 on the substrate can completely cover the vertical projection of the first chip 12a on the substrate, thereby achieving a better heat dissipation effect for the first chip 12a. It should be noted that the shape, cross-sectional dimensions, etc. of the first heat sink 17 can be the same as the shape, cross-sectional dimensions, etc. of the first chip 12a, so that the vertical projection of the first heat sink 17 on the substrate can completely overlap with the vertical projection of the first chip 12a on the substrate. Alternatively, the cross-sectional dimensions of the first heat sink 17 can be larger than the cross-sectional dimensions of the first chip 12a, so that the vertical projection area of ​​the first heat sink 17 on the substrate can be larger than the vertical projection of the first chip 12a on the substrate, and the projection of the first heat sink 17 completely covers the projection of the first chip 12a.

[0176] It can be understood that in order to transfer the heat of the chip module 10 to the outside of the chip module 10, the first heat sink 17 can be exposed or the first heat sink 17 can be connected to other structural parts to transfer the heat and achieve heat dissipation. For example, the first heat sink 17 can be connected to the circuit board to transfer the heat of the chip module 10 to the circuit board, thereby achieving heat dissipation.

[0177] In order to expose the first heat sink or connect it to other structural parts, the first heat sink needs to be exposed from the second package. For example, after covering the packaging layer on the second surface, the packaging layer can be thinned by grinding to form the second package, and the conductive part and the first heat sink are exposed. Due to the existence of process tolerances, etc., in order to ensure the exposure of the first heat sink, it is usually necessary to grind and remove part of the first heat sink, that is, the grinding and removal depth of the packaging layer (thickness in the x direction) needs to reach a position that can remove part of the first heat sink. The first heat sink is thinned at the same time as the packaging layer. However, since the molding material of the first heat sink is different from the molding material of the packaging layer, during the thinning process, delamination, cracks or separation problems are prone to occur at the intersection of the circumferential side wall of the first heat sink and the packaging layer, resulting in poor yield. Moreover, when the chip module is fixed to the circuit board by welding or other methods, the solder on the circuit board can easily enter the delamination, cracks or separation parts, thereby causing problems such as short circuits.

[0178] Therefore, in the embodiment of the present application, as shown in FIG3 , the first end surface of the first heat sink 17 is recessed in the thickness direction relative to the surface of the second package 14 facing away from the substrate 11. That is, the first end surface of the first heat sink 17 is recessed inward from the surface of the second package 14 facing away from the substrate 11. In the thickness direction (x direction), the distance from the first end surface of the first heat sink 17 to the second surface 11b is smaller than the distance from the surface of the second package 14 facing away from the substrate 11 to the second surface 11b, so that a predetermined distance is maintained between the first end surface of the first heat sink 17 and the surface of the second package 14 facing away from the substrate 11 in the x direction. It should be noted that, since the first end surface of the first heat dissipation member 17 is sunken from the side of the second package 14 facing away from the substrate 11, the side of the second package 14 facing away from the substrate 11 is actually non-planar. In order to illustrate that there is a preset distance between the first end surface of the first heat dissipation member 17 and the side of the second package 14 facing away from the substrate 11 in the x direction, the side of the second package 14 facing away from the substrate 11 can be a virtual plane, and the virtual plane can be consistent with the side of the packaging thin layer (the part of the packaging layer that has not been removed) formed after the packaging layer is thinned, which is facing away from the substrate. The preset distance between the first end surface of the first heat dissipation member 17 and the side of the second package 14 facing away from the substrate 11 can be the preset distance between the virtual plane and the first end surface of the first heat dissipation member 17 in the thickness direction, as shown in h in Figure 3.

[0179] During the thinning process of the packaging layer, the grinding and removal depth (thickness in the x direction) does not reach the position of the first heat sink 17 (the first end face position). After the packaging layer is thinned, the first end of the first heat sink 17 is located inside the portion of the packaging layer (the packaging thin layer) that has not been removed (as shown in Figure 15e). For example, a preset distance can be provided between the first end face of the first heat sink 17 and the side of the packaging thin layer facing away from the substrate. After the second packaging member 14 is formed by the packaging thin layer so that the first end face of the first heat sink 17 is recessed inward relative to one side of the second packaging layer 14, the first end face of the first heat sink 17 and the side of the second packaging layer facing away from the substrate 11 still retain the preset distance. The first heat sink is not thinned while the packaging layer is thinned, thus avoiding problems such as delamination, cracks or separation at the junction of the circumferential side wall of the first heat sink 17 and the packaging layer during the thinning process. The grinding operability and reliability of the side of the packaging layer facing away from the substrate 11 during the thinning process can be improved, the yield rate can be improved, and the occurrence of problems such as short circuit can be avoided, thereby having higher reliability.

[0180] Exemplarily, the preset distance h between the first end face of the first heat sink 17 and the side of the second package 14 facing away from the substrate 11 can be in the range of 10μm to 20μm, ensuring that the position of the first heat sink 17 will not be removed during the thinning process of the package layer. After the thinning process, the first end of the first heat sink 17 is located inside the package thin layer that has not been removed, thereby improving the reliability and operability of the thinning process.

[0181] In some examples, as shown in FIG3 , a groove 18 may be provided on a surface of the second package 14 facing away from the substrate 11. For example, the second package 14 may be formed by processing a thin package layer through laser grooving or other methods, and the groove 18 may be formed on the surface of the second package 14 facing away from the substrate 11. The groove 18 may be located on a side of the first heat sink 17 facing away from the substrate 11, and the groove 18 may extend to the first end of the first heat sink 17, thereby causing the first end surface of the first heat sink 17 to be recessed inward relative to the surface of the second package 14 facing away from the substrate 11.

[0182] Illustratively, the first end of the first heat sink 17 can be partially exposed on the side of the second package 14 facing away from the substrate 11 through the groove 18, so that the heat of the first chip 12a can be transferred to the outside of the chip module 10 through the first heat sink 17, or the first end of the first heat sink 17 can be connected to other structural parts.

[0183] For example, when the chip module 10 is connected and assembled with the circuit board, the first end of the first heat sink 17 can be fixedly assembled with the circuit board, so that the heat of the first chip 12a can be transferred to the circuit board and dissipated. For example, as shown in FIG4 , the end of the conductive member 15 facing away from the substrate and the end of the first heat sink 17 facing away from the substrate can be exposed from the second package 14. When the chip module 10 is connected and assembled with the circuit board, the end of the conductive member 15 facing away from the substrate can be fixed to the circuit board by welding or other means to achieve electrical connection. The exposed portion of the first heat sink 17 can be fixedly assembled with the circuit board to transfer the heat of the first chip to the outside of the chip module.

[0184] The shape of the groove 18 can be circular. Alternatively, in some examples, the shape of the groove 18 can also be rectangular, elliptical or other regular or irregular shapes.

[0185] FIG5 is a schematic diagram of the cross-sectional structure of another chip module provided in an embodiment of the present application.

[0186] Alternatively, in some examples, as shown in FIG. 5 , the chip module 10 may further include a first connector 110 . The first connector 110 may be disposed on the first heat sink 17 , and the first connector 110 may be located in the provided groove.

[0187] Among them, the setting of the groove can enable the first connector to have a higher interface freedom during the molding process. For example, in the process of preparing the spherical first connector, the molding material of the first connector can be placed in the groove and there is a gap between it and the second package, so that the molding material of the first connector has a high degree of freedom, which is beneficial to the spherical molding of the first electrical connector and improves the molding yield of the first electrical connector.

[0188] It should be noted that the first connector 110 can partially fill the groove, allowing the first connector 110 to maintain a higher degree of interface freedom during the molding process. If the vertical projection of the formed first connector 110 on the substrate 11 partially covers the vertical projection of the groove on the substrate 11, as shown in Figure 5, a gap 181 can be formed between the outer wall surface of the first connector 110 and the second package 14. In other words, the vertical projection of the first connector 110 on the first end of the first heat sink 17 partially covers the exposed portion of the first end of the first heat sink 17, allowing a portion of the first heat sink 17 to still be exposed from the side of the second package 14 facing away from the substrate 11.

[0189] Alternatively, the first connector 110 may also fill the entire groove, such that the vertical projection of the first connector 110 on the substrate 11 completely covers the vertical projection of the groove on the substrate 11, and the outer wall surface of the first connector 110 located in the groove extends to the second package 14, so that the vertical projection of the first connector 110 on the first end of the first heat sink 17 can completely cover the exposed portion of the first end of the first heat sink 17, and the first heat sink 17 will not be exposed from the side of the second package 14 facing away from the substrate 11.

[0190] FIG6 is a schematic diagram of the chip module and the circuit board assembly in FIG5 .

[0191] As shown in Figure 6, when assembled and connected with the circuit board 20, the first heat sink 17 can be fixedly assembled with the circuit board 20 through the first connecting member 110, thereby improving the assembly stability of the chip module 10 and the circuit board 20, and can also transfer heat to the circuit board 20 for dissipation, thereby improving the heat dissipation effect.

[0192] Illustratively, the end of the first connector 110 facing away from the first heat sink 17 can protrude from the side of the second package 14 facing away from the substrate 11, that is, the end of the first connector 110 facing away from the first heat sink 17 protrudes from the second package 14, thereby facilitating the assembly of the first connector 110 and the circuit board 20.

[0193] In some examples, the first connector 110 may be a welding member, for example, the first connector 110 may also be a solder ball, such as a tin ball, and the first connector 110 may be fixed to the conductive member on the circuit board 20 by welding.

[0194] In some examples, the first connector 110 can be electrically connected to the circuit board 20, and the first heat sink 17 can be electrically connected to the chip through the substrate 11, so that the chip can be electrically connected to the circuit board 20 through the first heat sink 17 and the first connector 110. For example, as shown in FIG6 , the substrate 11 can have a connecting trace 111e, and the fourth chip 12d located on the second surface 11b can be electrically connected to the first heat sink 17 through the connecting trace 111e. The first heat sink 17 can be electrically connected to the circuit board 20 through the first connector 110, thereby electrically connecting the fourth chip 12d to the circuit board 20. For example, this connection method can achieve grounding of the fourth chip 12d.

[0195] Of course, in other examples, the first heat sink 17 and the chip may not be connected, and the first connector 110 and the circuit board 20 may only serve as a heat-conducting connection without the need for an electrical connection.

[0196] Alternatively, in some examples, the first connector 110 may also be other types of connecting structural members. For example, the first connector 110 may also be an adhesive layer, a clamping member, a threaded fastener, etc., so that the chip module 10 can be fixed to the circuit board 20 by bonding, clamping, threaded fastening, etc.

[0197] It should be noted that, in some examples, as shown in Figure 6, the number of first connecting members 110 fixed on the first heat sink 17 can be multiple. For example, multiple first connecting members 110 can be arranged in an array on the first heat sink 17, and the multiple first connecting members 110 can be arranged at intervals.

[0198] FIG7 is a schematic diagram of the cross-sectional structure of another chip module provided in an embodiment of the present application.

[0199] Alternatively, in some other examples, as shown in FIG. 7 , the number of the first connecting member 110 may also be one.

[0200] The following describes the assembly relationship among the first chip 12 a , the first heat sink 17 , and the substrate 11 by taking the example that the first heat sink 17 covers at least the first region of the first chip 12 a .

[0201] In some examples, as shown in FIG. 7 , the first chip 12 a may be disposed on the first surface 11 a of the substrate 11 .

[0202] The first chip 12a has a first electrical connector 121a on the surface facing the substrate 11. The connecting traces 111d of the substrate 11 can extend to the first surface 11a of the substrate 11. The first electrical connector 121a of the first chip 12a and the connecting traces 111d can be electrically connected via soldering elements 16, thereby achieving an electrical connection between the first chip 12a and the substrate 11. Heat from the first chip 12a is transferred to the substrate 11 via the first electrical connector 121a, and then dissipated via the first heat sink 17. The end surface of the first electrical connector 121a connected to the substrate 11 forms a heat conduction region (e.g., a first region) of the first chip 12a.

[0203] For example, the first heat sink 17 can be fixed to the second surface 11b of the substrate 11. For example, the second end of the first heat sink 17 is fixed to the second surface 11b of the substrate 11, so that the first chip 12a and the first heat sink 17 are respectively located on the first surface 11a and the second surface 11b of the substrate 11, resulting in a relatively simple structural design. When preparing the chip module 10, the first heat sink 17 can be placed on the second surface 11b when the chip is placed on the second surface 11b. This is fully compatible with the existing DSBGA package chip module preparation process in the related art, does not require additional steps, and is conducive to cost savings.

[0204] In the embodiment of the present application, a simulation is performed on the heat dissipation effect of the chip module 10. Fig. 8 is a schematic diagram of a junction-to-board thermal resistance model of the first chip in the chip module of Fig. 7 .

[0205] As shown in FIG8 , first electrical connector 121a of first chip 12a is connected to connection trace 111d on first surface 11a of substrate 11 via soldering member 16. Taking the example of first heat sink 17 being secured to conductive member 21 on a circuit board by soldering, a soldering layer 22 may be provided between first heat sink 17 and conductive member 21. Connection trace 111e on second surface 11b of substrate 11 is connected to conductive member 21 on the circuit board via first heat sink 17 and soldering layer 22. First heat sink 17 is formed of copper.

[0206] The position of the first chip 12a opposite to the heat conduction area can serve as a heat source S. Heat can be transferred from the first electrical connector 121a of the first chip 12a to the circuit board in sequence along the thickness direction, forming a constant temperature surface H on the circuit board side.

[0207] A DSBGA packaged chip module from the related art serves as a comparison group. In this comparison group, the solder balls are positioned in an ideal location for theoretically optimal heat dissipation. For example, the solder balls are positioned below the heat-conducting area of ​​the first chip. The first electrical connector of the first chip is connected to the connecting traces on the first surface of the substrate via a soldering member, and the connecting traces on the second surface of the substrate are connected to the conductive members on the circuit board via the solder balls and solder layer. The solder balls are tin balls. Table 1 shows the molding materials and thermal conductivity coefficients of the structural components in the aforementioned model. Chip module 400 in the comparison group shares other structural designs with chip module 10 in the embodiment of the present application.

[0208] Table 1 shows the molding materials and thermal conductivity of some structural components in the above model.

[0209] FIG. 9 is a schematic diagram of heat conduction simulation of the first chip of the ball grid array chip module in the related art, and FIG. 10 is a schematic diagram of heat conduction simulation of the first chip in the chip module of FIG. 7 .

[0210] As shown in Figures 9 and 10, even compared with the theoretically ideal ball grid array chip module 500, the chip module 10 of the embodiment of the present application uses a first heat sink 17 formed of metal copper to replace the solder balls, so that the vertical projection of the first heat sink 17 at least covers the vertical projection of a portion of the heat conduction area of ​​the first chip 12a (such as covering the first area), and the temperature difference is reduced by 35%, which has a more significant heat dissipation effect.

[0211] FIG11 is a schematic cross-sectional structure diagram of another chip module provided in an embodiment of the present application.

[0212] In some examples, as shown in FIG. 11 , to further improve heat dissipation performance, a first heat dissipation member 17 is fixed on the second surface 11 b of the substrate 11 , and the substrate 11 may further be provided with a second heat dissipation member 112 .

[0213] The molding material of the second heat sink 112 can also be a material with high thermal conductivity. The molding material of the second heat sink 112 can be the same as the molding material of the first heat sink 17. The molding material, shape and thermal conductivity of the second heat sink 112 can refer to the first heat sink 17 and will not be repeated in this example.

[0214] The second heat sink 112 can be located on the side of the first surface 11a facing the second surface 11b. The second heat sink 112 is located between the first surface 11a and the side of the second package 14 facing away from the substrate 11. This means that the second heat sink 112 does not protrude from the first surface 11a. The vertical projection of the second heat sink 112 on the substrate 11 can at least partially overlap with the vertical projection of the first heat sink 17 on the substrate 11. This means that the projection of the second heat sink 112 along the x-direction on the substrate 11 at least partially overlaps with the projection of the first heat sink 17 along the x-direction on the substrate 11. This reduces the thermal resistance in the heat dissipation path from the first chip 12a to the first heat sink 17, further improving the heat dissipation effect.

[0215] It should be noted that the vertical projections of the second heat sink 112 and the first heat sink 17 on the substrate 11 can completely overlap, or the vertical projections of the second heat sink 112 and the first heat sink 17 on the substrate 11 can partially overlap. For example, the vertical projection of the second heat sink 112 on the substrate 11 can cover at least 50% of the vertical projection area of ​​the first heat sink 17 on the substrate 11, ensuring better heat dissipation effect.

[0216] In one possible implementation, as shown in FIG11 , the second heat sink 112 can be located inside the substrate 11 , that is, between the first surface 11 a and the second surface 11 b , without being exposed from the first surface 11 a or the second surface 11 b . This improves heat dissipation while simplifying the structural design and facilitating implementation.

[0217] FIG12 is a schematic diagram of the cross-sectional structure of another chip module provided in an embodiment of the present application.

[0218] In another possible implementation, as shown in Figure 12, one end of the second heat sink 112 can be located inside the substrate 11, and the other end of the second heat sink 112 can extend toward the second package 14 along the thickness direction. The second end of the first heat sink 17 can be fixed to the other end of the second heat sink 112, so that the first heat sink 17 is fixed on the second surface 11b, which is conducive to increasing the thickness of the second heat sink 112 and further reducing the thermal resistance, and enriching the fixed assembly method between the first heat sink 17 and the second surface 11b of the substrate 11, with better structural design flexibility.

[0219] Illustratively, the other end surface of the second heat sink 112 can extend to the side of the substrate 11 facing away from the first surface 11a, and the other end surface of the second heat sink 112 can be flush with the side of the substrate 11 facing away from the first surface 11a, so that the other end surface of the second heat sink 112 is used to form part of the second surface 11b, and the first heat sink 17 is fixed on the other end surface of the second heat sink 112.

[0220] For example, to achieve the fixation between the first heat sink 17 and the second heat sink 112, the chip module 10 may further include a second connector 120, through which the first heat sink 17 may be fixed to an end surface of the second heat sink 112 facing away from the first surface 11a.

[0221] The second connecting member 120 may also be a welding member, for example, the second connecting member 120 may be a solder ball, a solder pad, etc., so that the first heat sink 17 can be fixed to the end surface of the second heat sink 112 by welding.

[0222] Alternatively, the second connecting member 120 may also be other types of connecting structural members. For example, the second connecting member 120 may also be an adhesive layer, a clip, a threaded fastener, etc., so that the first heat sink 17 can be fixed together with the end face of the second heat sink 112 by bonding, clipping, threaded fastening, etc.

[0223] FIG13 is a schematic diagram of the cross-sectional structure of another chip module provided in an embodiment of the present application.

[0224] Alternatively, in some other examples, as shown in FIG13 , the second end of the first heat sink 17 can extend into and be fixed to the interior of the substrate 11, that is, the first heat sink 17 is inserted into the substrate 11, a portion of the first heat sink 17 is located inside the substrate 11, and a portion of the first heat sink 17 is located within the second package 14. Extending and fixing the second end of the first heat sink 17 into and inside the substrate 11 further reduces thermal resistance and improves heat dissipation, thereby reducing the number of heat sinks provided on the substrate 11, simplifying the structural design and molding process, and reducing costs.

[0225] FIG14 is a schematic diagram of the cross-sectional structure of another chip module provided in an embodiment of the present application.

[0226] Alternatively, in some other examples, as shown in FIG. 14 , the first chip 12 a may be disposed on the second surface 11 b of the substrate 11 .

[0227] The first chip 12a has a second electrical connector 121c on the surface facing the substrate 11, and the connecting trace 111d of the substrate 11 can be located on the second surface 11b of the substrate 11. The first chip 12a can be electrically connected to the connecting trace 111d of the substrate 11 through the second electrical connector 121c, and then electrically connected to the conductive member 15 through the connecting trace 111d.

[0228] Correspondingly, the second electrical connector 121 c of the first chip 12 a may also be electrically connected to the connecting trace 111 d via the soldering member 16 .

[0229] The first heat sink 17 can be fixed on the side of the first chip 12a facing away from the substrate 11. The heat generated by the first chip 12a is transferred to the first heat sink 17 to achieve heat dissipation. The side of the first chip 12a facing the first heat sink 17 forms a heat conduction area of ​​the first chip 12a, further shortening the heat dissipation path, reducing thermal resistance, and improving heat dissipation efficiency.

[0230] For example, the first heat sink 17 can be formed by the back gold layer of the first chip 12a itself, thereby enriching the layout of the first chip 12a and the first heat sink 17 and improving the layout flexibility.

[0231] Of course, in some other examples, the first heat sink 17 may also be a heat dissipation structure component additionally provided on the first chip 12 a.

[0232] An embodiment of the present application also provides a method for preparing a chip module. FIG15 is a flow chart of a chip module preparation method provided in an embodiment of the present application. Referring to FIG15 , the above-mentioned chip module 10 can be prepared by this preparation method.

[0233] The preparation method comprises:

[0234] S101: Provide a substrate, a first heat sink, and a plurality of chips.

[0235] FIG15 a is a schematic diagram of a chip module provided in an embodiment of the present application after some chips are assembled on a substrate.

[0236] As shown in Figure 15a, the substrate 11 has a first surface 11a and a second surface 11b opposite to each other in the thickness direction. The substrate 11 has connecting traces inside, and the connecting traces can extend to the first surface 11a and the second surface 11b of the substrate 11. For example, the connecting trace 111a extends to the first surface 11a of the substrate 11, and the connecting trace 111c is located on the second surface 11b of the substrate 11.

[0237] The specific structures of the substrate 11 , the connecting wires, the chip and the first heat sink 17 can be found in the above text and will not be described in detail in this example.

[0238] S102 : Disposing some of the plurality of chips on a first surface to form a first package on the first surface.

[0239] As shown in Figure 15a, some chips are assembled on the first surface 11a of the substrate 11. For example, taking the first chip 12a fixed on the first surface 11a of the substrate 11 as an example, the first chip 12a, the second chip 12b and the third chip 12c are assembled and fixed on the first surface 11a, and the first chip 12a, the second chip 12b and the third chip 12c are electrically connected to the connection lines of the substrate 11 accordingly.

[0240] The chip can be fixed on the first surface 11a by surface mounted technology (SMT), or the chip can be fixed on the first surface 11a by welding, bonding, etc.

[0241] FIG15 b is a schematic diagram of a chip module provided in an embodiment of the present application after the first package is formed on the substrate.

[0242] As shown in FIG15b , a first package 13 is formed on the first surface 11a of the substrate 11. The first package 13 can cover the first surface 11a and at least partially encapsulate the chips on the first surface 11a within the first package 13, thereby achieving plastic sealing of the chips on the first surface 11a. For example, the first chip 12a, the second chip 12b, and the third chip 12c can be encapsulated within the first package 13.

[0243] S103: Disposing another portion of the plurality of chips on the second surface, with at least the first end of the first heat sink being located on the second surface.

[0244] FIG15c is a schematic diagram of a chip module provided in an embodiment of the present application after chips and solder joints are assembled on a substrate.

[0245] 15 c , another portion of chips is mounted on the second surface 11 b of the substrate 11 . For example, a fourth chip 12 d is mounted and fixed on the second surface 11 b , and the fourth chip 12 d is electrically connected to corresponding connection traces of the substrate 11 .

[0246] The chip can also be fixed on the second surface 11b by SMT mounting, welding, bonding, etc.

[0247] For example, before or after the chip is placed on the second surface 11b, at least the first end of the first heat sink can be positioned on the second surface. Referring to FIG. 15c , taking the second end of the first heat sink 17 fixed to the second surface 11b of the substrate 11 as an example, the first heat sink 17 can be fixed to the second surface 11b before or after the chip is placed on the second surface 11b. Furthermore, the vertical projection of the first heat sink 17 on the substrate 11 at least partially covers the vertical projection of the heat conduction area of ​​the first chip 12a on the substrate 11.

[0248] S104: forming an encapsulation layer on the second surface.

[0249] FIG15 d is a schematic diagram of a chip module in an embodiment of the present application after the encapsulation layer is formed on the second surface of the substrate.

[0250] 15d , the packaging layer 141 covers the second surface 11b and wraps the chip and the first heat sink 17 on the second surface 11b . For example, the fourth chip 12d and the first heat sink 17 are wrapped inside the packaging layer 141 .

[0251] S105: thinning the encapsulation layer to form an encapsulation thin layer.

[0252] For example, the encapsulation layer may be thinned by grinding or other methods.

[0253] Figure 15e is a schematic diagram of a chip module after the packaging layer is thinned in an embodiment of the present application.

[0254] Part of the encapsulation layer can be removed to achieve thinning of the encapsulation layer. As shown in FIG15e, the unremoved portion of the encapsulation layer forms an encapsulation thin layer 141a, which is used to form a second encapsulation component. After the encapsulation layer is thinned to form the encapsulation thin layer 141a, the first end of the first heat sink 17 is wrapped within the encapsulation thin layer 141a. For example, a predetermined distance h can be provided between the first end surface of the first heat sink 17 and the surface of the encapsulation thin layer 141a facing away from the substrate 11. After thinning, the first heat sink 17 is not exposed on the surface of the encapsulation thin layer 141a facing away from the substrate 11. That is, in the process of thinning the packaging layer, the depth of grinding and removal (thickness along the x-direction) does not reach the position of the first heat sink 17 (the first end face), and the first heat sink 17 is not thinned while the packaging layer is thinned. This avoids problems such as delamination, cracks or separation at the junction of the circumferential side wall of the first heat sink 17 and the packaging layer during the grinding and thinning process, improves the workability and reliability of the grinding of the packaging layer, improves the yield, and can also avoid problems such as short circuits.

[0255] S106 : processing the package thin layer to form a second package, so that an end surface of the first heat dissipation element is recessed in a thickness direction relative to a surface of the second package facing away from the substrate.

[0256] For example, the second package can be formed by grooving the package thin layer, or by targetedly removing the portion of the package thin layer opposite to one end of the first heat sink, so that the first end surface of the first heat sink is recessed inward relative to the side of the second package facing away from the substrate, that is, the first end surface of the first heat sink is recessed toward the first package in the thickness direction relative to the side of the second package facing away from the substrate.

[0257] Exemplarily, the step S106 of processing the encapsulation thin layer to form the second package may include: forming a groove on a surface of the encapsulation thin layer facing away from the substrate to form the second package.

[0258] For example, a groove may be formed on the surface of the packaging layer facing away from the substrate 11 by laser grooving to form the second packaging component.

[0259] FIG15f is a schematic diagram of a second package after being formed in a chip module provided in an embodiment of the present application.

[0260] As shown in FIG15f , the second package 14 is formed with a groove 18 on the side facing away from the substrate 11. The groove 18 can be located on the side of the first heat sink 17 facing away from the substrate 11. The groove 18 extends to the first end of the first heat sink 17, thereby causing the first end surface of the first heat sink 17 to be recessed in the thickness direction relative to the side of the second package 14 facing away from the substrate 11. This ensures that a predetermined distance h is maintained between the first end surface of the first heat sink 17 and the side of the second package 14 facing away from the substrate 11 in the thickness direction.

[0261] To form conductive elements of the chip module to achieve electrical connection between the chip module and an external circuit board, before forming a packaging layer on the second surface in step S104 , the method further includes: forming a plurality of spaced solder joints on the second surface.

[0262] For example, multiple solder balls can be formed on the second surface by tinning as multiple solder joints 15a (see FIG. 15c ), and the multiple solder joints 15a are spaced apart from each other. The solder joints 15a can be electrically connected to the corresponding connection traces on the second surface 11b, thereby achieving electrical connection between the chip and the corresponding solder joints.

[0263] Step S104 of forming a packaging layer on the second surface includes: wrapping the solder joints with the packaging layer (see FIG. 15 d ).

[0264] After forming the packaging layer on the second surface in step S104, the method further includes: thinning the solder joint member to form a conductive member.

[0265] Among them, the packaging layer and the solder joint parts can be simultaneously thinned by grinding and removing (refer to Figure 15d and Figure 15e), and the unremoved packaging thin layer 141a is used to form the second packaging part 14, and the unremoved part of the solder joint parts is used to form the conductive part 15, ensuring that the end of the conductive part 15 facing away from the substrate 11 is exposed on the side of the second packaging part 14 facing away from the substrate 11, so that the conductive part 15 is exposed from the second packaging part 14.

[0266] Exemplarily, thinning the solder joint member to form the conductive member may include:

[0267] S1041: Thinning the weld joint to form a transition weld joint.

[0268] The portion of the solder joint that is not removed after thinning forms a transition solder joint 15b (see FIG. 15f ).

[0269] S1042: forming a notch structure on a surface of the packaging thin layer facing away from the substrate.

[0270] For example, a notch structure 19a can be formed on the side of the packaging thin layer facing away from the substrate 11 by laser grooving or the like. The notch structure 19a can be arranged around the transition solder joint 15b so that after the packaging thin layer forms the second package, the second package 14 has a notch structure 19a on the side facing away from the substrate 11 (as shown in FIG. 15f ).

[0271] S1043: Disposing a first solder structure on the transition solder joint, and subjecting the transition solder joint and the first solder structure to a reflow process to form a conductive member.

[0272] FIG15g is a schematic diagram of a chip module provided in an embodiment of the present application after a first solder structure and a second solder structure are provided on a transition solder joint.

[0273] As shown in Figure 15g, the first solder structure 130 is arranged on the transition solder joint 15b, wherein the first solder structure 130 can be tin paste, and the first solder structure 130 can also be fixed on the transition solder joint 15b by printing or other methods, so that the transition solder joint 15b and the first solder structure 130 form a conductive part 15 after reflow treatment (as shown in Figure 15i).

[0274] The notch structure 19a can increase the interface freedom of the transition solder joint 15b and the first solder structure 130, which is beneficial to the reflow molding of the conductive component 15, and is particularly beneficial to the molding of a spherical conductive component.

[0275] Of course, in some examples, step S1042 may be omitted, that is, there is no need to form the notch structure 19 a on the surface of the second package facing away from the substrate.

[0276] In some examples, the conductive member 15 formed after reflow may partially fill the gap structure 19a, such as the vertical projection of the conductive member 15 on the substrate 11 partially covers the vertical projection of the gap structure 19a on the substrate 11, so that a gap 19 may exist between the outer wall surface of the conductive member 15 and the second package 14 (see FIG. 15i ).

[0277] Alternatively, in some examples, the formed conductive member 15 may also completely fill the gap structure 19a, such as the vertical projection of the conductive member 15 on the substrate 11 completely covers the vertical projection of the gap structure 19a on the substrate 11, so that the outer wall surface of the conductive member 15 can extend to the second package 14.

[0278] It is understandable that controlling the amount of the first solder structure 130 can achieve control of the thickness of the conductive part 15 after reflow, and can make the end of the conductive part 15 facing away from the substrate 11 protrude from the side of the second package 14 facing away from the substrate 11.

[0279] In some examples, a portion of the first end of the first heat sink 17 can be exposed from the second package 14 through the groove 18 (see FIG. 15 f ), so that heat can be transferred to the outside of the chip module 10 through the first heat sink 17 .

[0280] Alternatively, in some examples, the chip module may further include a first connector, which may be fixed to the first heat sink 17, so that the first heat sink 17 can be connected to a circuit board or other structural parts through the first connector to transfer heat to the outside of the chip module through the first heat sink 17 and the first connector. The specific structure of the first connector can be found above and will not be repeated in this example.

[0281] To form the first connector, after forming a groove on the surface of the packaging layer facing away from the substrate to form the second packaging member, the preparation method may further include:

[0282] S107 : Disposing a second solder structure on the first end of the first heat dissipation element.

[0283] As shown in FIG15g , the second solder structure 140 is placed on the first end of the first heat sink 17. The second solder structure 140 can be located in the groove 18. For example, the groove 18 can be arranged around the second solder structure 140. The groove 18 can increase the degree of freedom of the interface of the second solder structure 140, which is beneficial for the reflow molding of the first connector.

[0284] 15h is a bottom view schematic diagram of a chip module provided in an embodiment of the present application after a first solder structure and a second solder structure are arranged on a first heat sink.

[0285] As shown in Figure 15h, the second solder structure 140 can be fixed on the end face of the first end of the first heat sink 17. For example, the second solder structure 140 can be solder paste, and the second solder structure 140 can be fixed on the end face of the first end of the first heat sink 17 by printing or other means.

[0286] S108: reflow the second solder structure to form a first connector.

[0287] For example, after the solder paste undergoes a reflow process, it can form solder balls as the first connecting members.

[0288] FIG15i is a schematic diagram of a second solder structure after reflow in a chip module according to an embodiment of the present application. Referring to FIG15i , a first connector 110 is formed on the first heat sink 17 so that the first heat sink 17 can be assembled and connected to an external circuit board via the first connector 110.

[0289] In some examples, the first connector 110 formed after reflow can partially fill the groove, such as the vertical projection of the first connector 110 on the substrate 11 partially covers the vertical projection of the groove on the substrate 11, as shown in Figure 15i, so that there is a gap 181 between the first connector 110 and the second package 14, and the first end portion of the first heat sink 17 can still be exposed from the side of the second package 14 facing away from the substrate 11.

[0290] Alternatively, in some examples, the formed first connector 110 can also fill the entire groove, such as the vertical projection of the first connector 110 on the substrate 11 completely covers the vertical projection of the groove on the substrate 11, so that the outer wall surface of the first connector 110 extends to the second package 14, and the first heat sink 17 will not be exposed from the side of the second package 14 facing away from the substrate 11.

[0291] Accordingly, by controlling the amount of the second solder structure 140, the thickness of the first connector 110 after reflow can be controlled, and the end of the first connector 110 facing away from the first heat sink 17 can be set to protrude from the side of the second package 14 facing away from the substrate 11.

[0292] It should be noted that, in order to simplify the molding process, the notch structure and the groove can be molded simultaneously, and the printing molding and reflow treatment of the first solder structure and the second solder structure can also be molded simultaneously.

[0293] For example, when a groove is opened on the packaging thin layer by laser grooving or the like, a notch structure can be opened on the packaging thin layer simultaneously in the same manner, so that the formed second package 14 has a groove 18 and a notch structure 19a on the side facing away from the substrate 11 (see FIG. 15f ).

[0294] For example, when the first solder structure 130 is provided on the transition solder joint by printing or the like, the second solder structure 140 can also be provided on the first heat sink 17 simultaneously in the same manner (see FIG. 15g ).

[0295] When the first solder structure 130 and the transition solder joint are reflowed, the second solder structure 140 can also be reflowed simultaneously to form the conductive member 15 and the first connecting member 110 (see FIG. 15i ).

[0296] In some examples, the first chip is disposed on a first surface of the substrate, and a surface of the first chip facing the substrate has a first electrical connection.

[0297] The above-mentioned step S102 of disposing some of the chips in the plurality of chips on the first surface may include: mounting a first chip on the first surface, and electrically connecting the first chip to the substrate via a first electrical connector.

[0298] For example, the first electrical connector can be soldered to the connecting traces on the substrate to achieve electrical connection. This allows the first chip to be mounted on the first surface of the substrate and achieve electrical connection between the first chip and the substrate. Heat from the first chip can be transferred to the substrate via the first electrical connector, with the end surface of the first electrical connector connected to the substrate forming a heat conduction area for the first chip.

[0299] For example, providing the substrate and the first heat sink in step S101 may include S1011: securing the second end of the first heat sink to the second surface. This method can yield a chip module 10 (see FIG. 7 ) with a layout in which the first chip 12a is located on the first surface 11a and the first heat sink 17 is located on the second surface 11b.

[0300] The second end of the first heat sink can be mounted on the second surface of the substrate by SMT. Alternatively, in some examples, the second end of the first heat sink can be fixed to the second surface by other means, for example, by bonding.

[0301] In some examples, the substrate may further include a second heat sink. The second heat sink may be formed on the substrate while the substrate is being molded. That is, the second heat sink may be integrally formed during the molding process of the substrate.

[0302] Alternatively, the second heat dissipation member and the base plate may be formed separately and then assembled together.

[0303] The above step S1011 of fixing the second end of the first heat sink on the second surface may include: making the vertical projection of the first heat sink on the substrate and the vertical projection of the second heat sink on the substrate at least partially overlap, thereby further improving the heat dissipation effect through the second heat sink.

[0304] For example, the second heat sink can be fixed inside the substrate, that is, the second heat sink is located between the first surface and the second surface, and the first heat sink is assembled on the second surface. The assembly method can be seen in step S1011. This method can obtain a chip module 10 with a layout in which the first chip 12a is located on the first surface 11a, the first heat sink 17 is located on the second surface 11b, and the second heat sink 112 is disposed inside the substrate 11 (see Figure 11).

[0305] Alternatively, in some examples, one end of the second heat sink is located inside the substrate, and the other end of the second heat sink can extend toward the second package in the thickness direction, such as the end surface of the other end of the second heat sink extends to the side of the substrate facing away from the first surface, and the end surface of the other end of the second heat sink can form part of the second surface.

[0306] The aforementioned step S1011 of securing the second end of the first heat sink to the second surface may include: forming a second connector on the other end of the second heat sink, securing the second end of the first heat sink to the other end of the second heat sink via the second connector, thereby securing the first heat sink to the second surface of the substrate. This method can yield a chip module 10 (see FIG12 ) having a layout in which the first chip 12a is located on the first surface 11a, the first heat sink 17 is located on the second surface 11b, and one end of the second heat sink 112 is located within the substrate 11 and the other end is secured to the first heat sink.

[0307] In some other examples, step S101 of providing a substrate and a first heat sink may include S1012: securing the second end of the first heat sink to the interior of the substrate. This method can yield a chip module 10 (see FIG13 ) having a layout in which the first chip 12a is located on the first surface 11a and the first heat sink 17 is partially secured to the interior of the substrate 11.

[0308] Illustratively, the first heat dissipation element may be formed on the substrate while the substrate is being formed, that is, during the process of forming the substrate, the substrate with the first heat dissipation element inserted therein is integrally formed.

[0309] Alternatively, the first heat sink may also be fixed to the substrate in other ways, for example, it may be inserted on the substrate by bonding, snapping, interference fit, etc.

[0310] In some other examples, the first chip may be disposed on the second surface of the substrate, and the first chip may have a second electrical connection on a side facing the substrate.

[0311] In the above step S103, disposing another part of the plurality of chips on the second surface may include:

[0312] S1031: Disposing a first chip on the second surface, and electrically connecting the first chip to the substrate through a second electrical connection.

[0313] For example, the second electrical connector can also be welded and fixed to the connecting traces of the substrate to achieve electrical connection, thereby assembling the first chip on the second surface of the substrate in the above manner and achieving electrical connection between the first chip and the substrate.

[0314] S1032: Fix the first heat sink on the surface of the first chip facing away from the substrate.

[0315] The heat generated by the first chip can be directly dissipated through the first heat sink, and a surface of the first chip facing away from the first heat sink forms a heat conduction area.

[0316] For example, the first heat sink can be a back-gold layer on the first chip, and the first heat sink can be fixed to the surface of the first chip facing away from the substrate by SMT mounting, bonding, printing, etc. The above method can be used to obtain a chip module 10 (see FIG. 14 ) in which the first chip 12 a is located on the second surface 11 b and the first heat sink 17 is located on the first chip 12 a.

[0317] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances. The terms "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0318] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them. Although the embodiments of the present application have been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip module, characterized in that, Comprising: A substrate having a first surface and a second surface facing away from each other in the thickness direction; A first encapsulation member disposed on the first surface; A second encapsulation member disposed on the second surface; A plurality of chips respectively disposed on the first surface and the second surface, and at least part of the chips are wrapped in the first encapsulation member or the second encapsulation member. The plurality of chips include a first chip having a heat conduction area for achieving heat conduction contact; A first heat dissipation member located between the first surface and the side of the second encapsulation member facing away from the substrate, and at least the first end of the first heat dissipation member is located within the second encapsulation member. The vertical projection of the first heat dissipation member on the substrate at least partially covers the vertical projection of the heat conduction area on the substrate; The end surface of the first end of the first heat dissipation member is recessed in the thickness direction with respect to the surface of the second encapsulation member facing away from the substrate, and there is a preset distance between the end surface of the first end and the surface of the second encapsulation member facing away from the substrate.

2. The chip module according to claim 1, wherein, The preset distance is 10 μm to 20 μm.

3. The chip module according to claim 1 or 2, characterized in that There are a plurality of the heat conduction areas, and the plurality of heat conduction areas at least include a first area, and the first area is the area with the largest cross-sectional area among the plurality of heat conduction areas; The vertical projection of the first heat dissipation member on the substrate at least partially covers the vertical projection of the first area on the substrate.

4. The chip module according to claim 3, wherein, The vertical projection of the first heat dissipation member on the substrate at least covers 50% of the vertical projection area of the first area on the substrate.

5. The chip module according to any one of claims 1-4, characterized in that, The vertical projection of the first heat dissipation member on the substrate at least covers 50% of the vertical projection area of the first chip on the substrate.

6. The chip module according to claim 5, wherein The vertical projection of the first heat dissipation member on the substrate completely covers the vertical projection of the first chip on the substrate.

7. The chip module according to any one of claims 1-6, characterized in that, Further comprising: A plurality of spaced conductive members fixed on the second surface, and the conductive members are correspondingly electrically connected to the chips through the substrate; Part of the conductive members are located inside the second encapsulation member, and the end of the conductive member facing away from the substrate is exposed on the surface of the second encapsulation member facing away from the substrate.

8. The chip module according to claim 7, wherein The cross-sectional area of the first heat dissipation member is larger than the cross-sectional area of one of the conductive members.

9. The chip module according to claim 8, wherein, The cross-sectional area of the first heat dissipation member is greater than π*(D / 2) 2 , where the range of the D is 200 μm to 300 μm.

10. The chip module according to any one of claims 1-9, characterized in that, The thermal conductivity of the first heat dissipation member is greater than 100 W / mK.

11. The chip module according to any one of claims 1-10, characterized in that, The thickness of the first heat dissipation member is greater than 30 μm.

12. The chip module according to any one of claims 1-11, characterized in that, There is a groove on the surface of the second encapsulation member facing away from the substrate, and the groove extends to the first end of the first heat dissipation member to expose part of the first end.

13. The chip module according to any one of claims 1-11, characterized in that, Further comprising: A first connecting member fixed on the first end of the first heat dissipation member; The end of the first connecting member facing away from the first heat dissipation member protrudes from the surface of the second encapsulation member facing away from the substrate.

14. The chip module according to claim 13, wherein There is a gap between the first connecting member and the second encapsulation member.

15. The chip module according to any one of claims 7-9, characterized in that, The end of the conductive member facing away from the substrate protrudes from the surface of the second encapsulation member facing away from the substrate.

16. The chip module according to claim 15, characterized in that, There is a gap between the conductive member and the second encapsulation member.

17. The chip module according to any one of claims 1-16, characterized in that, The first chip is disposed on the first surface, and a first electrical connector is provided on a surface of the first chip facing the substrate. The first chip is electrically connected to the substrate through the first electrical connector; An end face of an end of the first electrical connector connected to the substrate forms the heat conduction region.

18. The chip module according to claim 17, wherein, In the thickness direction, the first heat sink further includes a second end opposite to the first end, and the second end of the first heat sink is fixed on the second surface.

19. The chip module according to claim 18, wherein The substrate has a second heat sink, and at least a part of a vertical projection of the second heat sink and the first heat sink on the substrate overlaps.

20. The chip module according to claim 19, wherein The second heat sink is located inside the substrate.

21. The chip module according to claim 19, characterized in that, One end of the second heat sink is located inside the substrate, and the other end of the second heat sink extends towards the inside of the second package along the thickness direction. The second end of the first heat sink is fixed to the other end of the second heat sink.

22. The chip module according to claim 17, wherein, In the thickness direction, the first heat sink further includes a second end opposite to the first end, and the second end is fixed inside the substrate.

23. The chip module according to any one of claims 1-16, characterized in that, The first chip is disposed on the second surface, and a second electrical connector is provided on a surface of the first chip facing the substrate. The first chip is electrically connected to the substrate through the second electrical connector; The first heat sink is fixed on a surface of the first chip facing away from the substrate, and a surface of the first chip facing the first heat sink forms the heat conduction region.

24. A method for preparing a chip module, characterized in that, Comprising: Providing a substrate, a first heat sink and a plurality of chips, wherein the substrate includes a first surface and a second surface opposite to each other in the thickness direction, the plurality of chips includes a first chip, and the first chip has a heat conduction region for realizing heat conduction contact; Setting some of the plurality of chips on the first surface, and forming a first package on the first surface, and the chips located on the first surface are at least partially wrapped in the first package; Setting another part of the plurality of chips on the second surface, and at least the first end of the first heat sink is located on the second surface, and at least a part of a vertical projection of the first heat sink on the substrate covers a vertical projection of the heat conduction region of the first chip on the substrate; Forming a packaging layer on the second surface, and the packaging layer wraps the chips and the first heat sink located on the second surface; Performing a thinning process on the packaging layer to form a thin packaging layer, and the first end of the first heat sink is wrapped inside the thin packaging layer; Processing the thin packaging layer to form a second package, so that an end face of the first end of the first heat sink is recessed in the thickness direction with respect to a surface of the second package facing away from the substrate, the chips located on the second surface are at least partially wrapped in the second package, the first heat sink is located between the first surface and a surface of the second package facing away from the substrate, and in the thickness direction, a preset distance is provided between the end face of the first end of the first heat sink and the surface of the second package facing away from the substrate.

25. The preparation method according to claim 24, characterized in that, Before forming the encapsulation layer on the second surface, the method further includes: forming a plurality of spaced solder joints on the second surface, and the solder joints are correspondingly electrically connected to the chip through the substrate; Forming the encapsulation layer on the second surface further includes: wrapping the encapsulation layer around the solder joints; After forming the encapsulation layer on the second surface, the method further includes: thinning the solder joints to form conductive members, and one end of the conductive members facing away from the substrate is exposed on the surface of the second package facing away from the substrate.

26. The preparation method according to claim 25, wherein, Thinning the solder joints to form conductive members includes: Thinning the solder joints to form transitional solder joints; Forming a notch structure on the surface of the encapsulation thin layer facing away from the substrate, and the notch structure is arranged around the transitional solder joints; Providing a first solder structure on the transitional solder joints, and after subjecting the transitional solder joints and the first solder structure to a reflow process, forming the conductive members, and one end of the conductive members facing away from the substrate protrudes from the surface of the second package facing away from the substrate.

27. The preparation method according to any one of claims 24-26, characterized in that, Processing the encapsulation thin layer to form the second package includes: Opening a groove on the surface of the encapsulation thin layer facing away from the substrate to form the second package, and the groove extends to the first end of the first heat sink so that part of the first end is exposed.

28. The preparation method according to claim 27, characterized in that, After opening the groove on the surface of the encapsulation thin layer facing away from the substrate, the method further includes: Providing a second solder structure on the first end of the first heat sink; After subjecting the second solder structure to a reflow process, forming a first connecting member, and one end of the first connecting member facing away from the first heat sink protrudes from the surface of the second package facing away from the substrate.

29. The preparation method according to any one of claims 24-28, characterized in that, On the surface of the first chip facing the substrate, there is a first electrical connecting member; Arranging some of the plurality of chips on the first surface includes: arranging the first chip on the first surface, and electrically connecting the first chip to the substrate through the first electrical connecting member, and the end surface of the first electrical connecting member connected to the substrate forms the heat conduction area.

30. The preparation method according to claim 29, characterized in that, In the thickness direction, the first heat sink further includes a second end opposite to the first end; Providing the substrate and the first heat sink includes: fixing the second end of the first heat sink on the second surface.

31. The preparation method according to claim 30, wherein, The substrate has a second heat sink; Fixing the second end of the first heat sink on the second surface includes: making at least part of the vertical projection of the first heat sink on the substrate and the vertical projection of the second heat sink on the substrate coincide.

32. The preparation method according to claim 31, wherein, One end of the second heat sink is located inside the substrate, and the other end of the second heat sink extends towards the inside of the second package along the thickness direction; Fixing the second end of the first heat sink on the second surface includes: forming a second connecting member on the other end of the second heat sink, and fixing the second end of the first heat sink to the other end of the second heat sink through the second connecting member.

33. The preparation method according to claim 29, characterized in that, In the thickness direction, the first heat sink further includes a second end opposite to the first end; The provided substrate and the first heat sink include: fixing the second end of the first heat sink inside the substrate.

34. The preparation method according to any one of claims 24-28, characterized in that, On the surface of the first chip facing the substrate, there is a second electrical connector. The setting of another part of the plurality of chips on the second surface includes: Setting the first chip on the second surface and electrically connecting the first chip to the substrate through the second electrical connector. Fixing the first heat sink on the surface of the first chip facing away from the substrate, and the surface of the first chip facing the first heat sink forms the heat conduction area.

35. An electronic device, characterized in that, It includes a housing, a circuit board, and the chip module according to any one of claims 1-34 above. The chip module is disposed on the circuit board, and the chip module is electrically connected to the circuit board. Both the circuit board and the chip module are assembled inside the housing.

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