Amplifier having multiple output ends

Abstract

The present disclosure provides an amplifier having multiple output ends, comprising an amplification circuit and a radio frequency switching circuit, wherein the amplification circuit is configured as a low-noise amplification circuit of a cascode structure to receive a radio frequency input signal and provide the amplified radio frequency signal to the radio frequency switching circuit; the radio frequency switching circuit comprises a center tap inductor, and is configured to provide the amplified radio frequency signal to multiple output ends of the amplifier by means of a center tap of the center tap inductor.

Description

Amplifiers with multiple outputs CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to Chinese application No. 202410024282.2 filed with the State Intellectual Property Office of China on January 5, 2024. Technical Field

[0002] The present disclosure relates to the technical field of integrated circuits, and more particularly, to an amplifier with multiple output terminals. Background Art

[0003] In the RF receive chain, the low-noise amplifier (LNA) is at the forefront of the entire chain, and its performance directly affects the performance of the entire receiver. In mobile terminals, such as smartphones, the receive chain may have single-ended input and multiple-ended output applications, and multiple outputs may be enabled simultaneously (for example, in dual-on mode). In this case, there are also high requirements for the isolation between the output ports of the multiple outputs. Therefore, the traditional output switch solution for achieving multi-port output is no longer applicable in this case due to the extremely poor output port isolation. In addition, the impedance of the traditional solution is reduced to half of the original value in dual-on mode, resulting in poor output impedance matching and reduced gain. Therefore, there is a need for a low-noise amplifier with good output impedance matching and gain performance, while maintaining high isolation between multiple output ports. Summary of the Invention

[0004] An embodiment of the present disclosure provides an amplifier with multiple output terminals, including an amplifier circuit and a radio frequency switch switching circuit. The amplifier circuit is configured as a low-noise amplifier circuit with a common source and common gate structure to receive a radio frequency input signal and provide the amplified radio frequency signal to the radio frequency switch switching circuit; the radio frequency switch switching circuit includes an intermediate tap inductor and is configured to provide the amplified radio frequency signal to the multiple output terminals of the amplifier through the intermediate tap of the intermediate tap inductor.

[0005] According to an embodiment of the present disclosure, the multiple output terminals include a first output terminal and a second output terminal, the amplifying circuit includes a first amplifying transistor and a second amplifying transistor connected in series, and is configured to amplify the RF input signal input from the first input terminal of the amplifier and output the amplified RF signal to the RF switch switching circuit; and the RF switch switching circuit includes first to sixth gating transistors, and is configured to select one or more of the first to sixth gating transistors based on a gating signal input from a gating signal input terminal, so that the signal output from the amplifying circuit is output through at least one of the first output terminal and the second output terminal.

[0006] According to an embodiment of the present disclosure, the first input terminal of the amplifier is connected to the gate of the first amplifying transistor, the first electrode of the second amplifying transistor is connected to the RF switch switching circuit, and the second electrode of the first amplifying transistor is connected to the ground voltage; and wherein, the RF switch switching circuit also includes a matching resistor, wherein the middle tap of the middle tap inductor is connected to the first electrode of the second amplifying transistor, the first end and the second end of the middle tap inductor are respectively connected to the first output end and the second output end through the first selection transistor and the second selection transistor, the third selection transistor is connected between the middle tap and the first end of the middle tap inductor, the fourth selection transistor is connected between the middle tap and the second end of the middle tap inductor, and the fifth selection transistor, the matching resistor and the sixth selection transistor are connected in series between the first end and the second end of the middle tap inductor.

[0007] According to an embodiment of the present disclosure, the selection signal input terminal includes a first selection signal input terminal and a second selection signal input terminal, and the RF switch switching circuit also includes a first inverter, a second inverter, a first AND gate, a second AND gate and a third AND gate, wherein the first selection signal input terminal is connected to the gate of the first selection transistor, the second selection signal input terminal is connected to the gate of the second selection transistor, the first selection signal input terminal is also connected to the first input terminal of the first AND gate, the second selection signal input terminal is also connected to the second input terminal of the first AND gate through the first inverter, and the output terminal of the first AND gate is connected to the gate of the third selection transistor, the first selection signal input terminal is also connected to the first input terminal of the second AND gate through the second inverter, the second selection signal input terminal is also connected to the second input terminal of the second AND gate, and the output terminal of the second AND gate is connected to the gate of the fourth selection transistor, and the first selection signal input terminal is also connected to the first input terminal of the third AND gate, the second selection signal input terminal is also connected to the second input terminal of the third AND gate, and the output terminal of the third AND gate is connected to the gates of the fifth and sixth selection transistors.

[0008] According to an embodiment of the present disclosure, the amplifying circuit further includes a first capacitor and a second capacitor, wherein the first capacitor is arranged between the first input terminal and the gate of the first amplifying transistor; and the second capacitor is arranged between the first electrode of the second amplifying transistor and the middle tap of the middle tap inductor.

[0009] According to an embodiment of the present disclosure, the amplifying circuit further includes a first resistor and a first bias voltage input terminal, wherein the first bias voltage input terminal is connected to the gate of the first amplifying transistor through the first resistor.

[0010] According to an embodiment of the present disclosure, the amplifying circuit further includes a second bias voltage input terminal, wherein the second bias voltage input terminal is connected to the gate of the second amplifying transistor.

[0011] According to an embodiment of the present disclosure, the amplifying circuit further includes a first inductor and a second inductor, wherein the first inductor is arranged between the second electrode of the first amplifying transistor and the ground voltage; and the second inductor is arranged between the first electrode of the second amplifying transistor and the power supply voltage.

[0012] According to an embodiment of the present disclosure, each of the first to second amplifying transistors and the first to sixth gating transistors is an N-type transistor, the first pole is the drain of the N-type transistor, and the second pole is the source of the N-type transistor.

[0013] According to an embodiment of the present disclosure, a first electrode of the first amplifying transistor is connected to a second electrode of the second amplifying transistor.

[0014] According to an embodiment of the present disclosure, the matching resistor is configured to provide output impedance matching when the signal output from the amplifying circuit is output simultaneously through both of the first output terminal and the second output terminal.

[0015] According to an embodiment of the present disclosure, the matching resistor is an adjustable resistor with an adjustable resistance value.

[0016] This disclosure proposes a low-noise amplifier capable of multi-port output, with single-pass and dual-pass operating modes. In dual-pass mode, it achieves excellent output impedance matching and gain, while maintaining high isolation between multiple output ports. Furthermore, the disclosed solution utilizes tapped inductors, resistors, switches, and the like to achieve single-pass and / or dual-pass output modes, eliminating the need to switch inductors or inductor values ​​to meet matching requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0018] FIG1 shows a schematic diagram of a low noise amplifier 100 supporting multiple outputs according to an embodiment of the present disclosure;

[0019] FIG2 shows a schematic diagram of a radio frequency path of the low noise amplifier 100 when the first output terminal is turned on according to an embodiment of the present disclosure;

[0020] FIG3 shows an example result of a performance parameter simulation of the low noise amplifier 100 according to an embodiment of the present disclosure when the first output terminal is turned on;

[0021] FIG4 shows a schematic diagram of a radio frequency path of the low noise amplifier 100 when the second output terminal is turned on according to an embodiment of the present disclosure;

[0022] FIG5 shows an example result of a performance parameter simulation of the low noise amplifier 100 according to an embodiment of the present disclosure when the second output terminal is turned on;

[0023] FIG6 shows a schematic diagram of a radio frequency path of the low noise amplifier 100 according to an embodiment of the present disclosure when the first output terminal and the second output terminal are simultaneously turned on;

[0024] FIG7 shows an example result of a performance parameter simulation of the low noise amplifier 100 according to an embodiment of the present disclosure when the first output terminal and the second output terminal are simultaneously turned on;

[0025] FIG8 shows an example simulation result of the isolation between the first output terminal and the second output terminal of the low noise amplifier 100 in a dual-pass working mode according to an embodiment of the present disclosure;

[0026] FIG9 a shows a schematic structural diagram of a low noise amplifier 900 according to an embodiment of the present disclosure;

[0027] FIG9 b shows a schematic circuit diagram of a low noise amplifier 900 according to an embodiment of the present disclosure;

[0028] FIG10 shows a schematic diagram of a radio frequency path of a low noise amplifier 900 according to an embodiment of the present disclosure when the first output terminal is turned on;

[0029] FIG11 shows an example result of a performance parameter simulation of the low noise amplifier 900 according to an embodiment of the present disclosure when the first output terminal is turned on;

[0030] FIG12 shows a schematic diagram of a radio frequency path of the low noise amplifier 900 when the second output terminal is turned on according to an embodiment of the present disclosure;

[0031] FIG13 shows an example result of a performance parameter simulation of the low noise amplifier 900 according to an embodiment of the present disclosure when the second output terminal is turned on;

[0032] FIG14 shows a schematic diagram of a radio frequency path of the low noise amplifier 900 according to an embodiment of the present disclosure when the first output terminal and the second output terminal are simultaneously turned on;

[0033] FIG15 shows an example result of a performance parameter simulation of the low noise amplifier 900 according to an embodiment of the present disclosure when the first output terminal and the second output terminal are simultaneously turned on; and

[0034] FIG. 16 shows an example simulation result of the isolation between the first output terminal and the second output terminal of the low noise amplifier 900 in a dual-pass working mode according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Before proceeding with the detailed description below, it may be helpful to set forth the definitions of certain words and phrases used throughout this patent document. The terms "couple," "connect," and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are in physical contact with each other. The terms "transmit," "receive," and "communicate," and their derivatives, encompass both direct and indirect communication. The terms "include," "comprise," and their derivatives, mean including, but not limited to. The term "or" is inclusive, meaning and / or. The phrases "associated with," "corresponding to," and their derivatives, mean including, included within, interconnected, containing, contained within, connected or connected with, coupled or coupled with, communicate with, cooperate with, intertwine, juxtapose, approach, bind or bind with, have, have an attribute of, have a relationship with, or have a relationship with, etc. The term "controller" refers to any device, system, or portion thereof that controls at least one operation. Such a controller may be implemented using hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, whether local or remote. The phrase "at least one of," when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one of the items in the list may be needed. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A, B, and C.

[0036] Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0037] In this patent document, the application combination of modules and the division level of submodules are only for illustration. Without departing from the scope of the present disclosure, the application combination of modules and the division level of submodules can have different ways. The embodiments of the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make this disclosure thorough and complete and to fully convey exemplary implementation methods to those skilled in the art. The embodiments of the present disclosure can be combined to form additional embodiments.

[0038] The present disclosure will be described in detail below with reference to exemplary embodiments of the present disclosure. However, the present disclosure is not limited to the embodiments described herein and may be implemented in many different forms. The described embodiments are intended only to make the present disclosure thorough and complete and to fully convey the concepts of the present disclosure to those skilled in the art. The features of the various described embodiments may be combined or replaced with each other unless expressly excluded or should be excluded based on the context.

[0039] In this disclosure, the singular form of an element may refer to its plural form, and the plural form of an element may also refer to its singular form. For example, "element" or "an element" may refer to "at least one element", "one or more elements" or "a plurality of elements".

[0040] In the present disclosure, a radio frequency path may refer to a circuit path in which a radio frequency signal is input from one or more input terminals of an LNA, undergoes amplification and other processing by the LNA, and is then output through one or more output terminals of the LNA.

[0041] In the present disclosure, the ground voltage may also be any other low voltage or logic low voltage suitable for normal operation of circuits and devices, and the power supply voltage may also be any other high voltage or logic high voltage suitable for normal operation of circuits and devices.

[0042] In the present disclosure, in the case of an NMOS transistor (or N-type transistor), the first electrode may be the drain of the transistor, and the second electrode may be the source of the transistor. In the case of a PMOS transistor (or P-type transistor), the first electrode may be the source of the transistor, and the second electrode may be the drain of the transistor. In the drawings of the present disclosure, an N-type transistor is used as an example for illustrative description. However, it should be understood that in other embodiments of the present disclosure, depending on the specific implementation, one or more of the amplifying transistor and the gating transistor may also be a P-type transistor, and the present disclosure is not limited thereto.

[0043] In this disclosure, only a low-noise amplifier (LNA) is used as an example for illustrative description. It should be understood that the technical solutions of the amplifiers according to the embodiments of the present disclosure can also be applied to any other type of amplifier circuit that supports or has multiple output terminals. In addition, for ease of description, only two output terminals are used as an example in the embodiments of the present disclosure. It should be understood that the amplifiers supporting multiple output terminals of the present disclosure can also include any other number of multiple output terminals.

[0044] In the present disclosure, a mode in which two output terminals are simultaneously selected or turned on may be referred to as a dual-on mode or a dual-pass (working) mode, and a mode in which only one of the two output terminals is selected or turned on may be referred to as a single-on mode or a single-pass (working) mode.

[0045] In this disclosure, a gate transistor may also be referred to as a switching transistor or a switch, etc.

[0046] FIG1 shows a schematic diagram of a low noise amplifier 100 supporting multiple outputs according to an embodiment of the present disclosure.

[0047] As shown in FIG1 , the low noise amplifier 100 can add two switches (e.g., switching transistors S1 and S2) to the output end of a general low noise amplifier (e.g., a cascode LNA) to select the RF output end (e.g., rfout1 and rfout2), thereby selecting the signal amplified by the amplifier circuit from at least one of rfout1 and rfout2. For example, the selection can be made by connecting the gates of the switching transistors S1 and S2 to the gates to perform the selection. In the circuit structure shown in FIG1 , M1 is sometimes referred to as an amplifier transistor, and M2 is sometimes referred to as a cascode transistor. In the present disclosure, for ease of description, the amplifier transistors and cascode transistors in the low noise amplifier are collectively referred to as amplifier transistors, unless otherwise specifically distinguished.

[0048] For the scheme of the low-noise amplifier 100, when Vs_out1 is high and Vs_out2 is low, the switching transistor S1 is turned on and the switching transistor S2 is turned off, so that the RF path is from rfin1 to rfout1 (as shown in Figure 2). Accordingly, Figure 3 shows an example result of the simulation of the performance parameters (e.g., scattering parameters (S parameters)) of the low-noise amplifier 100 in this state. As can be seen from Figure 3, in this state, the gain (e.g., S21 parameter) of the low-noise amplifier 100 corresponding to the first output terminal rfout1 is approximately 20.3801dB, and the output matching (e.g., S22 parameter) is approximately -24.9927dB. In the figures related to the simulation results of the present disclosure, it is assumed that the left part of the figure is the simulation result corresponding to the first output terminal rfout1, and the right part is the simulation result corresponding to the second output terminal rfout2.

[0049] When Vs_out1 is low and Vs_out2 is high, switching transistor S1 is off and switching transistor S2 is on, thereby establishing a RF path from rfin1 to rfout2 (as shown in FIG4 ). Accordingly, FIG5 illustrates example simulation results of performance parameters (e.g., S parameters) of the low-noise amplifier 100 in this state. As can be seen from FIG5 , in this state, the gain (e.g., S31 parameter) of the low-noise amplifier 100 corresponding to the second output terminal rfout2 is approximately 20.3801 dB, and the output match (e.g., S33 parameter) is approximately -24.9922 dB.

[0050] When Vs_out1 is high and Vs_out2 is high, both switching transistors S1 and S2 are turned on, so that the RF path is rfin1 and connects to both rfout1 and rfout2, that is, the dual-on mode (as shown in Figure 6). Accordingly, Figure 7 shows an example simulation result of the performance parameters (e.g., S parameters) of the low-noise amplifier 100 in this state. As can be seen from Figure 7, in this state, the gain (e.g., S21 parameter) corresponding to the first output terminal rfout1 of the low-noise amplifier 100 is approximately 16.2752dB, and the output matching (e.g., S22 parameter) is approximately -7.39916dB; the gain (e.g., S31 parameter) corresponding to the second output terminal rfout2 of the low-noise amplifier 100 is approximately 16.3797dB, and the output matching (e.g., S33 parameter) is approximately -7.68878dB.

[0051] In dual-pass mode, the load is doubled compared to single-channel output (for example, 50 ohm in single-channel mode becomes 25 ohm in dual-channel mode). Therefore, the output matching (for example, S22 and S33 shown in Figure 7) is very poor, which also leads to a deterioration of gain.

[0052] In addition, the isolation between the two output ports is also a very important performance indicator. For example, FIG8 shows an example simulation result of the isolation between the first output terminal rfout1 and the second output terminal rfout2 of the low-noise amplifier 100 according to an embodiment of the present disclosure in dual-pass operating mode. As shown in FIG8 , the isolation between the first output terminal rfout1 and the second output terminal rfout2 (e.g., parameter S32) is only about 4 dB (expressed in absolute value) in this case. However, in common application scenarios, the isolation should be at least 15 dB.

[0053] In order to solve the problem of poor isolation and poor matching and gain performance in the dual-pass working mode of the above-mentioned solution, the present disclosure further proposes a solution for converting single-ended to differential using a tapped inductor (e.g., an intermediate tapped inductor) to achieve multi-output, such as a low-noise amplifier 900. The structural schematic and circuit diagram of this solution are shown in Figures 9a and 9b. The output of the amplifier circuit 910 in the low-noise amplifier 900 can be connected to the intermediate tap of the tapped inductor D1 included in the RF switch switching circuit 920, and the other two ports of the inductor D1 are connected to rfout1 and rfout2 respectively through switching transistors. In addition, a matching resistor R2 is further added to the RF switch switching circuit 920 to adjust the output impedance matching, thereby achieving good output impedance matching and high RF gain, and there is also high isolation between rfout1 and rfout2.

[0054] This document uses a mid-tapped inductor to illustrate the circuit structure according to an embodiment of the present disclosure. It should be understood that in scenarios with multiple output terminals or multiple output channels, an inductor with multiple taps can also be used to achieve corresponding multi-channel outputs, and this disclosure does not limit this.

[0055] Specifically, FIG9a shows a schematic structural diagram of a low noise amplifier 900 according to an embodiment of the present disclosure, and FIG9b shows a schematic circuit diagram of a low noise amplifier 900 according to an embodiment of the present disclosure.

[0056] As shown in Figure 9a, a low-noise amplifier (LNA) 900 according to an embodiment of the present disclosure can have multiple output terminals. This disclosure uses two output terminals as an example for illustrative description. For example, the multiple output terminals can include a first output terminal rfout1 and a second output terminal rfout2. Furthermore, LNA 900 can also include one or more input terminals. This description uses a single input terminal as an example, such as the first input terminal rfin1. In embodiments with multiple input terminals and / or multiple output terminals, the amplifier circuit shown in Figure 9b can be expanded by replicating corresponding portions. Furthermore, as described above, LNA 900 can also include an amplifier circuit 910 and an RF switching circuit 920.

[0057] Amplifier circuit 910 may be the core circuit of LNA 900 for implementing signal amplification. For example, as shown in FIG9b , amplifier circuit 910 may include a first amplifier transistor M1 and a second amplifier transistor M2 connected in series, and may be configured to amplify a signal (e.g., an RF input signal) input from a first input terminal rfin1 of LAN 900 and output the amplified RF signal to RF switching circuit 920. Furthermore, amplifier circuit 910 may also include an input DC blocking capacitor C1, an output capacitor C2, inductors L1 and L2, a bias resistor R1, and the like. It should be understood that the circuit shown in FIG9b is merely an example, and depending on the specific configuration of the circuit, one or more of the input DC blocking capacitor C1 (hereinafter referred to as the first capacitor), the output capacitor C2 (hereinafter referred to as the second capacitor), the inductors L1 and L2, the bias resistor R1, and the like may be omitted from amplifier circuit 910, or amplifier circuit 910 may include any other number of these components.

[0058] The RF switch switching circuit 920 may include first to sixth selection transistors S1-S6, and may be a circuit configured to select one or more of the first to sixth selection transistors S1-S6 based on a selection signal input from a selection signal input terminal (for example, a first selection signal input terminal Vs_out1 and a second selection signal input terminal Vs_out2, etc.) so that the amplified signal output from the amplifying circuit 910 is output through at least one of the first output terminal rfout1 and the second output terminal rfout2.

[0059] In some embodiments, the first input terminal rfin1 of the LNA 900 is connected to the gate of the first amplifying transistor M1, the first electrode of the second amplifying transistor M2 is connected to the input terminal of the RF switching circuit 920 (e.g., the center tap of the center-tap inductor D1 included therein), and the second electrode of the first amplifying transistor M1 is connected to a ground voltage (e.g., GND).

[0060] In some embodiments, as described above, the RF switching circuit 900 further includes a center-tap inductor D1 and may further include a matching resistor R2.

[0061] In some embodiments, the center tap of the center-tapped inductor D1 is connected to the first electrode of the second amplifying transistor M2. The first and second ends of the center-tapped inductor D1 are connected to the first output terminal rfout1 and the second output terminal rfout2, respectively, via the first and second pass transistors S1 and S2. A third pass transistor S3 is connected between the center tap and the first end of the center-tapped inductor D1, and a fourth pass transistor S4 is connected between the center tap and the second end of the center-tapped inductor D1. A fifth pass transistor S5, a matching resistor R2, and a sixth pass transistor S6 can be connected in series between the first and second ends of the center-tapped inductor D1, that is, between the second electrodes of the first and second pass transistors S1 and S2. The configuration of the center-tapped inductor D1 enables the LNA 900 to achieve high isolation between the first and second output terminals rfout1 and rfout2 in dual-pass mode.

[0062] In some embodiments, the strobe signal input terminal may include a first strobe signal input terminal Vs_out1 and a second strobe signal input terminal Vs_out2. In addition, the RF switch switching circuit 900 may further include a first inverter INV1, a second inverter INV2, a first AND gate AND2_1, a second AND gate AND2_2, and a third AND gate AND2_3.

[0063] In some embodiments, the first selection signal input terminal Vs_out1 is connected to the gate of the first selection transistor S1, and the second selection signal input terminal Vs_out2 is connected to the gate of the second selection transistor S2. The first selection signal input terminal Vs_out1 is also connected to the first input terminal of the first AND gate AND2_1, and the second selection signal input terminal Vs_out2 is also connected to the second input terminal of the first AND gate AND2_1 through the first inverter INV1. The output terminal of the first AND gate AND2_1 is connected to the gate of the third selection transistor S3.

[0064] In some embodiments, the first selection signal input terminal Vs_out1 is further connected to the first input terminal of the second AND gate AND2_2 through the second inverter INV2, the second selection signal input terminal Vs_out2 is further connected to the second input terminal of the second AND gate AND2_2, and the output terminal of the second AND gate AND2_2 is connected to the gate of the fourth selection transistor S4.

[0065] In some embodiments, the first selection signal input terminal Vs_out1 is further connected to the first input terminal of the third AND gate AND2_3, the second selection signal input terminal Vs_out2 is further connected to the second input terminal of the third AND gate AND2_3, and the output terminal of the third AND gate AND2_3 is connected to the gates of the fifth selection transistor S5 and the sixth selection transistor S6.

[0066] The truth table of the logic control circuit composed of the first inverter INV1, the second inverter INV2, the first AND gate AND2_1, the second AND gate AND2_2 and the third AND gate AND2_3 as configured above is shown in Table 1 below.

[0067] [Table 1]

[0068] Thus, the gate voltages of the first to sixth pass transistors can be controlled by the two gating signals input from Vs_out1 and Vs_out2 via the logic control circuit as described above, thereby controlling the on or off state (or gating) of one or more of the first to sixth pass transistors. It should be understood that the logic control circuit can also be configured in any other suitable configuration, which is not limited herein.

[0069] In some embodiments, the amplifier circuit 910 may further include a first capacitor C1 and a second capacitor C2. The first capacitor C1 may be disposed between the first input terminal rfin1 and the gate of the first amplifier transistor M1; and the second capacitor C2 may be disposed between the first electrode (e.g., the drain) of the second amplifier transistor M2 and the center tap of the center tap inductor D1.

[0070] In some embodiments, the amplifier circuit 910 may further include a first resistor R1 and a first bias voltage input terminal vb1. The first bias voltage input terminal vb1 may be connected to the gate of the first amplifier transistor M1 via the first resistor R1, thereby providing the first amplifier transistor M1 with a suitable bias voltage required for normal operation of the transistor or circuit.

[0071] In some embodiments, the amplifier circuit 910 may further include a second bias voltage input terminal vb2 that may be connected to the gate of the second amplifier transistor M2 to provide the second amplifier transistor M2 with a suitable bias voltage required for normal operation of the transistor or circuit.

[0072] In some embodiments, the amplifier circuit 910 may further include a first inductor L1 and a second inductor L2. The first inductor L1 may be disposed between the second electrode of the first amplifier transistor M1 and a ground voltage; and the second inductor L2 may be disposed between the first electrode of the second amplifier transistor M2 and a power supply voltage (e.g., VDD).

[0073] In some embodiments, each of the first to second amplifying transistors and the first to sixth gating transistors may be an N-type transistor, and the first electrode may be a drain of the N-type transistor, and the second electrode may be a source of the N-type transistor.

[0074] In some embodiments, a first electrode of the first amplifying transistor M1 is connected to a second electrode of the second amplifying transistor M2 .

[0075] In some embodiments, matching resistor R2 is configured to provide output impedance matching when the signal output from amplifier circuit 910 is simultaneously output through both the first output terminal rfout1 and the second output terminal rfout2. For example, as shown in Table 1 above, when both Vs_out1 and Vs_out2 are high, S5 and S6 are turned on, allowing matching resistor R2 to operate normally. Matching resistor R2 can have a predetermined resistance value that provides appropriate output impedance matching. For example, matching resistor R2 can have a resistance value calculated based on the load of LNA 900. In other examples, matching resistor R2 can also be an adjustable resistor with an adjustable resistance value. In this case, the resistance value of matching resistor R2 can be adjusted based on the different loads of LNA 900, thereby providing appropriate output impedance matching under different load conditions.

[0076] In the example shown in Figure 9b , when Vs_out1 is high and Vs_out2 is low, S1 and S3 are on, S2, S4, S5, and S6 are off, and the RF path is from rfin1 to rfout1 (as shown in Figure 10 ). Accordingly, Figure 11 shows example simulation results of performance parameters (e.g., scattering parameters (S parameters)) of the LNA 900 in this state. As can be seen from Figure 11 , in this state, the gain (e.g., S21 parameter) of the LNA 900 corresponding to the first output terminal rfout1 is approximately 20.5117 dB, and the output match (e.g., S22 parameter) is approximately -21.3597 dB.

[0077] When Vs_out1 is low and Vs_out2 is high, S2 and S4 are on, S1, S3, S5, and S6 are off, and the RF path is from rfin to rfout2 (as shown in Figure 12). Accordingly, Figure 13 shows example simulation results of performance parameters (e.g., scattering parameters (S parameters)) of the LNA 900 in this state. As can be seen from Figure 13, in this state, the gain (e.g., S31 parameter) of the LNA 900 corresponding to the second output terminal rfout2 is approximately 20.5111 dB, and the output match (e.g., S33 parameter) is approximately -21.3841 dB.

[0078] When Vs_out1 and Vs_out2 are both high, gate transistors S1, S2, S5, and S6 are turned on, while S2 and S4 are turned off. The RF path, rfin, connects to both rfout1 and rfout2 (as shown in Figure 14), indicating dual-pass mode operation. Accordingly, Figure 15 shows example simulation results of performance parameters (e.g., scattering parameters (S parameters)) of the LNA 900 in this state. As shown in Figure 15, the gain (e.g., S21 parameter) corresponding to the first output terminal rfout1 of the LNA 900 is approximately 17.1829 dB, and the output match (e.g., S22 parameter) is approximately -10.5496 dB. The gain (e.g., S31 parameter) corresponding to the second output terminal rfout2 of the LNA 900 is approximately 16.9565 dB, and the output match (e.g., S33 parameter) is approximately -10.0399 dB.

[0079] FIG16 also shows exemplary simulation results of the isolation between the first output terminal rfout1 and the second output terminal rfout2 of LNA 900 in dual-pass mode according to an embodiment of the present disclosure. As shown in FIG16 , the isolation between the first output terminal rfout1 and the second output terminal rfout2 (e.g., parameter S32 or S23) is approximately 20.5136 dB (expressed in absolute value).

[0080] Next, Table 2 shows a performance comparison of the LNA 100 and the LNA 900 according to the embodiment of the present disclosure obtained through simulation and experiments.

[0081] [Table 2]

[0082] As can be seen from Table 2 above, the LNA 900 according to the embodiment of the present disclosure has comparable performance to the LNA 100 in single-pass mode, and has better matching and gain, as well as higher isolation in dual-pass mode.

[0083] It should be understood that the low-noise amplifier 100 or the low-noise amplifier 900 described above is merely illustrative, and that the amplifier according to an embodiment of the present disclosure may further include one or more other devices in addition to those included in the low-noise amplifier 100 or the low-noise amplifier 900, or may omit or replace any one or more of these devices, without limitation herein. Furthermore, embodiments of the present disclosure may further include any implementation method or operating method of the low-noise amplifier 100 or the low-noise amplifier 900 described above, as well as any circuit system including the low-noise amplifier 100 or the low-noise amplifier 900.

[0084] The hardware computing device described in this disclosure, as a whole or parts thereof, may be implemented through various suitable hardware means, including but not limited to FPGA, ASIC, SoC, discrete gate or transistor logic, discrete hardware components, or any combination thereof.

[0085] The block diagrams of circuits, devices, apparatuses, equipment, and systems described in this disclosure are intended only as illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these circuits, devices, apparatuses, equipment, and systems may be connected, arranged, or configured in any manner as long as the desired purpose is achieved.

[0086] Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.

[0087] Nothing in this disclosure should be construed as implying that any particular element, step, or function is an essential element that must be included in the claims scope. The scope of the patented subject matter is defined solely by the claims.

[0088] Exemplary embodiments of the present disclosure have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise indicated. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made to the present disclosure without departing from the spirit and scope of the claims.

Claims

1. An amplifier with multiple output terminals, comprising an amplification circuit and a radio frequency switch switching circuit, characterized in that, The amplification circuit is configured as a cascode low-noise amplification circuit to receive a radio frequency input signal and provide the amplified radio frequency signal to the radio frequency switch switching circuit; The radio frequency switch switching circuit includes a center-tapped inductor and is configured to provide the amplified radio frequency signal to multiple output terminals of the amplifier through the center tap of the center-tapped inductor.

2. The amplifier according to claim 1, characterized in that, The multiple output terminals include a first output terminal and a second output terminal, The amplification circuit includes a first amplification transistor and a second amplification transistor connected in series and is configured to amplify a radio frequency input signal input from a first input terminal of the amplifier and output the amplified radio frequency signal to the radio frequency switch switching circuit; And The radio frequency switch switching circuit includes a first gating transistor to a sixth gating transistor and is configured to gate one or more of the first gating transistor to the sixth gating transistor based on a gating signal input from a gating signal input terminal, so that the signal output from the amplification circuit is output through at least one of the first output terminal and the second output terminal.

3. The amplifier according to claim 2, characterized in that, The first input terminal of the amplifier is connected to the gate of the first amplification transistor, The first pole of the second amplification transistor is connected to the radio frequency switch switching circuit, The second pole of the first amplification transistor is connected to the ground voltage; and Wherein, the radio frequency switch switching circuit further includes a matching resistor, wherein, The center tap of the center-tapped inductor is connected to the first pole of the second amplification transistor, The first end and the second end of the center-tapped inductor are respectively connected to the first output terminal and the second output terminal through the first gating transistor and the second gating transistor, The third gating transistor is connected between the center tap and the first end of the center-tapped inductor, and the fourth gating transistor is connected between the center tap and the second end of the center-tapped inductor, The fifth gating transistor, the matching resistor and the sixth gating transistor are sequentially connected in series between the first end and the second end of the center-tapped inductor.

4. The amplifier according to claim 3, characterized in that, The gating signal input terminal includes a first gating signal input terminal and a second gating signal input terminal, and the radio frequency switch switching circuit further includes a first inverter, a second inverter, a first AND gate, a second AND gate and a third AND gate, wherein, The first gating signal input terminal is connected to the gate of the first gating transistor, The second gating signal input terminal is connected to the gate of the second gating transistor, The first gating signal input terminal is further connected to the first input terminal of the first AND gate, the second gating signal input terminal is further connected to the second input terminal of the first AND gate through the first inverter, and the output terminal of the first AND gate is connected to the gate of the third gating transistor, The first strobe signal input terminal is also connected to the first input terminal of the second AND gate through the second inverter, the second strobe signal input terminal is also connected to the second input terminal of the second AND gate, and the output terminal of the second AND gate is connected to the gate of the fourth strobe transistor, and the first strobe signal input terminal is also connected to the first input terminal of the third AND gate, the second strobe signal input terminal is also connected to the second input terminal of the third AND gate, and the output terminal of the third AND gate is connected to the gates of the fifth and sixth strobe transistors.

5. The amplifier according to claim 3, characterized in that, The amplifier circuit further includes a first capacitor and a second capacitor, wherein, the first capacitor is disposed between the first input terminal and the gate of the first amplifying transistor; and the second capacitor is disposed between the first pole of the second amplifying transistor and the center tap of the center-tapped inductor.

6. The amplifier according to claim 3, characterized in that, The amplifier circuit further includes a first resistor and a first bias voltage input terminal, wherein, the first bias voltage input terminal is connected to the gate of the first amplifying transistor through the first resistor.

7. The amplifier according to claim 3, characterized in that, The amplifier circuit further includes a second bias voltage input terminal, wherein, the second bias voltage input terminal is connected to the gate of the second amplifying transistor.

8. The amplifier according to claim 3, characterized in that, The amplifier circuit further includes a first inductor and a second inductor, wherein, the first inductor is disposed between the second pole of the first amplifying transistor and the ground voltage; and the second inductor is disposed between the first pole of the second amplifying transistor and the power supply voltage.

9. The amplifier according to claim 3, characterized in that, Each of the first amplifying transistor to the second amplifying transistor and the first strobe transistor to the sixth strobe transistor is an N-type transistor, the first pole is the drain of the N-type transistor, and the second pole is the source of the N-type transistor.

10. The amplifier according to claim 3, characterized in that, The first pole of the first amplifying transistor is connected to the second pole of the second amplifying transistor.

11. The amplifier according to claim 3, characterized in that, The matching resistor is configured to provide output impedance matching when the signal output from the amplifier circuit is output simultaneously through two of the first output terminal and the second output terminal.

12. The amplifier according to claim 11, characterized in that, The matching resistor is an adjustable resistor with adjustable resistance value.

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