Gate driving apparatus and driving method therefor, and display substrate and display apparatus

Abstract

A gate driving apparatus and a driving method therefor, and a display substrate and a display apparatus. The gate driving apparatus comprises a shift control circuit, an m-stage intermediate gate driving circuit (G100), a (2S+1)-stage first-type offset gate driving circuit (G101) and a (2S+1)-stage second-type offset gate driving circuit (G102), wherein the shift control circuit outputs an initial row control signal to the 4S+2 stages of offset gate driving circuits, and under the control of the initial row control signal, one stage is selected from the (2S+1)-stage first-type offset gate driving circuit (G101) as a first-type initial gate driving circuit, and one stage is selected from the (2S+1)-stage second-type offset gate driving circuit (G102) as a second-type initial gate driving circuit; and in the cascading direction of multi-stage gate driving circuits, the first-type initial gate driving circuit and the second-type initial gate driving circuit have the same offset direction relative to the m-stage intermediate gate driving circuit, and the number of offset stages of the first-type initial gate driving circuit and the number of offset stages of the second-type initial gate driving circuit relative to the m-stage intermediate gate driving circuit are both N stages.

Description

Gate driving device and driving method thereof, display substrate, and display device

[0001] This application claims priority to PCT international applications No. PCT / CN2024 / 071143, No. PCT / CN2024 / 071152, and No. PCT / CN2024 / 071147, filed on January 8, 2024, priority to PCT international application No. PCT / CN2024 / 075364, filed on February 1, 2024, and priority to Chinese patent applications No. 202410129327.2, No. 202410130614.5, and No. 202410130058.1, filed on January 30, 2024. The contents of the above-mentioned PCT international applications and Chinese patent applications should be understood as being incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and specifically to a gate driving device and a driving method thereof, a display substrate, and a display device. Background Art

[0003] Micro-OLEDs (Micro Organic Light-Emitting Diodes) are a type of microdisplay that has been developed in recent years, with silicon-based OLEDs being one of them. Silicon-based OLEDs are a novel display technology that combines semiconductor manufacturing processes with OLED display technology, using wafers as substrates for manufacturing OLED devices. By combining the advantages of both semiconductor manufacturing processes and OLED display technology, silicon-based OLEDs not only offer a high pixel density (PPI), but also high brightness, low power consumption, fast response time, a wide color gamut, and excellent thermal stability.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] In a first aspect, an embodiment of the present disclosure provides a gate drive device, comprising a shift control circuit and a multi-stage cascaded gate drive circuit, wherein the multi-stage gate drive circuit comprises a 4S+2-stage offset gate drive circuit and an m-stage intermediate gate drive circuit. In the direction of the cascade of the multi-stage gate drive circuit, the 4S+2-stage offset gate drive circuit comprises a 2S+1-stage first-type offset gate drive circuit located on one side of the m-stage intermediate gate drive circuit, and a 2S+1-stage second-type offset gate drive circuit located on the other side of the m-stage intermediate gate drive circuit, where m and S are both positive integers.

[0007] The shift control circuit is electrically connected to the 4S+2-level offset gate drive circuit and is configured to output an initial row control signal to the 4S+2-level offset gate drive circuit. Under the control of the initial row control signal, one level is selected from the 2S+1-level first-level offset gate drive circuit as the first-level initial gate drive circuit, and one level is selected from the 2S+1-level second-level offset gate drive circuit as the second-level initial gate drive circuit; in the direction of the cascade of the multi-level gate drive circuits, the offset direction of the first-level initial gate drive circuit and the second-level initial gate drive circuit relative to the m-level intermediate gate drive circuit are consistent, and the number of offset levels relative to the m-level intermediate gate drive circuits is N, where N is an integer less than or equal to S.

[0008] In an exemplary embodiment, the offset gate driver circuit includes a row control circuit, an offset shift register circuit, an initial signal terminal, and a row control terminal; in the row control circuit, an input terminal is connected to the initial signal terminal, a control terminal is connected to the row control terminal, and an output terminal is connected to the input terminal of the offset shift register circuit;

[0009] The row control circuit is configured to receive a forward and reverse scan control signal from the row control end, and to receive an initial signal from the initial signal end. Under the control of the forward and reverse scan control signal, one of the first type of initial gate drive circuit and the second type of initial gate drive circuit is used as the starting row of the gate drive circuit, and the other is used as the cutting-off row of the gate drive circuit, and the initial signal is provided to the starting row of the gate drive circuit.

[0010] In an exemplary embodiment, the row control circuit includes a forward and reverse scan control circuit, the forward and reverse scan control circuit includes a third control terminal and a fourth control terminal, the row control terminal includes a first transmission control terminal and a second transmission control terminal, and in a first type of offset gate drive circuit, the third control terminal in the forward and reverse scan control circuit is electrically connected to the second transmission control terminal, and the fourth control terminal is electrically connected to the first transmission control terminal; in a second type of offset gate drive circuit, the third control terminal in the forward and reverse scan control circuit is electrically connected to the first transmission control terminal, and the fourth control terminal is electrically connected to the second transmission control terminal;

[0011] The input end of the forward and reverse scan control circuit is electrically connected to the initial signal end, and the output end is electrically connected to the input end of the corresponding offset shift register circuit.

[0012] In an exemplary embodiment, the row control circuit includes an initial row control circuit, the initial row control circuit includes a first control terminal and a second control terminal, the row control terminals include 2S+1 first-type initial row control terminals and 2S+1 second-type initial row control terminals; the first control terminals of the 2S+1-level first-type offset gate drive circuits are respectively electrically connected to the 2S+1 first-type initial row control terminals, and the second control terminals of the 2S+1-level first-type offset gate drive circuits are respectively electrically connected to the 2S+1 second-type initial row control terminals; the first control terminals of the 2S+1-level second-type offset gate drive circuits are respectively electrically connected to the 2S+1 first-type initial row control terminals, and the second control terminals of the 2S+1-level second-type offset gate drive circuits are respectively electrically connected to the 2S+1 second-type initial row control terminals;

[0013] The input end of the initial row control circuit is connected to the initial signal end, and the output end is electrically connected to the input end of the corresponding forward and reverse scan control circuit; the input end of the forward and reverse scan control circuit is electrically connected to the initial signal end through the corresponding initial row control circuit.

[0014] In an exemplary embodiment, the shift control circuit includes a logic decoding circuit, which includes 2S+1 decoding result output terminals and inverting output terminals of the 2S+1 decoding result output terminals, the 2S+1 decoding result output terminals respectively serve as the 2S+1 first-type initial row control terminals, and the inverting output terminals of the 2S+1 decoding result output terminals respectively serve as the 2S+1 second-type initial row control terminals.

[0015] In an exemplary embodiment, the logic decoding circuit is a standard decoder, and the number of decoding result output terminals of the standard decoder is greater than or equal to 2S+1;

[0016] In the direction from low to high, the first decoding result output terminal to the 2S+1 decoding result output terminal serve as the first first-type initial row control terminal to the 2S+1 first-type initial row control terminal in the direction from the first-type offset gate drive circuit to the second-type offset gate drive circuit, respectively;

[0017] In the direction from low bit to high bit, the inverting output end of the first decoding result output end to the inverting output end of the 2S+1 decoding result output end respectively serve as the first second type initial row control end to the 2S+1 second type initial row control end in the direction from the first type offset gate drive circuit to the second type offset gate drive circuit.

[0018] In an exemplary embodiment, the 2S+1-stage first-type offset gate driver circuit includes 2S first-side offset transmission control circuits. The first-side offset shift register circuits of two adjacent stages are cascade-connected via one of the first-side offset transmission control circuits. In the direction from the first-type offset gate driver circuit to the second-type offset gate driver circuit, in the first-side offset shift register circuits of two adjacent stages, the input end of the first-side offset transmission control circuit is connected to the output end of the first-side offset shift register circuit of the previous stage, and the output end of the first-side offset transmission control circuit is connected to the input end of the first-side offset shift register circuit of the next stage.

[0019] The offset transmission control circuit on the first side includes a first forward and reverse scan control terminal and a second forward and reverse scan control terminal. In the offset transmission control circuit on the first side, the first forward and reverse scan control terminal is electrically connected to the corresponding second type initial row control terminal, and the second forward and reverse scan control terminal is electrically connected to the corresponding first type initial row control terminal.

[0020] In an exemplary embodiment, in the direction from the first type of offset gate drive circuit to the second type of offset gate drive circuit, the first positive and negative scan control terminals of the first first-side offset transmission control circuit to the 2S first-side offset transmission control circuit are electrically connected to the second decoding result output terminal to the 2S+1 decoding result output terminal in the direction from low bit to high bit, respectively, and the second positive and negative scan control terminals of the first first-side offset transmission control circuit to the 2S first-side offset transmission control circuit are electrically connected to the inverting output terminal of the second decoding result output terminal to the inverting output terminal of the 2S+1 decoding result output terminal in the direction from low bit to high bit, respectively.

[0021] In an exemplary embodiment, the 2S+1-stage second-type offset gate driver circuit includes 2S second-side offset transmission control circuits, and the second-side offset shift register circuits of two adjacent stages are cascade-connected via one of the second-side offset transmission control circuits. In the direction from the second-type offset gate driver circuit to the first-type offset gate driver circuit, in the second-side offset shift register circuits of two adjacent stages, the input end of the second-side offset transmission control circuit is connected to the output end of the second-side offset shift register circuit of the previous stage, and the output end of the second-side offset transmission control circuit is connected to the input end of the second-side offset shift register circuit of the next stage.

[0022] The offset transmission control circuit on the second side includes a first forward and reverse scan control terminal and a second forward and reverse scan control terminal. In the offset transmission control circuit on the second side, the first forward and reverse scan control terminal is electrically connected to the corresponding first type initial row control terminal, and the second forward and reverse scan control terminal is electrically connected to the corresponding second type initial row control terminal.

[0023] In an exemplary embodiment, in the direction from the first type of offset gate drive circuit to the second type of offset gate drive circuit, the second forward and reverse scan control terminals of the first second-side offset transmission control circuit to the 2S second-side offset transmission control circuit are electrically connected to the second decoding result output terminal to the 2S+1 decoding result output terminal in the direction from low bit to high bit, respectively, and the first forward and reverse scan control terminals of the first second-side offset transmission control circuit to the 2S second-side offset transmission control circuit are electrically connected to the inverting output terminal of the second decoding result output terminal to the inverting output terminal of the 2S+1 decoding result output terminal in the direction from low bit to high bit, respectively.

[0024] In an exemplary embodiment, the gate drive circuit further includes an offset row drive enhancement circuit, a reset control circuit and a reset control terminal; the offset row drive enhancement circuit is located in the corresponding offset gate drive circuit, and in the offset row drive enhancement circuit, the input terminal is electrically connected to the output terminal of the corresponding offset shift register circuit, the output terminal is electrically connected to the corresponding pixel drive circuit in the display area, and the enable signal terminal is connected to the corresponding reset control circuit; in the reset control circuit, the input terminal is connected to the corresponding reset control terminal, the output terminal is connected to the enable signal terminal in the corresponding offset row drive enhancement circuit, and is configured to receive a reset control signal Tn from the reset control terminal, and under the control of the reset control signal, the corresponding offset row drive enhancement circuit is set to a high impedance state.

[0025] In an exemplary embodiment, the shift control circuit includes a decoding logic circuit and 2S cascade-connected half-adder logic circuits, wherein the output terminals of the half-adder logic circuit include a sum output terminal and a carry output terminal, and the input terminals of the half-adder logic circuit include an addend input terminal and an augend input terminal; the decoding logic circuit includes 2S+1 decoding result output terminals;

[0026] In the direction from low to high, among the 2S+1 decoding result output terminals, the inverting output terminal of the first decoding result output terminal is electrically connected to the addend input terminal of the first half adder logic circuit, and the second decoding result output terminal to the 2S decoding result output terminals are electrically connected to the summand input terminal of the second half adder logic circuit to the summand input terminal of the 2S half adder logic circuit, respectively, and the input value of the summand input terminal of the first-stage half adder logic circuit is always 1; and among the 2S half adders, the carry output terminal of the upper-stage half adder logic circuit is connected to the addend input terminal of the lower-stage half adder logic circuit.

[0027] In an exemplary embodiment, in a direction from the 2S+1-stage first-class offset gate driver circuit to the m-stage intermediate offset gate driver circuit, the reset control terminal includes first to 2S first-class reset control terminals electrically connected to the reset control circuits in the first-stage first-class offset gate driver circuit to the 2S-stage first-class offset gate driver circuit, respectively;

[0028] In the direction from low to high, the sum output terminal of the first half adder logic circuit to the sum output terminal of the 2Sth half adder logic circuit serve as the first first type reset control terminal to the 2Sth first type reset control terminal respectively.

[0029] In an exemplary embodiment, in a direction from the 2S+1-stage first-type offset gate driver circuit to the m-stage intermediate offset gate driver circuit, the reset control terminal includes first to 2S second-type reset control terminals electrically connected to the reset control circuits in the second-stage second-type offset gate driver circuit to the 2S+1-stage second-type offset gate driver circuit, respectively;

[0030] In the direction from low bit to high bit, the carry output terminal of the first half adder logic circuit to the carry output terminal of the 2Sth half adder logic circuit serve as the first second type reset control terminal to the 2Sth second type reset control terminal respectively.

[0031] In an exemplary embodiment, S takes a value of 8, the shift control circuit includes a decoding logic circuit, the decoding logic circuit is a standard 5-32 decoder, and the 2S+1 decoding result output terminals are respectively the 17 low-order decoding result output terminals of the standard 5-32 decoder.

[0032] In an exemplary embodiment, the logic decoding circuit includes at least one 3-wire-8-wire decoder, 2S+1 expansion circuits and at least one expansion input terminal. The number of the output terminals of the at least one 3-wire-8-wire decoder is 2S+1. The input terminals of the logic decoding circuit include three input terminals of the 3-wire-8-wire decoder and the at least one expansion input terminal. The input terminals of the 2S+1 expansion circuits are connected to the 2S+1 output terminals of the at least one 3-wire-8-wire decoder, and the output terminals of the 2S+1 expansion circuits serve as the 2S+1 output terminals of the logic decoding circuit respectively.

[0033] In an exemplary embodiment, S takes a value of 8, and the logic decoding circuit includes two 3-8 decoders, seventeen expansion circuits, and two expansion input terminals, wherein the two expansion input terminals include a first expansion input terminal and a second expansion input terminal, wherein the three input terminals of one 3-line-8-line decoder serve as the first input terminal to the third input terminal of the logic decoding circuit, the first expansion input terminal serves as the fourth input terminal of the logic decoding circuit, the second expansion input terminal serves as the fifth input terminal of the logic decoding circuit, and the inverting output terminal from the first input terminal to the third input terminal serves as the input terminal of the other 3-line-8-line decoder.

[0034] In an exemplary embodiment, the two 3-8 decoders include a first 3-8 decoder and a second 3-8 decoder, and the seventeen expansion circuits include sixteen first expansion circuits and one second expansion circuit;

[0035] The first 3-8 decoder, eight of the first expansion circuits, one second expansion circuit, and the two expansion input terminals constitute a 5-9 decoder; the second 3-8 decoder, another eight first expansion circuits, and the two expansion input terminals constitute a 5-8 decoder.

[0036] In an exemplary embodiment, the 5-9 decoder includes nine decoding output terminals and inverted output terminals of the nine decoding output terminals, and the 5-8 decoder includes eight decoding output terminals and inverted output terminals of the eight decoding output terminals;

[0037] The 2S+1 first-type initial row control terminals include the nine decoding output terminals of the 5-9 decoder and the eight decoding output terminals of the 5-8 decoder; the 2S+1 second-type initial row control terminals include the inverting output terminals of the nine decoding output terminals of the 5-9 decoder and the inverting output terminals of the eight decoding output terminals of the 5-8 decoder.

[0038] In an exemplary embodiment, among the nine decoding output terminals of the 5-9 decoder, in the direction from high to low, the first decoding output terminal to the ninth decoding output terminal serve as the first first-type initial row control terminal to the ninth first-type initial row control terminal in the direction from the first-type offset gate driving circuit to the second-type offset gate driving circuit, respectively;

[0039] Among the eight decoding output terminals of the 5-8 decoder, in the direction from high to low, the first decoding output terminal to the eighth decoding output terminal serve as the first first-class initial row control terminal to the eighth first-class initial row control terminal in the direction from the second-class offset gate drive circuit to the first-class offset gate drive circuit, respectively.

[0040] In an exemplary embodiment, among the inverted output terminals of the nine decoded output terminals of the 5-9 decoder, in the direction from high to low, the inverted output terminal of the first decoded output terminal to the inverted output terminal of the ninth decoded output terminal respectively serve as the first to the ninth second-type initial row control terminals in the direction from the first-type offset gate driving circuit to the second-type offset gate driving circuit;

[0041] Among the inverting output ends of the eight decoding output ends of the 5-8 decoder, in the direction from high to low, the inverting output end of the first decoding output end to the inverting output end of the eighth decoding output end serve as the first second-class initial row control end to the eighth second-class initial row control end in the direction from the second-class offset gate drive circuit to the first-class offset gate drive circuit, respectively.

[0042] In an exemplary embodiment, S takes a value of 8, and the shift control circuit includes a 3-7 thermometer decoder and a 5-9 logic operation circuit;

[0043] In the direction from the 2S+1-level first-class offset gate driving circuit to the m-level intermediate offset gate driving circuit, the reset control terminal includes first to 2S first-class reset control terminals electrically connected to the reset control circuits in the first-level first-class offset gate driving circuit to the 2S-level first-class offset gate driving circuit, respectively;

[0044] Among the nine output terminals of the 5-9 logic operation circuit, in the direction from high to low, the first output terminal to the ninth output terminal serve as the first first-class reset control terminal to the ninth first-class reset control terminal respectively;

[0045] Among the seven output terminals of the 3-7 thermometer decoder, in the direction from low to high, the first output terminal to the seventh output terminal serve as the tenth first-class reset control terminal to the sixteenth first-class reset control terminal respectively.

[0046] In an exemplary embodiment, in a direction from the 2S+1-stage first-type offset gate driver circuit to the m-stage intermediate offset gate driver circuit, the reset control terminal includes first to 2S second-type reset control terminals electrically connected to the reset control circuits in the second-stage second-type offset gate driver circuit to the 2S+1-stage second-type offset gate driver circuit, respectively;

[0047] Among the inverting output terminals of the nine output terminals of the 5-9 logic operation circuit, in the direction from high to low, the inverting output terminal of the first output terminal to the inverting output terminal of the ninth output terminal serve as the first second-type reset control terminal to the ninth second-type reset control terminal respectively;

[0048] Among the inverting output terminals of the seven output terminals of the 3-7 thermometer decoder, in the direction from low to high, the inverting output terminal of the first output terminal to the inverting output terminal of the seventh output terminal serve as the tenth second-type reset control terminal to the sixteenth second-type reset control terminal respectively.

[0049] In an exemplary embodiment, the offset shift register circuit also includes an enable signal terminal, and the output terminal of the reset control circuit is also electrically connected to the enable signal terminal of the corresponding offset shift register circuit, and is configured to receive a reset control signal from the reset control terminal. Under the control of the reset control signal, the corresponding offset shift register circuit is set to a high-impedance state.

[0050] In a second aspect, the present disclosure provides a working method of a gate drive device, which is applied to the gate drive device described in any of the above embodiments, wherein the gate drive device includes a shift control circuit and a multi-stage cascaded gate drive circuit, in the direction of the cascade of the multi-stage gate drive circuit, the multi-stage gate drive circuit includes a 4S+2-stage offset gate drive circuit and an m-stage intermediate gate drive circuit, the 4S+2-stage offset gate drive circuit includes a 2S+1-stage first-type offset gate drive circuit located on one side of the m-stage intermediate gate drive circuit, and a 2S+1-stage second-type offset gate drive circuit located on the other side of the m-stage intermediate gate drive circuit, m and S are both positive integers, and the shift control circuit is electrically connected to the 4S+2-stage offset gate drive circuit; the working method includes:

[0051] The shift control circuit outputs an initial row control signal to the 4S+2-level offset gate drive circuit. Under the control of the initial row control signal, one level is selected from the 2S+1-level first-level offset gate drive circuit as the first-level initial gate drive circuit, and one level is selected from the 2S+1-level second-level offset gate drive circuit as the second-level initial gate drive circuit; in the direction of the cascade of the multi-level gate drive circuits, the offset direction of the first-level initial gate drive circuit and the second-level initial gate drive circuit relative to the m-level intermediate gate drive circuit are consistent, and the number of offset levels relative to the m-level intermediate gate drive circuits is N, where N is an integer less than or equal to S.

[0052] In a third aspect, the present disclosure provides a display substrate comprising a display area and a non-display area; the display area comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area comprises the gate driving device described in any of the above embodiments, the gate driving device comprises a plurality of cascaded gate driving circuits, and at least one gate driving circuit is connected to the scanning signal line in the display area.

[0053] In a fourth aspect, the present disclosure provides a display device comprising the display substrate described in any of the above embodiments.

[0054] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The accompanying drawings are intended to facilitate understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0056] FIG1 is a schematic structural diagram of a silicon-based OLED display device;

[0057] FIG2 is a schematic diagram of a planar structure of a display area in a silicon-based OLED display device;

[0058] FIG3 is a schematic diagram of the cross-sectional structure of a display area in a silicon-based OLED display device;

[0059] FIG4 a is an equivalent circuit diagram of a pixel driving circuit;

[0060] FIG4 b is an equivalent circuit diagram of a pixel driving circuit;

[0061] FIG5a is a driving timing diagram of the pixel driving circuit shown in FIG4b;

[0062] FIG5b is a driving timing diagram of the pixel driving circuit shown in FIG4b;

[0063] FIG6 a is a schematic structural diagram of a gate driving device provided by an embodiment of the present disclosure;

[0064] FIG6 b is a schematic structural diagram of a shift control circuit provided by an exemplary embodiment of the present disclosure;

[0065] FIG6c is a schematic structural diagram of a shift control circuit provided by an exemplary embodiment of the present disclosure;

[0066] FIG6 d is a schematic structural diagram of a gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0067] FIG6e is a schematic structural diagram of a gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0068] FIG7 is a working principle diagram of a first operation circuit provided by an exemplary embodiment of the present disclosure;

[0069] FIG8 is a working principle diagram of a second operation circuit provided by an exemplary embodiment of the present disclosure;

[0070] FIG9 a is a working principle diagram of the latch in FIG8 provided by an exemplary embodiment of the present disclosure;

[0071] FIG9 b is a timing diagram of an operation of a latch provided by an exemplary embodiment of the present disclosure;

[0072] FIG10 is a working principle diagram of a third operation circuit provided by an exemplary embodiment of the present disclosure;

[0073] FIG11 is a working principle diagram of a level converter provided by an exemplary embodiment of the present disclosure;

[0074] FIG12 is a working principle diagram of a row drive enhancer provided by an exemplary embodiment of the present disclosure;

[0075] FIG13 is a schematic structural diagram of a shift register circuit provided by an exemplary embodiment of the present disclosure;

[0076] FIG14 is a diagram showing the working principle of a trigger provided by an exemplary embodiment of the present disclosure;

[0077] FIG15 is a timing diagram of an operation of a trigger provided by an exemplary embodiment of the present disclosure;

[0078] FIG16 a is a schematic structural diagram of a 2S+1 level first type gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0079] FIG16 b is a schematic structural diagram of a 2S+1 level second type gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0080] FIG16c is a schematic structural diagram of an m-level intermediate gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0081] FIG16 d is a schematic diagram of the architecture of a gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0082] FIG17 is a schematic structural diagram of a shift control circuit provided by an exemplary embodiment of the present disclosure;

[0083] FIG18 is a schematic structural diagram of a shift control circuit provided by an exemplary embodiment of the present disclosure;

[0084] FIG19 is a truth table of a 5-17 decoder provided by an exemplary embodiment of the present disclosure;

[0085] FIG20 is a truth table of a 5-17 decoder provided by an exemplary embodiment of the present disclosure;

[0086] FIG21 is a truth table of the sum output terminals of 16 half adders provided by an exemplary embodiment of the present disclosure;

[0087] FIG22 is a truth table of the carry output terminals of 16 half adders provided by an exemplary embodiment of the present disclosure;

[0088] FIG23 is a schematic diagram of a start row control provided by an exemplary embodiment of the present disclosure;

[0089] FIG24 is a schematic diagram of a cut-off row control provided by an exemplary embodiment of the present disclosure;

[0090] FIG25 is a working principle diagram of a 5-17 decoder provided by an exemplary embodiment of the present disclosure;

[0091] FIG26 is a schematic structural diagram of a shift control circuit provided by an exemplary embodiment of the present disclosure;

[0092] FIG27 is a working principle diagram of a 5-9 decoder provided by an exemplary embodiment of the present disclosure;

[0093] FIG28 is a working principle of a 5-8 decoder provided by an exemplary embodiment of the present disclosure;

[0094] FIG29 illustrates the working principle of a 3-7 thermometer decoder and a 5-9 logic operation circuit provided by an exemplary embodiment of the present disclosure;

[0095] FIG30 a is a working principle diagram of a second expansion circuit provided by an exemplary embodiment of the present disclosure;

[0096] FIG30 b is a working principle diagram of a first expansion circuit provided by an exemplary embodiment of the present disclosure;

[0097] FIG31 is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0098] FIG32 is a schematic structural diagram of a display device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0099] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to the general design

[0100] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0101] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0102] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0103] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0104] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0105] In this specification, in order to distinguish the two electrodes of a transistor other than the gate electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode. The first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, the terms "source electrode" and "drain electrode" can be interchanged.

[0106] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0107] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0108] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0109] FIG1 is a schematic diagram of the structure of a silicon-based OLED display device. As shown in FIG1 , the silicon-based OLED display device may include a display area and a non-display area. The display area may include multiple scan signal lines, multiple data signal lines, and multiple sub-pixels Pxij forming multiple pixel rows and multiple pixel columns. The multiple scan signal lines are respectively arranged in the multiple pixel rows, and the multiple data signal lines are respectively arranged in the multiple pixel columns. Each sub-pixel Pxij may include at least a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel driving circuit of each sub-pixel Pxij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel Pxij may refer to the sub-pixel in the i-th pixel row and the j-th pixel column. The pixel driving circuit of the sub-pixel Pxij is respectively connected to the i-th scan signal line and the j-th data signal line, where i and j may be natural numbers. The non-display area may include a display driver integrated circuit (DDIC), a gate driver in panel (GD or GIP), and a data driver (SD). The display driver circuit may include at least a timing controller (TCON). The timing controller is configured to generate timing signals required by the gate driver, such as a start signal (STV) and a clock signal (CKV), and send the timing signals to the gate driver. The gate driver is respectively connected to a plurality of scan signal lines in the display area, and the gate driver is configured to provide the required timing signals (timing) to the connected pixel driver circuit to realize the display progressive scanning function. The data driver is respectively connected to a plurality of data signal lines in the display area, and the data driver is configured to provide the required data signals (data) to the connected pixel driver circuit to realize the switching and control of the display screen. In one exemplary embodiment, the non-display area may include a gamma register, which may be provided inside or outside a data driver (which may be referred to as a data driver circuit). The data driver may provide a data signal to a connected pixel driver circuit based on a gamma voltage in the gamma register. In another exemplary embodiment, the non-display area may include an oscillator, which may be connected to a timing controller and may function as a frequency generator to provide a clock signal to the timing controller.

[0110] In one exemplary embodiment, a silicon-based OLED display device may utilize a single-chip display architecture ("One Chip"), integrating a gate driver, data driver, clock control unit, image processing unit, and storage unit on a single chip. A chip with a One Chip architecture includes both digital and analog components, making it a mixed-signal chip.

[0111] In another exemplary embodiment, the silicon-based OLED display device can be a dual-chip display architecture (Two Chip), in which the gate driving device and the data driving device are integrated in the display substrate, and the clock control unit, the image processing unit, the mobile industry processor interface (MIPI) and the storage unit are integrated in one chip, which is bonded to the display substrate through the COC process.

[0112] Figure 2 is a schematic diagram of the planar structure of a display area in a silicon-based OLED display device. As shown in Figure 2, the display area may include multiple pixel units P arranged in a matrix on a plane parallel to the display device. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is respectively connected to a scan signal line and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0113] In an exemplary embodiment, the first subpixel P1 may be a red (R) subpixel emitting red light, the second subpixel P2 may be a blue (B) subpixel emitting blue light, and the third subpixel P3 may be a green (G) subpixel emitting green light.

[0114] In an exemplary embodiment, the shape of the sub-pixels can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. The three sub-pixels can be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a herringbone arrangement, etc., which is not limited in this disclosure. In other possible embodiments, the pixel unit can include four sub-pixels, which is not limited in this disclosure.

[0115] FIG3 is a schematic diagram of the cross-sectional structure of the display area in a silicon-based OLED display device, illustrating a structure that uses white light + color filter to achieve full color. As shown in FIG3 , in a direction perpendicular to the display device, the silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the silicon substrate 101, a color filter structure layer 105 disposed on the side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on the side of the color filter structure layer 105 away from the silicon substrate 101, and a cover layer 107 disposed on the side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited in this disclosure.

[0116] In an exemplary embodiment, the silicon substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 may be prepared on the silicon substrate 101 by a silicon semiconductor process. The driving circuit layer 102 may include a plurality of circuit units. The circuit units may include at least a pixel driving circuit. The pixel driving circuit is connected to a scanning signal line and a data signal line, respectively. The pixel driving circuit may include a plurality of transistors and a storage capacitor. FIG3 shows only one transistor as an example. The transistor may include a gate electrode G, a first electrode S, and a second electrode D. The gate electrode G, the first electrode S, and the second electrode D may be connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-vias), and may be connected to other electrical structures (such as traces, etc.) through the connection electrodes.

[0117] In an exemplary embodiment, the light-emitting structure layer 103 may include a plurality of light-emitting devices, each of which may include at least an anode, an organic light-emitting layer, and a cathode. The anode may be connected to the second pole D of the transistor via a connecting electrode, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to the second power line. The organic light-emitting layer emits light under the drive of the anode and the cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML for short), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device that emits white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0118] In an exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can be encapsulated using a thin film encapsulation (TFE) method to ensure that external moisture cannot enter the light-emitting structure layer. The color filter structure layer 105 can include at least a red filter unit, a blue filter unit, and a green filter unit. The red filter unit is set in the red sub-pixel to filter the white light emitted by the light-emitting device into red light. The blue filter unit is set in the blue sub-pixel to filter the white light emitted by the light-emitting device into blue light. The green filter unit is set in the green sub-pixel to filter the white light emitted by the light-emitting device into green light. The cover layer 107 can be made of glass or a flexible plastic material such as colorless polyimide.

[0119] Figure 4a is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 4a, the pixel driving circuit has a 4T2C structure, which can include four transistors (a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4) and two storage capacitors (a first capacitor C1 and a second capacitor C2). The pixel driving circuit is connected to six signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a data signal line DATA, a first power line VDD, and a second power line VSS).

[0120] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first end of the first capacitor C1, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the first electrode of the third transistor T3, the second end of the first capacitor C1, and the first end of the second capacitor C2, respectively. The third node N3 is connected to the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4, respectively.

[0121] In an exemplary embodiment, the first transistor T1 can be referred to as a write switch transistor, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the data signal line DATA, and a second electrode of the first transistor T1 is connected to the first node N1.

[0122] In an exemplary embodiment, the second transistor T2 is called a display switch transistor, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the first power line VDD, and a second electrode of the second transistor T2 is connected to the second node N2.

[0123] In an exemplary embodiment, the third transistor T3 may be referred to as a driver transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

[0124] In an exemplary embodiment, the fourth transistor T4 can be called an auto zero transistor, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the second power line VSS, and a second electrode of the fourth transistor T4 is connected to the third node N3.

[0125] In an exemplary embodiment, a first end of the first capacitor C1 is connected to the first node N1, a second end of the first capacitor C1 is connected to the second node N2, a first end of the second capacitor C2 is connected to the second node N2, and a second end of the second capacitor C2 is connected to the first power line VDD.

[0126] In an exemplary embodiment, the light emitting device EL may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). The first electrode of the light emitting device XL is connected to the third node N3, and the second electrode of the light emitting device EL is connected to the common voltage line VCOM.

[0127] In an exemplary embodiment, the signal of the first power line VDD may be a continuously provided high level signal, and the signals of the second power line VSS and the common voltage line VCOM may be continuously provided low level signals.

[0128] In an exemplary embodiment, the first to fourth transistors T1 to T4 may be P-type transistors (PMOS) or N-type transistors (NMOS). For example, the first to fourth transistors T1 to T4 are all P-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the product yield.

[0129] In an exemplary embodiment, the first to fourth transistors T1 to T4 may include P-type transistors and N-type transistors. For example, the first to third transistors T1 to T3 may be P-type transistors, and the fourth transistor T4 may be an N-type transistor, as shown in FIG4a. In an exemplary embodiment, the first to fourth transistors T1 to T4 are all P-type transistors. For example, the first to fourth transistors T1 to T4 may all be P-type transistors, as shown in FIG4b.

[0130] FIG5a is a driving timing diagram of the pixel driving circuit shown in FIG4a. As shown in FIG5a, in an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0131] The first phase A1 can be called the initialization phase. The signals of the first scan signal line S1 and the second scan signal line S2 are low-level signals, and the signal of the third scan signal line S3 is a high-level signal, so that the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on. The first transistor T1 is turned on so that the bias voltage Vofs output by the data signal line DATA is written into the first capacitor C1, and the potential Vs of the first node N1 (i.e., the gate electrode of the third transistor T3) is Vofs. The second transistor T2 is turned on so that the first power supply voltage ELVDD output by the first power line VDD is written into the second node N2, and the potential Vg of the second node N2 (i.e., the first electrode of the third transistor T3) is ELVDD. At this time, the gate-source voltage Vgs of the third transistor T3 is ELVDD-Vofs, and the storage voltage V of the first capacitor C1 is V cs =ELVDD-Vofs, the potential Vd of the third node N3 (ie, the second electrode of the third transistor T3) = Vg+Vth, preparing for the next stage of discharge. ofs >|Vth|, where Vth is the threshold voltage of the third transistor T3.

[0132] The second stage A2 can be called the self-discharge stage. The signal of the third scanning signal line S3 is a high-level signal, and the fourth transistor T4 is continuously turned on. The signal of the first scanning signal line S1 changes from a low-level signal to a high-level signal, causing the first transistor T1 to be disconnected first, and the first node N1 to float. Subsequently, the signal of the second scanning signal line S2 changes from a low-level signal to a high-level signal, causing the second transistor T2 to be disconnected, and the second node N2 forms a loop through the turned-on third transistor T3, the third node N3 and the turned-on fourth transistor T4, and begins to discharge, and the potential of the second node N2 drops. Because the first node N1 is floating, the voltage difference across the first capacitor C1 remains unchanged, and thus the potential of the first node N1 drops as the potential of the second node N2 drops. Due to the back-gate effect of the third transistor T3, the gate-source voltage Vgs of the third transistor T3 remains unchanged, and thus the equivalent threshold voltage |V th_EF |As the potential of the second node N2 decreases, the equivalent threshold voltage of the third transistor T3 gradually increases. th_EF |=α(ELVDD-Vs)+|Vth|, α is the back gate coefficient. When the equivalent threshold voltage of the third transistor T3 |V th_EF When Vgs increases to the gate-source voltage Vgs of the third transistor T3, the third transistor T3 is turned off and the second node N2 stops discharging.

[0133] The third stage A3 can be called the data writing stage and the threshold compensation stage. The signal of the second scan signal line S2 is a high-level signal, and the second transistor T2 is continuously off. The signal of the third scan signal line S3 is a high-level signal, and the fourth transistor T4 is continuously on. The signal of the first scan signal line S1 changes from a high-level signal to a low-level signal, turning on the first transistor T1. The turning on of the first transistor T1 causes the data voltage Vdata output by the data signal line DATA to be written to the first node N1, and the potential of the first node N1 changes from Vofs to Vdata. Since the second node N2 is floating, threshold compensation can be achieved in this stage.

[0134] The fourth phase A4 can be referred to as the light-emitting phase. The signals on the second and third scan signal lines S2 and S3 are low-level signals, while the signal on the first scan signal line S1 is high-level. This turns on the second transistor T2, while the first and fourth transistors T1 and T4 are off. Turning on the second transistor T2 causes the power supply voltage output from the first power line VDD to provide a driving voltage to the first electrode of the light-emitting device EL through the turned-on second and third transistors T2 and T3, driving the light-emitting device EL to emit light.

[0135] In the light-emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0136] FIG5 b is a driving timing diagram of the pixel driving circuit shown in FIG4 b . As shown in FIG5 b , the operation process of the pixel driving circuit in FIG4 b may include a first stage A1 to a fourth stage A4. FIG5 b differs from FIG5 a in that the timing of the third scanning signal line S3 is different. In FIG4 a and FIG5 a , the fourth transistor T4 is an N-type transistor (high level turns on, low level turns off), while in FIG4 b and FIG5 b , the fourth transistor T4 is a P-type transistor (high level turns off, low level turns on).

[0137] The signals of the first scanning signal line S1, the second scanning signal line S2 and the third scanning signal line S3 in Figures 5a and 5b are usually provided by the gate driving circuit. The gate driving circuit is usually in a cascade connection relationship. There are often technical problems of signal input errors or initial signal input errors in the gate driving circuit between two adjacent levels, resulting in the pixel driving circuit not being able to work normally. Under normal circumstances, the displayed image will be displayed in the center. In practice, there is a technical problem of incomplete image display due to occlusion (such as mechanical occlusion). A shift control circuit can be set in the gate driving circuit to control the shift of the displayed image to avoid occlusion of the displayed image. In actual applications, there are problems such as high cost of the shift control circuit, complex circuit and large area occupied by the shift control circuit.

[0138] An embodiment of the present disclosure provides a gate driving device, which may include a shift control circuit and a multi-stage cascaded gate driving circuit. The multi-stage gate driving circuit includes a 4S+2-stage offset gate driving circuit and an m-stage intermediate gate driving circuit. In the direction of the cascade of the multi-stage gate driving circuit, the 4S+2-stage offset gate driving circuit includes a 2S+1-stage first-type offset gate driving circuit located on one side of the m-stage intermediate gate driving circuit, and a 2S+1-stage second-type offset gate driving circuit located on the other side of the m-stage intermediate gate driving circuit. Both m and S are positive integers.

[0139] The shift control circuit is electrically connected to the 4S+2-level offset gate drive circuit and is configured to output an initial row control signal to the 4S+2-level offset gate drive circuit. Under the control of the initial row control signal, one level is selected from the 2S+1-level first-level offset gate drive circuit as the first-level initial gate drive circuit, and one level is selected from the 2S+1-level second-level offset gate drive circuit as the second-level initial gate drive circuit; in the direction of the cascade of the multi-level gate drive circuits, the offset direction of the first-level initial gate drive circuit and the second-level initial gate drive circuit relative to the m-level intermediate gate drive circuit are consistent, and the number of offset levels relative to the m-level intermediate gate drive circuits is N, where N is an integer less than or equal to S.

[0140] In the gate drive device provided by the present disclosure, a shift control circuit is electrically connected to a 4S+2-stage offset gate drive circuit and is configured to output an initial row control signal to the 4S+2-stage offset gate drive circuit. Under the control of the initial row control signal, one stage is selected from the 2S+1-stage first-stage offset gate drive circuit as the first-stage initial gate drive circuit, and one stage is selected from the 2S+1-stage second-stage offset gate drive circuit as the second-stage initial gate drive circuit. In the direction of the cascade of the multi-stage gate drive circuits, the first-stage initial gate drive circuit and the second-stage initial gate drive circuit are offset in the same direction relative to the m-stage intermediate gate drive circuits, and the number of offset stages relative to the m-stage intermediate gate drive circuits is N. The technical solution provided by the embodiments of the present disclosure can shift the first-stage initial shift register circuit and the second-stage initial shift register circuit, thereby achieving pixel-level alignment or preventing incomplete displayed images due to occlusion.

[0141] As shown in FIG6a and FIG16a to FIG16c, the gate driving device provided by the embodiment of the present disclosure can shift the control circuit and the multi-stage cascade gate driving circuit. The multi-stage gate driving circuit may include a 4S+2-stage offset gate driving circuit and an m-stage intermediate gate driving circuit G100. In the direction of the cascade of the multi-stage gate driving circuit, the 4S+2-stage offset gate driving circuit includes a 2S+1-stage first-type offset gate driving circuit G101 located on one side of the m-stage intermediate gate driving circuit G100, and a 2S+1-stage second-type offset gate driving circuit G102 located on the other side of the m-stage intermediate gate driving circuit. Both m and S are positive integers.

[0142] The shift control circuit is electrically connected to the 4S+2-level offset gate drive circuit and is configured to output an initial row control signal to the 4S+2-level offset gate drive circuit. Under the control of the initial row control signal, one level is selected from the 2S+1-level first-level offset gate drive circuit G101 as the first-level initial gate drive circuit, and one level is selected from the 2S+1-level second-level offset gate drive circuit G102 as the second-level initial gate drive circuit; in the direction of the cascade of the multi-level gate drive circuits, the offset direction of the first-level initial gate drive circuit and the second-level initial gate drive circuit relative to the m-level intermediate gate drive circuit is consistent, and the number of offset levels relative to the m-level intermediate gate drive circuit is N, where N is an integer less than or equal to S.

[0143] In an exemplary embodiment, the offset gate driving circuit includes a row control circuit 01, an offset shift register circuit, an initial signal terminal IN_STV, and a row control terminal; in the row control circuit 01, the input terminal is connected to the initial signal terminal IN_STV, the control terminal is connected to the row control terminal, the output terminal is connected to the input terminal of the offset shift register circuit, and the output terminal of the offset shift register circuit is electrically connected to the corresponding pixel row in the display area;

[0144] The row control circuit 01 is configured to receive a forward and reverse scan control signal from the row control terminal, and an initial signal from the initial signal terminal IN_STV. Under the control of the forward and reverse scan control signal, one of the first type of initial gate drive circuit and the second type of initial gate drive circuit is used as the starting row of the gate drive circuit, and the other is used as the cut-off row of the gate drive circuit, and the initial signal is provided to the starting row of the gate drive circuit.

[0145] In an exemplary embodiment, the row control circuit 01 may include a forward and reverse scan control circuit 01-2, the forward and reverse scan control circuit 01-2 may include a third control terminal K3 and a fourth control terminal K4, the row control terminal may include a first transmission control terminal GSD_BW and a second transmission control terminal GSD_FW, in the first type of offset gate drive circuit G101, the third control terminal K3 in the forward and reverse scan control circuit 01-2 is electrically connected to the second transmission control terminal GSD_FW, and the fourth control terminal K4 is electrically connected to the first transmission control terminal GSD_BW; in the second type of offset gate drive circuit G102, the third control terminal K3 in the forward and reverse scan control circuit 01-2 is electrically connected to the first transmission control terminal GSD_BW, and the fourth control terminal K4 is electrically connected to the second transmission control terminal GSD_FW; the input terminal of the forward and reverse scan control circuit 01-2 is electrically connected to the initial signal terminal IN_STV, and the output terminal is electrically connected to the input terminal of the corresponding offset shift register circuit.

[0146] In an exemplary embodiment, the row control circuit 01 may include an initial row control circuit 01-1, and the initial row control circuit 01-1 may include a first control terminal K1 and a second control terminal K2. The row control terminals may include 2S+1 first-type initial row control terminals and 2S+1 second-type initial row control terminals; the first control terminal K1 in the 2S+1-level first-type offset gate driver circuit G101 is electrically connected to the 2S+1 first-type initial row control terminals, respectively, and the second control terminal K2 in the 2S+1-level first-type offset gate driver circuit is electrically connected to the 2S+1 second-type initial row control terminals, respectively; the first control terminal K1 in the 2S+1-level second-type offset gate driver circuit G102 is electrically connected to the 2S+1 first-type initial row control terminals, respectively, and the second control terminal K2 in the 2S+1-level second-type offset gate driver circuit G102 is electrically connected to the 2S+1 second-type initial row control terminals, respectively.

[0147] The input end of the initial row control circuit 01-1 is connected to the initial signal end IN_STV, and the output end is electrically connected to the input end of the corresponding forward and reverse scan control circuit 01-2; the input end of the forward and reverse scan control circuit 01-2 is electrically connected to the initial signal end IN_STV through the corresponding initial row control circuit 01-1, and the output end can be electrically connected to the input end of the corresponding offset shift register circuit.

[0148] In an exemplary embodiment, the shift control circuit includes a logic decoding circuit, which includes 2S+1 decoding result output terminals and inverting output terminals of the 2S+1 decoding result output terminals. In an exemplary embodiment, the 2S+1 decoding result output terminals can each serve as 2S+1 first-type initial row control terminals, and the inverting output terminals of the 2S+1 decoding result output terminals can each serve as 2S+1 second-type initial row control terminals.

[0149] In an exemplary embodiment, as shown in FIG6b and FIG6c, the logic decoding circuit may be a standard decoder, wherein the number of decoding result output terminals of the standard decoder is greater than or equal to 2S+1; in the direction from the lower bit (Y0) to the higher bit (Y2S), the first decoding result output terminal Y0 to the 2S+1 decoding result output terminal Y2S serve as the first first-type initial row control terminal IN_ZS to the 2S+1 first-type initial row control terminal IN_Z_S in the direction from the first-type offset gate driver circuit G101 to the second-type offset gate driver circuit G102, respectively;

[0150] In the direction from the low bit (Y0) to the high bit (Y2S), the inverting output terminal (Y0_) of the first decoding result output terminal (Y0) to the inverting output terminal (Y2S_) of the 2S+1 decoding result output terminal (Y2S) respectively serve as the first second-type initial row control terminal IN_ZS_ to the 2S+1 second-type initial row control terminal IN_Z_S_ in the direction from the first-type offset gate drive circuit G101 to the second-type offset gate drive circuit G102.

[0151] In an exemplary embodiment, as shown in FIG6b and FIG6c, the decoding logic circuit 600 may include n input terminals A0 to An. 2S+1 decoding result output terminals are configured to control the start row, and 2S sum output terminals of the half-adder logic circuits are configured to control the stop row and reset the non-display area.

[0152] In an exemplary embodiment, a 2S+1-stage first-type offset gate driver circuit G101 may include 2S first-side offset transmission control circuits P10-1. The first-side offset shift register circuits P101 of two adjacent stages may be cascade-connected via one of the first-side offset transmission control circuits P10-1. In a direction from the first-type offset gate driver circuit G101 to the second-type offset gate driver circuit G102, in the first-side offset shift register circuits P101 of two adjacent stages, the input end of the first-side offset transmission control circuit P10-1 is connected to the output end of the first-side offset shift register circuit P101 of the previous stage, and the output end of the first-side offset transmission control circuit P10-1 is connected to the input end of the first-side offset shift register circuit P101 of the next stage.

[0153] The offset transmission control circuit P10-1 on the first side may include a first forward and reverse scan control terminal GSD1 and a second forward and reverse scan control terminal GSD2. In the offset transmission control circuit P10-1 on the first side, the first forward and reverse scan control terminal GSD1 is electrically connected to the corresponding second type initial row control terminal, and the second forward and reverse scan control terminal GSD2 is electrically connected to the corresponding first type initial row control terminal.

[0154] In an exemplary embodiment, in the direction from the first type of offset gate drive circuit G101 to the second type of offset gate drive circuit G102, the first forward and reverse scan control terminals GSD1 of the first first-side offset transmission control circuit P10-1 to the 2S first-side offset transmission control circuit P10-1 are respectively electrically connected to the second decoding result output terminal Y1 to the 2S+1 decoding result output terminal Y2S in the low-to-high direction, and the second forward and reverse scan control terminals GSD2 of the first first-side offset transmission control circuit to the 2S first-side offset transmission control circuit are respectively electrically connected to the inverting output terminal Y1_ of the second decoding result output terminal to the inverting output terminal Y2S_ of the 2S+1 decoding result output terminal in the low-to-high direction.

[0155] In an exemplary embodiment, a 2S+1-stage second-type offset gate driver circuit G102 may include 2S second-side offset transmission control circuits P10-2. The second-side offset shift register circuits P102 of two adjacent stages may be cascade-connected via one of the second-side offset transmission control circuits P10-2. In a direction from the second-type offset gate driver circuit G102 to the first-type offset gate driver circuit G101, in the second-side offset shift register circuits P102 of two adjacent stages, the input end of the second-side offset transmission control circuit P10-2 is connected to the output end of the second-side offset shift register circuit P102 of the previous stage, and the output end of the second-side offset transmission control circuit P10-2 is connected to the input end of the second-side offset shift register circuit P102 of the next stage.

[0156] The offset transmission control circuit P10-2 on the second side may include a first forward and reverse scan control terminal GSD1 and a second forward and reverse scan control terminal GSD2. In the offset transmission control circuit P10-2 on the second side, the first forward and reverse scan control terminal GSD1 is electrically connected to the corresponding first type initial row control terminal, and the second forward and reverse scan control terminal GSD2 is electrically connected to the corresponding second type initial row control terminal.

[0157] In an exemplary embodiment, in the direction from the first type of offset gate drive circuit G101 to the second type of offset gate drive circuit G102, the second forward and reverse scan control terminals GSD2 of the first second-side offset transmission control circuit P10-2 to the 2S second-side offset transmission control circuit P10-2 are respectively electrically connected to the second decoding result output terminal Y1 to the 2S+1 decoding result output terminal Y2S in the direction from low bit to high bit, and the first forward and reverse scan control terminals GSD1 of the first second-side offset transmission control circuit P10-2 to the 2S second-side offset transmission control circuit P10-2 are respectively electrically connected to the inverting output terminal Y1_ of the second decoding result output terminal to the inverting output terminal Y2S_ of the 2S+1 decoding result output terminal in the direction from low bit to high bit.

[0158] In an exemplary embodiment, the gate drive circuit may further include an offset row drive enhancement circuit P400, a reset control circuit 10-3 and a reset control terminal (IN_TS to IN_T_S-1, IN_TS_ to IN_T_S-1_); the offset row drive enhancement circuit P400 is located in the corresponding offset gate drive circuit, and in the offset row drive enhancement circuit P400, the input terminal is electrically connected to the output terminal of the corresponding offset shift register circuit, the output terminal is electrically connected to the corresponding pixel drive circuit in the display area, and the enable signal terminal is connected to the corresponding reset control circuit 10-3; in the reset control circuit 10-3, the input terminal is connected to the corresponding reset control terminal, and the output terminal is connected to the enable signal terminal in the corresponding offset row drive enhancement circuit P400, and is configured to receive a reset control signal from the reset control terminal, and under the control of the reset control signal, the corresponding offset row drive enhancement circuit P400 is set to a high impedance state. The offset row driving enhancement circuit P400 stops outputting signals to the display area in a high-impedance state. The pixel driving circuit connected to the high-impedance row driving circuit P400 cannot receive signals from the gate driving circuit and does not display an image.

[0159] In an exemplary embodiment, as shown in FIG6 b and FIG6 c , the shift control circuit may include a decoding logic circuit 600 and 2S cascade-connected half-adder logic circuits 700. The output terminals of the half-adder logic circuit 700 may include sum output terminals (S0 to S2S-1) and carry output terminals (C0 to C2S-1). The input terminals of the half-adder logic circuit may include an addend input terminal (A) and an augend input terminal (B). The decoding logic circuit may include 2S+1 decoding result output terminals (Y0 to Y2S).

[0160] In the direction from low bit (Y0) to high bit (Y2S), among the 2S+1 decoding result output terminals, the inverting output terminal Y0_ of the first decoding result output terminal Y0 is electrically connected to the addend input terminal A of the first half adder logic circuit 701, and the second decoding result output terminal Y1 to the 2S decoding result output terminal Y2S are electrically connected to the addend input terminal B of the second half adder logic circuit 702 to the addend input terminal B of the 2S half adder logic circuit 7 (2S), respectively. The input value of the addend input terminal of the first-stage half adder logic circuit 701 is always 1; among the 2S half adders, the carry output terminal (C0 to C2S) of the upper-stage half adder logic circuit is connected to the addend input terminal (A) of the next-stage half adder.

[0161] The technical solution provided by the embodiment of the present disclosure can achieve pixel-level alignment or avoid incomplete display images due to occlusion by shifting the first type of initial shift register circuit and the second type of initial shift register circuit; the shift control circuit combines the decoding logic circuit and the half-adder logic circuit as shown in Figures 6b and 6c. The circuit structure is simple, and part of the decoding result output end of the decoder can be reused as the input end of the half adder, which can reduce costs and reduce the area occupied by the shift control circuit.

[0162] In an exemplary embodiment, in a direction of the 2S+1-stage first-class offset gate driver circuit G101 to the m-stage middle offset gate driver circuit G100, the reset control terminal may include first to 2S first-class reset control terminals (IN_TS to IN_T_S-1) electrically connected to the reset control circuits in the first-stage first-class offset gate driver circuit G101 to the 2S-stage first-class offset gate driver circuit G101, respectively;

[0163] In the direction from low to high, the sum output terminal S1 of the first half adder logic circuit 701 to the sum output terminal S2S-1 of the 2Sth half adder logic circuit serve as the first first-class reset control terminal IN_TS to the 2Sth first-class reset control terminal IN_T_S-1 respectively.

[0164] In an exemplary embodiment, in a direction from the 2S+1-stage first-class offset gate driver circuit G101 to the m-stage middle offset gate driver circuit G100, the reset control terminal may include first to 2S-th second-class reset control terminals (IN_TS_ to IN_T_S-1_) electrically connected to the reset control circuits in the second-class offset gate driver circuit G102 to the 2S+1-stage second-class offset gate driver circuit G102, respectively;

[0165] In the direction from low to high, the carry output terminal C0 of the first half adder logic circuit to the carry output terminal C2S-1 of the 2Sth half adder logic circuit can be used as the first second-type reset control terminal IN_TS_ to the 2Sth second-type reset control terminal IN_T_S-1_ respectively.

[0166] In an exemplary embodiment, the shift control circuit may further include 2S inverters, the half-adder logic circuit 700 may be a half adder 700, and the half adder 700 may include an addend input terminal A and an addend input terminal B. In the direction from low to high, the first decoding result output terminal Y0 is connected to the addend input terminal A of the first half adder 701 through the first inverter, and the input value of the addend input terminal B of the first half adder 701 is always 1; the second decoding result output terminal Y1 to the 2S decoding result output terminal Y2S-1 are respectively connected to the addend input terminal B of the second half adder 702 to the 2S half adder 7(2S-1) through the second inverter to the 2S inverters. In the first half adder 701 to the 2S half adder 7(2S-1), the carry output terminal of the previous half adder is connected to the addend input terminal A of the next half adder.

[0167] In an exemplary embodiment, the value of S can be 8, and the shift control circuit can include a decoding logic circuit 600, which can be a standard 5-32 decoder. The 2S+1 decoding result output terminals are respectively the 17 low-order decoding result output terminals (Y0 to Y16) of the standard 5-32 decoder.

[0168] The gate drive device provided by the embodiment of the present disclosure has a simple circuit structure of the shift control circuit, which can improve the efficiency of display image shifting. The output end of the decoder is multiplexed as the input end of the half adder, thereby improving the utilization rate of the decoder output end, reducing the cost and the area of ​​the shift control circuit to a certain extent. It can be applied to display substrates with limited hardware resources and a small area, such as silicon-based OLED display substrates.

[0169] The technical solution of the gate driving device disclosed in the present invention is described below through exemplary embodiments.

[0170] As shown in FIG6d, it is a schematic diagram of the structure of a multi-stage cascade gate drive circuit (including a multi-stage intermediate stage shift register circuit). Each gate drive circuit may include a logic control circuit 10 and a target signal generating circuit 20. The logic control circuit 10 may include a logic control unit (for example, it may include at least one of a transmission gate, a logic control transistor, a NAND gate, and an inverter), which is mainly used for addressing, forward and reverse scanning control, etc. (10-3 is a reset control subcircuit, which is configured to reset the row drive enhancer 400). Among them, Z0 to Zn+1 and Z0_ to Zn+1 are respectively configured to be reset and controlled. n+1_ is a scan start line control signal terminal, IN_STV is a start signal STV input terminal (set to input the first signal A_D1, the second signal B_D1 and the third signal C_D1), the signals input by the second forward and reverse scan control terminal GSD2 and the first forward and reverse scan control terminal GSD1 are mutually inverse signals (for example, one of the signals input by the first forward and reverse scan control terminal GSD1 and the second forward and reverse scan control terminal GSD2 is a high level 1 and the other is a low level 0); the target signal generation circuit 20 may include a shift register circuit 100, a logical operation circuit (Logical Transition Unit) 200, a level conversion circuit (Level shifter) 300 and a line driver enhancement circuit (Line Driver) 400, mainly used to generate a line drive timing signal as shown in Figure 5a or Figure 5b. In an exemplary embodiment, the gate drive circuit can be arranged in a non-display area of ​​the display substrate, can be located on one side of the pixel row direction of the display area in the display substrate, or can be located on both sides of the pixel row direction of the display area in the display substrate. The gate drive device may include multiple cascaded gate drive circuits, at least one of which is connected to a scan signal line in a pixel row in the display area, providing a scan signal to the connected scan signal line. When the gate drive device is positioned on both sides of the pixel row in the display area, the scan signal lines in the pixel row are driven by two gate drive circuits, forming a bilateral drive structure. This ensures high pixel density drive capability and prevents drive signal distortion.

[0171] Figure 6e is a schematic diagram of the structure of a target signal generating circuit 20 in a gate driver circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 6e, the target signal generating circuit 20 in the gate driver circuit may include a shift register circuit 100, a logical operation circuit (Logical Transition Unit) 200, a level shifter circuit (Level Shifter) 300, and a line driver enhancement circuit (Line Driver) 400.

[0172] In an exemplary embodiment, the shift register circuit 100 may be a shift register circuit composed of a D flip-flop (D Flip Flop, abbreviated as DFF). The shift register circuit 100 is connected to the display driver circuit and receives a timing signal generated by the display driver circuit. The timing signal may include a start signal STV and a clock signal CKV. The D flip-flop is configured to shift and register the received timing signal to initially generate a timing sequence that can be shifted row by row. The logic operation circuit 200 is connected to the shift register circuit 100 and is configured to perform a logic operation on the shifted signal to generate a plurality of target timing sequences with different waveforms. The level conversion circuit 300 is connected to the logic operation circuit 200 and is configured to perform voltage domain conversion on the target timing sequence. The row drive enhancement circuit 400 is connected to the level conversion circuit 300 and is configured to enhance the converted signal, thereby enhancing the output capability and outputting the scan signal to the display area.

[0173] In an exemplary embodiment, the pixel driving circuit in the display area includes a first scan signal line S1, a second scan signal line S2, and a third scan signal line S3. The level conversion circuit 300 and the row drive enhancement circuit 400 constitute an output circuit. The output circuit may include three output sub-circuits. Each sub-output circuit may include a level converter and a row drive enhancer. One output sub-circuit is connected to the first scan signal line S1 of a pixel row in the display area and is configured to output a first scan signal to the display area. Another output sub-circuit is connected to the second scan signal line S2 of a pixel row in the display area and is configured to output a second scan signal to the display area. Still another output sub-circuit is connected to the third scan signal line S3 of a pixel row in the display area and is configured to output a third scan signal to the display area.

[0174] In an exemplary embodiment, the first scan signal may be referred to as a write switch (WS) signal, configured to control the on / off switching of a first transistor T1 in a pixel driving circuit. The second scan signal may be referred to as a display switch (DS) signal, configured to control the on / off switching of a second transistor T2 in the pixel driving circuit. The third scan signal may be referred to as a display reset signal (Auto Zero, AZ) signal, configured to control the on / off switching of a fourth transistor T4 in the pixel driving circuit.

[0175] In an exemplary embodiment, since signals such as the start signal and the clock signal are output by the display driver circuit, their voltage domains are inconsistent with the voltage domain of the pixel driver circuit. By converting the level converter in the level conversion circuit 300, the required voltage (0V to -2V & -5V) is introduced, thereby ensuring that the voltage of the output gate drive signal matches that of the pixel driver circuit.

[0176] In an exemplary embodiment, the start signal STV may be referred to as a frame start signal, with a period of one frame, and the clock signal CKV may be referred to as a row driving clock signal, with a period of one row.

[0177] In an exemplary embodiment, the logic operation circuit 200 may include at least a first operation circuit, a second operation circuit, and a third operation circuit, the first operation circuit being configured to generate a write switch signal WS, the second operation circuit being configured to generate a display switch signal DS, and the third operation circuit being configured to generate a display reset signal AZ.

[0178] FIG7 is a diagram illustrating the working principle of a first arithmetic circuit according to an exemplary embodiment of the present disclosure. The first arithmetic circuit may include nine components, namely four inverters (INVX), three NOR gates (NOR), one NAND gate (NAND), and one two-way selector (MUX2). As shown in FIG7 , the first arithmetic circuit may include a first NAND gate 301, a first inverter 401, a second inverter 402, a third inverter 403, a fourth inverter 404, a first NOR gate 501, a second NOR gate 502, a third NOR gate 503, and a two-way selector 510.

[0179] In an exemplary embodiment, a first input terminal of the first NAND gate 301 is connected to the second input terminal B_Qn of the logic operation circuit, a second input terminal of the first NAND gate 30 is connected to the third input terminal C_Qn of the logic operation circuit, an output terminal of the first NAND gate 301 is connected to the input terminal of the first inverter 401, an output terminal of the first inverter 401 is connected to the first input terminal of the first NOR gate 501, a second input terminal of the first NOR gate 501 is connected to the first input terminal IN_A_Qn_ of the logic operation circuit, an output terminal of the first NOR gate 501 is connected to the input terminal of the second inverter 402, an output terminal of the second inverter 402 is connected to the first input terminal of the second NOR gate 502, a second input terminal of the second NOR gate 502 is connected to the clock signal terminal CKV4 of the logic operation circuit, an output terminal of the second NOR gate 502 is connected to the input terminal of the fourth inverter 404, and an output terminal of the fourth inverter 404 is connected to the second input terminal of the two-way selector 510. The input of the third inverter 403 is connected to the second reset terminal IN_LF_pulse2 of the logic operation circuit. The output of the third inverter 403 is connected to the second input terminal of the third NOR gate 503. The first input of the third NOR gate 503 is connected to the first reset terminal IN_LF_pulse1 of the logic operation circuit. The output of the third NOR gate 503 is connected to the control terminal of the two-way selector 510. The first input of the two-way selector 510 is connected to the input terminal IN_A_Qn of the inverted first input signal of the logic operation circuit. The output of the two-way selector 510 serves as the output terminal of the first operation circuit (which can serve as the write switch signal terminal WSn of the logic operation circuit) and is connected to the input terminal of a level shifter (e.g., the first level shifter) to output the write switch signal WSn to the level shifter.

[0180] In an exemplary embodiment, the first operation circuit operates as follows: the first NAND gate 301 and the first inverter 401 perform an AND operation on the second input signal B_Qn at the second input terminal IN_B_Qn and the third input signal C_Qn at the third input terminal IN_C_Qn. The first NOR gate 501 and the second inverter 402 perform an OR operation on the AND operation result and the first input signal A_Qn_ at the first input terminal IN_A_Qn_. The second NOR gate 502 and the fourth inverter 404 perform an OR operation on the OR operation result and the fourth clock signal CKV4 at the fourth clock signal terminal IN_CKV4, i.e., F1 = B_Qn & C_Qn + A_Qn_ + CKV4. The third inverter 403 inverts the second reset signal at the second reset terminal LF_pulse2. The third NOR gate 503 performs a NOR operation on the inverted result and the first reset signal at the first reset terminal LF_pulse1, i.e., F2 serves as a control signal of the two-way selector 510. When F2=1, the output end of the two-way selector 510 outputs A_Qn (ie, the inverted signal of the first input signal A_Qn_); when F2=0, the output end of the two-way selector 510 outputs F1.

[0181] FIG8 is a schematic diagram of the working principle of a second arithmetic circuit according to an exemplary embodiment of the present disclosure. The second arithmetic circuit may include nine parts, each of which is composed of six inverters, one NOR gate, one NAND gate, and one latch (D-Latch). As shown in FIG8 , the second arithmetic circuit may include a second NAND gate 302, a fifth inverter 405, a sixth inverter 406, a seventh inverter 407, an eighth inverter 408, a ninth inverter 409, a tenth inverter 410, a fourth NOR gate 504, and a latch 520.

[0182] In an exemplary embodiment, an input terminal of the fifth inverter 405 is connected to a write switch signal terminal WSn of the logic operation circuit, an output terminal of the fifth inverter 405 is connected to an input terminal of the sixth inverter 406, an output terminal of the sixth inverter 406 is connected to an input terminal of the seventh inverter 407, an output terminal of the seventh inverter 407 is connected to an input terminal of the eighth inverter 408, an output terminal of the eighth inverter 408 is connected to an input terminal of the ninth inverter 409, an output terminal of the ninth inverter 409 is connected to an input terminal of the tenth inverter 410, an output terminal of the tenth inverter 410 is connected to an enable signal terminal EN of a latch 520, and an input terminal of the latch 520 is connected to a second input terminal IN_B_Q of the logic operation circuit. n, the output of the latch 520 is connected to the second input of the fourth NOR gate 504, the first input of the fourth NOR gate 504 is connected to the duty control terminal IN_D_Qn of the logic operation circuit, the output of the fourth NOR gate 504 is connected to the first input of the second NAND gate 302, the second input of the second NAND gate 302 is connected to the second reset terminal LF_pulse2 of the logic operation circuit, and the output of the second NAND gate 302 serves as the output terminal OUT_DS of the second operation circuit and the display switch signal terminal OUT_DSn, and is connected to the display switch control terminal DS of the at least one pixel driving circuit, outputting the display switch signal to the display switch control terminal DS of the at least one pixel driving circuit. In an exemplary embodiment, the output of the second NAND gate 302 can be connected to the input of another level shifter (e.g., a second level shifter), outputting the display switch signal DSn to the level shifter. The level shifter performs level shifting on the display switch signal DSn and outputs it to the corresponding row driver booster (e.g., the second row driver booster). After the row driver booster performs signal amplification, the signal is output to the display switch control terminal of the corresponding pixel driving circuit.

[0183] In an exemplary embodiment, the operating principle of the second operation circuit is as follows: the fifth inverter 405 to the tenth inverter 410 delay the signal written to the switch signal terminal OUT_WSn and then input it to the enable signal terminal EN of the latch 520, which serves as the enable signal of the latch 520. The second input signal of the second input terminal IN_B_Qn of the logic operation circuit serves as the input signal of the latch 520. When the enable signal at the enable signal terminal EN is low, the output of the latch 520 remains unchanged. When the enable signal at the enable signal terminal EN is high, the output of the latch 520 changes with the second input signal. Subsequently, the fourth NOR gate 504 performs a NOR operation on the duty control signal D_Qn at the duty control terminal IN_D_Qn and the signal at the first output terminal OUT_Q of the latch 520. The second NAND gate 302 performs a NAND operation on the NOR operation result and the second reset signal at the second reset terminal LF_pulse2. The logical expression is: Where Q is the output signal of latch 520 (when the enable signal EN input to the enable signal terminal of latch 520 is high, Q = B_Qn; when the enable signal EN input to the enable signal terminal of latch 520 is low, the signal output from output terminal Q remains the original output signal; under normal operation, the enable signal EN input to the enable signal terminal of latch 520 is high, Q = B_Qn). LF_pulse2 is the reset signal. Under normal operation, LF_pulse2 = 1, and DSn = D_Qn + Q. When a global reset is required, LF_pulse2 = 0, and the output signal DSn of the second arithmetic circuit is high (i.e., DSn = 1). D_Qn is the emission duty control signal. When the emission duty is 100%, D_Qn remains low, and DSn = Q. To adjust the emission duty, the duty cycle of D_Qn can be adjusted.

[0184] As shown in FIG9a, a working principle diagram of a latch 520 according to an exemplary embodiment of the present disclosure is shown. The latch 520 includes one inverter and four NAND gates. As shown in FIG9b, the latch 520 includes a twenty-first NAND gate 521, a twenty-second NAND gate 522, a twenty-third NAND gate 523, a twenty-fourth NAND gate 524, and a twenty-fifth inverter 525. The first input terminal of the twenty-first NAND gate 521 is connected to the second input terminal B_Qn of the logic operation circuit, the second input terminal of the twenty-first NAND gate 521 is connected to the enable signal terminal EN, the output terminal of the twenty-first NAND gate 521 is connected to the first input terminal of the twenty-second NAND gate 522, and the second input terminal of the twenty-second NAND gate 522 is connected to the second input terminal of the latch 520. The output terminal OUT_Q_ is connected, and the output terminal of the twenty-second NAND gate 522 serves as the first output terminal Q of the latch 520; the input terminal of the twenty-fifth inverter 525 is connected to the second input terminal IN_B_Qn of the logic operation circuit, the output terminal of the twenty-fifth inverter 525 is connected to the first input terminal of the twenty-third NAND gate 523, the second input terminal of the twenty-third NAND gate 523 is connected to the enable signal terminal EN, the output terminal of the twenty-third NAND gate 523 is connected to the second input terminal of the twenty-fourth NAND gate 524, the first input terminal of the twenty-fourth NAND gate 524 is connected to the first output terminal OUT_Q of the latch 520, and the output terminal of the twenty-fourth NAND gate 524 serves as the second output terminal OUT_Q_ of the latch 520. As shown in Figure 9c, it is a working timing diagram of the latch provided in an embodiment of the present disclosure (the horizontal axis in Figure 9c is time, the unit is microseconds; the vertical axis is voltage, the unit is volt V); in Figure 9b, the signal of the first node B1 is the result of the NAND operation obtained by performing a NAND operation on the second input signal B_Qn and the enable signal EN, the signal of the second node B2 is the result of the NAND operation obtained by performing a NAND operation on the second input signal B_Qn after being inverted by the inverter and the enable signal EN, the output signal Q is the result of the NAND operation obtained by performing a NAND operation on the signal of the first node B1 and the signal of the output terminal OUT_Q_, and the output signal Q_ is the result of the NAND operation obtained by performing a NAND operation on the signal of the second node B2 and the signal of the output terminal Q.

[0185] As shown in FIG9b , in the first stage t1, the enable signal EN is a high-level signal and the second input signal B_Qn is a low-level signal. The signal of the first node B1 obtained by performing a NAND operation on the enable signal EN and the second input signal B_Qn is a high-level signal. The signal of the second node B2 obtained by performing a NAND operation on the second input signal B_Qn after inverting the second input signal B_Qn and performing a NAND operation on the enable signal EN is a low-level signal. The signal of the second node B2 and the signal of the first output terminal OUT_Q obtained by performing a NAND operation on the second output terminal OUT_Q is a high-level signal. Since the signals of the first node B1 and the second output terminal OUT_Q_ are both high-level, the signal of the first output terminal OUT_Q obtained by performing a NAND operation on the signal of the first node B1 and the signal of the second output terminal OUT_Q_ is a low-level signal. In the second stage t2, the enable signal EN is a low-level signal and the second input signal B_Qn changes from a low-level signal to a high-level signal. Since the enable signal EN is a low-level signal, the first node B1 and the second node B2 are both high-level signals. The first output terminal OUT_Q maintains the low level of the previous stage, and the second output terminal OUT_Q_ maintains the high level signal of the previous stage; in the third stage t3, the enable signal EN and the second input signal B_Qn are both high level signals, the first node B1 obtained by performing a NAND operation on the enable signal EN and the second input signal B_Qn is a low level signal, the signal of the first node B1 and the signal of the second output terminal OUT_Q_ are performed a NAND operation to obtain the first output terminal OUT_Q is a high level signal, the second input signal B_Qn is inverted and performed a NAND operation on the enable signal EN to obtain the second node B2 is a high level signal, the second section The second output terminal OUT_Q_ obtained by performing a NAND operation on the signal at point B2 and the signal at the first output terminal OUT_Q is a low-level signal; the timing of the fourth stage t4 and the sixth stage t6 is the same as that of the second stage t2, the timing of the fifth stage t5 and the seventh stage t7 is the same as that of the third stage t3, and the timing of the eighth stage t8 and the tenth stage t10 is the same as that of the first stage t1; in the ninth stage t9 and the eleventh stage t11, the second input signal B_Qn changes from a high-level signal to a low-level signal, and the timing of other signals is the same as that of the second stage t2.

[0186] As can be seen from Figures 9a and 9b, the latch 520 has the following three states in total. The first state: the enable signal EN is at a high level (1), the second input signal B_Qn is a low level signal (0), the signal of the first node B1 is at a high level, the signal of the second node B2 is at a low level, the signal of the second output terminal Q_ is a high level signal, and the signal of the first output terminal OUT_Q is a low level signal (called a latch set 0 operation); the second state: the enable signal EN is at a low level (0), the second input signal B_Qn is any signal (high level or low level), the first node B 1 and the signals of the second node B2 are both high level, the second output terminal OUT_Q_ and the first output terminal Q maintain the original output signal and do not change with the change of the second input signal B_Qn (called the holding stage, the stage of latching 1-bit binary number); the third state: the enable signal EN is high level (1), the second input signal B_Qn is a high level signal (1), the signal of the first node B1 is low level, the signal of the second node B2 is high level, the signal of the first output terminal Q is a high level signal (latch set 1 stage), and the signal of the second output terminal OUT_Q_ is a low level signal.

[0187] The D latch 520 in FIG8 primarily functions to prevent the high level of the display switch signal DSn from enclosing the first low level of the write switch signal WSn (i.e., the first low level of the write switch signal WSn at least partially overlaps with the high level of the display switch signal DSn). If the high level of the display switch signal DSn shifts forward to enclose the first low level of the write switch signal WSn, the time for writing the first power supply voltage at the second node N2 of the pixel driver circuit and the time for writing the bias voltage Vofs at the first node N1 of the pixel driver circuit will be shortened, resulting in incomplete initialization. If the first low level of the write switch signal WSn shifts backward to enclose the high level of the display switch signal DSn, the self-discharge time of the pixel driver circuit will be shortened, resulting in inaccurate threshold voltage readings. The D latch 520 operates normally only when the enable signal EN input to the enable signal terminal EN of the latch 520 is at a high level (i.e., EN=1). If the enable signal at the enable signal terminal EN is not at a high level (e.g., EN=0), the latch state is indeterminate, and the signal output from the first output terminal Q of the latch 520 is indeterminate.

[0188] Figure 10 is a schematic diagram illustrating the operation principle of a third arithmetic circuit according to an exemplary embodiment of the present disclosure. The third arithmetic circuit may include two components: a NOR gate and a NAND gate. As shown in Figure 9 , the third arithmetic circuit may include a fifth NOR gate 505 and a third NAND gate 303.

[0189] In an exemplary embodiment, a first input terminal of the fifth NOR gate 505 is connected to the third input terminal C_Qn of the logic operation circuit, a second input terminal of the fifth NOR gate 505 is connected to the second input terminal B_Qn of the logic operation circuit, a third input terminal of the fifth NOR gate 505 is connected to the duty control terminal D_Qn of the logic operation circuit, an output terminal of the fifth NOR gate 505 is connected to the first input terminal of the third NAND gate 303, a second input terminal of the third NAND gate 303 is connected to the second reset terminal LF_pulse2 of the logic operation circuit, and an output terminal of the third NAND gate 303 serves as the output terminal OUT_AZ of the third operation circuit and as the display reset signal terminal AZn of the logic operation circuit, and is connected to the display reset control terminal AZ in at least one pixel driving circuit, and outputs a display reset signal to the display reset control terminal AZ in the at least one pixel driving circuit. In an exemplary embodiment, the output end of the third NAND gate 303 can be connected to the input end of another level converter (e.g., a third level converter), and a display reset signal is output to the level converter. The level converter converts the display reset signal into a voltage domain and outputs the signal to a corresponding row driver enhancer (e.g., a third row driver enhancer). The row driver enhancer enhances the converted signal and outputs the signal to a display reset control terminal AZ in a corresponding pixel driver circuit.

[0190] In an exemplary embodiment, the operating principle of the third operation circuit is as follows: the fifth NOR gate 505 performs a NOR operation on the third input signal of the third input terminal IN_C_Qn, the second input signal of the second input terminal IN_B_Qn, and the duty control signal of the duty control terminal IN_D_Qn, and the third NAND gate 303 performs a NAND operation on the NOR operation result and the second reset signal of the second reset terminal IN_LF_pulse2. The logical expression thereof is: Among them, LF_pulse2 is the initialization signal, which maintains a high level under normal working conditions (i.e., LF_pulse2=1), then AZn=B_Qn+C_Qn+D_Qn. When LF_pulse2 is a low level (i.e., LF_pulse2=0), then AZn=1, and AZn outputs a high level. When the luminous time accounts for 100%, D_Qn remains at a low level, then AZn=B_Qn+C_Qn. When it is necessary to adjust the luminous time proportion, it can be done by adjusting the duty cycle of D_Qn. That is, the duty cycle control signal of the duty cycle control terminal D_Qn can simultaneously affect the write switch signal DSn and the display reset signal AZn, and the write switch signal DSn and the display reset signal AZn can be simultaneously controlled by the duty cycle control signal of the duty cycle control terminal D_Qn, thereby adjusting and controlling the luminous time proportion of the luminous stage.

[0191] FIG11 is a diagram illustrating the working principle of a level converter according to an exemplary embodiment of the present disclosure. As shown in FIG11 , the level converter may include an eleventh inverter 411 , a first P-type field effect transistor 501P, a second P-type field effect transistor 502P, a first N-type field effect transistor 501N, and a second N-type field effect transistor 502N.

[0192] In an exemplary embodiment, the input terminal IN_shifter of the level converter is respectively connected to the input terminal of the eleventh inverter 411 and the gate electrode of the first P-type field effect transistor 501P (wherein, the input terminal of the second level converter is electrically connected to the display switch signal terminal OUT_DSn in the logic operation circuit, and the input terminal of the third level converter is electrically connected to the display reset signal terminal AZ in the path operation circuit), the output terminal of the eleventh inverter 411 is connected to the gate electrode of the second P-type field effect transistor 502P, and the first electrode of the first P-type field effect transistor 501P and the first electrode of the second P-type field effect transistor 502P are both connected to the first power supply The first power supply line VDD is connected to the first P-type field effect transistor 501P. The second electrode of the first P-type field effect transistor 501N is connected to the second electrode of the first N-type field effect transistor 501N, the gate electrode of the second N-type field effect transistor 502N, and the second output terminal OUT_B_shifter of the level shifter. The second electrode of the second P-type field effect transistor 502P is connected to the gate electrode of the first N-type field effect transistor 501N, the second electrode of the second N-type field effect transistor 502N, and the first output terminal OUT_shifter of the level shifter. The first electrode of the first N-type field effect transistor 501N and the first electrode of the second N-type field effect transistor 502N are both connected to the second power supply line VSS. The first output terminal of the second level shifter is electrically connected to the first input terminal of the second row driver booster; the second output terminal of the second level shifter is electrically connected to the second input terminal of the second row driver booster; the first output terminal of the third level shifter is electrically connected to the first input terminal of the third row driver booster; and the second output terminal of the third level shifter is electrically connected to the second input terminal of the third row driver booster.

[0193] In an exemplary embodiment, the operating principle of the level shifter is as follows: when the input signal at the input terminal IN_shifter of the level shifter is at a low level, the first P-type field-effect transistor 501P is turned on, the second P-type field-effect transistor 502P is turned off, the output signal at the second output terminal OUT_B_shifter of the level shifter is the signal of the first power line VDD, the second N-type field-effect transistor 502N is turned on, the output signal at the first output terminal OUT_shifter of the level shifter is the signal of the second power line VSS, and the first N-type field-effect transistor 501N is turned off. When the input signal at the input terminal IN_shifter of the level shifter is at a high level, the first P-type field-effect transistor 501P is turned off, the second P-type field-effect transistor 502P is turned on, the output signal at the first output terminal OUT_shifter of the level shifter is the signal of the first power line VDD, the first N-type field-effect transistor 501N is turned on, the output signal at the second output terminal OUT_B_shifter of the level shifter is the signal of the second power line VSS, and the second N-type field-effect transistor 502N is turned off.

[0194] FIG12 is a schematic diagram illustrating the operating principle of a row driver enhancer according to an exemplary embodiment of the present disclosure. As shown in FIG12 , the row driver enhancer may include a fourth NAND gate 304, a fifth NAND gate 305, a first transmission gate 201, a twelfth inverter 412, a third P-type field effect transistor 503P, and a third N-type field effect transistor 503N. The third P-type field effect transistor 503P and the third N-type field effect transistor 503N have a relatively large width-to-length ratio to improve driving capability. The row driver enhancer can enhance the driving capability of a signal. The signal enhanced by the row driver enhancer can enhance the driving capability and can be suitable for driving an entire row of pixel driver circuits. In an exemplary embodiment, the enable signal input terminal IN_EN in FIG12 can be electrically connected to the reset control circuit 10-3 in FIG6 d and configured to receive a reset control signal from the reset control circuit 10-3. The reset control circuit 10-3 may include a NAND gate and an inverter, wherein the two input terminals of the NAND gate are respectively connected to the reset control terminal and the reset terminal, the output terminal of the NAND gate is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the enable signal input terminal IN_EN in the row driver enhancer.

[0195] In an exemplary embodiment, a first input terminal IN_driver of the row driver booster is connected to a first input terminal of a fourth NAND gate 304, an enable signal terminal EN of the row driver booster is connected to a second input terminal of the fourth NAND gate 304, an output terminal of the fourth NAND gate 304 is connected to an input terminal of the first transmission gate 201, an output terminal of the first transmission gate 201 is connected to a gate electrode of a third P-type field effect transistor 503P, and a first electrode of the third P-type field effect transistor 503P is connected to a first power supply line VDD. A second input terminal IN_B_driver of the row driver booster is connected to a first input terminal of a fifth NAND gate 305, an enable signal EN of the row driver booster is connected to a second input terminal of the fifth NAND gate 305, an output terminal of the fifth NAND gate 305 is connected to an input terminal of a twelfth inverter 412, an output terminal of the twelfth inverter 412 is connected to a gate electrode of a third N-type field effect transistor 503N, and a first electrode of the third N-type field effect transistor 503N is connected to a second power supply line VSS. The second electrode of the third P-type field-effect transistor 503P and the second electrode of the third N-type field-effect transistor 503N are connected to the output terminal OUT_driver of the row driver booster. The first transmission gate 201 and the twelfth inverter 412 have active-high enable terminals connected to the first power line VDD, and active-low enable terminals connected to the second power line VSS. The fourth NAND gate 304 and the fifth NAND gate 305 have active-high enable terminals connected to the first power line VDD, and active-low enable terminals connected to the ground line GND. In an exemplary embodiment, the output terminal of the second row driver booster is electrically connected to the display switch control terminal DS of the corresponding pixel driver circuit, and the output terminal of the third row driver booster is electrically connected to the display reset control terminal AZ of the corresponding pixel driver circuit.

[0196] In an exemplary embodiment, when the enable signal input to the enable signal terminal IN_EN of the row driver booster is a first level signal, the row driver booster is in a high-impedance state. This satisfies the requirement that, when the gate driver circuit is bilaterally driven (i.e., the gate driver circuit is located on both sides of the display area of ​​the display substrate), the enable signal input to the enable signal terminal of the row driver booster located on one side of the display area is set to the first level, so that the modified row driver booster is in a high-impedance state, thereby achieving unilateral driving of the gate driver circuit. That is, when gate driver circuits are provided on both sides of the display area, the high-impedance state of the row driver booster can achieve unilateral driving of the gate driver circuit (the row driver booster on one side of the display area is in a high-impedance state) or bilateral driving (the row driver boosters on both sides of the display area are not in a high-impedance state).

[0197] In an exemplary embodiment, the first level of the enable signal input to the enable signal terminal EN of the row driver booster may be a low level, that is, the enable signal is a low level. The embodiments of the present disclosure are not limited thereto. The row driver booster can be configured according to the circuit structure of the row driver booster so that the row driver booster is in a high-impedance state when the enable signal is at the first level.

[0198] In an exemplary embodiment, the row driver booster operates as follows:

[0199] When the enable signal at the enable signal terminal EN is 0, the fourth NAND gate 304 and the fifth NAND gate 305 output 1 (high level). The output of the fourth NAND gate 304 outputs 1 (high level) after passing through the first transmission gate 201, the third P-type field effect transistor 503P is turned off, and the output of the fifth NAND gate 305 outputs 0 (low level) after passing through the twelfth inverter 412, the third N-type field effect transistor 503N is turned off, and the entire circuit is in a high-impedance state.

[0200] When the enable signal at the enable signal terminal EN is 1, the circuit output is determined by the input signals at the first input terminal IN_driver and the second input terminal IN_B_driver of the row driver enhancer. The input signal at the first input terminal IN_driver and the input signal at the second input terminal IN_B_driver of the row driver enhancer are opposite direction signals. The opposite direction signals mean that the input signal at the first input terminal IN_driver is a high level signal 1, and the input signal at the second input terminal IN_B_driver is a low level signal 0; the input signal at the first input terminal IN_driver is a low level signal 0, and the input signal at the second input terminal IN_B_driver is a high level signal 1.

[0201] When the input signal at the first input terminal IN_driver of the row driver booster is 1 and the input signal at the second input terminal IN_B_driver is 0, the fourth NAND gate 304 outputs 0. The output of the fourth NAND gate 304 is output as 0 after passing through the first transmission gate 201, and the third P-type field effect transistor 503P is turned on. The fifth NAND gate 305 outputs 1. The output of the fifth NAND gate 305 is output as 0 after passing through the twelfth inverter 412, and the third N-type field effect transistor 503N is turned off. The output signal at the output terminal OUT_driver of the row driver booster is the signal of the first power line VDD (high level).

[0202] When the input signal at the first input terminal IN_driver of the row driver booster is 0 and the input signal at the second input terminal IN_B_driver is 1, the fourth NAND gate 304 outputs 1. The output of the fourth NAND gate 304 outputs 1 after passing through the first transmission gate 201, and the third P-type field effect transistor 503P is turned off. The fifth NAND gate 305 outputs 0. The output of the fifth NAND gate 305 outputs 1 after passing through the twelfth inverter 412, and the third N-type field effect transistor 503N is turned on. The output signal at the output terminal OUT_driver of the row driver booster is the signal of the second power line VSS (low level).

[0203] In an exemplary embodiment, when the enable signal at the enable signal terminal EN is 0, the circuit output is in a high-impedance state. When the enable signal at the enable signal terminal EN is 1, the circuit output does not change the logical relationship between the high and low inputs and outputs; the enable signal at the enable signal terminal EN is a high-configuration control signal. In principle, the row driver booster is a buffer with a large width-to-length ratio, resulting in high output current and high drive capability. Furthermore, the row driver booster has low output impedance and strong drive capability.

[0204] In an exemplary embodiment, the input terminal IN_shifter of the level converter can be connected to the output terminal of the logic operation circuit 200, the first output terminal OUT_shifter of the level converter can be connected to the first input terminal IN_driver of the row driver enhancer, the second output terminal OUT_B_shifter of the level converter can be connected to the second input terminal IN_B_driver of the row driver enhancer, and the output terminal OUT_driver of the row driver enhancer can be connected to the scan signal line of the display area.

[0205] In an exemplary embodiment, as shown in Figure 13, which is a circuit schematic diagram of a shift register circuit provided in an exemplary embodiment of the present disclosure, each gate drive circuit may include four triggers (DFF1 to DFF4), and the shift registers in multiple rows of gate drive circuits are cascaded. For example, the first output terminal OUT_A_Qn (which can be used as the output terminal of the inverted signal of the first shift signal, wherein the second output terminal OUT_A_Qn_ can be used as the output terminal of the first shift signal) of the n-th row gate drive circuit is connected to the input terminal IN_A_Dn+1 of the first trigger DFF1 of the n+1-th row gate drive circuit; the first output terminal OUT_A_Qn+1 of the first trigger DFF1 of the n+1-th row gate drive circuit is connected to the input terminal IN_A_Dn of the first trigger DFF1 of the n-th row gate drive circuit. Similarly, the first output terminal OUT_B_Qn (which can serve as the second shift signal output terminal) of the second flip-flop DFF2 of the gate driver circuit in the nth row is connected to the input terminal IN_B_Dn+1 (which can serve as the second signal input terminal) of the second flip-flop DFF2 of the gate driver circuit in the n+1th row; the first output terminal OUT_B_Qn+1 of the second flip-flop DFF2 of the gate driver circuit in the n+1th row is connected to the input terminal IN_B_Dn of the second flip-flop DFF2 of the gate driver circuit in the nth row. The first output terminal OUT_C_Qn (which can serve as the third shift signal output terminal) of the third flip-flop DFF3 of the gate driver circuit in the nth row is connected to the input terminal IN_C_Dn+1 (which can serve as the third signal input terminal) of the third flip-flop DFF3 of the gate driver circuit in the n+1th row; and the first output terminal OUT_C_Qn+1 of the third flip-flop DFF3 of the gate driver circuit in the n+1th row is connected to the input C_Dn of the third flip-flop DFF3 of the gate driver circuit in the nth row. The first output terminal OUT_D_Qn of the fourth trigger DFF4 of the gate driving circuit of the nth row is connected to the input terminal IN_D_Dn+1 of the fourth trigger DFF4 of the gate driving circuit of the n+1th row; the first output terminal OUT_D_Qn+1_ of the fourth trigger DFF4 of the gate driving circuit of the n+1th row is connected to the input terminal IN_D_Dn of the fourth trigger DFF4 of the gate driving circuit of the nth row.

[0206] In an exemplary embodiment, as shown in FIG13 , the logic control circuit 10 in the gate drive circuit may include a forward and reverse scan control circuit, and the forward and reverse scan control circuit may include a forward scan control circuit 10-1 and a reverse scan control circuit 10-2. Each forward and reverse scan control circuit may include a first forward and reverse scan control terminal GSD1 and a second forward and reverse scan control terminal GSD2. In the forward scan control circuit 10-1, the first forward and reverse scan control terminal GSD1 is connected to the first transmission signal terminal GSD_BW, and the second forward and reverse scan control terminal GSD2 is connected to the second transmission signal terminal GSD_FW. In the reverse scan control circuit 10-2, the first forward and reverse scan control terminal GSD1 is connected to the second transmission signal terminal GSD_FW, and the second forward and reverse scan control terminal GSD2 is connected to the second transmission signal terminal GSD_FW. The control terminal GSD2 is connected to the first transmission signal terminal GSD_BW, and the two cascaded triggers can be connected through the forward and reverse scan control circuit. Taking the first trigger as an example: the first output terminal OUT_A_Qn of the first trigger DFF1 of the n-th stage gate drive circuit is connected to the input terminal IN_A_Dn+1 of the first trigger DFF1 of the n+1-th stage gate drive circuit through the forward scan control circuit 10-1; the first output terminal OUT_A_Qn+1 of the first trigger DFF1 of the n+1-th stage gate drive circuit is connected to the input terminal IN_A_Dn (which can be used as the above-mentioned first signal input terminal) of the first trigger DFF1 of the n-th stage gate drive circuit through the reverse scan control circuit 10-2. In the case of forward scanning, the forward scanning control circuit 10-1 (i.e., the first forward and reverse scanning control circuit 10-1) is turned on and scans in the direction from the nth row to the n+1th row (i.e., the forward scanning control circuit 10-1 is turned on and the reverse scanning control circuit 10-2 is turned off by the signal input to the first forward and reverse scanning control terminal GSD1 and the second forward and reverse scanning control terminal GSD2). In the case of reverse scanning, the reverse scanning control circuit 10-2 (i.e., the second forward and reverse scanning control circuit 10-2) is turned on and scans in the direction from the n+1th row to the nth row (i.e., the forward scanning control circuit 10-1 is turned off and the reverse scanning control circuit 10-2 is turned on by the signal input to the first forward and reverse scanning control terminal GSD1 and the second forward and reverse scanning control terminal GSD2). In an exemplary embodiment, the forward and reverse scanning control circuits may be transmission gates.

[0207] In an exemplary embodiment, FIG13 is a diagram illustrating the operating principle of a shift register circuit according to an exemplary embodiment of the present disclosure. The shift register circuit may be composed of a flip-flop (D Flip Flop) as shown in FIG14 . The flip-flop (which may be a D flip-flop) may include nine parts, namely three transmission gates (TG), four inverters (INVX), and two NAND gates (NAND). The inverters may also be referred to as NOT gates. As shown in FIG14 , the flip-flop may include a second transmission gate 202, a third transmission gate 203, a fourth transmission gate 204, a sixth NAND gate 306, a seventh NAND gate 307, a twelfth inverter 412, a thirteenth inverter 413, a fourteenth inverter 414, and a fifteenth inverter 415.

[0208] In an exemplary embodiment, an input terminal of the twelfth inverter 412 is connected to the clock signal terminal IN_CK of the shift register circuit, and an output terminal of the twelfth inverter 412 is connected to the first node CK_. An input terminal of the thirteenth inverter 413 is connected to the first node CK_, and an output terminal of the thirteenth inverter 413 is connected to the second node CK'. A first terminal of the second transmission gate 202 is connected to the input terminal IN_D of the shift register circuit, a second terminal of the second transmission gate 202 is connected to the output terminal of the fourteenth inverter 414 and the first input terminal of the sixth NAND gate 306, respectively, a high-level active enable terminal of the second transmission gate 202 is connected to the first node CK_, and a low-level active enable terminal of the second transmission gate 202 is connected to the second node CK'. A second input terminal of the sixth NAND gate 306 is connected to the reset terminal RN of the shift register circuit. An output terminal of the sixth NAND gate 306 is connected to the input terminal of the fourteenth inverter 414 and the first terminal of the third transmission gate 203, respectively. An active-high enable terminal of the fourteenth inverter 414 is connected to the second node CK′, and an active-low enable terminal of the fourteenth inverter 414 is connected to the first node CK_. A second terminal of the third transmission gate 203 is connected to the input terminal of the fifteenth inverter 415 and the first terminal of the fourth transmission gate 204, respectively. An active-high enable terminal of the third transmission gate 203 is connected to the second node CK′, and an active-low enable terminal of the third transmission gate 203 is connected to the first node CK_. The output end of the fifteenth inverter 415 is connected to the first input end of the seventh NAND gate 307 and the first output end OUT_Q of the shift register circuit, the second end of the fourth transmission gate 204 is respectively connected to the output end of the seventh NAND gate 307 and the second output end OUT_Q_ of the shift register circuit, the high-level effective enable end of the fourth transmission gate 204 is connected to the first node CK_, the low-level effective enable end of the fourth transmission gate 204 is connected to the second node CK', and the second input end of the seventh NAND gate 307 is connected to the reset end RN of the trigger.

[0209] In an exemplary embodiment, the trigger is active on a rising edge. With each rising edge, the output maintains the state of the previous stage input to the input terminal IN_D. RN is the reset signal terminal (or initialization signal terminal). When it is high, the shift register circuit is active. FIG15 shows an operational timing diagram of the trigger shown in FIG14 . In FIG15 , the horizontal axis represents time in microseconds, and the vertical axis represents voltage in volts (V). The operation of the trigger may include the first stage p1 to the sixth stage p6 (the signal input to the initialization signal terminal RN is high during the first stage p1 to the ninth stage p9):

[0210] Phase 1 p1: The input signal at the clock signal terminal CK of the flip-flop is low, the input signal D at the input terminal IN_D of the flip-flop is low, the first node CK_ is high, the second node CK' is low, the second transmission gate 202 and the fourth transmission gate 204 are turned on, and the third transmission gate 203 is turned off. Since the second transmission gate 202 is turned on, the low-level signal at the input terminal IN_D is transmitted to the node A via the second transmission gate 202. Node A (which can be called the third node of the flip-flop) is low, and node D_ (which can be called the fourth node of the flip-flop) is high. Since the third transmission gate 203 is turned off, the node D_' (which can be called the fifth node of the flip-flop) remains high. The output signal Q at the first output terminal OUT_Q of the flip-flop is low. Since the fourth transmission gate 204 is turned on, the high level of node D_' is transmitted to the second output terminal OUT_Q_ of the flip-flop via the fourth transmission gate 204. The output signal Q_ at the second output terminal OUT_Q_ of the flip-flop is high. In the second stage p2, the input signal of the clock signal terminal CK of the trigger is high, the input signal of the input terminal IN_D of the trigger is low, the first node CK_ is low, the second node CK' is high, the second transmission gate 202 and the fourth transmission gate 204 are disconnected, and the third transmission gate 203 is turned on. Since the second transmission gate 202 is disconnected, the low-level signal of the input terminal D cannot be transmitted to the node A through the second transmission gate 202. Node A maintains the low level of the previous stage, and node D_ maintains the high level of the previous stage. Since the third transmission gate 203 is turned on, node The high-level signal of D is transmitted to the node D_' via the third transmission gate 203. The node D_' is at a high level, and the output signal Q of the first output terminal OUT_Q of the trigger is at a low level. Since the fourth transmission gate 204 is disconnected, the high level of the node D_' cannot be transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The low level of the first output terminal OUT_Q of the trigger and the high level of the initial signal terminal RN are NANDed by the seventh NAND gate 307 to obtain a high level. The output signal Q_ of the second output terminal OUT_Q_ of the trigger is at a high level.

[0211] The third stage p3: The working sequence is the same as the first stage p1 and will not be repeated here.

[0212] Phase 4 p4: The input signals of the clock signal terminal CK and the input signal of the input terminal IN_D of the trigger are both high, the first node CK_ is low, the second node CK' is high, the second transmission gate 202 and the fourth transmission gate 204 are disconnected, and the third transmission gate 203 is turned on. Since the second transmission gate 202 is disconnected, the high-level signal D of the input terminal IN_D cannot be transmitted to the node A through the second transmission gate 202. Node A maintains the low level of the previous phase, and node D_ maintains the high level of the previous phase. Since the third transmission gate 203 is turned on, the high level of node D The high-level signal is transmitted to the node D_' via the third transmission gate 203. The node D_' is at a high level, and the output signal Q of the first output terminal OUT_Q of the trigger is at a low level. Since the fourth transmission gate 204 is disconnected, the high level of the node D_' cannot be transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The low level of the first output terminal OUT_Q of the trigger and the high level of the initial signal terminal RN are NANDed by the seventh NAND gate 307 to obtain a high level. The output signal Q_ of the second output terminal OUT_Q_ of the trigger is at a high level.

[0213] Fifth stage p5: The input signal at the clock signal terminal CK of the trigger is low, the input signal at the input terminal IN_D of the trigger is high, the first node CK_ is high, the second node CK' is low, the second transmission gate 202 and the fourth transmission gate 204 are turned on, and the third transmission gate 203 is turned off. Since the second transmission gate 202 is turned on, the high-level signal D at the input terminal IN_D is transmitted to the node A via the second transmission gate 202. Node A is high, and node D_ becomes low. Since the third transmission gate 203 is turned off, node D_' remains high. The output signal Q at the first output terminal OUT_Q of the trigger is low. Since the fourth transmission gate 204 is turned on, the high level of node D_' is transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The output signal Q_ at the second output terminal OUT_Q_ of the trigger is high.

[0214] Phase 6 p6: The input signal of the clock signal terminal CK of the flip-flop and the input signal D of the input terminal OUT_D are both high, the first node CK_ is low, the second node CK' is high, the second transmission gate 202 and the fourth transmission gate 204 are disconnected, and the third transmission gate 203 is turned on. Since the second transmission gate 202 is disconnected, the high-level signal of the input terminal IN_D cannot be transmitted to the node A through the second transmission gate 202. Node A maintains the high level of the previous phase, and node D_ maintains the low level of the previous phase. Since the third transmission gate 203 is turned on, node D_ The low-level signal of the trigger is transmitted to the node D_' via the third transmission gate 203. The node D_' is at a low level, and the output signal Q of the first output terminal OUT_Q of the trigger is at a high level. Since the fourth transmission gate 204 is disconnected, the low level of the node D_' cannot be transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The high level of the first output terminal OUT_Q of the trigger and the high level of the initial signal terminal RN are obtained by the NAND operation of the seventh NAND gate 307 to obtain a low level. The output signal Q_ of the second output terminal OUT_Q_ of the trigger is at a low level.

[0215] Seventh stage p7: the input signal at the clock signal terminal CK of the trigger is low, the input signal D at the input terminal IN_D of the trigger is high, the first node CK_ is high, the second node CK' is low, the second transmission gate 202 and the fourth transmission gate 204 are turned on, and the third transmission gate 203 is turned off. Since the second transmission gate 202 is turned on, the high-level signal at the input terminal IN_D is transmitted to the node A via the second transmission gate 202. Node A is high, and node D_ is low. Since the third transmission gate 203 is turned off, node D_' remains at its original low level. The output signal Q at the first output terminal OUT_Q of the trigger is high. Since the fourth transmission gate 204 is turned on, the low level at the node D_' is transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The output signal Q_ at the second output terminal OUT_Q_ of the trigger is low.

[0216] The eighth stage p8: The working sequence is the same as that of the sixth stage p6, and will not be repeated here.

[0217] Ninth stage p9: the input signal of the clock signal terminal CK of the trigger is low, the input signal D of the input terminal IN_D of the trigger is low, the first node CK_ is high, the second node CK' is low, the second transmission gate 202 and the fourth transmission gate 204 are turned on, and the third transmission gate 203 is turned off. Since the second transmission gate 202 is turned on, the low-level signal at the input terminal IN_D is transmitted to the node A via the second transmission gate 202. Node A is low, and node D_ is high. Since the third transmission gate 203 is turned off, the node D_' maintains its original low level. The output signal Q of the first output terminal OUT_Q of the trigger is high. Since the fourth transmission gate 204 is turned on, the low level of the node D_' is transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The output signal Q_ of the second output terminal OUT_Q_ of the trigger is low.

[0218] Combining the first stage p1 to the ninth stage p9, the working principle of the trigger is:

[0219] (1) When the input signal of the clock signal terminal CK of the trigger is at a low level and the input signal D of the input terminal IN_D of the trigger is at a low level, the second transmission gate 202 is turned on, the third transmission gate 203 is turned off, and the fourth transmission gate 204 is turned on. The node A is a low level signal, the node D_ is a high level signal, the output signal Q of the first output terminal OUT_Q of the trigger maintains the original level signal (for example, a low level), and the output signal Q_ of the second output terminal OIT_Q_ of the trigger maintains the original level signal (for example, a high level).

[0220] (2) When the input signal of the clock signal terminal CK of the trigger is at a high level and the input signal D of the input terminal IN_D of the trigger is at a low level, the second transmission gate 202 is disconnected, the third transmission gate 203 is turned on, and the fourth transmission gate 204 is disconnected. Node A and node D_ maintain their original potentials. When node A is originally a low-level signal and node D_ is originally a high-level signal, the output of the first output terminal OUT_Q of the trigger is low-level, and the output of the second output terminal OUT_Q_ of the trigger is high-level; when node A is originally a high-level signal and node D_ is originally a low-level signal, the output signal Q of the first output terminal OUT_Q of the trigger is high-level, and the output signal Q_ of the second output terminal OUT_Q_ of the trigger is low-level.

[0221] (3) When the input signal of the clock signal terminal CK of the trigger is at a low level and the input signal of the input terminal IN_D of the trigger is at a high level, the second transmission gate 202 is turned on, the third transmission gate 203 is turned off, and the fourth transmission gate 204 is turned on. Node A is a high-level signal, and node D_ is a low-level signal. The signal after the third transmission gate 203 is latched (i.e., the signal from node D_' to the first output terminal OUT_Q and the second output terminal OUT_Q_ is latched), and the output is maintained (i.e., the output signal Q of the first output terminal OUT_Q of the trigger and the output signal Q_ of the second output terminal OUT_Q_ of the trigger maintain their original levels);

[0222] (4) When the input signal of the clock signal terminal CK of the trigger is at a high level and the input signal of the input terminal IN_D of the trigger is at a high level, the second transmission gate 202 is disconnected, the third transmission gate 203 is turned on, and the fourth transmission gate 204 is disconnected. Node A and node D_ maintain their original potentials. When node A is originally a low-level signal and node D_ is originally a high-level signal, the output of the first output terminal OUT_Q of the trigger is low-level, and the output of the second output terminal OUT_Q_ of the trigger is high-level; when node A is originally a high-level signal and node D_ is originally a low-level signal, the output signal Q of the first output terminal OUT_Q of the trigger is high-level, and the output signal Q_ of the second output terminal OUT_Q_ of the trigger is low-level.

[0223] In an exemplary embodiment, the function of the first flip-flop DFF1 is to shift the first signal A_Dn input to the first signal input terminal IN_A_Dn (the shift clock signal is CKV1), the function of the second flip-flop DFF2 is to shift the second signal B_Dn input to the second signal input terminal IN_B_Dn (the shift clock signal is CKV2), the function of the third flip-flop DFF3 is to shift the third signal C_Dn input to the third signal input terminal IN_C_Dn (the shift clock signal is CKV3), and the function of the fourth flip-flop DFF4 is to shift the fourth signal D_Dn input to the fourth signal input terminal IN_D_Dn (the shift clock signal is CKV5), thereby providing an initial signal for the logic operation circuit 200.

[0224] In an exemplary embodiment, under normal circumstances, the display image is displayed in a display area located in the center of the display substrate. The position of the display area (i.e., the position of the displayed image) is generally fixed. In actual products, the image may be mechanically blocked due to alignment issues, or pixel-level alignment may be required during assembly, requiring the displayed image to be moved. While maintaining the resolution of the displayed image, at least one of the rows and columns may need to be added. Combined with the configuration of the shift register circuit 100, the function of moving the displayed image position can be referred to as the Orbit function. The vertical Orbit function (moving the displayed image in the column direction Y) can be implemented through the addressing configuration of the gate driver circuit, and the horizontal Orbit function (moving the displayed image in the row direction X) can be implemented through the configuration of the data driver circuit.

[0225] As shown in Figures 16a to 16d, the multi-stage cascaded gate drive circuit may include an m-stage intermediate gate drive circuit G100 and a 4S+2-stage offset gate drive circuit. In the direction of the multi-stage gate drive circuit cascade, the 4S+2-stage offset gate drive circuit may include a 2S+1-stage first-type offset gate drive circuit G101 located on one side of the m-stage intermediate gate drive circuit G100, and a 2S+1-stage second-type offset gate drive circuit G102 located on the other side of the multi-stage intermediate gate drive circuit G100; the 2S+1-stage first-type offset gate drive circuit G101 may include a first offset gate drive circuit G1011 on the first side of the S stage (which may include Orbit1 to OrbitS) and a second offset gate drive circuit G1012 on the first side of the S+1 stage (which may include Orbit0, Orbit-1 to Orbit-S). The first offset gate drive circuit G1011 on the first side of the S stage is located away from the second offset gate drive circuit G1012 on the first side of the S+1 stage. The 2S+1-level second-type offset gate driver circuit G102 may include a first offset gate driver circuit G1021 on the second side of the S-level (which may include Orbit-1 to Orbit-S) and a second offset gate driver circuit G1022 on the second side of the S+1-level (which may include Orbit0, Orbit1 to OrbitS). The first offset gate driver circuit G1021 on the second side of the S-level is located on the side of the second offset gate driver circuit G1012 on the second side of the S+1-level away from the m-level intermediate gate driver circuit G100. FIG16a shows a structural schematic diagram of the 2S+1-level first-type offset gate driver circuit G101, FIG16b shows a structural schematic diagram of the 2S+1-level second-type offset gate driver circuit G102, FIG16c shows a structural schematic diagram of the m-level intermediate gate driver circuit G100, and FIG16d shows a structural schematic diagram of the m-level intermediate gate driver circuit G100 and the 4S+2-level offset gate driver circuit.

[0226] As shown in Figures 16a to 16d, in the direction of the cascade of the multi-stage gate driving circuit, the display area may include m intermediate normal display rows and 2S+1 offset display rows on the first side located on one side of the m intermediate normal display rows, and 2S+1 offset display rows on the second side located on the other side of the m intermediate normal display rows. The 2S+1 offset display rows on the first side may include S first offset display rows on the first side and S+1 second offset display rows on the first side, and the S first offset display rows on the first side are located on the side of the S+1 second offset display rows on the first side away from the m intermediate normal display rows; the 2S+1 offset display rows on the second side may include S first offset display rows on the second side and S+1 second offset display rows on the second side, and the S first offset display rows on the second side are located on the side of the S+1 second offset display rows on the second side away from the m intermediate normal display rows.

[0227] In the direction of the cascade of the multi-stage gate driving circuit, the m-stage intermediate gate driving circuit G100 is electrically connected to the m intermediate normal display rows located in the display area, the first offset gate driving circuit G1011 on the first side of the S-stage is electrically connected to the S first offset display rows on the first side, and the second offset gate driving circuit G1012 on the first side of the S+1-stage is electrically connected to the S+1 second offset display rows on the first side; the first offset gate driving circuit G1021 on the second side of the S-stage is electrically connected to the S first offset display rows on the second side, and the second offset gate driving circuit G1022 on the second side of the S+1-stage is electrically connected to the S+1 second offset display rows on the second side. The display rows may be pixel rows in the display area, and at least some of the pixel rows may include multiple pixel driving circuits arranged along the row direction.

[0228] As shown in FIG16a to FIG16c, at least part of the gate driving circuit may include a shift register circuit 100, and the shift register circuits 100 in the multi-stage gate driving circuit may be connected in cascade, wherein the multi-stage shift register circuit 100 may include an m-stage intermediate shift register circuit P100 located in the m-stage intermediate gate driving circuit G100, an offset shift register circuit P101 located on the first side of the 2S+1 stage in the 2S+1 first-type offset gate driving circuit G101, and an offset shift register circuit P102 located on the second side of the 2S+1 stage in the 2S+1 second-type offset gate driving circuit G102; and an offset shift register circuit P101 located on the first side of the 2S+1 stage. 1 may include a first offset shift register circuit P1011 on the first side of the S stage in the first offset gate driver circuit G1011 located on the first side of the S stage, and a second offset shift register circuit P1012 on the first side of the S+1 stage in the second offset gate driver circuit G1012 located on the first side of the S+1 stage; 2The offset shift register circuit P102 on the second side of the S+1 stage may include a first offset shift register circuit P1021 on the second side of the S stage in the first offset gate driver circuit G1021 located on the second side of the S stage, and a second offset shift register circuit P1022 on the second side of the S+1 stage in the second offset gate driver circuit G1022 located on the second side of the S+1 stage.

[0229] In an exemplary embodiment, the m-level intermediate gate drive circuit G100 is not limited to that shown in FIG16c, and may be as shown in FIG6d; in the m-level intermediate shift register circuit P100, a forward and reverse scan control circuit may be set between two adjacent shift registers, as shown in FIG13, and the forward and reverse scan control circuit may include a first forward and reverse scan control circuit 10-1 (which may be called a forward scan control circuit) and a second forward and reverse scan control circuit 10-2 (which may be called a reverse scan control circuit), the first forward and reverse scan control circuit 10-1 and the second forward and reverse scan control circuit 10-2 can be connected to the first forward and reverse scan control terminal GSD1 and the second forward and reverse scan control terminal GSD2. In the first forward and reverse scan control circuit 10-1, the first forward and reverse scan control terminal GSD1 is connected to the first transmission signal terminal GSD_BW, and the second forward and reverse scan control terminal GSD2 is connected to the second transmission signal terminal GSD_FW. In the second scan control circuit 10-2, the first forward and reverse scan control terminal GSD1 is connected to the second transmission signal terminal GSD_FW, and the second forward and reverse scan control terminal GSD2 is connected to the first transmission signal terminal GSD_BW. In the case of forward scanning, the signal provided by the first transmission signal terminal GSD_BW is a high-level signal, and the signal provided by the second transmission signal terminal GSD_FW is a low-level signal, the first forward and reverse scanning control circuit 10-1 is turned on, and the second forward and reverse scanning control circuit 10-2 is turned off; in the case of reverse scanning, the signal provided by the first signal transmission terminal GSD_BW is a low-level signal, and the signal provided by the second signal transmission terminal GSD_FW is a high-level signal, the first forward and reverse scanning control circuit 10-1 is turned off, and the second forward and reverse scanning control circuit 10-2 is turned on.

[0230] In an exemplary embodiment, as shown in FIG16 a, the 2S+1-stage first-type offset gate driver circuit G101 may include 2S first-side offset transmission control circuits P10-1, and the offset shift register circuits P101 of the first side of two adjacent stages may be cascade-connected through one of the first-side offset transmission control circuits P10-1. In the direction from the first-type offset gate driver circuit G101 to the second-type offset gate driver circuit G102, in the first-side offset shift register circuits P101 of the two adjacent stages, the input end of the first-side offset transmission control circuit P10-1 is connected to the output end of the first-side offset shift register circuit P101 of the previous stage, and the output end of the first-side offset transmission control circuit P10-1 is connected to the input end of the first-side offset shift register circuit P101 of the next stage; the 2S first-side offset transmission control circuits P10-1 may include S -1 first-side first offset transmission control circuit P10-11, S first-side second offset transmission control circuits P10-12, and 1 first-side third offset transmission control circuit P10-13. Among the S-1 first-side first offset transmission control circuits P10-11, each first-side first offset transmission control circuit P10-11 is located between two adjacent first-side first offset shift register circuits P1011; among the S first-side second offset transmission control circuits P10-12, each first-side second offset transmission control circuit P10-12 is located between two adjacent first-side second offset shift register circuits P1012; and 1 first-side third offset transmission control circuit P10-13 can be located between the first-side first offset gate shift register circuit P1011 and the adjacent first-side second offset shift register circuit P1012.

[0231] In an exemplary embodiment, as shown in FIG16 b , the 2S+1-stage second-type offset gate driver circuit G102 may include 2S second-side offset transmission control circuits P10-2. The second-side offset shift register circuits P102 of two adjacent stages may be cascade-connected via one of the second-side offset transmission control circuits P10-2. In the direction from the second-type offset gate driver circuit G102 to the first-type offset gate driver circuit G101, in the second-side offset shift register circuits P102 of two adjacent stages, the input end of the second-side offset transmission control circuit P10-2 is connected to the output end of the second-side offset shift register circuit P102 of the previous stage, and the output end of the second-side offset transmission control circuit P10-2 is connected to the input end of the second-side offset shift register circuit P102 of the next stage. The 2S second-side offset transmission control circuits P10-2 may include S-1 first offset transmission control circuits P10-21 on the second side, S second offset transmission control circuits P10-22 on the second side, and 1 third offset transmission control circuit P10-23 on the second side. Among the S-1 first offset transmission control circuits P10-11 on the second side, each first offset transmission control circuit P10-21 on the second side is located between the first offset shift register circuits P1021 on the second side of two adjacent levels; among the S second offset transmission control circuits P10-22 on the second side, each second offset transmission control circuit P10-22 on the second side is located between the second offset shift register circuits P1022 on the second side of two adjacent levels; 1 third offset transmission control circuit P10-23 on the first side can be located between the first offset shift register circuit P1021 on the second side and the adjacent second offset shift register circuit P1022 on the second side.

[0232] In an exemplary embodiment, as shown in Figures 16a and 16b, in the 4S+2-level offset gate driver circuit, each level of the offset gate driver circuit may further include a row control circuit 01. In the row control circuit 01, the input terminal is connected to the initial signal terminal IN_STV, the control terminal is connected to the row control terminal, and the output terminal is connected to the input terminal of the corresponding offset shift register circuit. In an exemplary embodiment, the control terminals in the row control circuit 01 may include a first control terminal K1 to a fourth control terminal K4, and the row control terminals may include a first transmission control terminal GSD_BW, a second transmission control terminal GSD_FW, 2S+1 first-type initial row control terminals and 2S+1 second-type initial row control terminals; the 2S+1 first-type initial row control terminals may include S first initial row control terminals IN_Zi, S third initial row control terminals IN_Z_j, and 1 fifth initial row control terminal IN_Z0, and the 2S+1 second-type initial row control terminals may include S second initial row control terminals IN_Zi_, S fourth initial row control terminals IN_Z_j_, and 1 sixth initial row control terminal IN_Z0_, where i ranges from 1 to S, and j ranges from 1 to S. In an exemplary embodiment, the row control circuit 01 may include an initial row control circuit 01-1 and a forward and reverse scan control circuit 01-2, the input terminal of the initial row control circuit 01-1 is connected to the initial signal terminal IN_STV, the first control terminal K1 is electrically connected to the corresponding first-type initial row control terminal, the second control terminal K2 is electrically connected to the corresponding second-type initial row control terminal, and the output terminal is electrically connected to the input terminal of the corresponding forward and reverse scan control circuit 01-2; the input terminal of the forward and reverse scan control circuit 01-2 is electrically connected to the output terminal of the corresponding initial row control circuit 01-1, in the first-type offset gate drive circuit G101, the third control terminal K3 of the forward and reverse scan control circuit 01-2 is electrically connected to the second transmission control terminal GSD_FW, and the fourth control terminal K4 is electrically connected to the first transmission control terminal GSD_BW; in the second-type offset gate drive circuit G102, the third control terminal K3 of the forward and reverse scan control circuit 01-2 is electrically connected to the first transmission control terminal GSD_BW, and the fourth control terminal K4 is electrically connected to the second transmission control terminal GSD_FW. The connection relationship between the control terminal and the row control terminal is as follows:

[0233] In the first offset gate driver circuit G1011 on the first side of the S stage, the S first control terminals K1 are electrically connected to the S first initial row control terminals IN_Zi, respectively, the S second control terminals K2 are electrically connected to the S second initial row control terminals IN_Zi_, the S third control terminals K3 are electrically connected to the second transmission control terminal GSD_FW, and the S fourth control terminals K4 are electrically connected to the first transmission control terminal GSD_BW;

[0234] In the second offset gate driver circuit G1012 on the first side of the S+1 stage, in a second offset gate driver circuit G1012 on the first side adjacent to the first offset gate driver circuit G1011 on the first side of the S stage, the first control terminal K1 is electrically connected to the fifth initial row control terminal IN_Z0, and the second control terminal K2 is electrically connected to the sixth initial row control terminal IN_Z0_; in the second offset gate driver circuit G1012 on the first side of the S stage close to the middle gate driver circuit G100 of the m stage, the S first control terminals K1 are respectively electrically connected to the S third initial row control terminals IN_Z_j, the S second control terminals K2 are respectively electrically connected to the S fourth initial row control terminals IN_Z_j__, the S third control terminals K3 are all electrically connected to the second transmission control terminal GSD_FW, and the S fourth control terminals K4 are all electrically connected to the first transmission control terminal GSD_BW;

[0235] In the first offset gate driver circuit G1021 on the second side of the S stage, the S first control terminals K1 are electrically connected to the S third initial row control terminals IN_Z_j, respectively, the S second control terminals K2 are electrically connected to the S fourth initial row control terminals IN_Z_j, respectively, the S third control terminals K3 are electrically connected to the first transmission control terminal GSD_BW, and the S fourth control terminals K4 are electrically connected to the second transmission control terminal GSD_FW.

[0236] In the second offset gate driver circuit G1022 on the second side of the S+1 level, in a second offset gate driver circuit G1012 on the first side adjacent to the first offset gate driver circuit G1021 on the second side of the S level, the first control terminal K1 is electrically connected to the fifth initial row control terminal IN_Z0, and the second control terminal K2 is electrically connected to the sixth initial row control terminal IN_Z0_; in the second offset gate driver circuit G1022 on the second side of the S level close to the m-level intermediate gate driver circuit G100, the S first control terminals K1 are respectively electrically connected to the S first initial row control terminals IN_Z_i, the S second control terminals K2 are respectively electrically connected to the S second initial row control terminals IN_Z_i__, the S third control terminals K3 are all electrically connected to the first transmission control terminal GSD_BW, and the S fourth control terminals K4 are all electrically connected to the second transmission control terminal GSD_FW.

[0237] In an exemplary embodiment, as shown in Figures 16a and 16b, the offset transmission control circuit P10-1 on the first side and the offset transmission control circuit P10-2 on the second side may include a first forward and reverse scan control terminal GSD1 and a second forward and reverse scan control terminal GSD2. In the offset transmission control circuit P10-1 on the first side, the first forward and reverse scan control terminal GSD1 is electrically connected to the corresponding second-type initial row control terminal, and the second forward and reverse scan control terminal GSD2 is electrically connected to the corresponding first-type initial row control terminal; in the offset transmission control circuit P10-2 on the second side, the first forward and reverse scan control terminal GSD1 is electrically connected to the corresponding first-type initial row control terminal, and the second forward and reverse scan control terminal GSD2 is electrically connected to the corresponding second-type initial row control terminal. For example, in the first offset transmission control circuit P10-11 of the S-1 first side, the first forward and reverse scan control terminal GSD1 is electrically connected to the first to S-1 second initial row control terminals IN_Zi_, and the second forward and reverse scan control terminal GSD2 is electrically connected to the first to S-1 first initial row control terminals IN_Zi; in the second offset transmission control circuit P10-12 of the first first side, the first forward and reverse scan control terminal GSD1 is electrically connected to the sixth initial row control terminal IN_Z0_, and the second forward and reverse scan control terminal GSD2 is electrically connected to the fifth initial row control terminal IN_Z0; in the second offset transmission control circuit P10-12 of the second to S first sides, the first forward and reverse scan control terminal GSD1 is electrically connected to the second to S fourth initial row control terminals IN_Z_j_, and the second forward and reverse scan control terminal GSD2 is electrically connected to the second to S third initial row control terminals IN_Z_j, respectively. connected; in the first offset transmission control circuit P10-21 of the S-1 second side, the first forward and reverse scan control terminal GSD1 is electrically connected to the first to S-1 first initial row control terminals IN_Zi, and the second forward and reverse scan control terminal GSD2 is electrically connected to the first to S-1 second initial row control terminals IN_Zi_; in the second offset transmission control circuit P10-22 of the first second side, the first forward and reverse scan control terminal GSD1 is electrically connected to the fifth initial row control terminal IN_Z0, and the second forward and reverse scan control terminal GSD2 is electrically connected to the sixth initial row control terminal IN_Z0_; in the second offset transmission control circuit P10-22 of the second to S second sides, the first forward and reverse scan control terminal GSD1 is electrically connected to the second to S third initial row control terminals IN_Z_j, and the second transmission control terminal GSD2 is electrically connected to the second to S fourth initial row control terminals IN_Z_j_.

[0238] In an exemplary embodiment, as shown in Figures 16a and 16b, the gate drive circuit may further include an offset row drive enhancement circuit P400, a reset control circuit 10-3 and a reset control terminal Tn; the offset row drive enhancement circuit P400 is located in the corresponding offset gate drive circuit, and in the offset row drive enhancement circuit P400, the input terminal is electrically connected to the output terminal of the corresponding offset shift register circuit, the output terminal is electrically connected to the corresponding pixel drive circuit in the display area, and the enable signal terminal is connected to the corresponding reset control circuit 10-3; in the reset control circuit 10-3, the input terminal is connected to the corresponding reset control terminal IN_Tn, and the output terminal is connected to the enable signal terminal in the corresponding offset row drive enhancement circuit P400, and is configured to receive the reset control signal Tn from the reset control terminal IN_Tn, and under the control of the reset control signal Tn, the corresponding offset row drive enhancement circuit P400 is set to a high impedance state.

[0239] In an exemplary embodiment, in the direction of the 2S+1-level first-class offset gate driver circuit G101 to the m-level intermediate offset gate driver circuit G100, the reset control terminal Tn may include 2S first-class reset control terminals electrically connected to the reset control circuit 10-3 in the first-level first-class offset gate driver circuit to the 2S-level first-class offset gate driver circuit, and 2S second-class reset control terminals electrically connected to the reset control circuit 10-3 in the second-level second-class offset gate driver circuit to the 2S+1-level second-class offset gate driver circuit.

[0240] In an exemplary embodiment, the 2S first-side reset control terminals may include S first-side first reset control terminals and S first-side second reset control terminals. In the direction from the m-level intermediate offset gate driver circuit G100 to the 2S+1-level first-side offset gate driver circuit, the S first-side first reset control terminals may include the first first-side first reset control terminal IN_T1 to the S-th first-side first reset control terminal IN_TS; in the direction from the 2S+1-level first-side offset gate driver circuit to the m-level intermediate offset gate driver circuit G100, the S first-side second reset control terminals may include the first first-side second reset control terminal IN_T0, the second first-side second reset control terminal IN_T_1 to the S-th first-side second reset control terminal IN_T_S-1.

[0241] In an exemplary embodiment, the 2S second-type reset control terminals may include S second-side first reset control terminals and S second-side second reset control terminals. In the direction from the 2S+1-level second-type offset gate driver circuit G102 to the m-level intermediate offset gate driver circuit G100, the S second-side first reset control terminals may include the first second-side first reset control terminal IN_T1_ to the S-th second-side first reset control terminal IN_TS_; in the direction from the m-level intermediate offset gate driver circuit G100 to the 2S+1-level second-type offset gate driver circuit, the S second-side second reset control terminals may include the first second-side second reset control terminal IN_T_0_, the second second-side second reset control terminal IN_T_1_ to the S-th second-side second reset control terminal IN_T_S-1_.

[0242] In an exemplary embodiment, the offset shift register circuit may further include an enable signal terminal, and the output terminal of the reset control circuit 10-3 may further be electrically connected to the enable signal terminal of the corresponding offset shift register circuit, and be configured to receive the reset control signal Tn from the reset control terminal IN_Tn, and under the control of the reset control signal Tn, the corresponding offset shift register circuit is set to a high impedance state.

[0243] In an exemplary embodiment, the row control circuit 01 can be configured to receive an initial row control signal. Under the control of the initial row control signal, one level is selected from the offset shift register circuit P101 on the first side of the 2S+1 level as the first type of initial shift register circuit, and one level is selected from the offset shift register circuit P102 on the second side of the 2S+1 level as the second type of initial shift register circuit. In the direction of the cascade of the multi-stage shift register circuits, the offset direction of the first type of initial shift register circuit and the second type of initial shift register circuit relative to the m-stage intermediate shift register circuit are consistent, and the number of offset levels relative to the multi-stage intermediate shift register circuit is N, where N is an integer, S is a positive integer, and N is less than or equal to S. That is, the row control circuit 01 can be configured to receive an initial row control signal, and under the control of the initial row control signal, select one level from the 2S+1-level first-level offset gate drive circuit G101 as the first-level initial gate drive circuit, and select one level from the 2S+1-level second-level offset gate drive circuit G102 as the second-level initial gate drive circuit; in the direction of the cascade of the multi-level gate drive circuits, the offset direction of the first-level initial gate drive circuit and the second-level initial gate drive circuit relative to the m-level intermediate gate drive circuit is consistent, and the number of offset levels relative to the multi-level intermediate gate drive circuits is N, N is an integer, S is a positive integer, and N is less than or equal to S.

[0244] In an exemplary embodiment, the movement directions of the first type initial shift register circuit and the second type initial shift register circuit can be controlled by a row control circuit, which can solve the technical problem of being unable to display a complete image due to occlusion, or can be applicable to pixel-level alignment.

[0245] In an exemplary embodiment, the row control circuit 01 can be configured to receive a forward and reverse scan control signal from a row control terminal, and an initial signal from an initial signal terminal IN_STV. Under the control of the forward and reverse scan control signal, one of the first type initial shift register circuit and the second type initial shift register circuit is used as the starting row of the shift register circuit, and the other is used as the ending row of the shift register circuit, and an initial signal is provided to the starting row of the shift register circuit. That is, the row control circuit 01 can be configured to receive a forward and reverse scan control signal from a row control terminal, and an initial signal from an initial signal terminal IN_STV. Under the control of the forward and reverse scan control signal, one of the first type initial gate drive circuit and the second type initial gate drive circuit is used as the starting row of the gate drive circuit, and the other is used as the ending row of the gate drive circuit, and an initial signal is provided to the starting row of the gate drive circuit.

[0246] In an exemplary embodiment, S can be 8, 4S+2 can be 34, and 2S+1 can be 17. The 4S+2-level offset gate driver circuit can include a 2S+1 (17)-level first-type offset gate driver circuit G101 and a 2S+1 (17)-level second-type offset gate driver circuit G102. The corresponding display area can include 2S+1 first-side offset display rows electrically connected to the 2S+1 (17)-level first-type offset gate driver circuit G101, and 2S+1 second-side offset display rows electrically connected to the 2S+1 (17)-level second-type offset gate driver circuit G102. That is, under the control of the 4S+2-level (34-level) offset gate driver circuit, the display image in the display area can be shifted upward by 1 to 8 rows, or shifted downward by 1 to 8 rows.

[0247] In an exemplary embodiment, the gate driving device may further include a shift control circuit. As shown in FIG17 , the shift control circuit may include a standard 5-32 decoder 600, an accumulator, and 16 inverters (the sixteenth inverter 416 to the thirty-first inverter 431). The accumulator may include 16 cascade-connected half adders 700 (including the first half adder 701 to the sixteenth half adder 716). The accumulator and the inverter constitute part of the logic operation circuit of the shift control circuit, and the standard 5-32 decoder constitutes the part of the shift control circuit without the logic operation circuit. The shift control circuit may include 5 input terminals and 49 output terminals, wherein the 5 input terminals (the first input terminal A0 to the fifth input terminal A4) may include the input terminals of a standard 5-32 decoder, and the 49 output terminals may include 17 standard decoding result output terminals Y0 to Y16, 16 half adder sum output terminals S0 to S15, and 16 half adder carry output terminals C0 to C15.

[0248] In an exemplary embodiment, as shown in FIG17 , the standard 5-32 decoder utilizes the lower 17 bits of the standard decoding result output terminals Y0 to Y16 to produce the 5-17 decoder shown in FIG17 . The upper 15 bits of the decoding result output terminals Y17 to Y31 of the 5-32 decoder can be expanded to include other functions. As shown in FIG17 , the 16 half adders may include the first half adder 701 to the sixteenth half adder 716 , and the 16 inverters may include the sixteenth inverter 416 to the thirty-first inverter 431 .

[0249] In an exemplary embodiment, FIG18 is a schematic structural diagram of a shift control circuit. The 17 standard decoding result output terminals in FIG17 may include a first standard decoding result output terminal Y0 to a seventeenth standard decoding result output terminal Y16. The first standard decoding result output terminal Y0 to the seventeenth standard decoding result output terminal Y16 are configured to control a start row, the sum output terminals S0 to S15 of the 16 half adders are configured to control a reset of a non-display area, and the carry output terminals C0 to C15 of the 16 half adders are configured to control a stop row.

[0250] Figure 19 shows the truth table of a 5-17 decoder. The 5-17 decoder includes 17 inputs. Each input generates a 17-bit output, with only one bit being 1, while the remaining 16 bits are all 0. This characteristic can be exploited to use the 1-bit output as a select signal for a row in the 17-stage first-type offset gate driver circuit G101 and the 17-stage second-type offset gate driver circuit G102 (Orbit), thereby turning on the starting row of the display. The remaining 16 rows are all turned off. Therefore, the signals output from the 17 standard decoding result output terminals can be used to select and control the starting row of the display in the 17-stage first-type offset gate driver circuit G101 and the 17-stage second-type offset gate driver circuit G102 (Orbit). That is, one stage can be selected from the 17-stage first-side offset shift register circuit P101 as the first-type initial shift register circuit, and one stage can be selected from the 17-stage second-side offset shift register circuit P102 as the second-type initial shift register circuit. In other words, one level is selected from the 17-level first-level offset gate driving circuit G101 as the first-level initial gate driving circuit, and one level is selected from the 2S+1-level second-level offset gate driving circuit G102 as the second-level initial gate driving circuit.

[0251] In an exemplary embodiment, the first standard decoding result output terminal Y0 to the seventeenth standard decoding result output terminal Y16 can be respectively used as 17 first-type initial row control terminals, and the inverting output terminal Y0_ of the first standard decoding result output terminal Y0 to the inverting output terminal Y16_ of the seventeenth standard decoding result output terminal Y16 can be respectively used as 17 second-type initial row control terminals; the first standard decoding result output terminal Y0 to the sixteenth standard decoding result output terminal Y15 can also be respectively connected to the second transmission terminals of the sixteen first-side offset transmission control circuits P10-1. The first standard decoding result output terminal Y0 through the sixteenth standard decoding result output terminal Y15 can be electrically connected to the first forward and reverse scan control terminals GSD1 of the sixteen first-side offset transmission control circuits P10-1, and to the second transmission control terminals GSD2 of the sixteen second-side offset transmission control circuits P10-2. In an exemplary embodiment, the first standard decoding result output terminal Y0 through the seventeenth standard decoding result output terminal Y16 can be connected to the inverting output terminals of the corresponding standard decoding result output terminals via seventeen inverters, and the output terminals of the seventeen inverters can serve as the inverting output terminals Y0_ of the first standard decoding result output terminal Y0 through the inverting output terminals Y16_ of the seventeenth standard decoding result output terminal Y16.

[0252] In an exemplary embodiment, as shown in FIG17 , the shift control circuit may further include a thirty-second inverter 432 , the input of which is electrically connected to the seventeenth standard decoding result output terminal Y16 , and the output of which may serve as a second type initial row control terminal.

[0253] In an exemplary embodiment, the first standard decoding result output terminal Y0 to the seventh standard decoding result output terminal Y7 can be respectively used as the eighth first initial row control terminal IN_Z8 to the first first initial row control terminal IN_Z1, the eighth standard decoding result output terminal Y8 can be used as the fifth initial row control terminal IN_Z0, and the ninth standard decoding result output terminal Y9 to the seventeenth standard decoding result output terminal Y16 can be respectively used as the first third initial row control terminal IN_Z_1 to the eighth third initial row control terminal IN_Z_8; the inverting output terminal Y of the first standard decoding result output terminal Y0 The inverted output terminals Y7_ of the seventh standard decoding result output terminal Y0_ through the seventh standard decoding result output terminal Y7 can serve as the eighth second initial row control terminal IN_Z8_ through the first first initial row control terminal IN_Z1_, respectively. The inverted output terminal Y8_ of the eighth standard decoding result output terminal Y8 can serve as the sixth initial row control terminal IN_Z0_. The inverted output terminals Y9_ of the ninth standard decoding result output terminal Y9 through the inverted output terminals Y16_ of the seventeenth standard decoding result output terminal Y16 can serve as the first fourth initial row control terminal IN_Z1 through the eighth third initial row control terminal IN_Z8_, respectively. In an exemplary embodiment, the output terminals of the sixteenth inverter 416 through the thirty-second inverter 432 can serve as the inverted output terminals Y0_ of the first standard decoding result output terminal Y0 through the inverted output terminals Y16_ of the seventeenth standard decoding result output terminal Y16, respectively.

[0254] As shown in Figure 20, this is the truth table of the inverted output terminal Y0_ of the first standard decoding result output terminal Y0 to the inverted output terminal Y15_ of the sixteenth standard decoding result output terminal Y15. The sixteenth inverter 416 to the thirty-first inverter 431 respectively invert the results of the first standard decoding result output terminal Y0 to the sixteenth standard decoding result output terminal Y15, and each output result includes a 16-bit output, and the 1-bit output originally having a value of 1 is changed to 0, and the 15-bit output originally having a value of 0 is changed to 1.

[0255] In an exemplary embodiment, as shown in FIG17 , in the low-to-high-order direction, the first standard decoding result output terminal Y0 is connected to the addend input terminal A of the first half adder 701 via the sixteenth inverter 416 (the first inverter in the shift control circuit), and the input value of the augend input terminal B of the first half adder 701 is always 1; the second standard decoding result output terminal Y1 to the sixteenth standard decoding result output terminal Y15 are connected to the augend input terminals B of the second half adders 702 to the sixteenth half adders 716 via the seventeenth inverter 417 (the second inverter in the shift control circuit) to the thirty-first inverter 431 (the sixteenth inverter in the shift control circuit), respectively. In the first standard decoding result output terminal Y0 to the sixteenth standard decoding result output terminal Y15, the carry output terminal Cout of the previous stage is connected to the addend input terminal A of the half adder of the next stage, and 16 half adders are cascaded to form an accumulator.

[0256] In an exemplary embodiment, as shown in FIG17 , the shift control circuit may include a high voltage clamp circuit 800 (Tie High), the output end of the high voltage clamp circuit 800 is connected to the addend input end B of the first half adder 701, and the value outputted by the output end of the high voltage clamp circuit 800 is always 1.

[0257] In an exemplary embodiment, the result of the half adder sum Sum (sum output terminal Si) is the cumulative sum without carry after the addition operation, and is accumulated in the direction from the first standard decoding result output terminal Y0 to the sixteenth standard decoding result output terminal Y15. According to the logic circuit structure, in the 16-bit output result, with the output result Yx=0 as the boundary, the sum output terminal Si=0 from Y0 to Yx, and the sum output terminal Si=1 from Yx+1 to Y15, as shown in Figure 21, which is the truth table of the sum output terminals of 16 half adders, and the values ​​of x and i are both integers.

[0258] In an exemplary embodiment, the half adder carry Cout (carry output terminal Ci) is the carry result after the addition operation, and is accumulated in the direction from Y0 to Y15. According to the logic circuit structure, with Yx=0 as the boundary, the sum output terminal Si=1 from Y0 to Yx-1, and Si=0 from Yx to Y15, as shown in Figure 22, which is the truth table of the carry output terminals of 16 half adders.

[0259] In an exemplary embodiment, the characteristics of the output results of the sum output terminals Si of the 16 half adders can be utilized to use Y0 to Y15 as reset signals for controlling the equally spaced shifting of the display. The reset signals are set to be active high, meaning that when the reset signal is 0, the corresponding display area can display data normally; otherwise, the display content is cleared, meaning no data is displayed. As shown in FIG23 , the sum output terminals Si of the 16 half adders can be configured to control the reset of the first-type initial gate driver circuit located away from the m-stage intermediate gate driver circuit. In this exemplary embodiment, in the direction from the 2S+1-stage first-type gate driver circuit G102 to the 2S+1-stage second-type gate driver circuit G102, the sum output terminals S0 of the first half adder 701 to the sum output terminals S16 of the 16th half adder 716 can serve as the first to 16th first-type reset control terminals, respectively.

[0260] In an exemplary embodiment, the characteristics of the output results of the carry output terminals Ci of the 16 half adders can be utilized to use Y0 to Y15 as reset signals for controlling the equally spaced shifting of the display. The reset signals are set to be active high, meaning that when the reset signal is 0, the corresponding display area can display data normally; otherwise, the display content is cleared, meaning no data is displayed. As shown in FIG24 , the carry output terminals Ci of the 16 half adders can be configured to control the reset of the second-type initial gate driver circuit located away from the m-stage intermediate gate driver circuit. In an exemplary embodiment, in the direction from the 2S+1-stage first-type gate driver circuit G102 to the 2S+1-stage second-type gate driver circuit G102, the carry output terminals C0 of the first half adder 701 to the carry output terminals C16 of the 16th half adder 716 can serve as the first to the 16th second-type reset control terminals, respectively.

[0261] In an exemplary embodiment, the operating principle diagram of the standard 5-17 decoder 600 in FIG17 may be shown in FIG25 . The lower 17 bits of the standard decoding result output terminals Y0 to Y16 of the standard 5-32 decoder are used, and the upper 15 bits of the standard decoding result output terminals can be expanded to other functions, which is equivalent to saving 15 AND gate logic circuits, that is, saving 180 MOS transistors, thereby saving hardware resources to a certain extent. As shown in FIG25 , the 5-17 decoder 600 may include 17 AND gate logic circuits, each of which includes five input terminals, and the five output terminals respectively correspond to the first input terminal A0 to the fifth input terminal A4 of the 5-17 decoder. Each input terminal of the AND gate logic circuit can be electrically connected to the corresponding input terminal or the inverting output terminal of the corresponding input terminal. The input terminals of the 17 AND gate logic circuits can respectively serve as the first decoding result output terminal Y0 to the seventeenth decoding result output terminal Y16. The shift control circuit in Figure 17 only adds 16 half adders and 16 inverters to the standard 5-17 decoder 600, reducing costs to a certain extent. Y0 to Y15 of the 17-bit standard decoding result output terminals Y0 to Y16 are multiplexed as input signals for the cutoff control function (stages Y0 to Y15 can each serve as inputs for 16 half adders), improving the utilization of the standard decoding result output terminals. Furthermore, the half adder and the number output terminal Si are used to control the reset of the first type of initial gate drive circuit on the side away from the m-stage intermediate gate drive circuit. The half adder's carry output terminal Ci is used to control the reset of the second type of initial gate drive circuit on the side away from the m-stage intermediate gate drive circuit. This saves 16 inverters, which translates to 32 MOSFETs.

[0262] In an exemplary embodiment, the shift control circuit can also be implemented using the structure shown in FIG26 . As shown in FIG26 , the shift control circuit can include a non-standard 5-9 decoder 901, a 5-8 decoder 902, a 3-7 thermometer decoder 903, and a 5-9 logic operation circuit 904. The non-standard 5-9 decoder 901 and 5-8 decoder 902 are configured to control the start row, while the 3-7 thermometer decoder 903 and 5-9 logic operation circuit 904 are configured to control the end row and reset the non-display area. FIG27 shows a schematic diagram of the working principle of the 5-9 decoder 901, FIG28 shows a schematic diagram of the working principle of the 5-8 decoder 902, and FIG29 shows a schematic diagram of the working principle of the 3-7 thermometer decoder 903 and the 5-9 logic operation circuit 904. As can be seen from Figures 26 to 29 , the input and output of the shift control circuit are assembled from multiple devices, while the input and output of the shift control circuit shown in Figure 17 are not assembled. The shift control circuits in Figures 26 to 29 require, in addition to the 3-7 thermometer decoder 903 and the 5-8 decoder 902, a 5-9 logic operation circuit 904 and a non-standard 5-9 decoder 901. In contrast, the shift control circuit in Figure 17 requires, in addition to a standard 5-32 decoder, only one accumulator (including 16 half adders) and 16 inverters. This shows that the shift control circuit shown in Figure 17 is structurally simpler than the shift control circuits shown in Figures 26 to 29 , with relatively fewer logic circuits outside of standard devices. This makes it suitable for display substrates with limited hardware resources and smaller areas, such as silicon-based OLED display substrates.

[0263] In an exemplary embodiment, the logic decoding circuit may further include at least one 3-wire-8-wire decoder, 2S+1 expansion circuits and at least one expansion input terminal, the number of output terminals of at least one 3-wire-8-wire decoder is 2S+1, the input terminal of the logic decoding circuit includes three input terminals of the 3-wire-8-wire decoder and at least one expansion input terminal, the input terminals of the 2S+1 expansion circuits are connected to the 2S+1 output terminals of the at least one 3-wire-8-wire decoder, and the output terminals of the 2S+1 expansion circuits serve as the 2S+1 output terminals of the logic decoding circuit respectively.

[0264] In an exemplary embodiment, as shown in Figures 26 to 28 , S can take a value of 8. The logic decoding circuit can include two 3-8 decoders, seventeen expansion circuits KL, and two expansion input terminals. The two expansion input terminals include a first expansion input terminal A3 and a second expansion input terminal A4. The three input terminals (A0 to A2) of one 3-line to 8-line decoder can serve as the first to third input terminals of the logic decoding circuit. The first expansion input terminal A3 serves as the fourth input terminal of the logic decoding circuit. The second expansion input terminal A4 can serve as the fifth input terminal of the logic decoding circuit. The inverting output terminal A0_ of the first input terminal to the inverting output terminal A2_ of the third input terminal serve as input terminals of another 3-line to 8-line decoder. In other words, the shift control circuit can include five input terminals (A0 to A4) and 17 output terminals.

[0265] In the exemplary embodiment, as shown in Figures 26 to 28, two 3-8 decoders include a first 3-8 decoder and a second 3-8 decoder. The seventeen expansion circuits KL may include sixteen first expansion circuits KL1 and one second expansion circuit KL2. The first 3-8 decoder, eight of the first expansion circuits KL1, one second expansion circuit KL2, and two expansion input terminals (A3 and A4) form a 5-9 decoder 901. The second 3-8 decoder, eight of the first expansion circuits KL1, and two expansion input terminals (A3 and A4) form a 5-8 decoder 902. In other words, combining two standard 3-8 decoders with seventeen expansion circuits KL to form a logic decoding circuit can fully utilize the decoder output states and reduce costs. A standard 3-line to 8-line decoder is generally less expensive than a standard 5-line to 32-line decoder. By expanding the output states of the 3-line to 8-line decoder, costs can be effectively reduced.

[0266] As shown in FIG30 a , the second expansion circuit KL2 may include an eighth NAND gate 308 , a ninth NAND gate 309 , a sixth NOR gate 506 , and a nineteenth inverter 419 ;

[0267] In the eighth NAND gate 308, a first input terminal is connected to the inverting output terminal IN_A0_ of the first input terminal IN_A0 of the shift control circuit, a second input terminal is connected to the inverting output terminal IN_A1_ of the second input terminal IN_A1 of the shift control circuit, a third input terminal is connected to the inverting output terminal IN_A2_ of the third input terminal IN_A2 of the shift control circuit, and an output terminal is connected to the second input terminal of the sixth NOR gate 506.

[0268] In the ninth NAND gate 309, a first input terminal is connected to the fourth input terminal IN_A3 of the shift control circuit, a second input terminal is connected to the inverting output terminal IN_A4_ of the fifth input terminal IN_A4 of the shift control circuit, and an output terminal is connected to the first input terminal of the sixth NOR gate 506;

[0269] The output end of the sixth NOR gate 506 is connected to the input end of the nineteenth inverter 419. The output end of the sixth NOR gate 506 can serve as the ninth decoding output end OUT_Z8 of the 5-9 decoder 901. The output end of the nineteenth inverter 419 can serve as the inverting output end OUT_Z8_ of the ninth decoding output end OUT_Z8 of the 5-9 decoder 901.

[0270] As shown in FIG30 b , each first expansion circuit KL2 may include a tenth NAND gate 310 , a seventh NOR gate 507 , and a twentieth inverter 420 ;

[0271] In the tenth NAND gate 310, a first input terminal is connected to the fourth input terminal IN_A3 of the shift control circuit or the inverting output terminal IN_A3_ of the fourth input terminal IN_A3, a second input terminal is connected to the fifth input terminal IN_A4 of the shift control circuit or the inverting output terminal IN_A4_ of the fifth input terminal IN_A4, and an output terminal is connected to the first input terminal of the seventh NOR gate 507;

[0272] The output end of the seventh NOR gate 507 is connected to the input end of the twentieth inverter 420. The output end of the seventh NOR gate 507 can serve as one of the seventeen decoding output ends of the 5-8 decoder and the 5-9 decoder. The output end of the twentieth inverter 420 can serve as one of the inverting output ends of the seventeen decoding output ends of the 5-8 decoder and the 5-9 decoder. The second input end of the seventh NOR gate 507 can be connected to one of the output ends of the 3-8 decoder.

[0273] In an exemplary embodiment, as shown in Figures 27 and 28, in the 5-9 decoder 901, the second input terminal of the seventh NOR gate 507 in the first expansion circuit KL1 can be connected to one of the output terminals Yi in the first 3-8 decoder; in the 5-8 decoder 902, the second input terminal of the seventh NOR gate 507 in the first expansion circuit KL1 can be connected to one of the output terminals Yi in the second 3-8 decoder.

[0274] In an exemplary embodiment, as shown in Figures 27 and 28, in the first expansion circuit KL1 of the 5-9 decoder 901, the first input terminal of the tenth NAND gate 310 is connected to the fourth input terminal IN_A3 of the shift control circuit, and the second input terminal of the tenth NAND gate 310 is connected to the inverting output terminal IN_A4_ of the fifth input terminal IN_A4 of the shift control circuit; in the first expansion circuit KL1 of the 5-8 decoder 902, the first input terminal of the tenth NAND gate 310 is connected to the fourth input terminal IN_A3 of the shift control circuit, and the second input terminal of the tenth NAND gate 310 is connected to the fifth input terminal IN_A4 of the shift control circuit.

[0275] In an exemplary embodiment, as shown in Figures 27 and 28, in the 5-9 decoder 901, the output end of each seventh NOR gate 507 can be used as one of the decoding output ends of the 5-9 decoder 901, and the output end of the twentieth inverter 420 can be used as the inverted output end of one of the decoding output ends of the 5-9 decoder 901; in the 5-8 decoder 902, the output end of each seventh NOR gate 507 can be used as one of the decoding output ends of the 5-8 decoder 902, and the output end of the twentieth inverter 420 can be used as the inverted output end of one of the decoding output ends of the 5-8 decoder 902.

[0276] In an exemplary embodiment, as shown in Figures 26 to 28, the 5-9 decoder 901 may include nine decoding output terminals (OUT_Z0 to OUT_Z8) and inverting output terminals of the nine decoding output terminals (OUT_Z0_ to OUT_Z8_), and the 5-8 decoder may include eight decoding output terminals (OUT_Z_1 to OUT_Z_8) and inverting output terminals of the eight decoding output terminals (OUT_Z_1_ to OUT_Z_8_); 2S+1 first-type initial row control terminals may include nine decoding output terminals in the 5-9 decoder and eight decoding output terminals in the 5-8 decoder; 2S+1 second-type initial row control terminals may include the inverting output terminals of the nine decoding output terminals in the 5-9 decoder and the inverting output terminals of the eight decoding output terminals in the 5-8 decoder.

[0277] In an exemplary embodiment, as shown in FIG16 a to FIG16 b and FIG26 to FIG28 , among the nine decoded output terminals of the 5-9 decoder, in the direction from the high bit (OUT_Z8) to the low bit (OUT_Z0), the first decoded output terminal OUT_Z8 to the ninth decoded output terminal OUT_Z0 serve as the first first-type initial row control terminal IN_Z8 to the ninth first-type initial row control terminal IN_Z0 in the direction from the first-type offset gate driver circuit G101 to the second-type offset gate driver circuit G102, respectively.

[0278] Among the eight decoding output terminals of the 5-8 decoder, in the direction from the high bit OUT_Z_8 to the low bit OUT_Z_1, the first decoding output terminal OUT_Z_8 to the eighth decoding output terminal OUT_Z_1 can respectively serve as the first first-class initial row control terminal IN_Z_8 to the eighth first-class initial row control terminal IN_Z_1 in the direction from the second-class offset gate driver circuit G102 to the first-class offset gate driver circuit G101.

[0279] In an exemplary embodiment, as shown in FIG16 a to FIG16 b and FIG26 to FIG28 , among the inverting output terminals (OUT_Z0_ to OUT_Z8_) of the nine decoding output terminals of the 5-9 decoder, in the direction from the high bit OUT_Z8_ to the low bit OUT_Z0_, the inverting output terminal OUT_Z8_ of the first decoding output terminal to the inverting output terminal OUT_Z0_ of the ninth decoding output terminal can respectively serve as the first second-type initial row control terminal IN_Z8__ to the ninth second-type initial row control terminal IN_Z0_ in the direction from the first-type offset gate driver circuit G101 to the second-type offset gate driver circuit G102;

[0280] Among the inverting output terminals (OUT_Z_1_ to OUT_Z_8_) of the eight decoding output terminals of the 5-8 decoder, in the direction from the high bit OUT_Z_8_ to the low bit OUT_Z_1_, the inverting output terminal OUT_Z_8_ of the first decoding output terminal to the inverting output terminal OUT_Z_1_ of the eighth decoding output terminal can respectively serve as the first second-class initial row control terminal IN_Z_8_ to the eighth second-class initial row control terminal IN_Z_1_ in the direction from the second-class offset gate driver circuit G102 to the first-class offset gate driver circuit G101.

[0281] In an exemplary embodiment, as shown in FIG16 a to FIG16 b , FIG26 and FIG29 , the value of S may be 8, and the shift control circuit may include a 3-7 thermometer decoder 903 and a 5-9 logic operation circuit 904 ;

[0282] In the direction of the 2S+1-level first-class offset gate driver circuit G101 to the m-level middle offset gate driver circuit G100, the reset control terminal may include first to 2S first-class reset control terminals (IN_TS to IN_T_S-1) electrically connected to the reset control circuits in the first-level first-class offset gate driver circuit G101 to the 2S-level first-class offset gate driver circuit G102, respectively;

[0283] Among the nine output terminals of the logic operation circuit 5-9, in the direction from the high bit IN_T8 to the low bit IN_T0, the first output terminal OUT_T8 to the ninth output terminal OUT_T0 can be respectively used as the first first-type reset control terminal IN_T8 to the ninth first-type reset control terminal IN_T0;

[0284] Among the seven output terminals of the 3-7 thermometer decoder, in the direction from the low bit OUT_T_1 to the high bit OUT_T_7, the first output terminal IN_T_1 to the seventh output terminal IN_T_7 can be used as the tenth first-type reset control terminal IN_T_1 to the sixteenth first-type reset control terminal IN_T_7 respectively.

[0285] In an exemplary embodiment, as shown in FIG16 a to FIG16 b, FIG26 and FIG29, in the direction of the 2S+1-stage first-type offset gate driver circuit G101 to the m-stage middle offset gate driver circuit G100, the reset control terminal may include first to 2S second-type reset control terminals (IN_TS_ to IN_T_S-1_) electrically connected to the reset control circuits in the second-stage second-type offset gate driver circuit G101 to the 2S+1-stage second-type offset gate driver circuit G102, respectively;

[0286] Among the nine inverting output terminals of the logic operation circuit 5-9, in the direction from the high bit OUT_T8_ to the low bit OUT_T1_, the inverting output terminal OUT_T8_ of the first output terminal to the inverting output terminal OUT_T1_ of the ninth output terminal can serve as the first second-type reset control terminal IN_T8_ to the ninth second-type reset control terminal IN_T1_, respectively;

[0287] Among the inverting output terminals of the seven output terminals of the 3-7 thermometer decoder, in the direction from the low bit OUT_T_1_ to the high bit OUT_T_7_, the inverting output terminal OUT_T_1_ of the first output terminal to the inverting output terminal OUT_T_1_ of the seventh output terminal can be respectively used as the tenth second-type reset control terminal IN_T_1__ to the sixteenth second-type reset control terminal IN_T_7_.

[0288] In an exemplary embodiment, as shown in Figures 16a, 16b, 26 and 27, the first decoding output terminal OUT_Z0 to the ninth decoding output terminal OUT_Z8 in the 5-9 decoder 901 can be used as the fifth initial row control terminal IN_Z0 and the eight first initial row control terminals (IN_Z1 to IN_Z8), respectively, and the inverting output terminal OUT_Z0_ of the first decoding output terminal to the inverting output terminal OUT_Z8_ of the ninth decoding output terminal in the 5-9 decoder 901 can be used as the sixth initial row control terminal IN_Z0_ and the eight second initial row control terminals (IN_Z1_ to IN_Z8_), respectively.

[0289] In an exemplary embodiment, as shown in Figures 16a, 16b, 26 and 28, the first decoding output terminal OUT_Z_1 to the eighth decoding output terminal OUT_Z_8 in the 5-8 decoder 902 can be respectively used as 8 third initial row control terminals (IN_Z_1 to IN_Z_8), and the inverting output terminal OUT_Z_1_ of the first decoding output terminal to the inverting output terminal OUT_Z_8_ of the eighth decoding output terminal in the 5-8 decoder 902 can be respectively used as 8 fourth initial row control terminals (IN_Z_1_ to IN_Z_8_).

[0290] In an exemplary embodiment, as shown in Figures 16a, 16b and 29, the first decoding output terminal OUT_T0 to the ninth decoding output terminal OUT_T8 in the 5-9 logic operation circuit 904 can be respectively used as the second reset control terminal IN_T0 of the first first side, the first reset control terminal IN_T1 of the first first side to the first reset control terminal IN_T8 of the eighth first side; the inverting output terminal OUT_T0_ of the first decoding output terminal to the inverting output terminal OUT_T8_ of the ninth decoding output terminal in the 5-9 logic operation circuit 904 can be respectively used as the second reset control terminal IN_T0_ of the first second side, the first reset control terminal IN_T1_ of the first second side to the first reset control terminal IN_T8_ of the eighth second side. The first decoding output terminal OUT_T_1 to the seventh decoding output terminal OUT_T_7 in the 3-7 thermometer decoder 903 can be respectively used as the second reset control terminal IN_T_1 of the second first side to the second reset control terminal IN_T_7 of the eighth first side; the inverse output OUT_T_1_ of the first decoding output terminal to the inverse output OUT_T_7_ of the seventh decoding output terminal in the 3-7 thermometer decoder 903 can be respectively used as the second reset control terminal IN_T_1_ of the second second side to the second reset control terminal IN_T_7_ of the eighth second side.

[0291] As shown in FIG29 , the three input terminals of the 3-7 decoding thermometer coder 903 are the first input terminal IN_A0 to the third input terminal IN_A2 of the shift control circuit, and the input terminals of the 5-9 logic operation circuit 904 include the fourth input terminal IN_A3 and the fifth input terminal IN_A4 of the shift control circuit. The 5-9 logic operation circuit 904 may include the first sub-circuit 101 to the tenth sub-circuit 110, and the 3-7 decoding thermometer coder 903 may include the first decoding sub-circuit 201 to the seventh decoding sub-circuit 207, wherein the output of the first sub-circuit 101 can serve as an input terminal of the first decoding sub-circuit 201 to the seventh decoding sub-circuit 207.

[0292] The first decoding sub-circuit 201 in the 3-7 thermometer decoder 903 includes two NOR gates. The three inputs of the first NOR gate are connected to the inverting output IN_A0_ of the first input terminal IN_A0 through the inverting output IN_A2_ of the third input terminal IN_A2, respectively. The output of the first NOR gate is connected to the second input of the second NOR gate and an input of the ninth sub-circuit 109. The first input of the second NOR gate is connected to the output of the first sub-circuit 101, and the output serves as the first output OUT_T_1 of the 3-7 thermometer decoder 903.

[0293] The second decoding sub-circuit 202 in the 3-7 thermometer decoder 903 includes two NOR gates. The two input terminals of the first NOR gate are respectively connected to the inverting output terminal IN_A1_ of the second input terminal IN_A1 and the inverting output terminal IN_A2_ of the third input terminal IN_A2. The output terminal of the first NOR gate is connected to the second input terminal of the second NOR gate and an input terminal of the eighth sub-circuit 108. The first input terminal of the second NOR gate is connected to the output terminal of the first sub-circuit 101. The output terminal serves as the second output terminal OUT_T_2 of the 3-7 thermometer decoder 903.

[0294] The third decoding sub-circuit 203 in the 3-7 thermometer decoder 903 includes a NAND gate, an inverter, and two NOR gates. The two inputs of the NAND gate are respectively connected to the inverting output terminal IN_A0_ of the first input terminal IN_A0 and the inverting output terminal IN_A1_ of the second input terminal IN_A1. The output of the NAND gate is connected to the input of the inverter. The output of the inverter is connected to the second input of the first NOR gate. The first input of the first NOR gate is connected to the inverting output terminal IN_A2_ of the third input terminal IN_A2. The output of the first NOR gate is connected to the second input of the second NOR gate and an input of the seventh sub-circuit 107. The first input of the second NOR gate is connected to the output of the first sub-circuit 101. The output of the second NOR gate serves as the third output terminal OUT_T_3 of the 3-7 thermometer decoder 903.

[0295] The fourth decoding sub-circuit 204 in the 3-7 thermometer decoder 903 includes an inverter and a NOR gate. The inverter input is connected to the inverting output IN_A2_ of the third input IN_A2, the output is connected to the second input of the NOR gate and an input of the sixth sub-circuit 106, the first input of the NOR gate is connected to the output of the first sub-circuit 101, and the output serves as the fourth output OUT_T_4 of the 3-7 thermometer decoder 903.

[0296] The fifth decoding sub-circuit 205 in the 3-7 thermometer decoder 903 includes a NAND gate, an inverter, and two NOR gates. The two inputs of the first NOR gate are respectively connected to the inverting output terminal IN_A0_ of the first input terminal IN_A0 and the inverting output terminal IN_A1_ of the second input terminal IN_A1. The output of the first NOR gate is connected to the input of the inverter. The output of the inverter is connected to the second input of the NAND gate. The first input of the NAND gate is connected to the inverting output terminal IN_A2_ of the third input terminal IN_A2. The output of the NAND gate is connected to the second input of the second NOR gate and an input of the fifth sub-circuit 105. The first input of the second NOR gate is connected to the output of the first sub-circuit 101. The output of the second NOR gate serves as the fifth output terminal OUT_T_5 of the 3-7 thermometer decoder 903.

[0297] The sixth decoding sub-circuit 206 in the 3-7 thermometer decoder 903 includes a NAND gate and a NOR gate. The three inputs of the NAND gate are connected to the inverting output IN_A0_ of the first input terminal IN_A0 to the inverting output IN_A2_ of the third input terminal IN_A2, respectively. The output of the NAND gate is connected to the second input of the NOR gate and an input of the fourth sub-circuit 104. The first input of the NOR gate is connected to the output of the first sub-circuit 101. The output serves as the sixth output OUT_T_6 of the 3-7 thermometer decoder 903.

[0298] The seventh decoding sub-circuit 207 in the 3-7 thermometer decoder 903 includes a NAND gate and a NOR gate. The three input terminals of the NAND gate are respectively connected to the inverting output terminal IN_A0_ of the first input terminal IN_A0 to the inverting output terminal IN_A2_ of the third input terminal IN_A2. The output terminal is connected to the second input terminal of the NOR gate and one input terminal of the third sub-circuit 103 and the tenth sub-circuit 110. The first input terminal of the NOR gate is connected to the output terminal of the first sub-circuit 101. The output terminal serves as the seventh output terminal OUT_T_7 of the 3-7 thermometer decoder 903.

[0299] The first sub-circuit 101 in the 5-9 logic operation circuit 904 may include an inverter and a NOR gate, wherein the two input terminals of the NOR gate are respectively connected to the inverting output terminal IN_A3_ of the fourth input terminal IN_A3 and the inverting output terminal IN_A4_ of the fifth input terminal IN_A4, and the input terminal is connected to the input terminal of the inverter. The output terminal of the inverter serves as the output terminal of the first sub-circuit 101 (which may be connected to the 3-7 thermometer decoder 903);

[0300] The second sub-circuit 102 in the 5-9 logic operation circuit 904 can be an inverter, the input end of the inverter is connected to the fifth input end IN_A4, the output end of the inverter serves as the inverted output end of an output end of the 5-9 logic operation circuit 904, and the fifth input end IN_A4 can serve as an output end of the 5-9 logic operation circuit 904;

[0301] The third sub-circuit 103 to the ninth decoding sub-circuit 109 in the 5-9 logic operation circuit 904 each include a NAND gate and two inverters. In each of the third sub-circuit 103 to the ninth decoding sub-circuit 109: the first input terminal of the NAND gate is connected to the inverting output terminal IN_A4_ of the fifth input terminal IN_A4, the second input terminal is connected to the 3-7 thermometer decoder 903, the output terminal is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the first input terminal of the NOR gate, the second input terminal of the NOR gate is connected to the fifth input terminal IN_A4, the output terminal of the NOR gate is connected to the input terminal of the second inverter, the output terminal of the second inverter can serve as an output terminal of the 5-9 logic operation circuit 904, and the output terminal of the NOR gate can serve as the inverting output terminal of an output terminal of the 5-9 logic operation circuit 904;

[0302] The tenth sub-circuit 110 in the 5-9 logic operation circuit 904 may include a NAND gate, a NOR gate, and an inverter. The two input terminals of the NAND gate are respectively connected to the inverting output terminal IN_A4_ of the fifth input terminal IN_A4 and the fourth input terminal IN_A3, the output terminal is connected to the first input terminal of the NOR gate, the second input terminal of the NOR gate is connected to the seventh decoding sub-circuit 207, and the output terminal of the NOR gate is connected to the input terminal of the inverter. The output terminal of the inverter can serve as the inverting output terminal of an output terminal of the 5-9 logic operation circuit 904, and the output terminal of the NOR gate can serve as an output terminal of the 5-9 logic operation circuit 904.

[0303] As shown in FIG29 , the third sub-circuit 103 may be connected to the seventh decoding sub-circuit 207, the fourth sub-circuit 104 may be connected to the sixth decoding sub-circuit 206, the fifth sub-circuit 105 may be connected to the fifth decoding sub-circuit 205, the sixth sub-circuit 106 may be connected to the fourth decoding sub-circuit 204, the seventh sub-circuit 107 may be connected to the third decoding sub-circuit 203, the eighth sub-circuit 108 may be connected to the second decoding sub-circuit 202, and the ninth sub-circuit 109 may be connected to the first decoding sub-circuit 201.

[0304] In an exemplary embodiment, as shown in FIG16a, FIG26 and FIG27, in the direction from the second type offset gate driver circuit G102 to the first type offset gate driver circuit G101: the second control terminal K2 of the row control circuit 01 in the second offset gate driver circuit G1012 (Orbit0) on the first side of the ninth stage, the first offset gate driver circuit G1011 (Orbit1) on the first side of the first stage to the first offset gate driver circuit G1011 (Orbit8) on the first side of the eighth stage can be respectively connected to the first decoding output terminal OUT_Z0 to the ninth decoding output terminal OUT_Z8 in the 5-9 decoder 901 in the direction from low to high; the first control terminal K1 of the row control circuit 01 in the second offset gate driver circuit G1012 (Orbit0) on the first side of the ninth stage, the first offset gate driver circuit G1011 (Orbit1) on the first side of the first stage to the first offset gate driver circuit G1011 (Orbit8) on the first side of the eighth stage can be respectively connected to the first decoding output terminal OUT_Z0 to the ninth decoding output terminal OUT_Z8 in the 5-9 decoder 901 in the direction from low to high. The inverting output terminal OUT_ZO_ of the first decoding output terminal OUT_Z0 in the first direction is connected to the inverting output terminal OUT_Z8_ of the ninth decoding output terminal OUT_Z8; the second forward and reverse scan control terminal GSD2 in the third offset transmission control circuit P10-13 on the first side and the first first offset transmission control circuit P10-11 on the first side to the seventh first offset transmission control circuit P10-11 on the first side can be respectively connected to the first decoding output terminal OUT_Z0 to the first decoding output terminal OUT_Z8_ in the direction from low to high in the 5-9 decoder 901. The eighth decoding output terminal OUT_Z7 is connected; the first forward and reverse scan control terminal GSD1 in the third offset transmission control circuit P10-13 on the first side, the first first offset transmission control circuit P10-11 on the first side to the seventh first offset transmission control circuit P10-11 on the first side can be respectively connected to the inverting output terminal OUT_Z0_ of the first decoding output terminal OUT_Z0 to the inverting output terminal OUT_Z7_ of the eighth decoding output terminal OUT_Z7 in the 5-9 decoder 901 from the low bit to the high bit direction.

[0305] In an exemplary embodiment, as shown in FIG16a, FIG26 and FIG28, in the direction from the first type offset gate driver circuit G101 to the second type offset gate driver circuit G102: the second control terminal K2 of the row control circuit 01 in the second offset gate driver circuit G1012 (Orbit-1) on the first side of the first stage to the second offset gate driver circuit G1012 (Orbit-8) on the first side of the eighth stage can be respectively connected to the first decoding output terminal OUT_Z_1 to the eighth decoding output terminal OUT_Z_8 in the 5-8 decoder 902 in the direction from low to high; the first control terminal K1 of the row control circuit 01 in the first offset gate driver circuit G1012 (Orbit-1) on the first side of the first stage to the first offset gate driver circuit G1012 (Orbit-8) on the first side of the eighth stage can be respectively connected to the first decoding output terminal OUT_Z_1 to the eighth decoding output terminal OUT_Z_8 in the 5-8 decoder 902 in the direction from low to high. _Z_1 is connected to the inverting output terminal OUT_Z_8_ of the eighth decoding output terminal OUT_Z_8; the second forward and reverse scan control terminal GSD2 in the first second offset transmission control circuit P10-12 on the first side to the eighth second offset transmission control circuit P10-12 on the first side can be respectively connected to the first decoding output terminal OUT_Z_1 to the eighth decoding output terminal OUT_Z_8 in the 5-8 decoder 902 from the low bit to the high bit direction; the first forward and reverse scan control terminal GSD1 in the first second offset transmission control circuit P10-12 on the first side to the eighth second offset transmission control circuit P10-12 on the first side can be respectively connected to the inverting output terminal OUT_Z_1_ of the first decoding output terminal OUT_Z_1 to the inverting output terminal OUT_Z_8_ of the eighth decoding output terminal OUT_Z_8 in the 5-8 decoder 902 from the low bit to the high bit direction.

[0306] In an exemplary embodiment, as shown in FIG16 b , FIG26 and FIG27 , in the direction from the second type offset gate driver circuit G102 to the first type offset gate driver circuit G101: the first control terminal K1 of the row control circuit 01 in the second offset gate driver circuit G1022 (Orbit0) on the second side of the ninth stage to the second offset gate driver circuit G1022 (Orbit8) on the second side of the eighth stage can be respectively connected to the first decoding output terminal OUT_Z0 to the ninth decoding output terminal OUT_Z8 in the 5-9 decoder 901 in the direction from low to high; the second control terminal K2 of the row control circuit 01 in the second offset gate driver circuit G1022 (Orbit0) on the second side of the ninth stage to the second offset gate driver circuit G1022 (Orbit8) on the second side of the eighth stage can be respectively connected to the inverting output terminal OUT_Z0 of the first decoding output terminal OUT_Z0 in the 5-9 decoder 901 in the direction from low to high. The inverting output terminal OUT_Z8_ of the decoding output terminal OUT_Z8 is connected; the first forward and reverse scan control terminal GSD1 in the third offset transmission control circuit P10-23 on the second side and the first second offset transmission control circuit P10-22 on the second side to the seventh second offset transmission control circuit P10-22 on the second side can be respectively connected to the first decoding output terminal OUT_Z0 to the eighth decoding output terminal OUT_Z7 in the 5-9 decoder 901 from the low bit to the high bit direction; the third offset transmission control circuit P10-23 on the second side and the second forward and reverse scan control terminal GSD2 in the first second offset transmission control circuit P10-22 on the second side to the seventh second offset transmission control circuit P10-22 on the second side can be respectively connected to the inverting output terminal OUT_Z0_ of the first decoding output terminal OUT_Z0 to the inverting output terminal OUT_Z7_ of the eighth decoding output terminal OUT_Z7 in the 5-9 decoder 901 from the low bit to the high bit direction.

[0307] In an exemplary embodiment, as shown in FIG16b, FIG26 and FIG28, in the direction from the first type offset gate driver circuit G101 to the second type offset gate driver circuit G102: the first control terminal K1 of the row control circuit 01 in the first offset gate driver circuit G1021 (Orbit-1) on the second side of the first stage to the first offset gate driver circuit G1021 (Orbit-8) on the second side of the seventh stage can be respectively connected to the second decoding output terminal OUT_Z_1 to the eighth decoding output terminal OUT_Z_ in the 5-8 decoder 902 in the direction from low to high; the second control terminal K2 of the row control circuit 01 in the first offset gate driver circuit G1022 (Orbit-1) on the second side of the first stage to the first offset gate driver circuit G1022 (Orbit-8) on the second side of the eighth stage can be respectively connected to the first decoding output terminal OUT_Z_1 to the eighth decoding output terminal OUT_Z_ in the direction from low to high in the 5-8 decoder 902. The inverting output terminal OUT_Z_1_ of Z_1 is connected to the inverting output terminal OUT_Z_8_ of the eighth decoding output terminal OUT_Z_8; the first forward and reverse scan control terminal GSD1 in the first first offset transmission control circuit P10-21 on the second side to the eighth first offset transmission control circuit P10-21 on the second side can be respectively connected to the first decoding output terminal OUT_Z_1 to the eighth decoding output terminal OUT_Z_8 in the 5-8 decoder 902 in the direction from low to high; the second forward and reverse scan control terminal GSD2 in the first first offset transmission control circuit P10-21 on the second side to the eighth first offset transmission control circuit P10-21 on the second side can be respectively connected to the inverting output terminal OUT_Z_1_ of the first decoding output terminal OUT_Z_1 to the inverting output terminal OUT_Z_8_ of the eighth decoding output terminal OUT_Z_8 in the direction from low to high in the 5-8 decoder 902.

[0308] In an exemplary embodiment, as shown in FIG16a and FIG29 , in the direction from the second-type offset gate driver circuit G102 to the first-type offset gate driver circuit G101, the ninth first-side second reset control terminal IN_T0 and the first first-side first reset control terminal IN_T1 to the eighth first-side first reset control terminal IN_T8 can be respectively connected to the first decoding output terminal OUT_T0 to the ninth decoding output terminal OUT_T8 in the 5-9 logic operation circuit 904, from the low bit to the high bit. In the direction from the first-type offset gate driver circuit G101 to the second-type offset gate driver circuit G102, the second first-side second reset control terminal IN_T_1 to the eighth first-side second reset control terminal IN_T_7 can be respectively connected to the first decoding output terminal OUT_T_1 to the seventh decoding output terminal OUT_T_7 in the 3-7 thermometer decoder 903, from the low bit to the high bit.

[0309] In an exemplary embodiment, as shown in Figures 16b and 29, in the direction from the second type offset gate driver circuit G102 to the first type offset gate driver circuit G101: the second reset control terminal IN_T0_ of the ninth second side, the first reset control terminal IN_T1__ of the first second side to the first reset control terminal IN_T8__ of the ninth second side can be respectively connected to the inverting output terminal OUT_T0_ of the first decoding output terminal OUT_T0 to the inverting output terminal OUT_T8_ of the ninth decoding output terminal OUT_T8 in the 5-9 logic operation circuit 904 in a direction from low bit to high bit. In the direction from the first type offset gate drive circuit G101 to the second type offset gate drive circuit G102: the second reset control terminal IN_T_1_ of the second second side to the second reset control terminal IN_T_7_ of the seventh second side can be respectively connected to the inverting output terminal OUT_T_1_ of the second decoding output terminal OUT_T_1 to the inverting output terminal OUT_T_7_ of the seventh decoding output terminal OUT_T_7 in the 3-7 thermometer decoder 903 in the direction from low to high.

[0310] In an exemplary embodiment, in a standard decoder, the number of input terminals is N, the number of output terminals is M, and the value of M is 2 to the power of N (i.e., M is 2 N ), for example, the above-mentioned standard 5-32 decoder has 5 input terminals (A0 to A4), and the number of output terminals M is 2 to the power of 5 (that is, the number of output terminals is 32, and the output terminals may include Y0 to Y31); the above-mentioned first 3-8 decoder and the second 3-8 decoder are standard 3-8 decoders, and the number of input terminals of the first 3-8 decoder and the second 3-8 decoder is 3 (A0 to A2), and the number of output terminals is 2 to the power of 3 (that is, the number of output terminals is 8), as shown in Figures 27 and 28, the output terminals of the first 3-8 decoder include Y0 to Y7, and the output terminals of the second 3-8 decoder include Y1 to Y8.

[0311] In an exemplary embodiment, as shown in FIG27 , eight first expansion circuits KL1 and one second expansion circuit KL2 are added to a first 3-8 decoder to obtain a non-standard 5-9 decoder 901 as shown in FIG27 . That is, non-standard 5-9 decoder 901 is obtained by expanding the standard first 3-8 decoder. As shown in FIG28 , eight first expansion circuits KL1 are added to a second 3-8 decoder to obtain a non-standard 5-8 decoder 902 as shown in FIG28 . That is, non-standard 5-8 decoder 902 is obtained by expanding the standard second 3-8 decoder. Typically, the cost of a standard 3-to-8-line decoder is lower than that of a standard 5-to-32-line decoder or a 4-to-16-line decoder. Expanding the output terminals of a 3-to-8-line decoder effectively reduces costs. Furthermore, for shift control circuits requiring 17 decoder output terminals, a standard 4-to-16 decoder still lacks one output terminal. Adding an additional decoder or expansion circuit to the standard 4-to-16 decoder costs more than adding an expansion circuit to a standard 3-to-8 decoder. Therefore, adding expansion circuits to two standard 3-to-8 decoders can reduce costs. As shown in Figures 26 and 28, adding expansion circuit KL to two standard 3-to-8 decoders reduces costs while fully utilizing the output terminals of the standard 3-to-8 decoder, improving output utilization.

[0312] An exemplary embodiment of the present disclosure provides an operating method for a gate device, which is applied to the gate driving device described in any of the above embodiments. The gate driving device includes a shift control circuit and a multi-stage cascaded gate driving circuit. In the cascade direction of the multi-stage gate driving circuit, the multi-stage gate driving circuit includes a 4S+2-stage offset gate driving circuit and an m-stage intermediate gate driving circuit. The 4S+2-stage offset gate driving circuit includes a 2S+1-stage first-type offset gate driving circuit located on one side of the m-stage intermediate gate driving circuit, and a 2S+1-stage second-type offset gate driving circuit located on the other side of the m-stage intermediate gate driving circuit. m and S are both positive integers. The shift control circuit is electrically connected to the 4S+2-stage offset gate driving circuit. The operating method includes:

[0313] The shift control circuit outputs an initial row control signal to the 4S+2-level offset gate drive circuit. Under the control of the initial row control signal, one level is selected from the 2S+1-level first-level offset gate drive circuit as the first-level initial gate drive circuit, and one level is selected from the 2S+1-level second-level offset gate drive circuit as the second-level initial gate drive circuit; in the direction of the cascade of the multi-level gate drive circuits, the offset direction of the first-level initial gate drive circuit and the second-level initial gate drive circuit relative to the m-level intermediate gate drive circuit are consistent, and the number of offset levels relative to the m-level intermediate gate drive circuits is N, where N is an integer less than or equal to S.

[0314] An exemplary embodiment of the present disclosure provides a display substrate, as shown in Figure 31, the display substrate may include a display area and a non-display area; the display area includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area includes the gate driving device described in any of the above embodiments, the gate driving device includes a plurality of cascaded gate driving circuits, and at least one gate driving circuit is connected to the scanning signal line in the display area.

[0315] The exemplary embodiments of the present disclosure further provide a display device, as shown in FIG32 , which may include the aforementioned display substrate. The display device provided in the embodiments of the present disclosure can be used in virtual reality (VR) devices, augmented reality (AR) devices, extended reality (XR) devices, mixed reality (MR) devices, sights and rangefinders, computers, mobile phones, wearable devices, electronic viewfinders (EVF), first person view (FPV) devices, drones, thermal imagers, night vision devices, infrared cameras, medical equipment, etc.

[0316] The present disclosure provides a gate drive device and operating method thereof, a display substrate, and a display device. In the gate drive device, a shift control circuit is electrically connected to a 4S+2-stage offset gate drive circuit and configured to output an initial row control signal to the 4S+2-stage offset gate drive circuit. Under the control of the initial row control signal, one stage is selected from the 2S+1-stage first-stage offset gate drive circuit as the first-stage initial gate drive circuit, and one stage is selected from the 2S+1-stage second-stage offset gate drive circuit as the second-stage initial gate drive circuit. In the direction of the cascade of the multi-stage gate drive circuits, the first-stage initial gate drive circuit and the second-stage initial gate drive circuit are offset in the same direction relative to the m-stage intermediate gate drive circuits, and the number of offset stages relative to the m-stage intermediate gate drive circuits is N. The technical solution provided by the embodiments of the present disclosure can shift the first-stage initial shift register circuit and the second-stage initial shift register circuit, thereby achieving pixel-level alignment or preventing incomplete displayed images due to occlusion.

[0317] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A gate drive device comprising a shift control circuit and a multi-stage cascaded gate drive circuit, wherein the multi-stage gate drive circuit comprises a 4S+2-stage offset gate drive circuit and m-stage intermediate gate drive circuits, wherein in the direction of the cascade connection of the multi-stage gate drive circuits, the 4S+2-stage offset gate drive circuit comprises a 2S+1-stage first-type offset gate drive circuit located on one side of the m-stage intermediate gate drive circuit, and a 2S+1-stage second-type offset gate drive circuit located on the other side of the m-stage intermediate gate drive circuit, where m and S are both positive integers; The shift control circuit is electrically connected to the 4S+2-level offset gate drive circuit and is configured to output an initial row control signal to the 4S+2-level offset gate drive circuit. Under the control of the initial row control signal, one level is selected from the 2S+1-level first-level offset gate drive circuit as the first-level initial gate drive circuit, and one level is selected from the 2S+1-level second-level offset gate drive circuit as the second-level initial gate drive circuit; in the direction of the cascade of the multi-level gate drive circuits, the offset direction of the first-level initial gate drive circuit and the second-level initial gate drive circuit relative to the m-level intermediate gate drive circuit are consistent, and the number of offset levels relative to the m-level intermediate gate drive circuits is N, where N is an integer less than or equal to S.

2. The gate driving device according to claim 1, wherein: The offset gate drive circuit includes a row control circuit, an offset shift register circuit, an initial signal terminal and a row control terminal; in the row control circuit, an input terminal is connected to the initial signal terminal, a control terminal is connected to the row control terminal, and an output terminal is connected to the input terminal of the offset shift register circuit; The row control circuit is configured to receive a forward and reverse scan control signal from the row control end, and to receive an initial signal from the initial signal end. Under the control of the forward and reverse scan control signal, one of the first type of initial gate drive circuit and the second type of initial gate drive circuit is used as the starting row of the gate drive circuit, and the other is used as the cutting-off row of the gate drive circuit, and the initial signal is provided to the starting row of the gate drive circuit.

3. The gate driving device according to claim 2, wherein: The row control circuit includes a forward and reverse scan control circuit, the forward and reverse scan control circuit includes a third control terminal and a fourth control terminal, the row control terminal includes a first transmission control terminal and a second transmission control terminal, in the first type of offset gate drive circuit, the third control terminal in the forward and reverse scan control circuit is electrically connected to the second transmission control terminal, and the fourth control terminal is electrically connected to the first transmission control terminal; in the second type of offset gate drive circuit, the third control terminal in the forward and reverse scan control circuit is electrically connected to the first transmission control terminal, and the fourth control terminal is electrically connected to the second transmission control terminal; The input end of the forward and reverse scan control circuit is electrically connected to the initial signal end, and the output end is electrically connected to the input end of the corresponding offset shift register circuit.

4. The gate driving device according to claim 3, wherein: The row control circuit includes an initial row control circuit, the initial row control circuit includes a first control terminal and a second control terminal, the row control terminals include 2S+1 first-type initial row control terminals and 2S+1 second-type initial row control terminals; the first control terminals in the 2S+1-level first-type offset gate drive circuits are respectively electrically connected to the 2S+1 first-type initial row control terminals, and the second control terminals in the 2S+1-level first-type offset gate drive circuits are respectively electrically connected to the 2S+1 second-type initial row control terminals; the first control terminals in the 2S+1-level second-type offset gate drive circuits are respectively electrically connected to the 2S+1 first-type initial row control terminals, and the second control terminals in the 2S+1-level second-type offset gate drive circuits are respectively electrically connected to the 2S+1 second-type initial row control terminals; The input end of the initial row control circuit is connected to the initial signal end, and the output end is electrically connected to the input end of the corresponding forward and reverse scan control circuit; the input end of the forward and reverse scan control circuit is electrically connected to the initial signal end through the corresponding initial row control circuit.

5. The gate driving device according to claim 4, wherein: The shift control circuit includes a logic decoding circuit, which includes 2S+1 decoding result output terminals and inverting output terminals of the 2S+1 decoding result output terminals. The 2S+1 decoding result output terminals serve as the 2S+1 first-type initial row control terminals, and the inverting output terminals of the 2S+1 decoding result output terminals serve as the 2S+1 second-type initial row control terminals.

6. The gate driving device according to claim 5, wherein: The logic decoding circuit is a standard decoder, and the number of decoding result output terminals of the standard decoder is greater than or equal to 2S+1; In the direction from low to high, the first decoding result output terminal to the 2S+1 decoding result output terminal serve as the first first-type initial row control terminal to the 2S+1 first-type initial row control terminal in the direction from the first-type offset gate drive circuit to the second-type offset gate drive circuit, respectively; In the direction from low bit to high bit, the inverting output end of the first decoding result output end to the inverting output end of the 2S+1 decoding result output end respectively serve as the first second type initial row control end to the 2S+1 second type initial row control end in the direction from the first type offset gate drive circuit to the second type offset gate drive circuit.

7. The gate driving device according to claim 5, wherein: The 2S+1-stage first-type offset gate drive circuit includes 2S first-side offset transmission control circuits. The first-side offset shift register circuits of two adjacent stages are cascade-connected via one of the first-side offset transmission control circuits. In the direction from the first-type offset gate drive circuit to the second-type offset gate drive circuit, in the first-side offset shift register circuits of two adjacent stages, the input end of the first-side offset transmission control circuit is connected to the output end of the first-side offset shift register circuit of the previous stage, and the output end of the first-side offset transmission control circuit is connected to the input end of the first-side offset shift register circuit of the next stage. The offset transmission control circuit on the first side includes a first forward and reverse scan control terminal and a second forward and reverse scan control terminal. In the offset transmission control circuit on the first side, the first forward and reverse scan control terminal is electrically connected to the corresponding second type initial row control terminal, and the second forward and reverse scan control terminal is electrically connected to the corresponding first type initial row control terminal.

8. The gate driving device according to claim 7, wherein: In the direction from the first type of offset gate drive circuit to the second type of offset gate drive circuit, the first positive and negative scan control terminals of the first first-side offset transmission control circuit to the 2S first-side offset transmission control circuit are respectively electrically connected to the second decoding result output terminal to the 2S+1 decoding result output terminal in the direction from low bit to high bit, and the second positive and negative scan control terminals of the first first-side offset transmission control circuit to the 2S first-side offset transmission control circuit are respectively electrically connected to the inverting output terminal of the second decoding result output terminal to the inverting output terminal of the 2S+1 decoding result output terminal in the direction from low bit to high bit.

9. The gate driving device according to claim 5, wherein: The 2S+1-stage second-type offset gate drive circuit includes 2S second-side offset transmission control circuits. The second-side offset shift register circuits of two adjacent stages are cascade-connected via one of the second-side offset transmission control circuits. In the direction from the second-type offset gate drive circuit to the first-type offset gate drive circuit, in the second-side offset shift register circuits of two adjacent stages, the input end of the second-side offset transmission control circuit is connected to the output end of the second-side offset shift register circuit of the previous stage, and the output end of the second-side offset transmission control circuit is connected to the input end of the second-side offset shift register circuit of the next stage. The offset transmission control circuit on the second side includes a first forward and reverse scan control terminal and a second forward and reverse scan control terminal. In the offset transmission control circuit on the second side, the first forward and reverse scan control terminal is electrically connected to the corresponding first type initial row control terminal, and the second forward and reverse scan control terminal is electrically connected to the corresponding second type initial row control terminal.

10. The gate driving device according to claim 9, wherein: In the direction from the first type of offset gate drive circuit to the second type of offset gate drive circuit, the second forward and reverse scan control terminals of the first second-side offset transmission control circuit to the 2S second-side offset transmission control circuit are respectively electrically connected to the second decoding result output terminal to the 2S+1 decoding result output terminal in the direction from low bit to high bit, and the first forward and reverse scan control terminals of the first second-side offset transmission control circuit to the 2S second-side offset transmission control circuit are respectively electrically connected to the inverting output terminal of the second decoding result output terminal to the inverting output terminal of the 2S+1 decoding result output terminal in the direction from low bit to high bit.

11. The gate driving device according to claim 2, wherein: The gate drive circuit also includes an offset row drive enhancement circuit, a reset control circuit and a reset control terminal; the offset row drive enhancement circuit is located in the corresponding offset gate drive circuit, and in the offset row drive enhancement circuit, the input terminal is electrically connected to the output terminal of the corresponding offset shift register circuit, the output terminal is electrically connected to the corresponding pixel drive circuit in the display area, and the enable signal terminal is connected to the corresponding reset control circuit; in the reset control circuit, the input terminal is connected to the corresponding reset control terminal, the output terminal is connected to the enable signal terminal in the corresponding offset row drive enhancement circuit, and is configured to receive a reset control signal from the reset control terminal, and under the control of the reset control signal, the corresponding offset row drive enhancement circuit is set to a high-impedance state.

12. The gate driving device according to claim 11, wherein: The shift control circuit includes a decoding logic circuit and 2S cascade-connected half-adder logic circuits, wherein the output terminals of the half-adder logic circuit include a sum output terminal and a carry output terminal, and the input terminals of the half-adder logic circuit include an addend input terminal and an augend input terminal; the decoding logic circuit includes 2S+1 decoding result output terminals; In the direction from low to high, among the 2S+1 decoding result output terminals, the inverting output terminal of the first decoding result output terminal is electrically connected to the addend input terminal of the first half adder logic circuit, and the second decoding result output terminal to the 2S decoding result output terminals are electrically connected to the summand input terminal of the second half adder logic circuit to the summand input terminal of the 2S half adder logic circuit, respectively, and the input value of the summand input terminal of the first-stage half adder logic circuit is always 1; and among the 2S half adders, the carry output terminal of the upper-stage half adder logic circuit is connected to the addend input terminal of the lower-stage half adder logic circuit.

13. The gate driving device according to claim 12, wherein: In the direction from the 2S+1-level first-class offset gate driving circuit to the m-level intermediate offset gate driving circuit, the reset control terminal includes first to 2S first-class reset control terminals electrically connected to the reset control circuits in the first-level first-class offset gate driving circuit to the 2S-level first-class offset gate driving circuit, respectively; In the direction from low to high, the sum output terminal of the first half adder logic circuit to the sum output terminal of the 2Sth half adder logic circuit serve as the first first type reset control terminal to the 2Sth first type reset control terminal respectively.

14. The gate driving device according to claim 12, wherein: In the direction from the 2S+1-level first-type offset gate driving circuit to the m-level middle offset gate driving circuit, the reset control terminal includes first to 2S second-type reset control terminals electrically connected to the reset control circuits in the second-level second-type offset gate driving circuit to the 2S+1-level second-type offset gate driving circuit, respectively; In the direction from low bit to high bit, the carry output terminal of the first half adder logic circuit to the carry output terminal of the 2Sth half adder logic circuit serve as the first second type reset control terminal to the 2Sth second type reset control terminal respectively.

15. The gate driving device according to any one of claims 1 to 14, wherein: The value of S is 8, the shift control circuit includes a decoding logic circuit, the decoding logic circuit is a standard 5-32 decoder, and the 2S+1 decoding result output terminals are respectively the 17 low-order decoding result output terminals of the standard 5-32 decoder.

16. The gate driving device according to claim 5, wherein: The logic decoding circuit includes at least one 3-line to 8-line decoder, 2S+1 expansion circuits and at least one expansion input terminal. The number of the output terminals of the at least one 3-line to 8-line decoder is 2S+1. The input terminal of the logic decoding circuit includes three input terminals of the 3-line to 8-line decoder and the at least one expansion input terminal. The input terminals of the 2S+1 expansion circuits are connected to the 2S+1 output terminals of the at least one 3-line to 8-line decoder. The output terminals of the 2S+1 expansion circuits serve as the 2S+1 output terminals of the logic decoding circuit respectively.

17. The gate driving device according to claim 16, wherein: The value of S is 8. The logic decoding circuit includes two 3-8 decoders, seventeen expansion circuits and two expansion input terminals. The two expansion input terminals include a first expansion input terminal and a second expansion input terminal. The three input terminals of one 3-line-8-line decoder serve as the first input terminal to the third input terminal of the logic decoding circuit, the first expansion input terminal serves as the fourth input terminal of the logic decoding circuit, the second expansion input terminal serves as the fifth input terminal of the logic decoding circuit, and the inverting output terminal from the first input terminal to the third input terminal serves as the input terminal of the other 3-line-8-line decoder.

18. The gate driving device according to claim 17, wherein: The two 3-8 decoders include a first 3-8 decoder and a second 3-8 decoder, and the seventeen expansion circuits include sixteen first expansion circuits and one second expansion circuit; The first 3-8 decoder, eight of the first expansion circuits, one second expansion circuit, and the two expansion input terminals constitute a 5-9 decoder; the second 3-8 decoder, another eight first expansion circuits, and the two expansion input terminals constitute a 5-8 decoder.

19. The gate driving device according to claim 18, wherein: The 5-9 decoder includes nine decoding output terminals and inverting output terminals of the nine decoding output terminals, and the 5-8 decoder includes eight decoding output terminals and inverting output terminals of the eight decoding output terminals; The 2S+1 first-type initial row control terminals include the nine decoding output terminals of the 5-9 decoder and the eight decoding output terminals of the 5-8 decoder; the 2S+1 second-type initial row control terminals include the inverting output terminals of the nine decoding output terminals of the 5-9 decoder and the inverting output terminals of the eight decoding output terminals of the 5-8 decoder.

20. The gate driving device according to claim 19, wherein: Of the nine decoding output terminals of the 5-9 decoder, in the direction from high to low, the first decoding output terminal to the ninth decoding output terminal serve as the first first-class initial row control terminal to the ninth first-class initial row control terminal in the direction from the first-class offset gate drive circuit to the second-class offset gate drive circuit, respectively; Among the eight decoding output terminals of the 5-8 decoder, from the high bit to the low bit, the first decoding output terminal to the eighth decoding output terminal serve as the direction from the second type offset gate drive circuit to the first type offset gate drive circuit. The first first-class initial row control terminal to the eighth first-class initial row control terminal.

21. The gate driving device according to claim 19, wherein: Among the inverted output terminals of the nine decoding output terminals of the 5-9 decoder, in the direction from high to low, the inverted output terminals of the first decoding output terminal to the inverted output terminals of the ninth decoding output terminal serve as the first to the ninth second-type initial row control terminals in the direction from the first-type offset gate drive circuit to the second-type offset gate drive circuit, respectively; Among the inverting output ends of the eight decoding output ends of the 5-8 decoder, in the direction from high to low, the inverting output end of the first decoding output end to the inverting output end of the eighth decoding output end serve as the first second-class initial row control end to the eighth second-class initial row control end in the direction from the second-class offset gate drive circuit to the first-class offset gate drive circuit, respectively.

22. The gate driving device according to claim 11, wherein: The value of S is 8, and the shift control circuit includes a 3-7 thermometer decoder and a 5-9 logic operation circuit; In the direction from the 2S+1-level first-class offset gate driving circuit to the m-level intermediate offset gate driving circuit, the reset control terminal includes first to 2S first-class reset control terminals electrically connected to the reset control circuits in the first-level first-class offset gate driving circuit to the 2S-level first-class offset gate driving circuit, respectively; Among the nine output terminals of the 5-9 logic operation circuit, in the direction from high to low, the first output terminal to the ninth output terminal serve as the first first-class reset control terminal to the ninth first-class reset control terminal respectively; Among the seven output terminals of the 3-7 thermometer decoder, in the direction from low to high, the first output terminal to the seventh output terminal serve as the tenth first-class reset control terminal to the sixteenth first-class reset control terminal respectively.

23. The gate driving device according to claim 22, wherein: In the direction from the 2S+1-level first-type offset gate driving circuit to the m-level middle offset gate driving circuit, the reset control terminal includes first to 2S second-type reset control terminals electrically connected to the reset control circuits in the second-level second-type offset gate driving circuit to the 2S+1-level second-type offset gate driving circuit, respectively; Among the inverting output terminals of the nine output terminals of the 5-9 logic operation circuit, in the direction from high to low, the inverting output terminal of the first output terminal to the inverting output terminal of the ninth output terminal serve as the first second-type reset control terminal to the ninth second-type reset control terminal respectively; Among the inverting output terminals of the seven output terminals of the 3-7 thermometer decoder, in the direction from low to high, the inverting output terminal of the first output terminal to the inverting output terminal of the seventh output terminal serve as the tenth second-type reset control terminal to the sixteenth second-type reset control terminal respectively.

24. The gate driving device according to any one of claims 11 to 14 and 22 to 24, wherein: The offset shift register circuit also includes an enable signal terminal, and the output terminal of the reset control circuit is also electrically connected to the enable signal terminal of the corresponding offset shift register circuit, and is configured to receive a reset control signal from the reset control terminal. Under the control of the reset control signal, the corresponding offset shift register circuit is set to a high-impedance state.

25. A gate device operating method, applied to the gate drive device according to any one of claims 1 to 24, the gate drive device comprising a shift control circuit and a multi-stage cascaded gate drive circuit, wherein in the direction of the cascade of the multi-stage gate drive circuit, the multi-stage gate drive circuit comprises a 4S+2-stage offset gate drive circuit and m-stage intermediate gate drive circuits, the 4S+2-stage offset gate drive circuit comprising a 2S+1-stage first-type offset gate drive circuit located on one side of the m-stage intermediate gate drive circuit, and a 2S+1-stage second-type offset gate drive circuit located on the other side of the m-stage intermediate gate drive circuit, wherein m and S are both positive integers, and the shift control circuit is electrically connected to the 4S+2-stage offset gate drive circuit; the operating method comprising: The shift control circuit outputs an initial row control signal to the 4S+2-level offset gate drive circuit. Under the control of the initial row control signal, one level is selected from the 2S+1-level first-level offset gate drive circuit as the first-level initial gate drive circuit, and one level is selected from the 2S+1-level second-level offset gate drive circuit as the second-level initial gate drive circuit; in the direction of the cascade of the multi-level gate drive circuits, the offset direction of the first-level initial gate drive circuit and the second-level initial gate drive circuit relative to the m-level intermediate gate drive circuit are consistent, and the number of offset levels relative to the m-level intermediate gate drive circuits is N, where N is an integer less than or equal to S.

26. A display substrate comprising a display area and a non-display area; the display area comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and at least one scanning signal line, the scanning signal line being configured to provide a scanning signal to the connected pixel driving circuit; the non-display area comprises a gate driving device as described in any one of claims 1 to 24, the gate driving device comprises a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area.

27. A display device comprising the display substrate according to claim 26.

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