Power supply and load changeover circuit, low-noise amplifier and electronic device

Abstract

The present application relates to the technical field of electronic devices, and discloses a power supply and load changeover circuit, a low-noise amplifier and an electronic device. The power supply and load changeover circuit comprises at least two power supplies, a changeover switch, at least two loads and at least two output ports; at least two ports of the changeover switch are electrically connected to the at least two power supplies, respectively, and at least two other ports of the changeover switch are electrically connected to the at least two output ports, respectively so as to be used for changing over and turning on at least four power supply paths; and the at least two loads are respectively arranged on paths between the at least two power supplies and the at least two output ports so as to adjust the load impedance values of the at least four power supply paths. On the basis of the solution of the present invention, the linearity, the power consumption and the working frequency band of the low-noise amplifier can be adjusted, so that the low-noise amplifier can obtain more different performance modes.

Description

Power supply and load switching circuits, low noise amplifiers and electronic devices

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 10, 2024, with application number 202410033939.1 and application name “Power supply and load switching circuit, low noise amplifier and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of electronic equipment, and in particular to a power supply and load switching circuit, a low-noise amplifier, and an electronic device. Background Art

[0003] In the RF receive links of wireless communication applications such as cellular, wireless fidelity (Wi-Fi), and satellite communications, low-noise amplifiers (LNAs) are often used to receive downlink signals in complex environments. Different application scenarios often require different performance for LNAs. For example, satellite communications typically place higher demands on linearity and noise, while cellular communications typically place higher demands on noise and power consumption.

[0004] Currently, the linearity and power consumption of a low-noise amplifier are generally adjusted by switching between two power supplies. However, there are relatively few adjustable performance modes, which cannot meet the requirements of more application scenarios of the low-noise amplifier.

[0005] Therefore, a new solution is urgently needed to solve the above problems.

[0006] Summary of the Invention

[0007] The present application provides a power supply and load switching circuit, a low-noise amplifier, and an electronic device. By switching multiple power supplies and multiple loads, the linearity, power consumption, and operating frequency band of the low-noise amplifier are adjusted, thereby enabling the low-noise amplifier to obtain more different performance modes.

[0008] To achieve the above objectives, this application adopts the following technical solutions:

[0009] In a first aspect, a power supply and load switching circuit is provided, comprising at least two power supplies, a switching switch, at least two loads, and at least two output ports; at least two ports of the switching switch are electrically connected to the at least two power supplies, respectively, and at least two other ports of the switching switch are electrically connected to the at least two output ports, respectively, for switching and conducting at least four power supply paths; the at least two loads are respectively arranged in paths between the at least two power supplies and the at least two output ports, for adjusting the load impedance values ​​of the at least four power supply paths.

[0010] In an embodiment of the present application, by switching different power supply paths of at least two power supplies, at least four performance modes with different linearity and power consumption can be obtained, and by switching different impedance values ​​of at least two loads, at least two performance modes with different operating frequency bands can be obtained, thereby enabling the low-noise amplifier to obtain more different performance modes.

[0011] In combination with the first aspect, in certain implementations of the first aspect, the at least two loads include a first load inductor and a second load inductor; the first load inductor and the second load inductor are respectively arranged in the path between the at least two power supplies and the switching switch.

[0012] In this implementation, the first load inductor and the second load inductor are respectively arranged in the path between at least two power supplies and the switching switch, so that the impedance value between the at least two power supplies and the switching switch can be adjusted, thereby adjusting the operating frequency band of the low-noise amplifier, so that the low-noise amplifier can obtain more different performance modes.

[0013] Optionally, the inductance value of the first load inductor and the inductance value of the second load inductor may be the same or different.

[0014] In combination with the first aspect, in some implementations of the first aspect, the first load inductor and the second load inductor are coupled.

[0015] In this implementation, when the first load inductor and the second load inductor are coupled, the impedance values ​​between at least two power supplies and the switching switch can be readjusted, thereby readjusting the operating frequency band of the low-noise amplifier, so that the low-noise amplifier can obtain more different performance modes.

[0016] In combination with the first aspect, in certain implementations of the first aspect, the at least two loads include a third load inductor and a fourth load inductor; the third load inductor and the fourth load inductor are respectively arranged in the path between the switching switch and the at least two output ports.

[0017] Optionally, the inductance value of the third load inductor and the inductance value of the fourth load inductor may be the same or different.

[0018] In this implementation, the third load inductor and the fourth load inductor are respectively arranged in the path between the switching switch and the at least two output ports, so that the impedance value between the switching switch and the at least two output ports can be adjusted, thereby adjusting the operating frequency band of the low-noise amplifier, so that the low-noise amplifier can obtain more different performance modes.

[0019] In combination with the first aspect, in some implementations of the first aspect, the third load inductor and the fourth load inductor are coupled.

[0020] In this implementation, when the third load inductor and the fourth load inductor are coupled, the impedance value between the switching switch and at least two output ports can be readjusted, thereby readjusting the operating frequency band of the low-noise amplifier, so that the low-noise amplifier can obtain more different performance modes.

[0021] In combination with the first aspect, in certain implementations of the first aspect, the at least two loads include a first load inductor, a second load inductor, a third load inductor, and a fourth load inductor; the first load inductor and the second load inductor are respectively arranged in the path between the at least two power supplies and the switching switch, the third load inductor and the fourth load inductor are respectively arranged in the path between the switching switch and the at least two output ports, and any two of the first load inductor, the second load inductor, the third load inductor, and the fourth load inductor are coupled to each other.

[0022] In this implementation, by respectively arranging the first load inductor, the second load inductor, the third load inductor, and the fourth load inductor in the paths between at least two power supplies and at least two output ports, and by establishing a coupling relationship between any two of the first load inductor, the second load inductor, the third load inductor, and the fourth load inductor, the impedance value between the at least two power supplies and the at least two output ports can be adjusted, thereby adjusting the operating frequency band of the low-noise amplifier, so that the low-noise amplifier can obtain more different performance modes.

[0023] Optionally, the inductance value of the first load inductor, the inductance value of the second load inductor, the inductance value of the third load inductor, and the inductance value of the fourth load inductor may be the same or different.

[0024] In combination with the first aspect, in certain implementations of the first aspect, the at least two power supplies include a first power supply and a second power supply; the first power supply and the second power supply are respectively electrically connected to at least two ports of the switching switch, and the voltage value of the first power supply is greater than the voltage value of the second power supply.

[0025] In this implementation, since the voltage value of the first power supply is different from the voltage value of the second power supply, the low noise amplifier can obtain a variety of performance modes with different linearity and power consumption.

[0026] In combination with the first aspect, in certain implementations of the first aspect, the switching switch includes a double-pole double-throw switch, and the at least two output ports include a first output port and a second output port; the two ports of the double-pole double-throw switch are electrically connected to the first power supply and the second power supply, respectively, and the other two ports of the double-pole double-throw switch are electrically connected to the first output port and the second output port, respectively.

[0027] In this implementation, the switch uses a double-pole double-throw switch, so that at least two power supplies can be switched into at least four power supply channels, so that the low-noise amplifier can obtain multiple performance modes with different linearity and power consumption.

[0028] In combination with the first aspect, in certain implementations of the first aspect, the two switch paths connecting the double-pole double-throw switch to the first power supply are respectively connected with m switch devices in parallel, and the two switch paths connecting the double-pole double-throw switch to the second power supply are respectively connected with n switch devices in parallel, where m≥n.

[0029] In this implementation, by connecting m switching devices in parallel to each of the two switching paths connecting the double-pole double-throw switch to the first power source, the conduction loss of the switch can be reduced. By connecting n switching devices in parallel to each of the two switching paths connecting the double-pole double-throw switch to the second power source, the conduction loss of the switch can be reduced. Furthermore, because the voltage of the first power source is greater than that of the second power source, m ≥ n can be set to accommodate conduction losses at different power source voltages.

[0030] Optionally, the switching device may be a metal oxide semiconductor field effect transistor (MOSFET).

[0031] In a second aspect, a low noise amplifier is provided, comprising the power supply and load switching circuit.

[0032] In an embodiment of the present application, by switching different power supply paths of at least two power supplies in the power supply and load switching circuit, at least four performance modes with different linearity and power consumption can be obtained. By switching different impedance values ​​of at least two loads, at least two performance modes with different operating frequency bands can be obtained, thereby enabling the low-noise amplifier to obtain more different performance modes.

[0033] In combination with the second aspect, in some implementations of the second aspect, the low-noise amplifier further includes a low-noise amplification module; the low-noise amplification module is electrically connected to the power supply and load switching circuit for performing low-noise amplification on the input signal.

[0034] In an embodiment of the present application, a power supply and load switching circuit is used to provide a low-noise amplifier module with power supplies of different voltage values ​​and loads of different impedance values, and the low-noise amplifier module performs low-noise amplification on the input signal, thereby enabling the low-noise amplifier to obtain more different performance modes.

[0035] In combination with the second aspect, in some implementations of the second aspect, the low-noise amplification module includes a first amplifier, a second amplifier, a bias circuit and a controller; the power supply and load switching circuit are electrically connected to the first amplifier, the second amplifier and the controller, respectively, and the first amplifier and the second amplifier are also electrically connected to the bias circuit; the first amplifier is configured to amplify the first input signal; the second amplifier is configured to amplify the second input signal; the bias circuit is configured to provide a bias voltage to the first amplifier and the second amplifier; and the controller is configured to provide a mode switching signal to the power supply and load switching module.

[0036] In an embodiment of the present application, by electrically connecting the first amplifier and the second amplifier to at least two output ports in the power supply and load switching circuit respectively, the first amplifier and the second amplifier can respectively obtain performance modes with different linearity, power consumption and operating frequency bands, thereby enabling the low-noise amplifier to obtain more different performance modes.

[0037] In combination with the second aspect, in certain implementations of the second aspect, the first amplifier includes a first transistor, a second transistor, a first input inductor, a first source inductor, a first input port, and a first output port; the bias circuit outputs a first bias voltage and a second bias voltage; the gate of the first transistor is connected to the first input port through the first input inductor, the source of the first transistor is grounded through the first source inductor, the drain of the first transistor is electrically connected to the source of the second transistor, the drain of the second transistor is electrically connected to the first output port, the gate of the first transistor is connected to the first bias voltage, and the gate of the second transistor is connected to the second bias voltage.

[0038] In an embodiment of the present application, a common-source and common-gate amplifier is formed by a first transistor and a second transistor to amplify a first input signal, impedance matching is performed on the first input signal through a first input inductor, and the gain of the first amplifier is adjusted through a first source inductor. In combination with a power supply and a load switching circuit having multiple performance modes, the low-noise amplifier can obtain more different performance modes.

[0039] In combination with the second aspect, in some implementations of the second aspect, the first amplifier further includes a first bias network and a second bias network; the first bias network is connected between the gate of the first transistor and the first bias voltage, and the second bias network is connected between the second transistor and the second bias voltage.

[0040] In this implementation, the first bias network isolates the current impact of the first bias voltage on the first transistor, and the second bias network isolates the current impact of the second bias voltage on the second transistor.

[0041] In combination with the second aspect, in certain implementations of the second aspect, the first amplifier further includes a first input capacitor, a first gate bias capacitor, and a first output capacitor; the first input capacitor is connected between the gate of the first transistor and the first input inductor, the first gate bias capacitor is connected between the gate of the second transistor and the ground terminal, and the first output capacitor is connected between the drain of the second transistor and the first output port.

[0042] In this implementation, the first output capacitor and the first input inductor are used to perform impedance matching on the first input signal, the first gate bias capacitor is used to filter the bias voltage of the second transistor, and the first output capacitor is used to filter the output signal.

[0043] In combination with the second aspect, in certain implementations of the second aspect, the first amplifier further includes a fifth switch and a sixth switch; the fifth switch is connected between the gate of the second transistor and the ground terminal, the sixth switch is connected between the gate of the second transistor and the second bias voltage, and the fifth switch and the sixth switch are also electrically connected to the controller respectively.

[0044] In this implementation, the fifth switch controls the on / off connection between the second transistor and the ground terminal, and the sixth switch controls the on / off connection between the second transistor and the bias circuit.

[0045] In combination with the second aspect, in some implementations of the second aspect, the first amplifier further includes a first auxiliary path; the two ends of the first auxiliary path are electrically connected to the source of the second transistor and the gate of the second transistor, respectively, and the first auxiliary path is also electrically connected to the controller.

[0046] In this implementation, when the second transistor works as a switching device, the second transistor can be directly bypassed through the first auxiliary path, thereby reducing the power consumption of the path caused by the second transistor.

[0047] In combination with the second aspect, in certain implementations of the second aspect, the second amplifier includes a third transistor, a fourth transistor, a second input inductor, a second source inductor, a second input port, and a second output port; the bias circuit outputs a third bias voltage and a fourth bias voltage; the gate of the third transistor is connected to the second input port through the second input inductor, the source of the third transistor is grounded through the second source inductor, the drain of the third transistor is electrically connected to the source of the fourth transistor, the drain of the fourth transistor is electrically connected to the second output port, the gate of the third transistor is connected to the third bias voltage, and the gate of the fourth transistor is connected to the fourth bias voltage.

[0048] In an embodiment of the present application, a common-source common-gate amplifier is formed by a third transistor and a fourth transistor to amplify the second input signal, impedance matching is performed on the second input signal through a second input inductor, and the gain of the second amplifier is adjusted through a second source inductor. In combination with a power supply and load switching circuit having multiple performance modes, the low-noise amplifier can obtain more different performance modes.

[0049] In combination with the second aspect, in some implementations of the second aspect, the second amplifier further includes a third bias network and a fourth bias network; the third bias network is connected between the gate of the third transistor and the third bias voltage, and the fourth bias network is connected between the fourth transistor and the fourth bias voltage.

[0050] In this implementation, the third bias network isolates the current impact of the third bias voltage on the third transistor, and the fourth bias network isolates the current impact of the fourth bias voltage on the fourth transistor.

[0051] In combination with the second aspect, in some implementations of the second aspect, the second amplifier further includes a second input capacitor, a second gate bias capacitor, and a second output capacitor; the second input capacitor is connected between the gate of the third transistor and the second input inductor, the second gate bias capacitor is connected between the gate of the fourth transistor and the ground terminal, and the second output capacitor is connected between the drain of the fourth transistor and the second output port.

[0052] In this implementation, the second input signal is impedance matched by the second output capacitor and the second input inductor, the bias voltage of the fourth transistor is filtered by the second gate bias capacitor, and the output signal is filtered by the second output capacitor.

[0053] In combination with the second aspect, in certain implementations of the second aspect, the second amplifier further includes a seventh switch and an eighth switch; the seventh switch is connected between the gate of the fourth transistor and the ground terminal, the eighth switch is connected between the gate of the fourth transistor and the fourth bias voltage, and the seventh switch and the eighth switch are also electrically connected to the controller respectively.

[0054] In this implementation, the seventh switch controls the on / off connection between the fourth transistor and the ground terminal, and the eighth switch controls the on / off connection between the fourth transistor and the bias circuit.

[0055] In combination with the second aspect, in certain implementations of the second aspect, the second amplifier further includes a second auxiliary path; the two ends of the second auxiliary path are electrically connected to the source of the fourth transistor and the gate of the fourth transistor, respectively, and the second auxiliary path is also electrically connected to the controller.

[0056] In the embodiment of the present application, when the fourth transistor works as a switching device, the fourth transistor can be directly bypassed through the second auxiliary path, thereby reducing the flow power consumption caused by the fourth transistor to the path.

[0057] In combination with the second aspect, in some implementations of the second aspect, the low-noise amplifier further includes a first carrier board and a first chip; the low-noise amplification module and the power supply and load switching circuit are integrated into the first chip, and the first chip is disposed on the first carrier board.

[0058] In the embodiment of the present application, the low-noise amplifier module is integrated with the power supply and load switching circuit into the same chip, thereby reducing the area of ​​the low-noise amplifier and facilitating assembly with other devices.

[0059] In combination with the second aspect, in certain implementations of the second aspect, the low-noise amplifier further includes a second carrier board, a second chip, and a third chip; the low-noise amplification module and the power supply and load switching circuit are respectively integrated in the second chip and the third chip, and the second chip and the third chip are arranged on the second carrier board.

[0060] In an embodiment of the present application, the low-noise amplifier module and the power supply and load switching circuit are integrated into different chips, respectively, so that the low-noise amplifier module and the power supply and load switching circuit can be easily modified or replaced.

[0061] In combination with the second aspect, in certain implementations of the second aspect, the low-noise amplifier further includes a third carrier board, a fourth chip, and a fifth chip; the low-noise amplification module and the power supply and load switching circuit are respectively integrated in the fourth chip and the fifth chip, and the fourth chip and the fifth chip are stacked on the third carrier board.

[0062] In the embodiment of the present application, the low noise amplifier module is integrated with the power supply and load switching circuit stack on the same carrier board, thereby reducing the size of the low noise amplifier.

[0063] In combination with the second aspect, in certain implementations of the second aspect, the low-noise amplifier further includes a fourth carrier board, a fifth carrier board, a sixth chip, and a seventh chip; the low-noise amplification module and the power supply and load switching circuit are respectively integrated in the sixth chip and the seventh chip, the sixth chip is arranged on the fourth carrier board, the seventh chip is arranged on the fifth carrier board, and the fourth carrier board and the fifth carrier board are stacked.

[0064] In this implementation, the low-noise amplifier module and the power supply and load switching circuit are stacked on different carrier boards, respectively, so that the low-noise amplifier module and the power supply and load switching circuit can be easily modified or replaced.

[0065] In a third aspect, a radio frequency front-end module is provided, including a low noise amplifier.

[0066] In a fourth aspect, a radio frequency front-end chip is provided, comprising the above-mentioned radio frequency front-end module.

[0067] In a fifth aspect, an electronic device is provided, comprising the low-noise amplifier.

[0068] In an embodiment of the present application, the electronic device receives a downlink signal through a low-noise amplifier and performs low-noise amplification on the downlink signal, thereby obtaining a received signal with a higher signal-to-noise ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] FIG1 is a schematic diagram of a scenario of a mobile communication system to which an embodiment of the present application is applicable;

[0070] FIG2 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0071] FIG3 is a schematic structural diagram of a radio frequency front-end module provided in an embodiment of the present application;

[0072] FIG4 is a circuit diagram of a low noise amplifier provided in an embodiment of the present application;

[0073] FIG5 is a diagram showing an operating mode of a low noise amplifier provided in an embodiment of the present application;

[0074] FIG6 is a diagram showing an operating mode of a low noise amplifier provided in another embodiment of the present application;

[0075] FIG7 is a circuit diagram of a power supply and load switching circuit provided in an embodiment of the present application;

[0076] FIG8 is a circuit diagram of a power supply and load switching circuit provided in yet another embodiment of the present application;

[0077] FIG9 is a circuit diagram of a power supply and load switching circuit provided in yet another embodiment of the present application;

[0078] FIG10 is a circuit diagram of a power supply and load switching circuit provided in yet another embodiment of the present application;

[0079] FIG11 is a circuit diagram of a power supply and load switching circuit provided in yet another embodiment of the present application;

[0080] FIG12 is a circuit diagram of a power supply and load switching circuit provided in yet another embodiment of the present application;

[0081] FIG13 is a circuit diagram of a switch provided in an embodiment of the present application;

[0082] FIG14 is a schematic diagram of the structure of a low noise amplifier provided in an embodiment of the present application;

[0083] FIG15 is a circuit diagram of a low noise amplifier provided in yet another embodiment of the present application;

[0084] FIG16 is a diagram showing an operating mode of a low noise amplifier provided in another embodiment of the present application;

[0085] FIG17 is a diagram showing an operating mode of a low noise amplifier provided in another embodiment of the present application;

[0086] FIG18 is a circuit diagram of a low noise amplifier provided in yet another embodiment of the present application;

[0087] FIG19 is a circuit diagram of a low noise amplifier provided in yet another embodiment of the present application;

[0088] FIG20 is a diagram showing a packaging structure of a low noise amplifier provided in an embodiment of the present application;

[0089] FIG21 is a diagram showing a packaging structure of a low noise amplifier provided in another embodiment of the present application;

[0090] FIG22 is a diagram showing a packaging structure of a low noise amplifier provided in another embodiment of the present application;

[0091] FIG23 is a packaging structure diagram of a low-noise amplifier provided in another embodiment of the present application. DETAILED DESCRIPTION

[0092] The following is a clear and detailed description of the technical solutions in the embodiments of the present application, with reference to the accompanying drawings. In the description of the embodiments of the present application, unless otherwise specified, " / " represents the meaning of "or." For example, A / B can represent A or B. "and / or" in the text is merely a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone.

[0093] The terms "first," "second," and the like are used for descriptive purposes only and should not be construed as suggesting or implying relative importance or implicitly designating the number of the technical features indicated. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0094] In order to facilitate the understanding of the embodiments of the present application, the relevant concepts involved in the embodiments of the present application are first briefly described.

[0095] 1. Radio frequency front end (RFFE)

[0096] In the field of communications, the RF front-end refers to a series of components between the RF transceiver and the antenna, mainly including the power amplifier (PA), antenna switch (Switch), filter (Filter), duplexer (Duplexer and Diplexer) and low-noise amplifier (LNA), which directly affect the signal transmission and reception of electronic equipment.

[0097] 2. Low noise amplifier (LNA)

[0098] In the communications field, a low-noise amplifier (LNA) is an amplifier with a very low noise figure. It is used as a high-frequency or intermediate-frequency preamplifier in various radio receivers, as well as in the amplification circuits of highly sensitive electronic detection equipment. When amplifying weak signals, the amplifier's own noise can significantly interfere with the signal, so it is desirable to reduce this noise to improve the output signal-to-noise ratio.

[0099] 3. Transmit (TX)

[0100] In the field of communications, transmission refers to the act of sending data from one device to another device or a group of devices.

[0101] 4. Receive (RX)

[0102] In the field of communications, reception refers to the process of converting transmitted signals into perceptible information.

[0103] 5. Uplink signal

[0104] In the field of communications, an uplink signal refers to an uplink beam emitted by an electronic device and received by a base station.

[0105] 6. Downlink signal

[0106] In the field of communications, a downlink signal refers to a downlink beam emitted by a base station and received by electronic equipment.

[0107] 7. Linearity

[0108] In the field of communications, linearity, also known as nonlinear error, refers to the degree of closeness and deviation between the actual input / output characteristic curve and the ideal input / output characteristic curve (called the fitted straight line).

[0109] 8. Mutual induction

[0110] In the field of circuits, mutual induction is a measure of the induction between two circuits or their components. Mutual induction occurs when a change in current in one coil induces an electromotive force in another nearby coil. Mutual induction is a common electromagnetic induction phenomenon that can occur not only between two coils wound on the same core, but also between any two circuits placed in close proximity.

[0111] 9. Impedance matching

[0112] In the field of communications, impedance matching refers to a suitable pairing between a signal source or transmission line and a load. When the internal resistance of the signal source is equal in magnitude and phase to the characteristic impedance of the connected transmission line, or when the characteristic impedance of the transmission line is equal in magnitude and phase to the impedance of the connected load, the input or output of the transmission line is said to be in an impedance matching state, referred to as impedance matching. Otherwise, it is called impedance mismatch.

[0113] 10. Gain

[0114] In the communications field, gain typically refers to the ratio of a system's signal output to its signal input. For example, antenna gain, a parameter that indicates the concentration of radiation from a directional antenna, is the ratio of the squares of the electric field strengths generated by a directional antenna and an omnidirectional antenna in a predetermined direction. Amplifier gain, representing the amplifier's power amplification factor, is expressed as the common logarithm of the ratio of output power to input power.

[0115] The above is a brief introduction to the nouns involved in the embodiments of this application, and no further details will be given below.

[0116] FIG1 is a schematic diagram of a scenario of a mobile communication system to which an embodiment of the present application is applicable.

[0117] As shown in Figure 1, the user can use the electronic device 100 to communicate with the base station 200. The embodiment of the present application does not specifically limit the type of the electronic device 100. In some embodiments, the electronic device 100 can be a mobile phone, a wearable device (such as a smart bracelet, a smart watch, a headset, etc.), a tablet computer, a laptop computer (laptop), a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a cellular phone, a personal digital assistant (PDA), an augmented reality (AR)\virtual reality (VR) device and other IOT (internet of things, Internet of Things) devices, and can also be a television, a large screen, a printer, a projector and other devices. For ease of understanding, the following embodiments are illustrative examples using the electronic device 100 as a mobile phone as an example.

[0118] FIG2 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0119] As shown in Figure 2, the electronic device 100 may include a baseband subsystem 10, a radio frequency subsystem 20 consisting of a radio frequency integrated circuit (RFIC) 21 and a radio frequency front end (RFFE) 22, an antenna (ANT) subsystem 30, a power subsystem 40, etc. These devices can be coupled through various interconnection buses or other electrical connection methods.

[0120] The baseband subsystem 10 can extract useful information or data bits from the baseband signal, or convert the information or data bits into a baseband signal to be sent. These information or data bits can be data representing user data such as voice, text, video, or control information. Exemplarily, the baseband subsystem 10 can implement signal processing operations such as modulation and demodulation, encoding and decoding. Different baseband signal processing operations can be provided for different wireless access technologies, such as 5G NR and 4G LTE. Therefore, in order to support multiple mobile communication modes, the baseband subsystem 10 can simultaneously include multiple processing cores or multiple hardware accelerators (HAC). The baseband subsystem 10 can be integrated into one or more chips.

[0121] For example, the baseband subsystem 10 can be an independent chip, which can be called a modem chip. The hardware components of the baseband subsystem 10 can be manufactured and sold in units of modem chips. Modem chips can also be called baseband chips or baseband processors. In addition, the baseband subsystem 10 can also be further integrated into a system on chip (SOC) chip and manufactured and sold in units of SOC chips. The software components of the baseband subsystem 10 can be built into the hardware components of the chip before the chip leaves the factory, or can be imported from other non-volatile memories into the hardware components of the chip after the chip leaves the factory, or these software components can be downloaded and updated online via the network.

[0122] In addition, since the RF signal is an analog signal, the signals processed by the baseband subsystem 10 are mainly digital signals, and the electronic device also needs an analog-to-digital converter. The analog-to-digital converter can include an analog-to-digital converter (ADC) that converts analog signals into digital signals, and a digital-to-analog converter (DAC) that converts digital signals into analog signals. It should be understood that the analog-to-digital converter and the digital-to-analog converter can be set in either the baseband subsystem 10 or the RF subsystem 20, and the embodiments of the present application do not impose any restrictions on this.

[0123] The RF subsystem 20 can be divided into an RF receive path and an RF transmit path. The RF receive path can receive RF signals through an antenna, process the RF signals, such as amplification, filtering, down-conversion and analog-to-digital conversion, to obtain baseband signals, and transmit them to the baseband subsystem 10. The RF transmit path can receive baseband signals from the baseband subsystem 10, process the baseband signals, such as up-conversion, amplification, filtering and digital-to-analog conversion, to obtain RF signals, and radiate the RF signals into space through an antenna. Specifically, the RF subsystem 20 may include electronic components such as RF switches, duplexers, antenna tuners, low noise amplifiers (LNAs), power amplifiers, mixers, local oscillators (LOs), filters, etc. These electronic components can be integrated into one or more chips as needed. The antenna can sometimes also be considered as part of the RF subsystem 20.

[0124] For example, the aforementioned electronic components can be separately installed in the antenna, RF front-end module 22, and RF transceiver chip 21 as needed. The RF transceiver chip 21 can be composed of components such as a mixer and a local oscillator. The local oscillator is used to provide a local oscillator signal; the mixer is used to mix the RF signal with the local oscillator signal provided by the local oscillator. The RF transceiver chip 21 can also be referred to as a receiver, transmitter, or transceiver.

[0125] The RF front-end module 22 can be composed of electronic components such as filters, low-noise amplifiers, power amplifiers, and RF switches. The RF switch is used to switch between RF signal reception and transmission, and between different frequency bands. The duplexer is used to isolate the transmit and receive paths of the RF signal, ensuring that both receive and transmit can function properly while sharing the same antenna. The filter retains signals within a specific frequency band while filtering out signals outside of that band. The low-noise amplifier amplifies the RF signal in the receive channel, and the power amplifier amplifies the RF signal in the transmit path.

[0126] In an embodiment of the present application, the low noise amplifier may include a power supply and a load switching circuit.

[0127] Here, the RF transceiver chip 21 can output control signals to components such as the RF switch in the RF front-end module 22 through the control line to control the RF switch to switch different links.

[0128] It should be understood that the above is only an example, and the RF subsystem 20 may also include other devices or adopt other integration methods. For example, some devices belonging to the RF front-end module 22 may be integrated into the RF transceiver chip 21, or the antenna and the RF front-end module 22 may be integrated into the RF transceiver chip 21. The specific settings and modifications can be made as needed, and the embodiments of the present application do not impose any restrictions on this.

[0129] The antenna subsystem 30 includes multiple antennas, where ANT1 represents the first antenna, ANTn represents the nth antenna, and n is a positive integer greater than 1. The antenna subsystem 30 may also include an antenna switch for switching to different antennas so that different signals are transmitted using different antennas.

[0130] The power subsystem 40 is used to power various components. For example, the power supply can provide voltage for a power amplifier. The power subsystem 40 may include multiple power supplies, which may be the same or different. The power subsystem 40 may also power the baseband subsystem 10, the radio frequency subsystem 20, and the antenna subsystem 30. Each subsystem may be powered by the same power supply or by different power supplies.

[0131] In addition, the electronic device 100 may also include an application subsystem, which can serve as the main control system or main computing system of the electronic device 100, for running the main operating system and application programs, managing the software and hardware resources of the entire electronic device 100, and providing a user interface for the user. The application subsystem may include one or more processing cores. In addition, the application subsystem may also include driver software related to other subsystems (such as the baseband subsystem 10). The baseband subsystem 10 may also include one or more processing cores, as well as hardware accelerators and caches.

[0132] It should be understood that the above is only an example of the structure of the electronic device 100. The electronic device 100 may also include other subsystems or devices, which can be specifically configured and modified as needed. The embodiments of the present application do not impose any restrictions on this.

[0133] FIG3 is a schematic structural diagram of a radio frequency front-end module provided in an embodiment of the present application.

[0134] As shown in Figure 3, the RF front-end module 22 may include a power amplifier 23, a low-noise amplifier 24, a duplexer 25, and a radio frequency switch 26. The input end of the power amplifier 23 is electrically connected to the output end of the radio frequency transceiver chip 21. The output end of the power amplifier 23 is electrically connected to the radio frequency switch 26 through the duplexer 25. The radio frequency switch 26 is also electrically connected to the input end of the low-noise amplifier 24 through the duplexer 25. The output end of the low-noise amplifier 24 is electrically connected to the radio frequency transceiver chip 21. Uplink signals flow through the power amplifier 23, and downlink signals flow through the low-noise amplifier 24.

[0135] The power amplifier 23 amplifies the power of the RF signal in the transmit path, the low-noise amplifier 24 amplifies the low-noise of the RF signal in the receive path, and the duplexer 25 isolates the transmit and receive paths of the RF signal, ensuring that both receive and transmit functions function properly while sharing the same antenna. The RF switch 26 switches between receiving and transmitting RF signals and between different frequency bands.

[0136] Currently, the low-noise amplifier (LNA) within the RF front-end module 22 often has different performance requirements for different application scenarios when receiving downlink signals in complex environments. For example, satellite communications applications generally have higher requirements for linearity and noise, while cellular communications applications generally have higher requirements for noise and power consumption. Existing LNAs typically use two power supplies to adjust the linearity and power consumption of the LNA, resulting in a limited number of adjustable performance modes and failing to meet the requirements of a wide range of LNA applications.

[0137] In view of this, an embodiment of the present application provides a power supply and load switching circuit. By switching different power supply paths of at least two power supplies, at least four performance modes with different linearity and power consumption can be obtained. By switching different impedance values ​​of at least two loads, at least two performance modes with different operating frequency bands can be obtained, thereby enabling the low-noise amplifier to obtain more different performance modes.

[0138] 4 to 6 , the following first describes in detail the problem that only two power supplies can be used in a low noise amplifier to adjust the linearity and power consumption of the low noise amplifier.

[0139] FIG4 is a circuit diagram of a low noise amplifier provided in an embodiment of the present application.

[0140] As shown in Figure 4, in one embodiment provided in the present application, the low noise amplifier includes a controller, a high voltage power supply Vdd_hi, a low voltage power supply Vdd_Lo, an eleventh switch S11, a twelfth switch S12, a load, an eleventh transistor Q11, a twelfth transistor Q12, a bias circuit, a thirteenth switch S13, a fourteenth switch S14, a fifteenth switch S15, an eleventh resistor R11, and an eleventh capacitor C11. The high-voltage power supply Vdd_hi is electrically connected to the load via an eleventh switch S11, and the low-voltage power supply Vdd_Lo is electrically connected to the load via a twelfth switch S12. The gate of the eleventh transistor Q11 is electrically connected to the input terminal, the source of the eleventh transistor Q11 is grounded, the drain of the eleventh transistor Q11 is electrically connected to the source of the twelfth transistor Q12, and the drain of the twelfth transistor is electrically connected to the load and the output terminal. The gate of the twelfth transistor Q12 is electrically connected to the bias circuit via an eleventh resistor R11 and a thirteenth switch S13, and the gate of the twelfth transistor Q12 is also electrically connected to ground via an eleventh capacitor C11 and a fifteenth switch S15. A common connection terminal between the eleventh resistor R11 and the thirteenth switch S13 is electrically connected to the low-voltage power supply Vdd_Lo via a fourteenth switch S14. A controller is also electrically connected to the eleventh switch S11, the twelfth switch S12, the thirteenth switch S13, the fourteenth switch S14, and the fifteenth switch S15, respectively.

[0141] In an embodiment of the present application, the eleventh transistor Q11 and the twelfth transistor Q12 form a cascode structure for amplifying the input signal. The eleventh resistor R11 and the eleventh capacitor C11 form an impedance structure for impedance matching the input signal, and cooperate with the cascode structure to achieve a low-noise amplification effect. The controller controls whether the bias circuit is connected to the twelfth transistor Q12 by turning the thirteenth switch S13 on and off, so that the twelfth transistor Q12 operates in an amplification mode or a switching mode. The controller controls whether the low-voltage power supply Vdd_Lo is connected to the twelfth transistor Q12 by turning the fourteenth switch S14 on and off, and controls whether the twelfth transistor Q12 is grounded by turning the fifteenth switch S15 on and off. The controller controls whether the high-voltage power supply Vdd_hi is connected to the load by turning the eleventh switch S11 on and off, and controls whether the low-voltage power supply Vdd_Lo is connected to the load by turning the twelfth switch S12 on and off, resulting in the low-noise amplifier being able to switch between only two power supplies. And the impedance value of the load remains unchanged, and the operating frequency band cannot be adjusted.

[0142] FIG5 is a diagram showing an operating mode of a low noise amplifier provided in an embodiment of the present application.

[0143] As shown in FIG5 , in one embodiment provided in the present application, the controller controls the eleventh switch S11 to be turned on, the twelfth switch S12 to be turned off, the thirteenth switch S13 to be turned on, the fourteenth switch S14 to be turned off, and the fifteenth switch S15 to be turned on, so that the high-voltage power supply Vdd_hi supplies power to the load, the bias circuit provides a bias voltage to the twelfth transistor Q12, and the low-noise amplifier is in an amplification mode with higher linearity.

[0144] FIG6 is a diagram showing an operating mode of a low noise amplifier provided in another embodiment of the present application.

[0145] As shown in FIG6 , in one embodiment provided herein, a controller controls the eleventh switch S11 to be disconnected, the twelfth switch S12 to be turned on, the thirteenth switch S13 to be disconnected, the fourteenth switch S14 to be turned on, and the fifteenth switch S15 to be disconnected, thereby enabling the low-voltage power supply Vdd_Lo to power the load, and the low-voltage power supply Vdd_Lo to provide voltage to the twelfth transistor Q12, placing the low-noise amplifier in a switching mode with low power consumption. Simultaneously, when the twelfth transistor Q12 is in switching mode, it is unable to provide a large output impedance to the eleventh transistor Q11, resulting in a low gain of the low-noise amplifier, making it impossible to achieve the requirements of high gain and high linearity.

[0146] Therefore, in order to solve the problem that there are only two performance modes in the embodiment of the present application and it cannot meet the requirements of more application scenarios of the low-noise amplifier, the present application provides a power supply and load switching circuit, which adjusts the linearity, power consumption and operating frequency band of the low-noise amplifier by switching multiple power supplies and multiple loads, so that the low-noise amplifier can obtain more different performance modes.

[0147] 7 to 13 , a power supply and load switching circuit for switching multiple power supplies and multiple loads will be described in detail below.

[0148] FIG7 is a circuit diagram of a power supply and load switching circuit provided in an embodiment of the present application.

[0149] As shown in FIG7 , in one embodiment provided herein, a power and load switching circuit includes a first power supply VDD1, a second power supply VDD2, a first double-pole double-throw switch DPDT1, a first load inductor Ld1, a second load inductor Ld2, a first output port OUT1, and a second output port OUT2. Two ports of the first double-pole double-throw switch DPDT1 are electrically connected to one end of the first load inductor Ld1 and one end of the second load inductor Ld2, respectively. The other end of the first load inductor Ld1 is connected to the first power supply VDD1, and the other end of the second load inductor Ld2 is connected to the second power supply VDD2. The other two ports of the first double-pole double-throw switch DPDT1 are electrically connected to the first output port OUT1 and the second output port OUT2, respectively. The voltage value of the first power supply VDD1 is greater than the voltage value of the second power supply VDD2.

[0150] Exemplarily, the first double-pole double-throw switch DPDT1 may have four switch paths: a first switch path S1, a second switch path S2, a third switch path S3 and a fourth switch path S4, which are respectively used to connect the first power supply VDD1 and the second power supply VDD2 to the first output port OUT1 and the second output port OUT2.

[0151] In the embodiment of the present application, a first switch path S1 within a first double-pole double-throw switch DPDT1 can be used to switch between the first power supply VDD1 and the first output port OUT1. When the first switch path S1 is on, the power and load switching circuit in the embodiment of the present application can use the first power supply VDD1 as a voltage source, use the first load inductor Ld1 to adjust the operating frequency, and output the supply voltage through the first output port OUT1.

[0152] The second power supply VDD2 and the second output port OUT2 can also be switched and connected via a second switch path S2 within the first double-pole double-throw switch DPDT1. When the second switch path S2 is on, the power and load switching circuit in the embodiment of the present application can use the second power supply VDD2 as a voltage source, use the second load inductor Ld2 to adjust the operating frequency band, and output the supply voltage through the second output port OUT2.

[0153] A third switch path S3 within the first double-pole double-throw switch DPDT1 can also be used to switch between the first power supply VDD1 and the second output port OUT2. When the third switch path S3 is on, the power and load switching circuit in this embodiment of the present application can use the first power supply VDD1 as a voltage source, use the first load inductor Ld1 to adjust the operating frequency, and output the supply voltage through the second output port OUT2.

[0154] The second power supply VDD2 and the first output port OUT1 can also be switched on and off via a fourth switch path S4 within the first double-pole double-throw switch DPDT1. When the fourth switch path S4 is on, the power and load switching circuit in this embodiment of the present application can use the second power supply VDD2 as a voltage source, use the second load inductor Ld2 to adjust the operating frequency, and output the supply voltage through the first output port OUT1.

[0155] FIG8 is a circuit diagram of a power supply and load switching circuit provided in yet another embodiment of the present application.

[0156] As shown in FIG8 , in one embodiment provided herein, a power and load switching circuit includes a first power supply VDD1, a second power supply VDD2, a first double-pole double-throw switch DPDT1, a first load inductor Ld1, a second load inductor Ld2, a first output port OUT1, and a second output port OUT2. Two ports of the first double-pole double-throw switch DPDT1 are electrically connected to one end of the first load inductor Ld1 and one end of the second load inductor Ld2, respectively. The other end of the first load inductor Ld1 is connected to the first power supply VDD1, and the other end of the second load inductor Ld2 is connected to the second power supply VDD2. The other two ports of the first double-pole double-throw switch DPDT1 are electrically connected to the first output port OUT1 and the second output port OUT2, respectively. The voltage of the first power supply VDD1 is greater than the voltage of the second power supply VDD2. The first load inductor Ld1 and the second load inductor Ld2 are coupled.

[0157] In the embodiment of the present application, since the first load inductor Ld1 and the second load inductor Ld2 are coupled, the inductance of the power path connected to the first power supply VDD1 is the sum of the inductance of the first load inductor Ld1 and the mutual inductance. The inductance of the power path connected to the second power supply VDD2 is the sum of the inductance of the second load inductor Ld2 and the mutual inductance, thereby enabling the power supply and load switching circuit to obtain two additional load impedance values, thereby enabling the low-noise amplifier to obtain performance modes for two additional operating frequency bands. At the same time, in conjunction with this, the first double-pole double-throw switch DPDT1 switches and connects the four power paths connecting the first power supply VDD1 and the second power supply VDD2 to the first output port OUT1 and the second output port OUT2, allowing the low-noise amplifier to obtain four performance modes with different sensitivity and power consumption. The combination of the two allows the low-noise amplifier to obtain a wider range of different performance modes.

[0158] FIG9 is a circuit diagram of a power supply and load switching circuit provided in yet another embodiment of the present application.

[0159] As shown in FIG9 , in one embodiment provided herein, a power and load switching circuit includes a first power supply VDD1, a second power supply VDD2, a first double-pole double-throw switch DPDT1, a third load inductor Ld3, a fourth load inductor Ld4, a first output port OUT1, and a second output port OUT2. Two ports of the first double-pole double-throw switch DPDT1 are connected to the first power supply VDD1 and the second power supply VDD2, respectively. The other two ports of the first double-pole double-throw switch DPDT1 are electrically connected to one end of the third load inductor Ld3 and one end of the fourth load inductor Ld4, respectively. The other end of the third load inductor Ld1 is electrically connected to the first output port OUT1, and the other end of the fourth load inductor Ld4 is electrically connected to the second output port OUT2. The voltage of the first power supply VDD1 is greater than the voltage of the second power supply VDD2.

[0160] In the embodiment of the present application, since the third load inductor Ld3 is disposed between the first double-pole double-throw switch DPDT1 and the first output port OUT1, the inductance of the power path connected to the first output port OUT1 is the inductance of the third load inductor Ld3. Since the fourth load inductor Ld4 is disposed between the first double-pole double-throw switch DPDT1 and the second output port OUT2, the inductance of the power path connected to the second output port OUT2 is the inductance of the fourth load inductor Ld4. This allows the power and load switching circuit to obtain two additional load impedance values, thereby enabling the low-noise amplifier to achieve performance modes in two additional operating frequency bands. Simultaneously, in conjunction with this, the first double-pole double-throw switch DPDT1 switches and connects four power paths connecting the first power supply VDD1 and the second power supply VDD2 to the first output port OUT1 and the second output port OUT2, enabling the low-noise amplifier to achieve four performance modes with different sensitivity and power consumption. The combination of these two modes allows the low-noise amplifier to achieve a wider range of different performance modes.

[0161] FIG10 is a circuit diagram of a power supply and load switching circuit provided in yet another embodiment of the present application.

[0162] As shown in FIG10 , in one embodiment provided herein, a power and load switching circuit includes a first power supply VDD1, a second power supply VDD2, a first double-pole double-throw switch DPDT1, a third load inductor Ld3, a fourth load inductor Ld4, a first output port OUT1, and a second output port OUT2. Two ports of the first double-pole double-throw switch DPDT1 are connected to the first power supply VDD1 and the second power supply VDD2, respectively. The other two ports of the first double-pole double-throw switch DPDT1 are electrically connected to one end of the third load inductor Ld3 and one end of the fourth load inductor Ld4, respectively. The other end of the third load inductor Ld1 is electrically connected to the first output port OUT1, and the other end of the fourth load inductor Ld4 is electrically connected to the second output port OUT2. The voltage of the first power supply VDD1 is greater than the voltage of the second power supply VDD2. The third load inductor Ld3 and the fourth load inductor Ld4 are coupled.

[0163] In the embodiment of the present application, due to the coupling relationship between the third load inductor Ld3 and the fourth load inductor Ld4, the inductance of the power path connected to the first output port OUT1 is the sum of the inductance of the third load inductor Ld3 and the mutual inductance, and the inductance of the power path connected to the second output port OUT2 is the sum of the inductance of the fourth load inductor Ld4 and the mutual inductance. This allows the power and load switching circuit to obtain two additional load impedance values, thereby enabling the low-noise amplifier to obtain performance modes in two additional operating frequency bands. Simultaneously, in conjunction with this, the first double-pole double-throw switch DPDT1 switches and connects the four power paths connecting the first power supply VDD1 and the second power supply VDD2 to the first output port OUT1 and the second output port OUT2, enabling the low-noise amplifier to obtain four performance modes with different sensitivity and power consumption. The combination of these two modes allows the low-noise amplifier to obtain a wider range of different performance modes.

[0164] FIG11 is a circuit diagram of a power supply and load switching circuit provided in yet another embodiment of the present application.

[0165] As shown in FIG11 , in one embodiment provided herein, a power and load switching circuit includes a first power supply VDD1, a second power supply VDD2, a first double-pole double-throw switch DPDT1, a first load inductor Ld1, a second load inductor Ld2, a third load inductor Ld3, a fourth load inductor Ld4, a first output port OUT1, and a second output port OUT2. Two ports of the first double-pole double-throw switch DPDT1 are connected to the first power supply VDD1 and the second power supply VDD2 via the first load inductor Ld1 and the second load inductor Ld2, respectively. The other two ports of the first double-pole double-throw switch DPDT1 are electrically connected to the first output port OUT1 and the second output port OUT2 via the third load inductor Ld3 and the fourth load inductor Ld4, respectively. The voltage of the first power supply VDD1 is greater than the voltage of the second power supply VDD2.

[0166] In the embodiment of the present application, since the first load inductor Ld1 is arranged between the first double-pole double-throw switch DPDT1 and the first power supply VDD1, the second load inductor Ld2 is arranged between the first double-pole double-throw switch DPDT1 and the second power supply VDD2, the third load inductor Ld3 is arranged between the first double-pole double-throw switch DPDT1 and the first output port OUT1, and the fourth load inductor Ld4 is arranged between the first double-pole double-throw switch DPDT1 and the second output port OUT2, the inductance of the power path between the first power supply VDD1 and the first output port OUT1 is the sum of the inductance of the first load inductor Ld1 and the inductance of the third load inductor Ld3, and the fourth load inductor Ld4 is arranged between the first double-pole double-throw switch DPDT1 and the second output port OUT2. The inductance of the power path between the first power supply VDD1 and the second output port OUT2 is the sum of the inductance of the first load inductor Ld1 and the inductance of the fourth load inductor Ld4; the inductance of the power path between the second power supply VDD2 and the second output port OUT2 is the sum of the inductance of the second load inductor Ld2 and the fourth load inductor Ld4; and the inductance of the power path between the second power supply VDD2 and the first output port OUT1 is the sum of the inductance of the second load inductor Ld2 and the third load inductor Ld3. As a result, the power supply and load switching circuit can obtain four additional load impedance values, and thus the low-noise amplifier can obtain performance modes in four additional operating frequency bands.

[0167] At the same time, in conjunction with this, the first double-pole double-throw switch DPDT1 switches and connects four power supply paths of the first power supply VDD1 and the second power supply VDD2 and the first output port OUT1 and the second output port OUT2, so that the low-noise amplifier can obtain four performance modes with different sensitivity and power consumption. The combination of the two enables the low-noise amplifier to obtain more different performance modes.

[0168] FIG12 is a circuit diagram of a power supply and load switching circuit provided in yet another embodiment of the present application.

[0169] As shown in FIG12 , in one embodiment provided herein, a power and load switching circuit includes a first power supply VDD1, a second power supply VDD2, a first double-pole double-throw switch DPDT1, a first load inductor Ld1, a second load inductor Ld2, a third load inductor Ld3, a fourth load inductor Ld4, a first output port OUT1, and a second output port OUT2. Two ports of the first double-pole double-throw switch DPDT1 are connected to the first power supply VDD1 and the second power supply VDD2 via the first load inductor Ld1 and the second load inductor Ld2, respectively. The other two ports of the first double-pole double-throw switch DPDT1 are electrically connected to the first output port OUT1 and the second output port OUT2 via the third load inductor Ld3 and the fourth load inductor Ld4, respectively. The voltage of the first power supply VDD1 is greater than the voltage of the second power supply VDD2. Any two of the first load inductor Ld1, the second load inductor Ld2, the third load inductor Ld3, and the fourth load inductor Ld4 are coupled.

[0170] In an embodiment of the present application, since the first load inductor Ld1 is arranged between the first double-pole double-throw switch DPDT1 and the first power supply VDD1, the second load inductor Ld2 is arranged between the first double-pole double-throw switch DPDT1 and the second power supply VDD2, the third load inductor Ld3 is arranged between the first double-pole double-throw switch DPDT1 and the first output port OUT1, the fourth load inductor Ld4 is arranged between the first double-pole double-throw switch DPDT1 and the second output port OUT2, and there is a coupling relationship between any two of the first load inductor Ld1, the second load inductor Ld2, the third load inductor Ld3 and the fourth load inductor Ld4. Therefore, the inductance of the power path between the first power supply VDD1 and the first output port OUT1 is the sum of the inductance of the first load inductor Ld1, the inductance of the third load inductor Ld3, and the mutual inductance of the first load inductor Ld1 and the third load inductor Ld3. The inductance of the power path between the first power supply VDD1 and the second output port OUT2 is the sum of the inductance of the first load inductor Ld1, the inductance of the fourth load inductor Ld4, and the mutual inductance of the first load inductor Ld1 and the fourth load inductor Ld4.

[0171] The inductance of the power path between the second power supply VDD2 and the second output port OUT2 is the sum of the inductance of the second load inductor Ld2, the inductance of the fourth load inductor Ld4, and the mutual inductance of the second and fourth load inductors Ld2 and Ld4. The inductance of the power path between the second power supply VDD2 and the first output port OUT1 is the sum of the inductance of the second load inductor Ld2, the inductance of the third load inductor Ld3, and the mutual inductance of the second and third load inductors Ld2 and Ld3. As a result, the power and load switching circuit can obtain four additional load impedance values, thereby enabling the low-noise amplifier to achieve four additional performance modes for the operating frequency bands. Simultaneously, the first double-pole double-throw switch DPDT1 switches and connects the four power paths between the first and second power supplies VDD1 and VDD2 and the first and second output ports OUT1 and OUT2, enabling the low-noise amplifier to achieve four performance modes with different sensitivity and power consumption. The combination of these two modes enables the low-noise amplifier to achieve a wider range of different performance modes.

[0172] FIG13 is a circuit diagram of a switching switch provided in an embodiment of the present application.

[0173] As shown in FIG13 , in one embodiment provided herein, a first double-pole double-throw switch DPDT1 may include four switch paths: a first switch path S1, a second switch path S2, a third switch path S3, and a fourth switch path S4. The first switch path S1 and the third switch path S3 are both electrically connected to a first power supply VDD1, and the second switch path S2 and the fourth switch path S4 are both electrically connected to a second power supply VDD2. m switching devices can be connected in parallel within the first switch path S1, m switching devices can be connected in parallel within the third switch path S3, n switching devices can be connected in parallel within the second switch path S2, and n switching devices can be connected in parallel within the fourth switch path S4, where m ≥ n.

[0174] In an embodiment of the present application, the first power supply VDD1 is greater than the second power supply VDD2. When the power supply and load switching circuit uses the first power supply VDD1 as the power supply, the power supply and load switching circuit generally operates in a high-linearity application scenario, and the current flowing through the switching device is large. Therefore, in order to reduce the conduction loss of the switching switch, m switching devices can be used. When the power supply and load switching circuit uses the second power supply VDD2 as the power supply, the power supply and load switching circuit generally operates in a low-power application scenario, and the current flowing through the switching device is small. Therefore, in order to reduce the conduction loss of the switching switch, n switching devices can be used. Optionally, the switching device can be a metal oxide semiconductor field effect transistor (MOSFET).

[0175] 14 to 19 , a solution of a low noise amplifier using a power supply and load switching circuit will be described in detail.

[0176] FIG14 is a schematic diagram of the structure of a low noise amplifier provided in an embodiment of the present application.

[0177] As shown in Figure 14, in one embodiment provided in the present application, the low-noise amplifier 24 includes a power supply and load switching circuit 241 and a low-noise amplification module 242. The power supply and load switching circuit 241 is electrically connected to the low-noise amplification module 242. The power supply and load switching circuit 241 is used to provide the low-noise amplification module 242 with a power supply and load that can be switched and configured. The low-noise amplification module 242 is used to perform low-noise amplification processing on the input signal.

[0178] FIG15 is a circuit diagram of a low noise amplifier provided in yet another embodiment of the present application.

[0179] As shown in FIG15 , in one embodiment provided herein, a low-noise amplifier includes a power supply and load switching circuit 241 and a low-noise amplifier module 242. The power supply and load switching circuit 241 includes a first power supply VDD1, a second power supply VDD2, a first double-pole double-throw switch DPDT1, a first load inductor Ld1, and a second load inductor Ld2. One port of the first double-pole double-throw switch DPDT1 is connected to the first power supply VDD1 via the first load inductor Ld1, and the other port of the first double-pole double-throw switch DPDT1 is connected to the second power supply VDD2 via the second load inductor Ld2. The low-noise amplifier module 242 includes a first amplifier A1 and a second amplifier A2. The other port of the first double-pole double-throw switch DPDT1 is electrically connected to the first amplifier A1, and the other port of the first double-pole double-throw switch DPDT1 is electrically connected to the second amplifier A2. The input port of the first amplifier A1 receives a first input signal IN1, and the output port of the first amplifier A1 outputs a first output signal OUT1. The input port of the second amplifier A2 is connected to the second input port IN2, and the output port of the second amplifier A2 is connected to the second output port OUT2. For example, the first double-pole double-throw switch DPDT1 may include a first switch path S1 and a third switch path S3, both connected to a first power supply VDD1, and a second switch path S2 and a fourth switch path S4, both connected to a second power supply VDD2. The voltage value of the first power supply VDD1 is greater than the voltage value of the second power supply VDD2.

[0180] In the embodiment of the present application, the first double-pole double-throw switch DPDT1 is used to switch between the first power supply VDD1, the first load inductor Ld1, and the first switch path S1 or the third switch path S3. It is also used to switch between the second power supply VDD2, the second load inductor Ld2, and the second switch path S2 or the fourth switch path S4. The first amplifier A1 is used to amplify input signals in a first frequency band, and the second amplifier A2 is used to amplify input signals in a second frequency band. The first and second frequency bands can be the same or different.

[0181] FIG16 is a diagram showing an operating mode of a low noise amplifier provided in another embodiment of the present application.

[0182] As shown in FIG16 , in one embodiment provided herein, the power and load switching circuit 241 is in a direct-on state, with the first amplifier A1 operating in a high-linearity mode in the first frequency band, and the second amplifier A2 operating in a low-power mode in the second frequency band. Specifically, the first double-pole double-throw switch DPDT1 switches on the first power supply VDD1, the first load inductor Ld1, the first switch path S1, and the first amplifier A1. The first power supply VDD1 provides power to the first amplifier A1, and the first load inductor Ld1 provides a load to the first amplifier A1, thereby enabling the first amplifier A1 to operate in the high-linearity mode in the first frequency band. The first double-pole double-throw switch DPDT1 switches on the second power supply VDD2, the second load inductor Ld2, the second switch path S2, and the second amplifier A2. The second power supply VDD2 provides power to the second amplifier A2, and the second load inductor Ld2 provides a load to the second amplifier A2, thereby enabling the second amplifier A2 to operate in the low-power mode in the second frequency band.

[0183] FIG17 is a diagram showing an operating mode of a low noise amplifier provided in another embodiment of the present application.

[0184] As shown in FIG17 , in one embodiment provided herein, the power and load switching circuit 241 is in a crossover state, with the first amplifier A1 operating in a low-power mode within the first frequency band, and the second amplifier A2 operating in a high-linearity mode within the second frequency band. Specifically, the first double-pole double-throw switch DPDT1 switches on the first power supply VDD1, the first load inductor Ld1, the third switch path S3, and the second amplifier A2, providing power to the second amplifier A2 via the first power supply VDD1 and providing a load to the second amplifier A2 via the first load inductor Ld1, thereby enabling the second amplifier A2 to operate in the low-power mode within the first frequency band. The first double-pole double-throw switch DPDT1 switches on the second power supply VDD2, the second load inductor Ld2, the fourth switch path S4, and the first amplifier A1, providing power to the first amplifier A1 via the second power supply VDD2 and providing a load to the first amplifier A1 via the second load inductor Ld2, thereby enabling the first amplifier A1 to operate in the high-linearity mode within the second frequency band.

[0185] Optionally, in one embodiment of the present application, when the first frequency band of the first amplifier A1 is the same as the second frequency band of the second amplifier A2, the first amplifier A1 and the second amplifier A2 can serve as a bypass structure of the filter to meet the high linearity requirements of the low noise amplifier during wireless communication.

[0186] FIG18 is a circuit diagram of a low noise amplifier provided in yet another embodiment of the present application.

[0187] As shown in FIG18 , in one embodiment provided herein, a low-noise amplifier includes a power supply and load switching circuit 241 and a low-noise amplifier module 242. The power supply and load switching circuit 241 includes a first power supply VDD1, a second power supply VDD2, a first double-pole double-throw switch DPDT1, a third load inductor Ld3, and a fourth load inductor Ld4. One input port of the first double-pole double-throw switch DPDT1 is connected to the first power supply VDD1, and the other input port of the first double-pole double-throw switch DPDT1 is connected to the second power supply VDD2. One output port of the first double-pole double-throw switch DPDT1 is electrically connected to the low-noise amplifier module 242 via the third load inductor Ld3, and the other output port of the first double-pole double-throw switch DPDT1 is electrically connected to the low-noise amplifier module 242 via the fourth load inductor Ld4. Exemplarily, the first double-pole double-throw switch DPDT1 includes a first switch path S1 and a third switch path S3 connected to the first power supply VDD1, and a second switch path S2 and a fourth switch path S4 connected to the second power supply VDD2. The voltage value of the first power source VDD1 is greater than the voltage value of the second power source VDD2.

[0188] In the embodiment of the present application, the first double-pole double-throw switch DPDT1 is used to switch between the first power supply VDD1 and the first switch path S1 or the third switch path S3, and is also used to switch between the second power supply VDD2 and the second switch path S2 or the fourth switch path S4. A third load inductor Ld3 is used as a load between the first and third switch paths S1, S3, and the low-noise amplifier module 242, and a fourth load inductor Ld4 is used as a load between the second and fourth switch paths S2, S4, and the low-noise amplifier module 242.

[0189] As shown in FIG18 , in one embodiment provided herein, a low-noise amplifier module 242 includes a first amplifier A1, a second amplifier A2, a bias circuit, and a controller. The bias circuit is configured to output a first bias voltage Vbias1, a second bias voltage Vbias2, a third bias voltage Vbias3, and a fourth bias voltage Vbias4. The controller is configured to output a first control signal Vct1 and a second control signal Vct2. The first control signal Vct1 is configured to control one of the first switch path S1 and the third switch path S3 of the first double-pole double-throw switch DPDT1 to be conductive, and the second control signal Vct2 is configured to control one of the second switch path S2 and the fourth switch path S4 of the first double-pole double-throw switch DPDT1 to be conductive.

[0190] The first amplifier A1 includes a first transistor Q1, a second transistor Q2, a first input inductor Lg1, a first source inductor Ls1, a first input port IN1, a first output port OUT1, a first bias network, a second bias network, a first input capacitor Cin1, a first gate bias capacitor Cg1, and a first output capacitor Cout1. The gate of the first transistor Q1 is connected to the first input port IN1 via the first input inductor Lg1. The source of the first transistor Q1 is grounded via the first source inductor Ls1. The drain of the first transistor Q1 is electrically connected to the source of the second transistor Q2. The drain of the second transistor Q2 is electrically connected to the first output port OUT1. The gate of the first transistor Q1 is connected to a first bias voltage Vbias1, and the gate of the second transistor Q2 is connected to a second bias voltage Vbias2.

[0191] A first bias network is connected between the gate of the first transistor Q1 and a first bias voltage Vbias1, and a second bias network is connected between the second transistor Q2 and a second bias voltage Vbias2. A first input capacitor Cin1 is connected between the gate of the first transistor Q1 and a first input inductor Lg1, a first bias capacitor Cg1 is connected between the gate of the second transistor Q2 and ground, and a first output capacitor Cout1 is connected between the drain of the second transistor Q2 and the first output port OUT1.

[0192] In an embodiment of the present application, a first transistor Q1 and a second transistor Q2 form a cascode amplifier for amplifying a first input signal and outputting it through a first output port OUT1. A first input inductor Lg1 is used for impedance matching the first input signal, a first source inductor Ls1 is used for adjusting the gain of the first amplifier A1, a first bias voltage Vbias1 is used to provide a first bias voltage for the first transistor Q1, and a second bias voltage Vbias2 is used to provide a second bias voltage for the second transistor Q2. A first bias network is used to isolate the current impact of the first bias voltage Vbias1 on the first transistor Q1, while a second bias network is used to isolate the current impact of the second bias voltage Vbias2 on the second transistor Q2. A first input capacitor Cin1 forms an LC network with the first input inductor Lg1 to impedance match the first input signal. A first gate bias capacitor Cg1 is used to filter the second bias voltage of the second transistor Q2, and a first output capacitor Cout1 is used to filter the first output signal. Combined with a power supply and load switching circuit with multiple performance modes, this low-noise amplifier can achieve a variety of different performance modes.

[0193] As shown in FIG18 , in one embodiment provided herein, the second amplifier A2 includes a third transistor Q3, a fourth transistor Q4, a second input inductor Lg2, a second source inductor Ls2, a second input port IN2, a second output port OUT2, a third bias network, a fourth bias network, a second input capacitor Cin2, a second gate bias capacitor Cg2, and a second output capacitor Cout2. The gate of the third transistor Q3 is connected to the second input port IN2 via the second input inductor Lg2, the source of the third transistor Q3 is grounded via the second source inductor Ls2, the drain of the third transistor Q3 is electrically connected to the source of the fourth transistor Q4, the drain of the fourth transistor Q4 is electrically connected to the second output port OUT2, the gate of the third transistor Q3 is connected to a third bias voltage Vbias3, and the gate of the fourth transistor Q4 is connected to a fourth bias voltage Vbias4.

[0194] A third bias network is connected between the gate of the third transistor Q3 and a third bias voltage Vbias3, and a fourth bias network is connected between the fourth transistor Q4 and a fourth bias voltage Vbias4. A second input capacitor Cin2 is connected between the gate of the third transistor Q3 and the second input inductor Lg2. A second bias capacitor Cg2 is connected between the gate of the fourth transistor Q4 and ground. A second output capacitor Cout2 is connected between the drain of the fourth transistor Q4 and the second output port OUT2.

[0195] In the embodiment of the present application, the third transistor Q3 and the fourth transistor Q4 form a cascode amplifier for amplifying the second input signal and outputting it through the second output port OUT2. The second input inductor Lg2 is used to perform impedance matching on the second input signal, the second source inductor Ls2 is used to adjust the gain of the second amplifier A2, the third bias voltage Vbias3 is used to provide a third bias voltage for the third transistor Q3, and the fourth bias voltage Vbias4 is used to provide a fourth bias voltage for the fourth transistor Q4. The third bias network is used to isolate the current impact of the third bias voltage Vbias3 on the third transistor Q3, and the fourth bias network is used to isolate the current impact of the fourth bias voltage Vbias4 on the fourth transistor Q4. The second input capacitor Cin2 is used to form an LC network with the second input inductor Lg2 to perform impedance matching on the second input signal. The second gate bias capacitor Cg2 is used to filter the fourth bias voltage of the fourth transistor Q4. The second output capacitor Cout2 is used to filter the second output signal. In combination with a power supply and load switching circuit having multiple performance modes, the low-noise amplifier can obtain more different performance modes.

[0196] FIG19 is a circuit diagram of a low noise amplifier provided in yet another embodiment of the present application.

[0197] As shown in FIG19 , in one embodiment provided herein, a low-noise amplifier includes a power supply and load switching circuit 241 and a low-noise amplifier module 242. The difference from the low-noise amplifier circuit shown in FIG18 is that the low-noise amplifier module 242 includes a first amplifier A1, a second amplifier A2, a bias circuit, and a controller. The bias circuit is configured to output a first bias voltage Vbias1, a second bias voltage Vbias2, a third bias voltage Vbias3, and a fourth bias voltage Vbias4. The controller is configured to output a first control signal Vct1, a second control signal Vct2, a third control signal Vct3, a fourth control signal Vct4, a fifth control signal Vct5, a sixth control signal Vct6, a seventh control signal Vct7, and an eighth control signal Vct8. The first control signal Vct1 is configured to control one of the first switch path S1 and the third switch path S3 of the first double-pole double-throw switch DPDT1 to be conductive, and the second control signal Vct2 is configured to control one of the second switch path S2 and the fourth switch path S4 of the first double-pole double-throw switch DPDT1 to be conductive.

[0198] The first amplifier A1 also includes a fifth switch S5, a sixth switch S6, and a first auxiliary path AUX1. The fifth switch S5 is connected between the gate of the second transistor Q2 and the ground terminal and receives the third control signal Vct3. The sixth switch S6 is connected between the gate of the second transistor Q2 and the second bias voltage Vbias2 and receives the fifth control signal Vct5. The two ends of the first auxiliary path AUX1 are respectively electrically connected to the source and gate of the second transistor Q2 and receive the fourth control signal Vct4.

[0199] Optionally, the first auxiliary path AUX1 may be formed by a switch and a matching network.

[0200] In the embodiment of the present application, the third control signal Vct3 is used to control the conduction and disconnection of the fifth switch S5 to control whether the gate of the second transistor Q2 is grounded. The fourth control signal Vct4 is used to control the conduction and disconnection of the first auxiliary path AUX1 to control whether the second transistor Q2 is bypassed. The fifth control signal Vct5 is used to control the conduction and disconnection of the sixth switch S6 to control whether the second bias voltage Vbias2 is connected to the gate of the second transistor Q2.

[0201] It should be noted that when the controller controls the first auxiliary path AUX1 to conduct via the fourth control signal Vct4, it bypasses the second transistor Q2. The controller also controls the sixth switch S6 to open via the fifth control signal Vct5, thereby disconnecting the second bias voltage Vbias2 of the second transistor Q2. The controller also controls the fifth switch S5 to open via the third control signal Vct3, thereby disconnecting the gate of the second transistor Q2 from ground. This reduces the drain parasitic capacitance of the first transistor Q1, thereby fully turning on the first transistor Q1, reducing the on-resistance, and reducing the additional power consumption of the first amplifier A1.

[0202] The second amplifier A2 further includes a seventh switch S7, an eighth switch S8, and a second auxiliary path AUX2. The seventh switch S7 is connected between the gate of the fourth transistor Q4 and the ground terminal and receives the eighth control signal Vct8. The eighth switch S8 is connected between the gate of the fourth transistor Q4 and the fourth bias voltage Vbias4 and receives the sixth control signal Vct6. The two ends of the second auxiliary path AUX2 are electrically connected to the source of the fourth transistor Q4 and the gate of the fourth transistor Q4, respectively, and receive the seventh control signal Vct7.

[0203] Optionally, the second auxiliary path AUX2 may be formed by a switch and a matching network.

[0204] In the embodiment of the present application, the eighth control signal Vct8 is used to control the conduction and disconnection of the seventh switch S7 to control whether the gate of the fourth transistor Q4 is grounded. The seventh control signal Vct7 is used to control the conduction and disconnection of the second auxiliary path AUX2 to control whether the fourth transistor Q4 is bypassed. The sixth control signal Vct6 is used to control the conduction and disconnection of the eighth switch S8 to control whether the fourth bias voltage Vbias4 is connected to the gate of the fourth transistor Q4.

[0205] It should be noted that when the controller controls the second auxiliary path AUX2 to be conductive via the seventh control signal Vct7, it bypasses the fourth transistor Q4. The controller also controls the eighth switch S8 to be disconnected via the sixth control signal Vct6, thereby disconnecting the fourth bias voltage Vbias4 of the fourth transistor Q4. The controller also controls the seventh switch S7 to be disconnected via the eighth control signal Vct8, thereby disconnecting the gate of the fourth transistor Q4 from the ground terminal. This reduces the drain parasitic capacitance of the third transistor Q3, thereby fully turning on the third transistor Q3, reducing the on-resistance, and reducing excess power consumption.

[0206] 20 to 23 , a solution of a low-noise amplifier packaged by a power supply and load switching circuit and a low-noise amplifier module will be described in detail.

[0207] FIG20 is a diagram showing the packaging structure of a low-noise amplifier provided in an embodiment of the present application.

[0208] As shown in Figure 20, in one embodiment provided in the present application, the low-noise amplifier includes a power supply and load switching circuit 241, a low-noise amplification module 242, a first carrier 243 and a first chip 244; the low-noise amplification module 242 and the power supply and load switching circuit 241 are integrated together in the first chip 244, and the first chip 244 is set on the first carrier 243.

[0209] In the embodiment of the present application, the low-noise amplifier module 242 and the power and load switching circuit 241 can be integrated into a first chip 244 using the same semiconductor process. The first chip 244 is then mounted on a first carrier board 243. This allows the low-noise amplifier module 242 and the power and load switching circuit 241 to be interconnected with other electronic components via the first carrier board 243, thereby achieving a low-noise amplification function during RF reception. The integration of the low-noise amplifier module 242 and the power and load switching circuit 241 into the same chip reduces the area of ​​the low-noise amplifier and facilitates assembly with other components.

[0210] FIG21 is a packaging structure diagram of another low-noise amplifier provided in an embodiment of the present application.

[0211] As shown in Figure 21, in one embodiment provided in the present application, the low noise amplifier includes a power supply and load switching circuit 241, a low noise amplification module 242, a second carrier board 245, a second chip 246 and a third chip 247. The low noise amplification module 242 and the power supply and load switching circuit 241 are respectively integrated into the second chip 246 and the third chip 247, and the second chip 246 and the third chip 247 are arranged on the second carrier board 245.

[0212] In an embodiment of the present application, the low-noise amplifier module 242 and the power supply and load switching circuit 241 can be integrated into a second chip 246 and a third chip 247 using different semiconductor processes, and both the second chip 246 and the third chip 247 are disposed on a second carrier board 245, thereby interconnecting the low-noise amplifier module 242 and the power supply and load switching circuit 241 with other electronic components via the second carrier board 245, thereby realizing a low-noise amplification function during the RF reception process. The low-noise amplifier module 242 and the power supply and load switching circuit 241 are respectively integrated into different chips, thereby facilitating modification or replacement of the low-noise amplifier module 242 and the power supply and load switching circuit 241.

[0213] FIG22 is a packaging structure diagram of a low-noise amplifier provided in another embodiment of the present application.

[0214] As shown in Figure 22, in one embodiment provided in the present application, the low noise amplifier includes a power supply and load switching circuit 241, a low noise amplification module 242, a third carrier board 248, a fourth chip 249 and a fifth chip 250. The low noise amplification module 242 and the power supply and load switching circuit 241 are respectively integrated into the fourth chip 249 and the fifth chip 250. The fourth chip 249 and the fifth chip 250 are stacked on the third carrier board 248.

[0215] In an embodiment of the present application, the low-noise amplifier module 242 and the power and load switching circuit 241 can be integrated into a fourth chip 249 and a fifth chip 250, respectively, using different semiconductor processes. The fourth chip 249 and the fifth chip 250 are then stacked and arranged on a third carrier board 248. This allows the low-noise amplifier module 242 and the power and load switching circuit 241 to be interconnected with other electronic components via the third carrier board 248, thereby achieving a low-noise amplification function during RF reception. For example, the larger chip of the fourth chip 249 and the fifth chip 250 is generally arranged closer to the third carrier board 248. The low-noise amplifier module 242 and the power and load switching circuit 241 are stacked and integrated together on the same carrier board, thereby reducing the size of the low-noise amplifier.

[0216] FIG23 is a packaging structure diagram of a low-noise amplifier provided in another embodiment of the present application.

[0217] As shown in Figure 23, in one embodiment provided in the present application, the low-noise amplifier includes a power supply and load switching circuit 241, a low-noise amplification module 242, a fourth carrier board 251, a fifth carrier board 252, a sixth chip 253 and a seventh chip 254. The low-noise amplification module 242 and the power supply and load switching circuit 241 are respectively integrated into the sixth chip 253 and the seventh chip 254. The sixth chip 253 is arranged on the fourth carrier board 251, the seventh chip 254 is arranged on the fifth carrier board 252, and the fourth carrier board 251 and the fifth carrier board 252 are stacked.

[0218] In an embodiment of the present application, the low-noise amplifier module 242 and the power supply and load switching circuit 241 can be integrated into a sixth chip 253 and a seventh chip 254 using different semiconductor processes, and the sixth chip 253 is disposed on a fourth carrier board 251, and the seventh chip 254 is disposed on a fifth carrier board 252. The fourth carrier board 251 and the fifth carrier board 252 are stacked, so that the low-noise amplifier module 242 and the power supply and load switching circuit 241 are interconnected with other electronic devices through the fourth carrier board 251 and the fifth carrier board 252, thereby realizing a low-noise amplification function during the radio frequency reception process. The low-noise amplifier module 242 and the power supply and load switching circuit 241 are stacked on different carrier boards, thereby facilitating modification or replacement of the low-noise amplifier module 242 and the power supply and load switching circuit 241.

[0219] An embodiment of the present application also provides an electronic device, including multiple low-noise amplifiers as described above, the low-noise amplifier including the above-mentioned power supply and load switching circuit, and by switching different power supply paths of at least two power supplies, at least four performance modes with different linearity and power consumption can be obtained, and by switching different impedance values ​​of at least two loads, at least two performance modes with different operating frequency bands can be obtained, thereby enabling the low-noise amplifier to obtain more different performance modes.

[0220] It should be understood that the above is only an example of the structure of the electronic device 100. The electronic device 100 may also include other subsystems or devices, which can be specifically configured and modified as needed. The embodiments of the present application do not impose any restrictions on this.

[0221] The beneficial effects that can be achieved by the electronic device provided in the above-mentioned embodiments of the present application can be referred to the beneficial effects corresponding to the modules provided above, and will not be repeated here.

[0222] It should be understood that the above is only to help those skilled in the art better understand the embodiments of the present application, and is not intended to limit the scope of the embodiments of the present application. Based on the above examples given, those skilled in the art can obviously make various equivalent modifications or changes. For example, some steps in the various embodiments of the above-mentioned detection method may be unnecessary, or some new steps may be added. Or a combination of any two or any multiple embodiments described above. Such modifications, changes or combined solutions also fall within the scope of the embodiments of the present application. In addition, the coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0223] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0224] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0225] It should also be understood that the above description of the embodiments of the present application focuses on emphasizing the differences between the various embodiments. The same or similar points that are not mentioned can be referenced with each other. For the sake of brevity, they will not be repeated here.

[0226] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0227] It should also be understood that in the embodiments of the present application, "pre-setting" and "pre-definition" can be achieved by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in a device (for example, including an electronic device), and the present application does not limit its specific implementation method.

[0228] It should also be understood that the division of the modes, situations, categories and embodiments in the embodiments of the present application is only for the convenience of description and should not constitute a special limitation. The features of various modes, categories, situations and embodiments can be combined without contradiction.

[0229] It should also be understood that in the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0230] Finally, it should be noted that the above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited to this. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims. In short, the above is only a preferred embodiment of the technical solution of the present application, and is not used to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of the present application.

Claims

1. A power supply and load switching circuit, characterized in that: It includes at least two power supplies, a switch, at least two loads and at least two output ports; At least two ports of the switch are electrically connected to the at least two power sources, respectively, and at least two other ports of the switch are electrically connected to the at least two output ports, respectively, for switching and conducting at least four power supply paths; The at least two loads are respectively arranged in the paths between the at least two power sources and the at least two output ports, so as to adjust the load impedance values ​​of the at least four power paths.

2. The power supply and load switching circuit according to claim 1, wherein: The at least two loads include a first load inductor and a second load inductor; The first load inductor and the second load inductor are respectively arranged in a path between the at least two power sources and the switch.

3. The power supply and load switching circuit according to claim 2, wherein: The first load inductor and the second load inductor are in a coupling relationship.

4. The power supply and load switching circuit according to any one of claims 1 to 3, wherein: The at least two loads include a third load inductor and a fourth load inductor; The third load inductor and the fourth load inductor are respectively arranged in the path between the switch and the at least two output ports.

5. The power supply and load switching circuit according to claim 4, wherein: The third load inductor and the fourth load inductor are in a coupling relationship.

6. The power supply and load switching circuit according to claim 1, wherein: The at least two loads include a first load inductor, a second load inductor, a third load inductor, and a fourth load inductor; The first load inductor and the second load inductor are respectively arranged in the path between the at least two power supplies and the switching switch, the third load inductor and the fourth load inductor are respectively arranged in the path between the switching switch and the at least two output ports, and any two of the first load inductor, the second load inductor, the third load inductor and the fourth load inductor are coupled to each other.

7. The power supply and load switching circuit according to any one of claims 1 to 3, wherein: The at least two power supplies include a first power supply and a second power supply; The first power supply and the second power supply are electrically connected to at least two ports of the switch respectively, and a voltage value of the first power supply is greater than a voltage value of the second power supply.

8. The power supply and load switching circuit according to claim 7, wherein: The switch comprises a double-pole double-throw switch, and the at least two output ports comprise a first output port and a second output port; Two ports of the double-pole double-throw switch are electrically connected to the first power supply and the second power supply respectively, and the other two ports of the double-pole double-throw switch are electrically connected to the first output port and the second output port respectively.

9. The power supply and load switching circuit according to claim 8, wherein: The two switch paths of the double-pole double-throw switch connected to the first power supply are respectively connected with m switch devices in parallel, and the two switch paths of the double-pole double-throw switch connected to the second power supply are respectively connected with n switch devices in parallel, where m≥n.

10. A low noise amplifier, characterized in that: A power supply and load switching circuit comprising the power supply and load switching circuit according to any one of claims 1 to 9.

11. The low noise amplifier according to claim 10, wherein: The low noise amplifier also includes a low noise amplification module; The low-noise amplification module is electrically connected to the power supply and load switching circuit to perform low-noise amplification on the input signal.

12. The low noise amplifier according to claim 11, wherein The low-noise amplification module includes a first amplifier, a second amplifier, a bias circuit and a controller; The power supply and load switching circuit are electrically connected to the first amplifier, the second amplifier and the controller respectively, and the first amplifier and the second amplifier are also electrically connected to the bias circuit; The first amplifier is configured to amplify the first input signal; The second amplifier is configured to amplify the second input signal; The bias circuit is configured to provide a bias voltage to the first amplifier and the second amplifier; The controller is configured to provide a mode switching signal to the power and load switching module.

13. The low noise amplifier according to claim 12, wherein: The first amplifier includes a first transistor, a second transistor, a first input inductor, a first source inductor, a first input port, and a first output port; the bias circuit outputs a first bias voltage and a second bias voltage; The gate of the first transistor is connected to the first input port through the first input inductor, the source of the first transistor is grounded through the first source inductor, the drain of the first transistor is electrically connected to the source of the second transistor, the drain of the second transistor is electrically connected to the first output port, the gate of the first transistor is connected to the first bias voltage, and the gate of the second transistor is connected to the second bias voltage.

14. The low noise amplifier according to claim 13, wherein: The first amplifier further includes a first bias network and a second bias network; The first bias network is connected between the gate of the first transistor and the first bias voltage, and the second bias network is connected between the second transistor and the second bias voltage.

15. The low noise amplifier according to claim 13, wherein: The first amplifier further includes a first input capacitor, a first gate bias capacitor, and a first output capacitor; The first input capacitor is connected between the gate of the first transistor and the first input inductor, the first gate bias capacitor is connected between the gate of the second transistor and the ground terminal, and the first output capacitor is connected between the drain of the second transistor and the first output port.

16. The low noise amplifier according to claim 13, wherein: The first amplifier further includes a fifth switch and a sixth switch; The fifth switch is connected between the gate of the second transistor and the ground terminal, the sixth switch is connected between the gate of the second transistor and the second bias voltage, and the fifth switch and the sixth switch are also electrically connected to the controller respectively.

17. The low noise amplifier according to claim 16, wherein: The first amplifier further includes a first auxiliary path; Two ends of the first auxiliary path are electrically connected to the source of the second transistor and the gate of the second transistor respectively, and the first auxiliary path is also electrically connected to the controller.

18. The low noise amplifier according to any one of claims 12 to 17, wherein: The second amplifier includes a third transistor, a fourth transistor, a second input inductor, a second source inductor, a second input port, and a second output port; the bias circuit outputs a third bias voltage and a fourth bias voltage; The gate of the third transistor is connected to the second input port through the second input inductor. The source of the transistor is grounded through the second source inductor, the drain of the third transistor is electrically connected to the source of the fourth transistor, the drain of the fourth transistor is electrically connected to the second output port, the gate of the third transistor is connected to the third bias voltage, and the gate of the fourth transistor is connected to the fourth bias voltage.

19. The low noise amplifier according to claim 18, wherein The second amplifier further includes a third bias network and a fourth bias network; The third bias network is connected between the gate of the third transistor and the third bias voltage, and the fourth bias network is connected between the fourth transistor and the fourth bias voltage.

20. The low noise amplifier according to claim 18, wherein The second amplifier further includes a second input capacitor, a second gate bias capacitor, and a second output capacitor; The second input capacitor is connected between the gate of the third transistor and the second input inductor, the second gate bias capacitor is connected between the gate of the fourth transistor and the ground terminal, and the second output capacitor is connected between the drain of the fourth transistor and the second output port.

21. The low noise amplifier according to claim 18, wherein The second amplifier further includes a seventh switch and an eighth switch; The seventh switch is connected between the gate of the fourth transistor and the ground terminal, the eighth switch is connected between the gate of the fourth transistor and the fourth bias voltage, and the seventh switch and the eighth switch are also electrically connected to the controller respectively.

22. The low noise amplifier according to claim 21, wherein The second amplifier further includes a second auxiliary path; Two ends of the second auxiliary path are electrically connected to the source of the fourth transistor and the gate of the fourth transistor respectively, and the second auxiliary path is also electrically connected to the controller.

23. The low noise amplifier according to claim 11, wherein The low noise amplifier further includes a first carrier board and a first chip; The low-noise amplifier module and the power supply and load switching circuit are integrated into the first chip, and the first chip is disposed on the first carrier board.

24. The low noise amplifier according to claim 11, wherein The low noise amplifier further includes a second carrier board, a second chip and a third chip; The low-noise amplifier module and the power supply and load switching circuit are integrated into the second chip and the third chip respectively. The second chip and the third chip are arranged on the second carrier board.

25. The low noise amplifier according to claim 11, wherein The low noise amplifier further includes a third carrier board, a fourth chip and a fifth chip; The low-noise amplifier module and the power supply and load switching circuit are respectively integrated into the fourth chip and the fifth chip, and the fourth chip and the fifth chip are stacked and arranged on the third carrier board.

26. The low noise amplifier according to claim 11, wherein The low noise amplifier further includes a fourth carrier board, a fifth carrier board, a sixth chip and a seventh chip; The low-noise amplifier module and the power supply and load switching circuit are respectively integrated in the sixth chip and the seventh chip. The sixth chip is arranged on the fourth carrier board, and the seventh chip is arranged on the fifth carrier board. The fourth carrier board and the fifth carrier board are stacked.

27. An electronic device, characterized in that: The low noise amplifier comprises the low noise amplifier according to any one of claims 10 to 26, wherein the low noise amplifier is used to receive a signal.

28. The power supply and load switching circuit according to claim 1, wherein: It includes at least two power supplies, a switch, at least two loads and at least two output ports; At least two ports of the switch are electrically connected to the at least two power sources, respectively, and at least two other ports of the switch are electrically connected to the at least two output ports, respectively, for switching and conducting at least four power supply paths; The at least two loads are respectively provided in paths between the at least two power sources and the at least two output ports, so as to adjust the load impedance values ​​of the at least four power paths; The at least four power supply paths include: a path between one of the power supplies and one of the output ports, a path between one of the power supplies and another output port, a path between another power supply and one of the output ports, and a path between another power supply and another output port; The at least two loads include a first load inductor, a second load inductor, a third load inductor, and a fourth load inductor; The first load inductor and the second load inductor are respectively arranged in the path between the at least two power supplies and the switching switch, the third load inductor and the fourth load inductor are respectively arranged in the path between the switching switch and the at least two output ports, and any two of the first load inductor, the second load inductor, the third load inductor and the fourth load inductor are coupled to each other.

29. The power supply and load switching circuit according to claim 28, wherein: The at least two power supplies include a first power supply and a second power supply; The first power supply and the second power supply are electrically connected to at least two ports of the switch respectively, and a voltage value of the first power supply is greater than a voltage value of the second power supply.

30. The power supply and load switching circuit according to claim 29, wherein: The switch comprises a double-pole double-throw switch, and the at least two output ports comprise a first output port and a second output port; Two ports of the double-pole double-throw switch are electrically connected to the first power supply and the second power supply respectively, and the other two ports of the double-pole double-throw switch are electrically connected to the first output port and the second output port respectively.

31. The power supply and load switching circuit according to claim 30, wherein: The two switch paths of the double-pole double-throw switch connected to the first power supply are respectively connected with m switch devices in parallel, and the two switch paths of the double-pole double-throw switch connected to the second power supply are respectively connected with n switch devices in parallel, where m≥n.

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