Semiconductor structure manufacturing method, semiconductor structure, and semiconductor device

Abstract

The present disclosure provides a semiconductor structure manufacturing method, a semiconductor structure, and a semiconductor device. The method comprises: providing a substrate, and etching the substrate to form an active structure, the active structure comprising a first end and a second end, and the first end of the active structure being farther from the substrate than the second end of the active structure; forming a first material layer on a first region of the substrate; forming, on the first material layer, a first dummy gate structure spanning the active structure; flipping the semiconductor structure, and removing the substrate to expose the second end of the active structure and the first material layer; using the first material layer as an etching mask, and etching the semiconductor structure until a preset height is reached; depositing a semiconductor material on the semiconductor structure to form a second dummy gate structure; etching the second dummy gate structure until the active structure in a source / drain region is exposed, so as to form a third dummy gate structure; and removing the first dummy gate structure and the third dummy gate structure to form a first gate structure and a second gate structure, respectively.

Description

Semiconductor structure preparation method, semiconductor structure and semiconductor device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202410034012.X and application date of January 9, 2024, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, and a semiconductor device. Background Art

[0004] As Moore's Law continues to deepen, furthering transistor scaling is a hot topic in the industry. Stacked transistors, by integrating two or more layers of transistors vertically, further increase transistor integration density and become a key technology for further scaling integrated circuits.

[0005] When stacked transistors are prepared using a traditional sequential approach, it is difficult to self-align the gate structures between upper and lower transistors, and the preparation process is complicated.

[0006] Summary of the Invention

[0007] The present disclosure provides a method for preparing a semiconductor structure, a semiconductor structure, and a semiconductor device.

[0008] The first aspect of the present disclosure provides a method for preparing a semiconductor structure. The method includes: providing a substrate and etching the substrate to form an active structure; wherein the active structure includes a first end and a second end, and the first end of the active structure is farther away from the substrate than the second end of the active structure; forming a first material layer on a first region of the substrate, the first region being located in the gate region on both sides of the active structure; forming a first dummy gate structure across the active structure on the first material layer; flipping the semiconductor structure and removing the substrate to expose the second end of the active structure and the first material layer; using the first material layer as an etching mask, etching the semiconductor structure until a preset height is reached; depositing semiconductor material on the semiconductor structure to form a second dummy gate structure; the height of the second dummy gate structure in the gate region is higher than the height of the second dummy gate structure in the source and drain region; etching the second dummy gate structure until the active structure in the source and drain region is exposed to form a third dummy gate structure; removing the first dummy gate structure and the third dummy gate structure to form a first gate structure and a second gate structure, respectively.

[0009] A second aspect of the present disclosure provides a semiconductor structure. This semiconductor structure can be fabricated using the fabrication method described in any embodiment of the first aspect. It includes: a first transistor; and a second transistor, wherein the first transistor and the second transistor are disposed opposite each other; wherein a first active structure of the first transistor and a second active structure of the second transistor form an active structure, and a first gate structure of the first transistor and a second gate structure of the second transistor are self-aligned.

[0010] A third aspect of the present disclosure provides a semiconductor device, comprising: a semiconductor structure as in any one of the embodiments of the second aspect.

[0011] Compared with the prior art, the present disclosure has the following beneficial effects:

[0012] In the present disclosure, during the preparation of the first transistor in the lower layer, a first material layer is set in the gate area, so that after flipping the wafer, the gate area of ​​the second transistor can be determined based on the position of the first material layer, thereby achieving self-alignment of the gate structures of the upper and lower transistors.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0015] FIG1 is a schematic flow chart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0016] FIG2 is a schematic structural diagram of a semiconductor structure provided according to an embodiment of the present disclosure.

[0017] 3 to 21 are schematic diagrams of a process for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0018] FIG22 is a schematic structural diagram of a semiconductor structure provided according to an embodiment of the present disclosure.

[0019] FIG23 is a schematic structural diagram of a semiconductor structure provided according to an embodiment of the present disclosure.

[0020] FIG24 is a schematic structural diagram of a semiconductor structure provided according to an embodiment of the present disclosure.

[0021] 25 to 30 are schematic diagrams of a process for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0022] 31 to 34 are schematic diagrams of a process for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0023] DESCRIPTION OF REFERENCE NUMERALS: semiconductor structure 10; first transistor 11; second transistor 12; active structure 13; first active structure 131; Second active structure 132; substrate 21; fin structure 211; first portion 2111 of the fin structure; second portion 2112 of the fin structure; oxide layer 22; silicon nitride material layer 23; first dummy gate structure 24; first material layer 25; shallow trench isolation structure 26; first spacer 27; first source-drain structure 28; first interlayer dielectric layer 29; first source-drain metal 30; first metal interconnect layer 31; first insulating layer 32; carrier 33; first groove 34; second dummy gate structure 35; third dummy gate structure 36; second spacer 37; second source-drain structure 38; second interlayer dielectric layer 39; metal gate structure 40; metal gate dielectric layer 401; metal gate electrode layer 402; first gate structure 41; second insulating layer 42; second gate structure 43; second source-drain metal 44; second metal interconnect layer 45; buried oxide layer 46; nanosheet structure 47. DETAILED DESCRIPTION

[0024] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible implementations consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present disclosure.

[0025] The terms used in the embodiments of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the embodiments of the present disclosure. The singular forms "a," "the," and "the" used in the present disclosure are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0026] As Moore's Law continues to deepen, furthering transistor scaling is a hot topic in the industry. Stacked transistors, through three-dimensional transistor stacking, enable the integration of two or more layers of transistors in a vertical space, helping to further increase transistor integration density and improve circuit performance. This is considered a key technology for continuing the scaling of integrated circuits.

[0027] In one embodiment, there are two schemes for the manufacturing process of stacked transistors, the first is a monolithic scheme, and the second is a sequential scheme.

[0028] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This means that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layers of transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and it is necessary to rely on two layers of transistors to form a basic complementary metal oxide semiconductor circuit, which has poor design flexibility.

[0029] The second solution is based on wafer bonding and layer-by-layer processing. In one example, the upper transistor is prepared by bonding a wafer on top of the fabricated lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance.

[0030] The current challenge of the above solution is that due to the fixed manufacturing process, there is a problem of difficulty in aligning the upper and lower transistors.

[0031] In order to solve the above technical problems, an embodiment of the present disclosure provides a method for preparing a semiconductor structure to achieve self-alignment of gate structures between upper and lower transistors.

[0032] In the embodiments of the present disclosure, the semiconductor structure can be applied to semiconductor devices such as memories and processors.

[0033] In some embodiments, embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure may include at least two transistors, which may be a first transistor and a second transistor. The first transistor and the second transistor are disposed opposite each other. A first active structure in the first transistor and a second active structure in the second transistor are formed through the same process. In this case, it can be understood that the first transistor and the second transistor are self-aligned.

[0034] In the embodiment of the present disclosure, the first transistor and the second transistor in the semiconductor structure may be transistors of the same type, such as any one of the following: a fin field effect transistor, a gate-all-around transistor, and a planar transistor.

[0035] In some embodiments, the present disclosure provides a method for fabricating a semiconductor structure.

[0036] FIG1 is a schematic flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG1 , the method for fabricating a semiconductor structure according to an embodiment of the present disclosure includes steps S101 to S108.

[0037] In step S101 , a substrate is provided, and the substrate is etched to form an active structure.

[0038] In one embodiment, the active structure includes a first end and a second end, and the first end of the active structure is farther from the substrate than the second end of the active structure.

[0039] It should be noted that when the transistor in the semiconductor structure is a fin field-effect transistor, the active structure is a fin structure; when the transistor in the semiconductor structure is a full-surround gate transistor, the active structure is a nanosheet structure; when the transistor in the semiconductor structure is a planar transistor, the active structure is a block structure.

[0040] In one embodiment, the substrate may be a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate, or a substrate made of other semiconductor materials, which is not limited in the embodiments of the present disclosure.

[0041] It is understood that when the type of semiconductor structure is different, the substrate configuration also varies accordingly. In one example, when the semiconductor structure is a fin field-effect transistor or a planar transistor, the semiconductor substrate can be a single-layer structure, that is, a substrate made of a single semiconductor material; when the semiconductor structure is a gate-all-around transistor, the semiconductor substrate can be a stacked structure, that is, a stacked layer formed by stacking Si material and silicon germanium (SiGe) material.

[0042] In some embodiments, when the semiconductor structure is a fin field effect transistor, the step S101 may include: etching the substrate to form a plurality of fin structures.

[0043] In some other embodiments, when the semiconductor structure is a gate-all-around transistor, the step S101 may include: etching the substrate to form a columnar structure, wherein the substrate may be formed of alternately deposited silicon layers and silicon germanium layers.

[0044] In some other embodiments, when the semiconductor structure is a planar transistor, the above step S101 may include: etching the substrate to form a block structure.

[0045] In the embodiment of the present disclosure, since the semiconductor structure includes two transistors, and the first active structure of the first transistor and the second active structure of the second transistor are formed by the same etching process, a larger etching depth can be used when etching the semiconductor substrate. In one example, the height of the fin structure (which can also be a columnar structure or a block structure) obtained by etching can be greater than 100nm. It should be noted that the height of the fin structure can be set according to actual conditions, and the embodiment of the present disclosure does not limit this.

[0046] In one embodiment, the substrate may be an SOI substrate, comprising: a first substrate layer, a second substrate layer, and a buried oxide layer stacked together, with the buried oxide layer located between the first substrate layer and the second substrate layer. Step S101 may include etching a first portion of the first substrate layer, the buried oxide layer, and the second substrate layer, while retaining a second portion of the second substrate layer, to form an active structure.

[0047] In one embodiment, the first substrate layer forms a first portion of an active structure (i.e., a first active structure of a first transistor), and the first portion of a second substrate layer forms a second portion of an active structure (i.e., a second active structure of a second transistor). The first portion of the active structure is further away from the substrate than the second portion of the active structure, with a first end of the active structure located at an end of the first portion, and a second end of the active structure located at an end of the second portion.

[0048] In one embodiment, an SOI substrate including a buried oxide layer can be formed through a variety of fabrication processes, which are not limited in the present disclosure. In one example, a SOI substrate having a buried oxide layer is prepared by sequentially performing a buried oxide layer fabrication, hydrogen ion implantation, bonding, and cleaving processes on a single crystal silicon wafer; alternatively, the SOI substrate is prepared by implanting oxygen ions to a certain depth below the surface of the silicon wafer. After the ion implantation, a high-temperature annealing step is performed to form a layer of buried silicon dioxide (buried oxide layer) within the silicon wafer.

[0049] In step S102 , a first material layer is formed on a first region of a substrate.

[0050] In one embodiment, the first region is located in the gate region on both sides of the active structure.

[0051] It is understood that after etching the substrate to form the active structure, a first material layer can be formed based on the etched substrate. The first material layer is located in the first region, that is, the first material layer is located in the gate region of the semiconductor structure, and the first material layer does not cover the active structure but is located on both sides of the active structure.

[0052] It should be noted that the semiconductor structure includes a gate structure that spans the active structure. The location of the gate structure can be divided into a gate region of the semiconductor structure. The semiconductor structure also includes source and drain structures located on both sides of the gate structure. The location of the source and drain structures can be divided into a source and drain region of the semiconductor structure. The gate region and the source and drain region can be spaced apart.

[0053] In some embodiments, the above step S102 may include: depositing a hard mask material on the etched substrate until the second groove formed by the active structure is filled, and using a back etching process to remove the hard mask material on the active structure to form a second material layer; removing the second material layer located on the source and drain areas to form a first material layer on the first area of ​​the substrate.

[0054] In one embodiment, the active structure protrudes from the second material layer, which can also be understood as the second material layer surrounding the circumference of the second end of the active structure but not covering the active structure.

[0055] It can be understood that after the second material layer on the source and drain regions is removed, the second material layer still remains in the gate region of the semiconductor structure, and the retained second material layer is the first material layer.

[0056] In one embodiment, the first material layer can be used as a hard mask in a subsequent etching process. The hard mask material forming the first material layer can be a material that is corrosion-resistant and has a high hardness. In one example, the hard mask material forming the first material layer can be silicon nitride (SiN), silicon dioxide (SiO2), etc.

[0057] In other embodiments, the above-mentioned step S102 may include: depositing a first oxide material on the etched substrate to form an oxide layer; depositing a hard mask material on the oxide layer until the second groove formed by the active structure is filled, and using a back etching process to remove the hard mask material on the active structure to form the above-mentioned second material layer.

[0058] It is understood that before forming the first material layer, a first oxide material can be deposited to form an oxide layer. The oxide layer can protect the active structure by preventing the first material layer from directly contacting the substrate and generating significant stress. In one example, when the active structure is a fin-shaped structure, the oxide layer can prevent the stress between the first material layer and the substrate from causing the fin-shaped structure to collapse. The oxide layer can also protect the surface of the active structure (such as the interface state).

[0059] In one embodiment, the first oxide material may be silicon dioxide, silicon oxycarbide (SiCO), etc., which is not limited in the embodiment of the present disclosure.

[0060] In step S103 , a first dummy gate structure is formed on the first material layer, crossing the active structure.

[0061] It is understandable that a semiconductor material is deposited on the first material layer to form a first dummy gate structure, wherein the first dummy gate structure spans the active structure and wraps the active structure.

[0062] In some embodiments, the semiconductor material forming the first dummy gate structure may be polysilicon.

[0063] In some embodiments, after forming the first dummy gate structure, spacers may be formed on both sides of the first dummy gate structure.

[0064] In some embodiments, after the above step S103, it can include: depositing a second oxide material in the source and drain region to form a shallow trench isolation structure, the shallow trench isolation structure covers the second part of the active structure and exposes the first part of the active structure; in the source and drain region, based on the first part, forming a first source and drain structure, a first source and drain metal and a first interlayer dielectric layer.

[0065] It is understood that after the dummy gate structure is formed, a second oxide material can be deposited in the source and drain regions to form a shallow trench isolation (STI) structure. The height of the STI structure is sufficient to ensure that the STI structure covers the second portion of the active structure and exposes the first portion of the active structure.

[0066] In some embodiments, the first portion of the active structure may be exposed by etching the shallow trench isolation structure, and the exposed first portion of the active structure is used in subsequent fabrication processes.

[0067] In the embodiment of the present disclosure, the second oxide material forming the shallow trench isolation structure may be silicon nitride (SiN, Si3N4), silicon dioxide, silicon oxycarbide, etc.

[0068] It should be noted that the etching processes mentioned in the embodiments of the present disclosure may include: dry etching, wet etching, reactive ion etching, chemical oxide removal process, etc., and the embodiments of the present disclosure are not limited to this.

[0069] In some embodiments, after exposing the first portion of the active structure, ion implantation may be performed at the connection between the first portion of the active structure and the second portion of the active structure to form an electrical isolation layer, which is used to electrically isolate the first portion of the active structure (the first active structure) and the second portion of the active structure (the second active structure).

[0070] In one embodiment, the ions implanted include P-type ions, N-type ions, or oxygen ions. The P-type ions may be one of the following: boron (B), gallium (Ga), or aluminum (Al). The N-type ions may be one of the following: phosphorus (P), arsenic (As), or antimony (Sb).

[0071] It should be noted that when the substrate has a buried oxide layer, the buried oxide layer can form a natural electrical isolation between the first portion and the second portion, thereby eliminating the need for ion implantation at the connection between the first portion and the second portion.

[0072] It can be understood that after the first portion of the active structure is exposed, a first source-drain structure, a first source-drain metal and a first interlayer dielectric layer may be formed in the source-drain region based on the first portion of the active structure.

[0073] In one embodiment, the first interlayer dielectric layer may wrap the first active structure, the first source / drain structure, and the first source / drain metal.

[0074] It should be noted that the first source-drain structure, the first source-drain metal and the first interlayer dielectric layer can all be formed through standard steps of a semiconductor manufacturing process, and the embodiments of the present disclosure do not limit this.

[0075] For example, a source / drain groove may be formed in the exposed first portion of the active structure. Source / drain epitaxial growth may be performed in the source / drain groove to obtain a first source / drain structure. A metal material may be deposited above the first source / drain structure to obtain a first source / drain metal. A semiconductor material may be deposited above the first active structure to obtain a first interlayer dielectric layer.

[0076] For example, a portion of the first active structure is removed by etching to provide source / drain grooves of the first semiconductor structure. A strained material such as silicon germanium or silicon carbide is formed in the source / drain grooves by selective epitaxial growth to fill the source / drain grooves of the first semiconductor structure. A heavy doping process is then performed to form the first source / drain structure on the strained material.

[0077] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present disclosure is a shorthand term, and in one example, refers to the first source electrode structure and / or the first drain electrode structure. Furthermore, the second source-drain structure, the first source-drain metal, the second source-drain metal, the source-drain grooves, and the like are similar to the first source-drain structure, where "source-drain" is a shorthand term for "source and / or drain."

[0078] In some embodiments, after the above step S103, the above method further includes: completing the post-process structure through standard steps of the semiconductor manufacturing process, and bonding the formed semiconductor structure to the carrier wafer.

[0079] It is understood that after forming the first interlayer dielectric layer, back-end processes (such as interlayer dielectric deposition, metal line formation, lead pad formation, etc.) can be performed on the first interlayer dielectric layer and the first dummy gate structure to form a first metal interconnect layer of the first transistor. An insulating material (such as silicon oxide) is deposited on the first metal interconnect layer to form a first insulating layer, and the first insulating layer is bonded to the carrier wafer.

[0080] In the embodiment of the present disclosure, the first semiconductor structure is bonded to the carrier wafer, which can provide physical support for the flipped semiconductor structure after flipping the wafer, effectively preventing the first semiconductor structure from being broken by external force during the preparation of the second transistor.

[0081] In step S104 , the semiconductor structure is flipped over and the substrate is removed to expose the second end of the active structure and the first material layer.

[0082] It is understood that the semiconductor structure formed in step S103 can be flipped over so that the substrate of the semiconductor structure faces upward, and then the substrate is removed by etching. After removing the substrate, the second end of the active structure and the first material layer formed in step S102 can be exposed.

[0083] In one embodiment, the first material layer is located on both sides of the active structure of the gate region.

[0084] In some implementations, when an oxide layer is formed on the substrate, the above step S104 may include: removing the substrate using a planarization process until the second end of the active structure and the oxide layer are exposed; and removing the oxide layer in the gate region to expose the first material layer in the gate region.

[0085] It is understandable that by performing a chemical-mechanical planarization (CMP) process on the substrate, the second end and the oxide layer of the active structure can be exposed, and then the oxide layer in the gate region is etched to expose the first material layer.

[0086] In step S105 , the semiconductor structure is etched using the first material layer as an etching mask until a preset height is reached.

[0087] It can be understood that using the first material layer as an etching mask can protect the first dummy gate structure at the bottom of the first material layer from being etched, while the remaining structures not covered by the first material layer will be etched to a preset height.

[0088] In one embodiment, the predetermined height is less than the height of the second portion of the active structure. The predetermined height is correlated with the width of the active region to ensure that a groove with a predetermined aspect ratio is formed in the gate region and that the height of the second portion of the active structure is sufficient for the back-side transistor.

[0089] In one embodiment, when preparing a 10 nm wide fin transistor, the preset height is 5-10 nm.

[0090] In one embodiment, the above-mentioned step S105 may include: using the first material layer as an etching mask to selectively etch the second end of the active structure in the gate area, the second end of the active structure in the source and drain area, and the shallow trench structure surrounding the active structure, until the height difference between the active structure and the first dummy gate structure reaches a preset height, thereby forming a first groove in the gate area.

[0091] It is understood that by selectively etching the second end of the active structure in the gate region, the height of the first dummy gate structure in the gate region can be maintained, and the active structure in the gate region is etched down to a predetermined height, thereby forming a first recess in the gate region. The position of the first recess corresponds to the position of the active structure. By selectively etching the second end of the active structure in the source / drain region and the shallow trench structure surrounding the active structure, the entire structure in the source / drain region can be etched down to a predetermined height, and the height of the source / drain region is the same as the height of the bottom of the first recess.

[0092] It should be noted that, in the semiconductor structure formed in step S105 , the height of the first dummy gate structure in the gate region is higher than the heights of other structures.

[0093] In some embodiments, after the above step S105 , the method may further include: removing the first material layer.

[0094] As can be understood, the first material layer is used to locate the gate region and serve as an etching mask in the etching process. After etching is completed in step S105, the height of the first dummy gate structure in the gate region is higher than the height of the source and drain regions, and the gate region can be preliminarily located. At this point, the first material layer can be removed.

[0095] In step S106 , a semiconductor material is deposited on the semiconductor structure to form a second dummy gate structure.

[0096] Wherein, the height of the second dummy gate structure in the gate region is higher than the height of the second dummy gate structure in the source and drain regions.

[0097] It can be understood that the height of the first pseudo gate in the gate region of the semiconductor structure formed in step S105 is higher than the height at other positions, and the semiconductor material is deposited on the semiconductor, and the height of the second pseudo gate structure formed in the gate region must be higher than the height in the source and drain regions.

[0098] In some embodiments, the semiconductor material of the second dummy gate structure may be the same as the material of the first dummy gate structure. In one example, the semiconductor material of the second dummy gate structure may be polysilicon, silicon nitride, or amorphous carbon.

[0099] In some embodiments, the above step S106 may include: depositing semiconductor material on the source and drain regions and the gate region having the first groove using an isotropic deposition method until the first groove is filled; etching polysilicon using an anisotropic etching method until the active structure of the source and drain regions is exposed, and forming a third dummy gate structure in the gate region.

[0100] It is understandable that, because the semiconductor material is deposited using an isotropic process, polysilicon will also be deposited on the sidewalls of the first recess formed in the gate region. Therefore, the deposition rate in the first recess will be higher than the deposition rate in the source and drain regions. Consequently, after the first recess is filled, the height of the second dummy gate structure in the first recess is higher than that in the source and drain regions. That is, the second dummy gate structure in the gate region is higher than the second dummy gate structure in the source and drain regions.

[0101] In one embodiment, based on the feature that the second dummy gate structure of the gate region is higher than the second dummy gate structure of the source and drain regions, the gate region and the source and drain regions can be distinguished, and the position of the gate region can be obtained in a self-aligned manner, so that a self-aligned dummy gate structure can be formed in subsequent steps.

[0102] In step S107 , the second dummy gate structure is etched until the active structure of the source and drain regions is exposed to form a third dummy gate structure.

[0103] It is understandable that, because the height of the second dummy gate structure in the gate region is higher than that in the source and drain regions, the second dummy gate structure formed in etching step S106 will first expose the active structures in the source and drain regions. When the active structures in the source and drain regions are exposed, etching can be stopped, and the second dummy gate structure in the gate region is retained, thus forming a third dummy gate structure.

[0104] In some embodiments, the above step S107 may include: etching the second dummy gate structure using an anisotropic etching method until the active structure of the source and drain regions is exposed, and forming a third dummy gate structure in the gate region.

[0105] It can be understood that by etching the second dummy gate structure using an anisotropic etching process, the height difference between the second dummy gate structure in the gate region and the source and drain region will not change, thereby removing the second dummy gate structure in the source and drain region and retaining the crystalline silicon structure (third dummy gate structure) in the gate region, thereby forming a self-aligned dummy gate structure of the semiconductor structure, that is, the first dummy gate structure and the third dummy gate structure are self-aligned.

[0106] In some embodiments, after the above step S107, it may include: thinning the shallow trench isolation structure in the source and drain region to expose the second portion of the active structure; in the source and drain region, forming a second source and drain structure, a second source and drain metal and a second interlayer dielectric layer based on the second portion of the active structure.

[0107] In one embodiment, the process of forming the second source-drain structure, the second source-drain metal and the second interlayer dielectric layer can refer to the process of forming the first source-drain structure, the first source-drain metal and the first interlayer dielectric layer, that is, refer to the description in one or more embodiments in step S103.

[0108] In step S108 , the first dummy gate structure and the third dummy gate structure are removed to form a first gate structure and a second gate structure respectively.

[0109] It can be understood that after forming the self-aligned first dummy gate structure and the third dummy gate structure, the first dummy gate structure and the third dummy gate structure can be removed, and metal material can be deposited to form the first gate structure and the second gate structure respectively.

[0110] It should be noted that the first gate structure and the second gate structure can be formed through standard steps of a semiconductor manufacturing process, and the embodiments of the present disclosure are not limited to this.

[0111] In the embodiment of the present disclosure, the metal materials of the first gate structure and the second gate structure may be tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), etc. The materials of the first gate structure and the second gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

[0112] In the embodiment of the present disclosure, the materials of the first gate structure and the second gate structure can be made of the same or different metal materials according to actual conditions, and the embodiment of the present disclosure does not limit this.

[0113] In some embodiments, the above step S108 may include: removing the first dummy gate structure and the third dummy gate structure, depositing a first metal material at the removed first dummy gate structure to form a first gate structure; the height of the first gate structure wraps the first portion of the active structure; and depositing a second metal material on the first gate structure until it covers the removed third dummy gate structure to form a second gate structure.

[0114] In one embodiment, the first end of the active structure is located at the first portion, and the first portion of the active structure is used to form a first transistor.

[0115] It can be understood that a first metal material is deposited at the first dummy gate structure to form a first gate structure, and the first gate structure is made to wrap the first part of the active structure, exposing the second part of the active structure, so that a first transistor can be formed based on the first part of the active structure. A second metal material is deposited on the first gate structure until the second metal material covers the removed third gate structure to form a second gate structure, so that the second gate structure wraps the second part of the active structure, so that a second transistor can be formed based on the second part of the active structure. In the above process, the first dummy gate structure and the third dummy gate structure are self-aligned, so that the first gate structure and the second gate structure are self-aligned.

[0116] In one embodiment, the first metal material is different from the second metal material.

[0117] In one embodiment, step S108 may include: removing the first dummy gate structure and the third dummy gate structure to form a metal gate; selectively etching the upper half of the metal gate, while retaining the lower half of the metal gate, to form a first gate structure; depositing an insulating dielectric on the first gate structure to form an insulating layer. The insulating layer is used to isolate the first gate structure of the first transistor from the second gate structure of the second transistor; and depositing a metal material on the insulating layer to form a second gate structure.

[0118] In one embodiment, the metal gate may include: a gate dielectric layer and a gate electrode layer.

[0119] In one embodiment, etching the upper metal gate may include etching the gate electrode layer in the upper half, wherein the gate dielectric layer and the gate electrode layer in the lower half form a first gate structure, and the gate dielectric layer in the upper half and the metal material deposited in the upper half form a second gate structure.

[0120] In one embodiment, etching the upper metal gate may further include etching the upper gate dielectric layer and the upper gate electrode layer. When a metal material is deposited on the insulating layer, a second gate structure is directly formed.

[0121] In some embodiments, after step S108 , the method further includes: completing a post-process structure through standard steps of a semiconductor manufacturing process to form the semiconductor structure in the embodiment of the present disclosure.

[0122] It can be understood that after the first gate structure and the second gate structure are formed, a subsequent process (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.) can be performed on the second source-drain metal and the second gate structure to form a second metal interconnect layer of the second transistor.

[0123] In the embodiment of the present disclosure, a substrate is provided and an active structure is formed on the substrate, so that the active structure of two transistors can be formed through one process; the first transistor is formed by using the first part of the active structure, and the second transistor is formed by using the second part of the active structure after flipping the wafer, so that the upper and lower layers of transistors are self-aligned.

[0124] In addition, during the preparation of the first transistor in the lower layer, a first material layer is set in the gate area so that the gate area of ​​the second transistor can be determined based on the position of the first material layer after flipping the wafer, thereby achieving self-alignment of the gate structures of the upper and lower transistors.

[0125] Below, taking the active structure in the semiconductor structure as a fin structure as an example, the preparation method of the semiconductor structure provided by the embodiment of the present disclosure is described. Figure 2 is a structural schematic diagram of a semiconductor structure provided according to an embodiment of the present disclosure. Among them, (a) in Figure 2 is a top view of the semiconductor structure. It should be noted that, for ease of understanding, only the fin structure, gate structure, and source-drain structure are shown in the top view; (b) in Figure 2 is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., AA' direction); (c) in Figure 2 is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., BB' direction); (d) in Figure 2 is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the fin structure (i.e., CC' direction).

[0126] As shown in FIG2 , a semiconductor structure 10 includes a first transistor 11 and a second transistor 12. The active structure in the semiconductor structure 10 is a plurality of fin-shaped structures. The fin-shaped structures are divided into two parts, denoted as a first part and a second part, respectively. The first part serves as the first active structure in the first transistor 11, and the second part serves as the second active structure in the second transistor 12. The first gate structure 41 in the first transistor 11 and the second gate structure 43 in the second transistor 12 are self-aligned.

[0127] In one embodiment, self-alignment means that the first gate structure 41 and the second gate structure 43 are aligned during the fabrication process.

[0128] The preparation process of the semiconductor structure shown in Figure 2 is described below in conjunction with the above-mentioned preparation method. Figures 3 to 21 are schematic diagrams of a preparation process of a semiconductor structure provided according to an embodiment of the present disclosure, wherein Figure 3 (a) to Figure 21 (a) are cross-sectional views of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., the AA' direction), Figure 3 (b) to Figure 21 (b) are cross-sectional views of the semiconductor structure along the cross-sectional direction of the source and drain structure (i.e., the BB' direction); Figure 3 (c) to Figure 21 (c) are cross-sectional views of the semiconductor structure along the cross-sectional direction of the fin structure (i.e., the CC' direction).

[0129] In one example, a process for preparing the semiconductor structure 10 may include the following steps:

[0130] Step 1: Patterning and etching are performed on the silicon substrate 21 through standard steps of semiconductor manufacturing technology to form a fin structure 211 , thereby obtaining the structure shown in FIG3 .

[0131] It should be noted that the height of the fin structure 211 may be greater than 100 nm.

[0132] Step 2: depositing an oxide material on the structure shown in FIG3 to form an oxide layer 22 of the fin structure; then depositing silicon nitride on the oxide layer 22 and etching back the silicon nitride to form a silicon nitride material layer on the substrate to obtain the structure shown in FIG4 .

[0133] Step 3: Open the gate region of the structure shown in FIG. 4 by photolithography and development, and deposit polysilicon on the gate region as a first dummy gate structure 24 to obtain the structure shown in FIG. 5 .

[0134] In one embodiment, the first dummy gate structure 24 spans across the plurality of fin structures 211 in the AA′ direction and is arranged at intervals in the CC′ direction.

[0135] Step 4: remove the silicon nitride material layer 23 in the area not covered by the dummy gate to obtain the structure shown in FIG. 6 .

[0136] It can be understood that the silicon nitride material layer that is not removed forms the first material layer 25 , and the first material layer 25 covers the first region.

[0137] In one embodiment, the first region is located at the gate region on both sides of the fin structure 211 .

[0138] Step 5: Deposit an oxide material in the source / drain region of the structure shown in FIG6 to form a first shallow trench isolation layer; then etch the first shallow trench isolation layer to form a second shallow trench isolation layer (i.e., shallow trench isolation structure 26). The top surface of the shallow trench isolation structure 26 is lower than the first portion 2111 (top) of the fin structure 211, resulting in the structure shown in FIG7.

[0139] Step 6: In the gate region of the structure shown in FIG7 , the first spacer 27 of the first transistor 11 is formed through standard steps of the semiconductor manufacturing process; in the source / drain region of the structure shown in FIG7 , the first source / drain structure 28 and the first interlayer dielectric layer 29 of the first transistor 11 are completed through standard steps of the semiconductor manufacturing process to obtain the structure shown in FIG8 .

[0140] Step 7: Complete the first source and drain metal 30 of the first transistor 11 in the source and drain regions of the structure shown in FIG8 , and complete the back-end interconnection process of the first transistor 11 above the source and drain regions and the gate region to form a first metal interconnection layer 31. The first metal interconnection layer 31 is connected to the first source and drain metal 30, resulting in the structure shown in FIG9 .

[0141] Step 8: Deposit an insulating oxide on the structure shown in FIG. 9 to form a first insulating layer 32 ; bond the carrier 33 to the first transistor 11 above the first insulating layer 32 , and then flip the wafer over to obtain the structure shown in FIG. 10 .

[0142] Step 9: Thin the wafer and use a chemical mechanical planarization process to selectively stop above the oxide layer 22, thereby exposing the end of the second portion 2112 of the fin structure 211 to obtain the structure shown in FIG11.

[0143] Step 10: Use a selective etching process to etch the oxide layer 22 and the fin structure 211 , etching at least to a preset height to obtain the structure shown in FIG. 12 .

[0144] In one embodiment, the first material layer 25 in the first region can serve as an etching mask to protect the first dummy gate structure 24 at the bottom of the first material layer 25 from being etched. Thus, multiple first grooves 34 are formed in the gate region along the AA' direction. The depth of the first grooves 34 is equal to a predetermined height.

[0145] Step 11: Deposit polysilicon on the structure shown in FIG. 12 using an isotropic deposition method to obtain the structure shown in FIG. 13 .

[0146] It should be noted that, because the deposition method is isotropic, deposition also occurs on the sidewalls of the first recess 34 in the gate region. Therefore, the deposition thickness in the first recess 34 (as indicated by the solid arrow in FIG13 ) is higher than that in the source and drain regions (as indicated by the dotted arrow in FIG13 ). When observing the cross-section of the fin structure ( FIG13 (c) ), the polysilicon in the gate region is thicker than the polysilicon in the source and drain regions.

[0147] In one embodiment, polysilicon is deposited until the first groove 34 in the gate region is filled, thereby obtaining the structure shown in FIG. 14 .

[0148] It should be noted that after the first groove 34 in the gate region is filled, a second dummy gate structure 35 is formed. When observing the cross-section of the fin structure ((c) in FIG14 ), the height of the second dummy gate structure 35 in the gate region (indicated by the solid arrow in FIG14 ) is higher than the height of the second dummy gate structure 35 in the source and drain regions (indicated by the dotted arrow in FIG14 ).

[0149] Step 12: Etch the second dummy gate structure 35 in the structure shown in FIG. 14 using an anisotropic etching method until the polysilicon in the source and drain regions is completely removed, leaving only the polysilicon in the gate region, to obtain the structure shown in FIG. 15 .

[0150] It should be noted that, due to the anisotropic etching method, the height difference between the polysilicon in the gate region and the source and drain regions does not change. After the polysilicon in the source and drain regions is completely etched, polysilicon still exists in the gate region. The polysilicon in the gate region can form the third dummy gate structure 36.

[0151] It should be noted that the third dummy gate structure 36 is located in the gate region, thereby achieving self-alignment with the first dummy gate structure 24 .

[0152] Step 13: remove the first material layer 25 on the structure shown in FIG. 15 , and selectively etch the shallow trench isolation structure 26 to expose the second portion 2112 of the fin structure 211 , thereby obtaining the structure shown in FIG. 16 .

[0153] It should be noted that the exposed second part 2112 of the fin structure 211 is prepared using the same process as the first part 2111 of the fin structure 211. Therefore, the fin structures 211 of the first transistor 11 and the second transistor 12 are of the same origin, so that during the preparation of the second transistor 12, the active structure is self-aligned without the need for additional photolithography.

[0154] In one embodiment, the first material layer 25 may be removed before the eleventh step.

[0155] Step 14: In the gate region of the structure shown in FIG16 , the second spacer 37 of the second transistor 12 is formed through standard steps of the semiconductor manufacturing process; in the source / drain region of the structure shown in FIG15 , the second source / drain structure 38 and the second interlayer dielectric layer 39 of the second transistor 12 are completed through standard steps of the semiconductor manufacturing process to obtain the structure shown in FIG17 .

[0156] Step 15: remove the first dummy gate structure 24 and the third dummy gate structure 36 , and deposit metal material at the positions of the first dummy gate structure 24 and the third dummy gate structure 36 to form a metal gate structure 40 , thereby obtaining the structure shown in FIG. 18 .

[0157] It should be noted that the metal gate structure 40 may include a metal gate dielectric layer 401 and a metal gate electrode layer 402 .

[0158] Step 16: Selectively etch the metal gate structure 40 in the structure shown in FIG. 18 to remove the metal gate structure 40 in the second transistor 12 region to obtain the structure shown in FIG. 19 .

[0159] It should be noted that, in this step, only the metal gate electrode layer 402 in the metal gate structure 40 may be etched.

[0160] In some embodiments, the metal gate dielectric layer 401 and the metal gate electrode layer 402 in the metal gate structure 40 may be etched.

[0161] It should be noted that the retained metal gate structure 40 in the region of the first transistor 11 may form a first gate structure 41 .

[0162] Step 17: Deposit an insulating material on the first gate structure 41 to form a second insulating layer 42 to obtain the structure shown in FIG. 20 .

[0163] Step 18: depositing a metal material on the second insulating layer 42 to form a second gate structure 43 of the second transistor 12 to obtain the structure shown in FIG. 21 .

[0164] In one embodiment, the first gate structure 41 of the first transistor 11 and the second gate structure 43 of the second transistor 12 may be self-aligned.

[0165] It should be noted that the second insulating layer 42 is used to electrically isolate the first gate structure 41 from the second gate structure 43 .

[0166] Step 19: Complete the second source and drain metal 44 of the second transistor 12 in the source and drain regions of the structure shown in FIG21 , and complete the back-end interconnection process of the second transistor 12 above the source and drain regions and the gate region to form a second metal interconnection layer 45. The second metal interconnection layer 45 is connected to the second source and drain metal 44, resulting in the structure shown in FIG2 .

[0167] At this point, the first transistor and the second transistor are completed, and the first gate structure 41 and the second gate structure 43 are aligned.

[0168] In one example, FIG22 is a schematic structural diagram of a semiconductor structure provided according to an embodiment of the present disclosure. FIG22(a) is a cross-sectional view of the semiconductor structure taken along the gate structure (i.e., the AA' direction), FIG22(b) is a cross-sectional view of the semiconductor structure taken along the source / drain structure (i.e., the BB' direction), and FIG22(c) is a cross-sectional view of the semiconductor structure taken along the fin structure (i.e., the CC' direction).

[0169] The second semiconductor structure differs from the first semiconductor structure in that the substrate 21 in the second semiconductor structure 10 may include a stacked first substrate layer, a second substrate layer, and a buried oxide layer 46. The buried oxide layer 46 is located between the first substrate layer and the second substrate layer. In one example, the substrate is a silicon-on-insulator (SOI) substrate.

[0170] In the second semiconductor structure, the first substrate layer can be used to form the first part 2111 of the fin structure, and the second part of the second substrate layer forms the second part 2112 of the fin structure, so that electrical isolation can be achieved by utilizing the buried oxide layer 46 between the first part 2111 of the fin structure and the second part 2112 of the fin structure.

[0171] In one example, FIG23 is a schematic structural diagram of a semiconductor structure provided according to an embodiment of the present disclosure. FIG24 is a schematic structural diagram of a semiconductor structure provided according to an embodiment of the present disclosure. (a) in FIG23 to (a) in FIG24 are cross-sectional views of the semiconductor structure taken along the cross-sectional direction of the gate structure (i.e., the AA' direction); (b) in FIG23 to (b) in FIG24 are cross-sectional views of the semiconductor structure taken along the cross-sectional direction of the source and drain structure (i.e., the BB' direction); and (c) in FIG23 to (c) in FIG24 are cross-sectional views of the semiconductor structure taken along the cross-sectional direction of the active structure (i.e., the CC' direction).

[0172] As shown in Figures 23 and 24, the first transistor 11 and the second transistor 12 are arranged back to back. The first active structure 131 of the first transistor 12 and the second active structure 132 of the second transistor 12 form an active structure 13, and the first gate structure 41 of the first transistor 11 and the second gate structure 43 of the second transistor 12 are self-aligned. The active structure in Figure 23 can be a nanosheet structure, and the active structure in Figure 24 can be a block structure.

[0173] It should be noted that the semiconductor structures shown in FIG. 22 to FIG. 24 can all be prepared using the steps in one or more embodiments corresponding to FIG. 1 .

[0174] The following is a brief description of the preparation process of the semiconductor structure shown in Figure 23 in conjunction with the steps in one or more embodiments corresponding to Figure 1. Figures 25 to 30 are schematic diagrams of a preparation process of a semiconductor structure provided according to an embodiment of the present disclosure, wherein Figures 25(a) to 30(a) are cross-sectional views of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., the AA' direction), Figures 25(b) to 30(b) are cross-sectional views of the semiconductor structure along the cross-sectional direction of the source and drain structure (i.e., the BB' direction); and Figures 25(c) to 30(c) are cross-sectional views of the semiconductor structure along the cross-sectional direction of the nanosheet structure (i.e., the CC' direction).

[0175] In one example, another process for preparing the semiconductor structure 10 may include the following steps:

[0176] Step 1: Patterning and etching the nanosheet structure 47 on the silicon substrate 21 using standard semiconductor fabrication process steps; depositing silicon nitride on the substrate 21 with the nanosheet structure 47, and etching back the silicon nitride to form a silicon nitride material layer on the substrate; depositing polysilicon on the gate region of the semiconductor structure 10 as a first dummy gate structure 24; removing the silicon nitride material layer in the area not covered by the first dummy gate structure 24 (source and drain regions) to form a first material layer 25; depositing an oxide material in the source and drain regions to form a first shallow trench isolation layer; etching the first shallow trench isolation layer to form a second shallow trench isolation layer (i.e., shallow trench isolation structure 26). The upper surface of the shallow trench isolation structure 26 is lower than the first portion of the nanosheet structure 47 (which subsequently forms the first active structure 131 in FIG. 23 ), resulting in the structure shown in FIG. 25 .

[0177] Step 2: In the gate region of the structure shown in FIG25 , the first spacer 27 of the first transistor 11 is formed using standard semiconductor fabrication steps. In the source / drain region, the first source / drain structure 28 and the first interlayer dielectric layer 29 of the first transistor 11 are formed using standard semiconductor fabrication steps. Subsequently, the first source / drain metal 30 of the first transistor 11 is formed in the source / drain region, and the back-end interconnection process for the first transistor 11 is completed above the source / drain region and the gate region, forming a first metal interconnect layer 31. The first metal interconnect layer 31 is connected to the first source / drain metal 30, resulting in the structure shown in FIG26 .

[0178] Step 3: Deposit an insulating oxide on the structure shown in Figure 26 to form a first insulating layer 32. A carrier wafer 33 is bonded to the first transistor 11 above the first insulating layer 32. The wafer is then flipped over, thinned, and subjected to a chemical mechanical planarization process, stopping above the first material layer 25 to expose the end of the second portion of the nanosheet structure 47, resulting in the structure shown in Figure 27.

[0179] Step 4: Use a selective etching process to etch the nanosheet structure 47 not covered by the first material layer 25 , etching at least a preset height to obtain the structure shown in FIG. 28 .

[0180] Here, the first material layer 25 in the first region can serve as an etching mask to protect the first dummy gate structure 24 at the bottom of the first material layer 25 from being etched. Thus, a first groove 34 is formed in the gate region in the AA' direction. The groove depth of the first groove 34 is equal to the predetermined height.

[0181] Step 5: Remove the first material layer 25 and deposit polysilicon using an isotropic deposition method to obtain the structure shown in FIG. 29 .

[0182] It should be noted that due to the isotropic deposition method, polysilicon is also deposited on the sidewalls of the first recess 34 in the gate region. Therefore, the deposition thickness in the first recess 34 is higher than that in the source and drain regions. When observing the cross-section of the fin structure, the polysilicon in the gate region is higher than the polysilicon in the source and drain regions. As an example, polysilicon deposition continues until the first recess 34 in the gate region is filled, resulting in the structure shown in Figure 29.

[0183] It should be noted that after the first groove 34 in the gate region is filled, a second dummy gate structure 35 is formed. When observing the cross-section of the fin structure ((c) in FIG. 29 ), the height of the second dummy gate structure 35 in the gate region is higher than the height of the second dummy gate structure 35 in the source and drain regions.

[0184] Step 6: Use anisotropic etching to etch the second dummy gate structure 35 in the structure shown in FIG. 29 until the polysilicon in the source and drain regions is completely removed, leaving only the polysilicon in the gate region, forming a third dummy gate structure 36, and obtaining the structure shown in FIG. 30 .

[0185] It should be noted that, due to the anisotropic etching method, the height difference between the polysilicon in the gate region and the source and drain regions does not change. After the polysilicon in the source and drain regions is completely etched, polysilicon still exists in the gate region. The polysilicon in the gate region can form the third dummy gate structure 36.

[0186] It should be noted that the third dummy gate structure 36 is located in the gate region, thereby achieving self-alignment with the first dummy gate structure 24 .

[0187] Step 7: In the gate region of the structure shown in FIG30 , the second spacer 37 of the second transistor 12 is formed through standard steps of the semiconductor manufacturing process; in the source and drain region of the structure shown in FIG15 , the second source and drain structure 38 and the second interlayer dielectric layer 39 of the second transistor 12 are completed based on the second portion of the nanosheet structure 47 (which subsequently forms the second active structure 132 in FIG23 ) through standard steps of the semiconductor manufacturing process. Subsequently, the first dummy gate structure 24 and the third dummy gate structure 36 are removed, and the first gate structure and the second gate structure are formed in the positions of the first dummy gate structure 24 and the third dummy gate structure 36. Subsequently, the second source and drain metal 44 of the second transistor 12 is completed in the source and drain region, and the back-end interconnection process of the second transistor 12 is completed above the source and drain region and the gate region to form a second metal interconnection layer 45. The second metal interconnection layer 45 is connected to the second source and drain metal 44 to obtain the structure shown in FIG23 .

[0188] At this point, the first transistor and the second transistor are completed, and the first gate structure 41 and the second gate structure 43 are aligned.

[0189] In some possible embodiments, when the active structure is a nanosheet structure, the semiconductor material forming the nanosheet structure and the semiconductor material forming the first pseudo-gate structure may be materials that have high etching selectivity to each other, so that there is no need to form a first material layer during the preparation of the semiconductor structure. It is only necessary to use a selective etching process after flipping the wafer to etch the nanosheet structure without etching the first pseudo-gate structure, so that a first groove is formed at the nanosheet structure, and then a second pseudo-gate structure that is self-aligned with the first pseudo-gate structure is formed.

[0190] In this process, there is no need to form a first material layer as a hard mask, thereby reducing the complexity of the preparation process of the semiconductor structure.

[0191] In one embodiment, the nanosheet structure may be formed of a first semiconductor material (in one example, silicon (Si), silicon carbide (SiC), etc.) or a second semiconductor material (in one example, silicon germanium (SiGe), etc.). The first semiconductor material and the second semiconductor material may be materials having high etch selectivity with each other. The first semiconductor material or the second semiconductor material may also be materials having high etch selectivity with the material forming the first gate structure.

[0192] For example, when the semiconductor material in the nanosheet structure that is in contact with the substrate is silicon germanium, and the material of the first gate structure is polysilicon, there is a high etching selectivity between silicon germanium and polysilicon.

[0193] In some embodiments, Figures 31 to 34 are schematic diagrams of a process for preparing a semiconductor structure according to an embodiment of the present disclosure. Figures 31(a) to 34(a) are cross-sectional views of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., the AA' direction), Figures 31(b) to 34(b) are cross-sectional views of the semiconductor structure along the cross-sectional direction of the source and drain structure (i.e., the BB' direction); and Figures 31(c) to 34(c) are cross-sectional views of the semiconductor structure along the cross-sectional direction of the nanosheet structure (i.e., the CC' direction).

[0194] In one example, another process for preparing the semiconductor structure 10 may include the following steps:

[0195] Step 1: Patterning and etching the silicon substrate 21 using standard semiconductor fabrication process steps to form a nanosheet structure 47; depositing polysilicon on the gate region of the semiconductor structure 10 to serve as the first dummy gate structure 24; depositing an oxide material in the source and drain regions to form a first shallow trench isolation layer; and etching the first shallow trench isolation layer to form a second shallow trench isolation layer (i.e., shallow trench isolation structure 26). The top surface of the shallow trench isolation structure 26 is lower than the first portion of the nanosheet structure 47 (which will subsequently form the first active structure 131 in FIG. 23 ), resulting in the structure shown in FIG. 31 .

[0196] Step 2: In the gate region of the structure shown in FIG31 , the first spacer 27 of the first transistor 11 is formed using standard semiconductor fabrication steps. In the source / drain region, the first source / drain structure 28 and the first interlayer dielectric layer 29 of the first transistor 11 are formed using standard semiconductor fabrication steps. Subsequently, the first source / drain metal 30 of the first transistor 11 is formed in the source / drain region, and the back-end interconnection process for the first transistor 11 is completed above the source / drain region and the gate region, forming a first metal interconnect layer 31. The first metal interconnect layer 31 is connected to the first source / drain metal 30, resulting in the structure shown in FIG32 .

[0197] Step 3: Deposit an insulating oxide on the structure shown in FIG32 to form a first insulating layer 32. A carrier wafer 33 is bonded to the first transistor 11 above the first insulating layer 32. The wafer is then flipped over, thinned, and the substrate 21 removed, exposing the end of the second portion of the nanosheet structure 47, resulting in the structure shown in FIG33.

[0198] Step 4: Use a selective etching process to etch the nanosheet structure 47, etching away at least a preset height to obtain the structure shown in FIG. 34 .

[0199] Here, the nanosheet structure 47 and the first gate structure 24 have a high etching selectivity, so that the first dummy gate structure 24 is not etched. Thus, a first groove 34 is formed in the gate region in the AA' direction. The groove depth of the first groove 34 is equal to the predetermined height.

[0200] Step 5: Deposit polysilicon using an isotropic deposition method to obtain the structure shown in FIG29 .

[0201] It can be understood that the subsequent steps are the same as the steps corresponding to Figures 29 to 30 until the structure shown in Figure 23 is obtained.

[0202] As an example, when the active structure is a nanosheet structure, the first transistor and the second transistor can be prepared without forming the first material layer 25, which effectively reduces the number of preparation steps and the complexity of preparation.

[0203] In one or more of the above-mentioned embodiments of preparing semiconductor structures, not only can the process flow of stacking transistors be greatly simplified, but also the consistency of the active structure and gate structure of the upper and lower transistors can be taken into account. In particular, the gate structure and active structure of the upper and lower transistors are self-aligned and stacked, which, on the one hand, solves the long-standing problems such as complex processes and alignment difficulties existing in the existing mainstream technical solutions for stacking transistors, and realizes the promotion of the industrialization of transistor stacking technology. On the other hand, through the self-aligned "back-to-back" active structure and gate structure, the upper and lower transistors can have independent signal and power supply networks, and are connected through local interconnection, which greatly releases metal wiring resources without changing the extremely miniaturized 4T track unit design.

[0204] Finally, the flip-chip approach to creating top-and-bottom transistors is compatible with existing mainstream device architectures, enabling front-and-back stacking of planar transistors, fin transistors, gate-all-around transistors, and even vertical transistors (VTFETs) without requiring specialized process development for specific device architectures. This flexibility offers significant scalability from the perspective of semiconductor process node iteration. The flip-chip transistor is conceptually advanced, possesses significant industrial value, and offers strong practicality and broad prospects for expansion.

[0205] In some embodiments, the present disclosure provides a semiconductor device. The semiconductor device includes: a semiconductor structure as described in the above embodiments. The structure of the semiconductor structure can be seen in the semiconductor structures shown in Figures 2 and 22 to 24 above.

[0206] In some embodiments, the present disclosure provides an electronic device. The electronic device includes a circuit board and a semiconductor device according to the above embodiment, disposed on the circuit board. The semiconductor device includes the above-described semiconductor structure. The structure of the semiconductor structure can be seen in the semiconductor structures shown in Figures 2 and 22 to 24 above.

[0207] In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0208] The above description is merely an exemplary embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor structure, wherein, Including: Providing a substrate and etching the substrate to form an active structure; wherein, the active structure includes a first end and a second end, and the first end of the active structure is farther from the substrate than the second end of the active structure; Forming a first material layer on a first region of the substrate, and the first region is located in gate regions on both sides of the active structure; Forming a first dummy gate structure across the active structure on the first material layer; Inverting the semiconductor structure and removing the substrate to expose the second end of the active structure and the first material layer; Using the first material layer as an etching mask to etch the semiconductor structure until a preset height is reached; Depositing a semiconductor material on the semiconductor structure to form a second dummy gate structure; the height of the second dummy gate structure in the gate region is higher than the height of the second dummy gate structure in the source-drain region; Etching the second dummy gate structure until the active structure in the source-drain region is exposed to form a third dummy gate structure; Removing the first dummy gate structure and the third dummy gate structure to form a first gate structure and a second gate structure respectively.

2. The preparation method according to claim 1, wherein, The step of using the first material layer as an etching mask to etch the semiconductor structure until a preset height is reached includes: Using the first material layer as an etching mask to selectively etch the second end of the active structure in the gate region, and the second end of the active structure in the source-drain region and the shallow trench structure surrounding the active structure until the height difference between the active structure and the first dummy gate structure reaches the preset height, and forming a first groove in the gate region.

3. The preparation method according to claim 2, wherein, The step of depositing a semiconductor material on the semiconductor structure to form a second dummy gate structure includes: Depositing a semiconductor material in an isotropic deposition manner on the source-drain region and the gate region having the first groove until the first groove is filled; The step of etching the second dummy gate structure until the active structure in the source-drain region is exposed to form a third dummy gate structure includes: Etching the second dummy gate structure by an anisotropic etching method until the active structure in the source-drain region is exposed and forming the third dummy gate structure in the gate region.

4. The preparation method according to claim 1, wherein, The step of removing the first dummy gate structure and the third dummy gate structure to form a first gate structure and a second gate structure respectively includes: Removing the first dummy gate structure and the third dummy gate structure; Depositing a first metal material at the position where the first dummy gate structure is removed to form the first gate structure; the first gate structure wraps a first part of the active structure; the first end is located in the first part; Depositing a second metal material on the first gate structure until covering the position where the third dummy gate structure is removed to form the second gate structure.

5. The preparation method according to claim 1, wherein, The step of forming a first material layer on a first region of the substrate includes: Deposit a hard mask material on the etched substrate until the second groove formed by the active structure is filled, and use an etch-back process to remove the hard mask material on the active structure to form a second material layer; the active structure protrudes from the second material layer; Remove the second material layer located on the source-drain region to form the first material layer on the first region of the substrate.

6. The preparation method according to claim 5, wherein, Before depositing the hard mask material on the etched substrate until the second groove formed by the active structure is filled, the method further includes: Deposit a first oxidation material on the etched substrate to form an oxide layer; The method of flipping the semiconductor structure and removing the substrate to expose the second end of the active structure and the first material layer located in the gate region includes: Use a planarization process to remove the substrate until the second part of the active structure and the oxide layer are exposed; Remove the oxide layer in the gate region to expose the first material layer in the gate region.

7. The preparation method according to claim 5, wherein, After forming a first dummy gate structure spanning the active structure on the first material layer, the method further includes: Deposit a second oxidation material in the source-drain region to form a shallow trench isolation structure, the shallow trench isolation structure covers the second part of the active structure and exposes the first part of the active structure; In the source-drain region, form a first source-drain structure, a first source-drain metal, and a first interlayer dielectric layer based on the first part; After etching the second dummy gate structure until the active structure in the source-drain region is exposed to form a third dummy gate structure, the method further includes: Thin the shallow trench isolation structure in the source-drain region to expose the second part of the active structure; In the source-drain region, form a second source-drain structure, a second source-drain metal, and a second interlayer dielectric layer based on the second part of the active structure.

8. The preparation method according to claim 1, wherein, The substrate includes: a first substrate layer, a second substrate layer, and a buried oxide layer stacked, and the buried oxide layer is located between the first substrate layer and the second substrate layer; Etching the substrate to form an active structure includes: Etch a first part of the first substrate layer, the buried oxide layer, and the second substrate layer, and retain a second part of the second substrate layer to form the active structure; Wherein, the first substrate layer forms a first part of the active structure, and the first part of the second substrate layer forms a second part of the active structure.

9. A semiconductor structure prepared by using the preparation method according to any one of claims 1 to 8, wherein, Includes: A first transistor; A second transistor, the first transistor and the second transistor are arranged back to back; Wherein, the first active structure of the first transistor and the second active structure of the second transistor form the active structure, and the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

10. The semiconductor structure according to claim 9, wherein, An isolation layer is formed between the first active structure and the second active structure, and the isolation layer is used to electrically isolate the first active structure and the second active structure; The isolation layer is generated from the buried oxide layer in the substrate.

11. A semiconductor device, wherein, Includes: The semiconductor structure according to claim 9 or 10.

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