Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a base substrate (10) and a first electrode layer (50). At least one first through-hole (501) is provided on the first electrode layer (50). The first through-hole (501) passes through the first electrode layer (50) in a direction perpendicular to the base substrate (10), and an orthographic projection of the first through-hole (501) on the base substrate (10) is within an isolation dam region (10e) and does not overlap with an orthographic projection of an isolation dam (204) on the base substrate (10). The display apparatus comprises the display substrate.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202410032875.3, filed on January 9, 2024, entitled “Display Substrate and Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display devices, and particularly to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0004] Currently, the first electrode layer covering the driving circuit layer is peeling off, affecting the product yield.

[0005] Summary of the Invention

[0006] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0007] This disclosure provides a display substrate, comprising:

[0008] A substrate, the substrate including a display area, a driving circuit area and an isolation dam area, the driving circuit area being located between the display area and the isolation dam area;

[0009] A driving circuit layer is disposed on the substrate, and the driving circuit layer includes an isolation dam, the orthographic projection of which is located on the substrate within the isolation dam area;

[0010] A first electrode layer is located on the side of the driving circuit layer away from the substrate, and the orthographic projection of the first electrode layer on the substrate is at least within the isolation dam area;

[0011] The first electrode layer is provided with at least one first through hole, the first through hole penetrates the first electrode layer in a direction perpendicular to the substrate, the orthographic projection of the first through hole on the substrate is located within the isolation dam area, and the orthographic projection of the first through hole on the substrate is set to not overlap with the orthographic projection of the isolation dam on the substrate.

[0012] In some exemplary embodiments, a breathable insulating layer is also included, the insulating layer being disposed within the first through-hole.

[0013] In some exemplary embodiments, the end of the insulating layer away from the substrate protrudes from the first through-hole, and the insulating layer covers the edge of the first through-hole away from the substrate.

[0014] In some exemplary embodiments, the material of the insulating layer includes polyimide adhesive.

[0015] In some exemplary embodiments, the isolation dam includes a first isolation dam and a second isolation dam, the first isolation dam being located on the side of the second isolation dam closer to the display area, and at least one of the first through holes having its orthographic projection on the substrate disposed between the orthographic projection of the first isolation dam on the substrate and the drive circuit area.

[0016] In some exemplary embodiments, the driving circuit layer includes a wiring layer, the orthographic projection of which onto the substrate lies within the isolation dam area;

[0017] The first electrode layer covers the surface of the wiring layer away from the substrate, the orthographic projection of the first via on the substrate is located within the orthographic projection of the wiring layer on the substrate, and one end of the first via near the substrate extends into the wiring layer.

[0018] In some exemplary embodiments, the trace layer includes a first trace layer, a second trace layer, and a third trace layer stacked sequentially along a direction away from the substrate, wherein the first electrode layer is located on the side of the third trace layer away from the second trace layer.

[0019] In some exemplary embodiments, the first isolation dam is disposed on the end face of the wiring layer away from the substrate, and the first electrode layer is configured to cover the first isolation dam;

[0020] The first electrode layer is provided with a second through hole, and the orthographic projection of the second through hole on the substrate at least partially overlaps with the orthographic projection of the first isolation dam on the substrate.

[0021] In some exemplary embodiments, the first through hole is provided in multiple forms, and at least one of the first through holes is positioned between the orthographic projection of the first isolation dam on the substrate and the orthographic projection of the second isolation dam on the substrate.

[0022] In some exemplary embodiments, a plurality of first through holes are provided, and the plurality of first through holes are arranged linearly, in an array, or irregularly on a plane parallel to the substrate.

[0023] In some exemplary embodiments, the first through hole is configured to extend along a direction perpendicular to the substrate, and the cross-section of the first through hole in the direction parallel to the substrate is configured as a rectangle, circle, ellipse, triangle, rhombus, or irregular shape.

[0024] In some exemplary embodiments, the total area of ​​the first through hole projected onto the substrate is set to be no less than 10% of the area of ​​the isolation dam area.

[0025] In some exemplary embodiments, the first electrode layer is provided with a third through hole, and the orthographic projection of the first electrode layer on the substrate is at least located within the driving circuit region, and the orthographic projection of the third through hole on the substrate is at least located within the driving circuit region.

[0026] This disclosure provides a display device, which includes the display substrate described above.

[0027] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0028] Overview of the attached figures

[0029] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0030] Figure 1 is a schematic diagram of a display device;

[0031] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0032] Figure 3 is a schematic cross-sectional view of a display substrate;

[0033] Figure 4 is a schematic diagram of a display substrate according to an exemplary embodiment of the present invention;

[0034] Figure 5 is a schematic cross-sectional view of point A in Figure 4;

[0035] Figure 6 is a sectional view along the BB direction in Figure 5;

[0036] Figure 7 is a schematic diagram of another display substrate according to this exemplary embodiment;

[0037] Figure 8 is a schematic diagram of another display substrate of this exemplary embodiment;

[0038] Figure 9 is a magnified view of part C in Figure 8;

[0039] Figure 10 is a schematic diagram of another display substrate according to this exemplary embodiment;

[0040] Figure 11 is a schematic diagram of another display substrate of this exemplary embodiment;

[0041] Figure 12 is a first fabrication schematic diagram of the display substrate of this exemplary embodiment;

[0042] Figure 13 is a second fabrication schematic diagram of the display substrate according to this exemplary embodiment.

[0043] Detailed Explanation

[0044] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0045] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0046] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0047] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0048] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0049] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0050] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0051] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0052] In this specification, "parallel" refers to two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" refers to two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0053] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0054] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0055] In the embodiments of this disclosure, "about" means a value that is not strictly limited and is within the range of process and measurement errors.

[0056] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn in unit rows, where n can be a natural number. The scan driver can receive clock signals, scan start signals, etc., from the timing controller to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The LED driver can receive clock signals, transmit stop signals, etc., from the timing controller to generate transmit signals to LED signal lines E1, E2, E3, ..., Eo. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0057] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting device in each sub-pixel is connected to the pixel driving circuit of its respective sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0058] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.

[0059] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0060] Figure 3 is a schematic cross-sectional view of a display substrate. As shown in Figure 3, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 20 disposed on a substrate 10, a light-emitting structure layer 30 disposed on the side of the driving circuit layer 20 away from the substrate 10, and an encapsulation structure layer 40 disposed on the side of the light-emitting structure layer 30 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0061] In an exemplary embodiment, the substrate 10 can be a flexible substrate or a rigid substrate. The driving circuit layer 20 can include multiple circuit units, each of which can include at least a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 30 can include multiple light-emitting devices, each of which can include at least an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The organic light-emitting layer can be a series OLED structure. The encapsulation structure layer 40 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to form an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 30, but is not limited thereto. For example, the first, second, and third encapsulation layers can all be inorganic materials or all be organic materials.

[0062] Currently, the first electrode layer in the border area exhibits peeling, meaning that part of the first electrode layer covering the driving circuit layer has detached from it. This increases resistance, affects the conductivity of the first electrode layer, and reduces the product yield. Through research and experimentation, the applicant discovered the cause of the first electrode layer peeling: during the patterning process of the first electrode layer, it is typically exposed to a high-temperature environment. This high temperature causes moisture to be released, and the first electrode layer blocks this moisture. Therefore, the first electrode layer is lifted by the moisture, leading to peeling.

[0063] Figure 4 is a schematic diagram of a display substrate according to an exemplary embodiment of the present invention. Figure 5 is a cross-sectional view at point A in Figure 4, and Figure 6 is a cross-sectional view along line BB in Figure 5. In some exemplary embodiments, a display substrate, as shown in Figures 4 to 6, includes a substrate 10, a driving circuit layer 20, and a first electrode layer 50. The substrate 10 includes a display area 10a, a driving circuit area 10d, and an isolation dam area 10e, with the driving circuit area 10d located between the display area 10a and the isolation dam area 10e. The driving circuit layer 20 is disposed on the substrate 10 and includes an isolation dam. The orthographic projection of the isolation dam 204 onto the substrate 10 is located within the isolation dam area 10e. The first electrode layer 50 is located on the side of the driving circuit layer 20 away from the substrate 10, and the orthographic projection of the first electrode layer 50 onto the substrate 10 is at least located within the isolation dam area 10e. The first electrode layer 50 is provided with at least one first through hole 501. The first through hole 501 penetrates the first electrode layer 50 in a direction perpendicular to the substrate 10 (i.e., the first direction). The orthographic projection of the first through hole 501 on the substrate 10 is located within the isolation dam region 10e and is configured not to overlap with the orthographic projection of the isolation dam 204 on the substrate 10. Thus, in this example, the display substrate, by adding the first through hole 501 to the first electrode layer 50, allows moisture to be released from the first through hole 501 in a timely manner, thereby preventing the first electrode layer 50 from detaching.

[0064] In some exemplary embodiments, as shown in Figures 4 to 6, the substrate 10 may include a display area 10a and a non-display area. The non-display area may include a bonding area 10c located on one side of the display area 10a and a border area 10b located on the other side of the display area 10a. In an exemplary embodiment, the display area 10a may include a plurality of sub-pixels arranged in a matrix. The sub-pixels may include pixel driving circuits and light-emitting devices. The bonding area 10c may include at least an isolation dam and a bonding circuit that connects the signal lines of the plurality of sub-pixels to an external driving device. The border area 10b may include at least an isolation dam, a gate driver on array (GOA) circuit, and power lines that transmit voltage signals to the plurality of sub-pixels. The bonding area 10c and the isolation dam of the border area 10b form a ring structure surrounding the display area 10a. In a plane parallel to the substrate 10, the border area 10b includes a driving circuit area 10d and an isolation dam area 10e arranged sequentially along a direction away from the display area 10a, such that the driving circuit area 10d is located between the isolation dam area 10e and the display area 10a.

[0065] In some exemplary embodiments, as shown in FIG6, the driving circuit layer 20 may be disposed on one side of the substrate 10 in a first direction. The driving circuit layer 20 may include a first planarization layer 201, a second planarization layer 202, and a third planarization layer 203 sequentially stacked in a direction away from the substrate 10. The driving circuit layer 20 has a fourth via 211 within the isolation dam region 10e. The driving circuit layer 20 may include a wiring layer 207, which may be disposed within the fourth via 211, such that the orthographic projection of the wiring layer 207 on the substrate 10 lies within the isolation dam region 10e. The wiring layer 207 may include a first wiring layer 208, a second wiring layer 209, and a third wiring layer 210 sequentially stacked in a direction away from the substrate 10. The first wiring layer 208, the second wiring layer 209, and the third wiring layer 210 are all made of conductive materials. The driving circuit layer 20 includes at least a gate driving circuit in the driving circuit region 10d, which can be connected to the first scan line and the second scan line of the pixel driving circuit in the display region 10a. The driving circuit layer 20 includes at least a power line in the isolation dam region 10e, which can be connected to the second power line VSS of the pixel driving circuit in the display region 10a.

[0066] In some exemplary embodiments, as shown in FIG6, the isolation dam 204 may include a first isolation dam 205 and a second isolation dam 206. Both the first isolation dam 205 and the second isolation dam 206 may extend along a direction parallel to the edge of the display area 10a. The first isolation dam 205 and the second isolation dam 206 are configured to block moisture from entering the display area 10a from the frame area 10b. In a second direction, the distance between the first isolation dam 205 and the edge of the display area 10a is less than the distance between the second isolation dam 206 and the edge of the display area 10a; that is, the first isolation dam 205 is located on the side of the second isolation dam 206 closer to the display area 10a. The first isolation dam 205 may be arranged on the end face of the wiring layer 207 away from the substrate 10, i.e., on the surface of the third wiring layer 210 away from the second wiring layer 209, and the second isolation dam 206 protrudes from the surface of the third wiring layer 210 away from the second wiring layer 209.

[0067] In some exemplary embodiments, as shown in FIG6, the first electrode layer 50 may cover the surface of the wiring layer 207 away from the substrate 10, that is, the first electrode layer 50 is located on the side of the third wiring layer 207 away from the second wiring layer 207. The first electrode layer 50 also covers the portion of the driving circuit layer 20 away from the substrate 10 and located in the driving circuit region 10d and the display region 10a. The first electrode layer 50 may be made of a conductive material, and the first electrode layer 50 may be arranged in the same layer as the anode of the light-emitting device. The first electrode layer 50 also covers the surfaces of the first isolation dam 205 except for the surface facing the wiring layer 207, so that the first isolation dam 205 is enclosed. Thus, the orthographic projection of the first electrode layer 50 on the substrate 10 may overlap with the isolation dam region 10e, and the orthographic projection of the first electrode layer 50 on the substrate 10 may overlap with the driving circuit region 10d. The low voltage (VSS) required by the pixel driving circuit in the display area 10a is introduced from the bonding pads of the bonding area 10c and delivered to the second power line VSS of each pixel driving circuit through the power line. Since the power line needs to be delivered through the first electrode layer 50, the impedance of the first electrode layer 50 is high, and there is a voltage drop in the voltage signal transmission. The voltage loss of the power line reduces the uniformity of the display brightness in the display area 10a and affects the high-quality display.

[0068] In some exemplary embodiments, as shown in FIG6, at least one first through-hole 501 is provided on the first electrode layer 50. The first through-hole 501 extends along a first direction and penetrates the first electrode layer 50. The orthographic projection of the at least one first through-hole 501 on the substrate 10 lies within the orthographic projection of the wiring layer 207 on the substrate 10. One end of the first through-hole 501 near the substrate 10 extends to the third wiring layer 210. The orthographic projection of the at least one first through-hole 501 on the substrate 10 may lie between the orthographic projection of the first isolation dam 205 on the substrate 10 and the drive circuit region 10d.

[0069] In some exemplary embodiments, as shown in Figures 5 and 6, multiple first through holes 501 are provided. The orthographic projections of the multiple first through holes 501 on the substrate 10 are all located between the orthographic projection of the first isolation dam 205 on the substrate 10 and the driving circuit area 10d. The hole shape and size of the multiple first through holes 501 are consistent. The cross-section of the multiple first through holes 501 in the direction parallel to the substrate 10 is set as rectangular, so that the first through hole 501 is a rectangular hole. However, it is not limited to this. For example, the first through hole 501 can be a round hole, a trapezoidal hole, a triangular hole, a rhomboid hole, a polygonal hole, an irregular hole, etc. The plurality of first through holes 501 are rectangular holes and are linearly arranged on a plane parallel to the substrate 10. The plurality of first through holes 501 are arranged at equal intervals along a second direction, which is parallel to the substrate 10 and perpendicular to the first direction. However, this is not limited to the above. For example, the plurality of first through holes 501 are not arranged at equal intervals along the second direction. Another example is that the plurality of first through holes 501 are staggered in a third direction. Yet another example is that the plurality of first through holes 501 are arranged in an array or irregularly, with the third direction parallel to the substrate 10 and perpendicular to the second direction.

[0070] Figure 7 is a schematic diagram of another display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 5 and 7, multiple first through holes 501 are provided. The multiple first through holes 501 have the same hole shape and size. The cross-section of the multiple first through holes 501 in the direction parallel to the substrate 10 is set to be circular, so that the first through holes 501 are circular holes. However, it is not limited to this. For example, the first through holes 501 can be trapezoidal holes, triangular holes, rhomboid holes, polygonal holes, irregular holes, etc. For another example, the hole shapes of the multiple first through holes 501 are not consistent. Some of the first through holes 501 can be circular holes, and some of the first through holes 501 can be rectangular holes. The multiple first through holes 501 are circular and are linearly arranged on a plane parallel to the substrate 10 (the plane formed by the second direction and the third direction). However, it is not limited to this. For example, the multiple first through holes 501 are irregularly arranged on a plane parallel to the substrate 10 (the plane formed by the second direction and the third direction).

[0071] In some exemplary embodiments, as shown in FIG5 and FIG6, a plurality of first through holes 501 are provided, and the orthographic projections of the plurality of first through holes 501 on the substrate 10 are all located between the orthographic projection of the first isolation dam 205 on the substrate 10 and the driving circuit area 10d. The total area of ​​the orthographic projections of the plurality of first through holes 501 on the substrate 10 is set to be not less than 10% of the total area of ​​the isolation dam area 10e.

[0072] Figure 8 is a schematic diagram of another display substrate according to this exemplary embodiment, and Figure 9 is a partially enlarged schematic diagram of point C in Figure 8. In some exemplary embodiments, as shown in Figures 8 and 9, the display substrate may include a breathable insulating layer 60, which may be located within the first through-hole 501, such that the insulating layer 60 fills the first through-hole 501. Furthermore, the insulating layer 60 may be made of polyimide (PI) adhesive. PI adhesive has good breathability, allowing water vapor to pass through, thus allowing water vapor to pass through the insulating layer 60 and be discharged through the first through-hole. PI adhesive is a high-performance polymer material with excellent comprehensive properties. It is one of the best heat-resistant engineering plastics currently available, possessing extremely high high-temperature resistance, reaching above 400°C, and its long-term operating temperature range is between -200°C and 300°C. PI adhesive also exhibits good electrical insulation properties and flame retardant rating, and is therefore widely used in various fields. Insulating layer 60 The insulating layer 60 fills each of the first through-holes 501. One end of the insulating layer 60 near the substrate 10 is attached to the third wiring layer 210, while the other end of the insulating layer 60 protrudes from the first through-hole 501. The edge of the first through-hole 501 away from the substrate 10 is designated as a first edge 502, and the insulating layer 60 covers the first edge 502, preventing the first electrode layer 50 from easily lifting off the edge of the first through-hole 501. The insulating layer 60 is made of the same material as the pixel definition layer in the light-emitting structure layer 30 and is disposed in the same layer as the pixel definition layer. The insulating layer 60 can be fabricated using the patterning process of the pixel definition layer.

[0073] Figure 10 is a schematic diagram of another display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in Figure 10, multiple first through holes 501 are provided. The orthographic projection of all the first through holes 501 on the substrate 10 can be located within the orthographic projection of the wiring layer 207 on the substrate 10. However, the multiple first through holes 501 are respectively located on both sides of the first isolation dam 205 in the second direction. Among them, the orthographic projection of a portion of the first through holes 501 on the substrate 10 can be located between the orthographic projection of the first isolation dam 205 on the substrate 10 and the driving circuit area 10d. The other portion of the first through holes 501 is located between the first isolation dam 205 and the second isolation dam 206, such that at least one orthographic projection of the first through hole 501 on the substrate 10 is located between the orthographic projection of the first isolation dam 205 on the substrate 10 and the orthographic projection of the second isolation dam 206 on the substrate 10. The hole type, opening size, and arrangement of the first through holes 501 on both sides of the second direction of the first isolation dam 205 can be the same, or at least one of the hole type, opening size, and arrangement of the first through holes 501 on both sides of the second direction of the first isolation dam 205 can be different. For example, the first through hole 501 on one side of the first isolation dam 205 is a rectangular hole, and the first through hole 501 on the other side is a round hole, but the opening size and arrangement of the first through holes 501 on both sides are the same.

[0074] Figure 11 is a schematic diagram of another display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in Figure 11, in addition to the first through-hole 501, the first electrode layer 50 may also have a second through-hole 503 and a third through-hole 504, both of which penetrate the first electrode layer 50. The first electrode layer 50 has at least one first through-hole 501. The orthographic projection of the at least one first through-hole 501 on the substrate 10 lies within the orthographic projection of the wiring layer 207 on the substrate 10. One end of the first through-hole 501 near the substrate 10 extends into the wiring layer 207. The orthographic projection of the at least one first through-hole 501 on the substrate 10 may lie between the orthographic projection of the first isolation dam 205 on the substrate 10 and the driving circuit region 10d. Furthermore, an insulating layer 60 is provided within the first through-hole 501. The second through-hole 503 is arranged corresponding to the first isolation dam 205. The second through-hole 503 extends to the surface of the first isolation dam 205, allowing water vapor to be discharged from the second through-hole 503. The orthographic projection of the second through-hole 503 on the base 10 lies within the orthographic projection of the first isolation dam 205 on the base 10. In addition, there are multiple second through-holes 503, and the multiple second through-holes 503 have the same hole shape and size. The multiple second through-holes 503 are circular holes, but not limited to this. For example, the second through-holes 503 can be rectangular holes, trapezoidal holes, triangular holes, rhomboid holes, polygonal holes, irregular holes, etc. The multiple second through-holes 503 can be arranged linearly. The third through-hole 504 is located in the portion of the first electrode layer 50 that covers the driving circuit region 10d. The third through-hole 504 extends in a direction perpendicular to the substrate 10 and extends to the end face of the driving circuit layer 20 away from the substrate 10, that is, to the end face of the third planarization layer 203 away from the substrate 10, so that water vapor can be discharged from the third through-hole 504. The orthographic projection of the third through-hole 504 on the substrate 10 is within the driving circuit region 10d. In addition, there are multiple third through-holes 504. The multiple third through-holes 504 have the same hole shape and size. The multiple third through-holes 504 are circular holes, but not limited to this. For example, the third through-hole 504 can be a rectangular hole, trapezoidal hole, triangular hole, rhomboid hole, polygonal hole, irregular hole, etc. The multiple third through-holes 504 can be arranged in an array.

[0075] Figure 12 is a first fabrication schematic diagram of the display substrate according to this exemplary embodiment, and Figure 13 is a second fabrication schematic diagram of the display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 11, 12, and 13, a fabrication method is applied to the display substrate shown in Figure 10. The fabrication method may include fabricating a driving circuit layer 20 on a substrate 10, fabricating a first electrode layer 50 on the driving circuit layer 20, and fabricating an insulating layer 60. During the fabrication of the driving circuit layer 20 on the substrate 10, a first planarization layer 201, a second planarization layer 202, a third planarization layer 203, a wiring layer 207, etc., need to be fabricated on the substrate 10 through processes such as coating, deposition, and etching to form the driving circuit layer 20. The driving circuit layer 20 covers the substrate 10, and a first isolation dam 205 and a second isolation dam 206 are also formed in this process. In the process of fabricating the first electrode layer 50 on the driving circuit layer 20, an electrode thin film 505 needs to be deposited on the driving circuit layer 20 first, as shown in Figure 12; then, photoresist is coated on the electrode thin film 505, and after pre-baking, it is exposed to ultraviolet light using a mask. After development, the photoresist pattern is retained only at the location of the first electrode layer 50. After post-baking, etching, and photoresist stripping, the electrode layer pattern 506 is obtained, as shown in Figure 13. The electrode layer pattern 506 includes the first electrode layer 50 with a first via 501, a second via 503, and a third via 504. The process of obtaining the electrode layer pattern 506 is the patterning process of the first electrode layer 50. The mask used in the patterning process of the first electrode layer 50 needs to match the first electrode layer 50 with the first via 501, the second via 503, and the third via 504. In the patterning process of the first electrode layer 50, the pre-baking, post-baking, and etching processes all require a high-temperature environment. Under this environment, moisture can be promptly removed through the first through-hole 501, the second through-hole 503, and the third through-hole 504, preventing peeling. During the fabrication of the insulating layer 60, the insulating layer 60 can be fabricated using the patterning process of the pixel definition layer in the light-emitting structure layer 30. First, an insulating film is deposited on the electrode layer pattern 506. Then, photoresist is coated onto the insulating film, exposed, developed, etched, and the photoresist removed to obtain the pixel definition layer pattern, which includes the insulating layer 60. The photomask used in this process needs to match the insulating layer 60. Subsequently, the fabrication of the light-emitting structure layer 30 and the encapsulation structure layer 40 is completed, thus completing the fabrication of the display substrate. The organic light-emitting layer in the light-emitting structure layer 30 can be a tandem OLED structure.

[0076] In some exemplary embodiments, a display device is provided, comprising the aforementioned display substrate, and may be an OLED display device. The display device provided in this disclosure can be applied to electronic devices, which may include mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, in-vehicle displays, and any product or component with display functionality, such as wearable devices, smartwatches, smart bracelets, smart glasses, smart headphones, smart clothing, head-mounted displays, etc. In this example, the display device is a mobile phone.

[0077] In conjunction with the above embodiments, the display substrate of this example, by adding a first through-hole 501 to the first electrode layer 50, allows moisture to be released in a timely manner through the first through-hole 501 during the manufacturing process of the display substrate, thereby preventing the first electrode layer 50 from detaching. An insulating layer 60 covers the location of the first through-hole 501, thus sealing the first through-hole 501 and preventing the upper structure from directly contacting the wiring layer. The insulating layer 60 is breathable and does not affect the release of moisture. Furthermore, the insulating layer 60 can wrap around the edge of the first through-hole 501, preventing the edge of the first through-hole 501 from warping.

[0078] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A display substrate, wherein, include: A substrate, the substrate including a display area, a driving circuit area and an isolation dam area, the driving circuit area being located between the display area and the isolation dam area; A driving circuit layer is disposed on the substrate, and the driving circuit layer includes an isolation dam, the orthographic projection of which is located on the substrate within the isolation dam area; A first electrode layer is located on the side of the driving circuit layer away from the substrate, and the orthographic projection of the first electrode layer on the substrate is at least within the isolation dam area; The first electrode layer is provided with at least one first through hole, the first through hole penetrates the first electrode layer in a direction perpendicular to the substrate, the orthographic projection of the first through hole on the substrate is located within the isolation dam area, and the orthographic projection of the first through hole on the substrate is set to not overlap with the orthographic projection of the isolation dam on the substrate.

2. The display substrate according to claim 1, wherein, It also includes a breathable insulating layer disposed within the first through hole.

3. The display substrate according to claim 2, wherein, The insulating layer protrudes from the first through hole at one end away from the substrate, and the insulating layer covers the edge of the first through hole away from the substrate.

4. The display substrate according to claim 2, wherein, The insulating layer is made of polyimide adhesive.

5. The display substrate according to claim 1, wherein, The isolation dam includes a first isolation dam and a second isolation dam. The first isolation dam is located on the side of the second isolation dam closer to the display area. At least one of the first through holes is positioned between the orthographic projection of the first isolation dam on the substrate and the drive circuit area.

6. The display substrate according to claim 5, wherein, The driving circuit layer includes a wiring layer, and the orthographic projection of the wiring layer on the substrate is located within the isolation dam area; The first electrode layer covers the surface of the wiring layer away from the substrate, the orthographic projection of the first via on the substrate is located within the orthographic projection of the wiring layer on the substrate, and one end of the first via near the substrate extends to the wiring layer.

7. The display substrate according to claim 6, wherein, The trace layer includes a first trace layer, a second trace layer, and a third trace layer stacked sequentially along a direction away from the substrate, wherein the first electrode layer is located on the side of the third trace layer away from the second trace layer.

8. The display substrate according to claim 6, wherein, The first isolation dam is disposed on the end face of the wiring layer away from the substrate, and the first electrode layer is configured to cover the first isolation dam; The first electrode layer is provided with a second through hole, and the orthographic projection of the second through hole on the substrate at least partially overlaps with the orthographic projection of the first isolation dam on the substrate.

9. The display substrate according to claim 5, wherein, The first through hole is provided in multiple ways, and at least one of the first through holes is positioned between the orthographic projection of the first isolation dam on the base and the orthographic projection of the second isolation dam on the base.

10. The display substrate according to claim 5, wherein, The first through hole is provided in multiple ways, and the multiple first through holes are arranged linearly, in an array, or irregularly on a plane parallel to the substrate.

11. The display substrate according to claim 5, wherein, The first through hole is configured to extend along a direction perpendicular to the substrate, and the cross-section of the first through hole parallel to the substrate is configured as a rectangle, circle, ellipse, triangle, rhombus or irregular shape.

12. The display substrate according to claim 5, wherein, The total area of ​​the first through hole projected onto the substrate is set to be no less than 10% of the area of ​​the isolation dam area.

13. The display substrate according to any one of claims 1 to 12, wherein, The first electrode layer is provided with a third through hole, and the orthographic projection of the first electrode layer on the substrate is at least located within the driving circuit region, and the orthographic projection of the third through hole on the substrate is at least located within the driving circuit region.

14. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 13.

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