Semiconductor memory

Abstract

The present disclosure provides a semiconductor memory, comprising a first amplification module, a first control transistor, a second control transistor and a second amplification module. At least part of a circuit structure of the first amplification module is the same as at least part of a circuit structure of the second amplification module. The first amplification module is connected to a bit line and a complementary bit line, and is used for amplifying a voltage difference between the bit line and the complementary bit line. The second amplification module is connected to a local data line and a complementary local data line, and is used for amplifying a voltage difference between the local data line and the complementary local data line. The local data line is connected to the bit line by means of the first control transistor, and the complementary local data line is connected to the complementary bit line by means of the second control transistor. A control end of the first control transistor and a control end of the second control transistor receive a column select signal. The layout structure of the first amplification module is made similar to the layout structure of the second amplification module, and a unified preparation process can be used to carry out device preparation, thereby reducing the process difficulty.

Description

semiconductor memory

[0001] Cross-references

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on January 10, 2024, with application number 202410034319.X and application name “Semiconductor Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to, but is not limited to, a semiconductor memory. Background Art

[0004] With the popularization of electronic devices such as mobile phones, tablets, and personal computers, semiconductor memory technology has also developed rapidly.

[0005] Dynamic Random Access Memory (DRAM) has an amplifier circuit that amplifies voltage differences to read or write data from memory cells. Improvements to the amplifier circuit can improve memory performance.

[0006] Summary of the Invention

[0007] The present application provides a semiconductor memory, comprising: a first amplifying module, a first control transistor, a second control transistor, and a second amplifying module; at least a portion of the circuit structure of the first amplifying module is identical to at least a portion of the circuit structure of the second amplifying module;

[0008] The first amplification module is connected to the bit line and the complementary bit line, and is used to amplify the voltage difference between the bit line and the complementary bit line;

[0009] The second amplification module is connected to the local data line and the complementary local data line, and is used to amplify the voltage difference between the local data line and the complementary local data line;

[0010] The local data line is connected to the bit line through the first control transistor, and the complementary local data line is connected to the complementary bit line through the second control transistor. The control end of the first control transistor and the control end of the second control transistor receive a column selection signal.

[0011] The semiconductor memory provided in the present application includes a first amplification module, a second amplification module, a first control transistor, and a second control transistor. The first amplification module is used to amplify the voltage difference between a bit line and a complementary bit line, and the second amplification module is used to amplify the voltage difference between a local data line and a complementary local data line. The bit line and the local data line are connected via the first control transistor, and the complementary bit line and the complementary local data line are connected via the second control transistor. In this way, data on the bit line and the complementary bit line are transmitted to data on the local data line and the complementary local data line. By arranging at least part of the circuit structure of the first amplification module to be identical to at least part of the circuit structure of the second amplification module, the layout structure of the first amplification module and the layout structure of the second amplification module are similar, and a unified manufacturing process can be used for device manufacturing, reducing the process difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0013] FIG1 is a circuit diagram of a semiconductor memory;

[0014] FIG2 is a possible timing control diagram of the semiconductor memory shown in FIG1 ;

[0015] FIG3 is a circuit diagram of a second amplification module;

[0016] FIG4 is a circuit diagram of another second amplification module;

[0017] FIG5 is a layout of a semiconductor memory;

[0018] FIG6 is a layout diagram of another semiconductor memory;

[0019] FIG7 is a circuit diagram of a semiconductor memory provided by some embodiments of the present application;

[0020] FIG8 is a circuit diagram of a semiconductor memory provided by other embodiments of the present application;

[0021] FIG9 is a circuit diagram of a semiconductor memory provided by yet other embodiments of the present application;

[0022] FIG10 is a circuit diagram of a semiconductor memory provided in some further embodiments of the present application;

[0023] FIG11 is a circuit diagram of a second amplification module provided in some embodiments of the present application;

[0024] FIG12 is a possible write timing control diagram of a semiconductor memory provided by some embodiments of the present application;

[0025] FIG13 is a possible readout timing control diagram of a semiconductor memory provided by some embodiments of the present application;

[0026] FIG14 is a layout diagram of a semiconductor memory provided in some embodiments of the present application;

[0027] FIG15 is a layout diagram of a semiconductor memory provided in some other embodiments of the present application;

[0028] FIG16 is a layout diagram of a semiconductor memory provided in some other embodiments of the present application.

[0029] Reference numerals:

[0030] 10. Half storage area; 20. Second control area; 30. First partial area; 301. Second amplification area; 302. Third control area; 303. Fourth control area; 304. Second storage area; 50. First control area; 60. Second partial area; 601. First amplification area; 602. Middle area; 603. Fifth control area; 604. First storage area; 605. Drive area; 606. First area; 70. First amplification module; 80. Second amplification module.

[0031] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0032] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present application.

[0033] It should be noted that the high level and low level referred to in the embodiments are relative concepts (i.e., the voltage value of the high level is higher than the voltage value of the corresponding low level), and do not limit the specific voltage value of the high level or the specific voltage value of the low level. Furthermore, the high levels applied to different signal lines in this specific embodiment are not limited to being equal. For example, the high level on the bit line BL and the high level on the word line can be different voltages, and the high levels of a specific signal line at different stages are not limited to being equal. Those skilled in the art will understand that the values ​​of the corresponding high level and low level can be set according to the process node, speed requirements, reliability requirements, etc.

[0034] A semiconductor memory includes a first amplifying module 70 and a second amplifying module 80. The first amplifying module 70 is used to amplify the voltage difference between a bit line BL and a complementary bit line BLB. The second amplifying module 80 is used to amplify the voltage difference between a local data line IO and a complementary local data line ION.

[0035] FIG1 is a circuit schematic diagram of a semiconductor memory. As shown in FIG1 , the first amplifying module 70 includes an eleventh transistor M11 , a twelfth transistor M12 , a seventeenth transistor M17 , and an eighteenth transistor M18 .

[0036] The first end of the eleventh transistor M11 and the first end of the twelfth transistor M12 receive the fourth power signal PCS_M, and the second end of the seventeenth transistor M17 and the second end of the eighteenth transistor M18 receive the fifth power signal NCS_M;

[0037] The second end of the eleventh transistor M11 is connected to the first end of the seventeenth transistor M17, the control end of the eleventh transistor M11 is connected to the second end of the twelfth transistor M12, the second end of the twelfth transistor M12 is connected to the first end of the eighteenth transistor M18, and the control end of the twelfth transistor M12 is connected to the second end of the eleventh transistor M11.

[0038] The first amplifying module 70 includes a thirteenth transistor M13 and a fourteenth transistor M14. The control end of the seventeenth transistor M17 is connected to the first end of the eighteenth transistor M18 via the thirteenth transistor M13. The control end of the eighteenth transistor M18 is connected to the first end of the seventeenth transistor M17 via the fourteenth transistor M14. The thirteenth transistor M13 and the fourteenth transistor M14 are turned on or off according to the isolation control signal ISO.

[0039] The first amplifying module 70 further includes a fifteenth transistor M15 and a sixteenth transistor M16. A first end of the fifteenth transistor M15 is connected to the control end of the seventeenth transistor M17, and a second end of the fifteenth transistor M15 is connected to the first end of the seventeenth transistor M17. A first end of the sixteenth transistor M16 is connected to the first end of the eighteenth transistor M18, and a second end of the sixteenth transistor M16 is connected to the control end of the eighteenth transistor M18. The control ends of the fifteenth transistor M15 and the sixteenth transistor M16 both receive an offset control signal OC, which is used to control whether the fifteenth transistor M15 and the sixteenth transistor M16 are turned on or off.

[0040] The semiconductor memory also includes a nineteenth transistor M19, a first end of the nineteenth transistor M19 is connected to the first end of the eighteenth transistor M18, a second end of the nineteenth transistor M19 receives a sixth power supply signal, the sixth power supply signal provides an equalizing voltage, and a control end of the nineteenth transistor M19 receives a second equalizing control signal PreEQ, the second equalizing control signal PreEQ is used to control the nineteenth transistor M19 to be turned on or off.

[0041] The eleventh transistor M11 and the twelfth transistor M12 are P-type transistors, and the thirteenth transistor M13 to the nineteenth transistor M19 are N-type transistors.

[0042] FIG2 is a possible timing control diagram for the first amplifying module 70 shown in FIG1 . The first amplifying module 70 may also use other timing control methods, which are not limited herein. As shown in FIG2 , in the precharge phase S1, the second equalization control signal PreEQ is high, the nineteenth transistor M19 is turned on, the isolation control signal ISO is high, the thirteenth transistor M13 and the fourteenth transistor M14 are turned on, the offset control signal OC is high, the fifteenth transistor M15 and the sixteenth transistor M16 are turned on, the fourth power supply signal PCS_M and the fifth power supply signal NCS_M are both at the equalization voltage, the word line signal WL is low, the word line is turned off, and the bit line BL and the complementary bit line BLB are precharged to the first precharge voltage.

[0043] In the offset cancellation phase S2, the second equalization control signal PreEQ is at a low level, the nineteenth transistor M19 is turned off, the isolation control signal ISO is at a low level, the thirteenth transistor M13 and the fourteenth transistor M14 are turned off, the offset control signal OC is at a high level, the fifteenth transistor M15 and the sixteenth transistor M16 are turned on, the fourth power supply signal PCS_M is the power supply voltage, the fifth power supply signal NCS_M is the ground voltage, the word line signal WL is at a low level, the word line is turned off, and a compensation voltage is formed on the bit line BL and the complementary bit line BLB.

[0044] In the charge sharing stage S3, the second equalization control signal PreEQ is at a low level, the nineteenth transistor M19 is turned off, the isolation control signal ISO is at a low level, the thirteenth transistor M13 and the fourteenth transistor M14 are turned off, the offset control signal OC is at a low level, the fifteenth transistor M15 and the sixteenth transistor M16 are turned off, the fourth power supply signal PCS_M and the fifth power supply signal NCS_M are both equalization voltages, the word line signal WL is at a high level, the word line is turned on, and a shared voltage is formed on the bit line BL and the complementary bit line BLB.

[0045] In the sensing and amplification stage S4, the second equalization control signal PreEQ is at a low level, the nineteenth transistor M19 is turned off, the isolation control signal ISO is at a high level, the thirteenth transistor M13 and the fourteenth transistor M14 are turned on, the offset control signal OC is at a low level, the fifteenth transistor M15 and the sixteenth transistor M16 are turned off, the fourth power supply signal PCS_M is the power supply voltage, the fifth power supply signal NCS_M is the ground voltage, the word line signal WL is at a high level, the word line is turned on, and the voltage difference between the bit line BL and the complementary bit line BLB is amplified.

[0046] It should be noted that the isolation control signal ISO, the offset control signal OC and the second equalization control signal PreEQ are not limited to the above control timings, and may also be other manners, which are not limited here.

[0047] Local data line IO is connected to bit line BL via first control transistor T1, and complementary local data line ION is connected to complementary bit line BLB via second control transistor T2. The control terminals of first control transistor T1 and second control transistor T2 receive column select signal CSL. Column select signal CSL controls the transmission of data between local data line IO and complementary local data line ION and data on bit line BL and complementary bit line BLB.

[0048] FIG3 is a circuit diagram of a second amplifying module 80. As shown in FIG3 , the second amplifying module 80 includes a 47th transistor M47, a 48th transistor M48, and a 49th transistor M49. A first end of the 47th transistor M47 is connected to the local data line 10, a second end of the 47th transistor M47 is connected to the complementary local data line ION, a first end of the 48th transistor M48 is connected to the local data line 10, a second end of the 48th transistor M48 receives a seventh power signal, a first end of the 49th transistor M49 is connected to the complementary local data line ION, a second end of the 49th transistor M49 receives the seventh power signal, and control ends of the 47th transistor M47, the 48th transistor M48, and the 49th transistor M49 receive a second complementary equalization control signal EqION. The second complementary equalization control signal EqION is used to control the 47th transistor M47, the 48th transistor M48, and the 49th transistor M49 to be turned on or off.

[0049] The voltage of the seventh power supply signal is a second precharge voltage. When the 47th transistor M47, the 48th transistor M48, and the 49th transistor M49 are turned on, the voltage on the local data line IO and the complementary local data line ION is charged to the second precharge voltage. The first precharge voltage and the second precharge voltage can be the same or different.

[0050] The second amplifying module 80 includes a 41st transistor M41, a 42nd transistor M42, a 43rd transistor M43, a 44th transistor M44, and a 45th transistor M45. A first end of the 44th transistor M44 is connected to the global data line YIO, a second end of the 44th transistor M44 is connected to the first end of the 42nd transistor M42, a second end of the 42nd transistor M42 is connected to the first end of the 41st transistor M41, a control end of the 42nd transistor M42 is connected to the local data line IO, and a second end of the 41st transistor M41 is grounded.

[0051] A first end of the forty-fifth transistor M45 is connected to the complementary global data line YION, a second end of the forty-fifth transistor M45 is connected to the first end of the forty-third transistor M43, a second end of the forty-third transistor M43 is connected to the first end of the forty-first transistor M41, and a control end of the forty-third transistor M43 is connected to the complementary local data line ION.

[0052] The control terminals of the 44th transistor M44, the 45th transistor M45, and the 41st transistor M41 all receive a read enable signal RdEn. When the read enable signal RdEn turns on the 44th transistor M44, the 45th transistor M45, and the 41st transistor M41, data on the local data line IO and the complementary local data line ION are amplified and then output to the global data line YIO and the complementary global data line YION.

[0053] The second amplification module 80 further includes a 46th transistor M46 and a 50th transistor M50. A first end of the 46th transistor M46 is connected to the global data line YIO, and a second end of the 46th transistor M46 is connected to the local data line 10. A first end of the 50th transistor M50 is connected to the complementary global data line YION, and a second end of the 50th transistor M50 is connected to the complementary local data line ION. A control end of the 46th transistor M46 and a control end of the 50th transistor M50 receive a write enable signal WrEn. When the write enable signal WrEn turns on the 46th transistor M46 and the 50th transistor M50, data on the global data line YIO and the complementary global data line YION are transmitted to the local data line 10 and the complementary local data line ION.

[0054] FIG4 is a circuit diagram of another second amplifying module 80. As shown in FIG4 , the second amplifying module 80 includes a 51st transistor M51, a 52nd transistor M52, a 53rd transistor M53, a 54th transistor M54, a 55th transistor M55, and a 56th transistor M56. A first end of the 51st transistor M51 and a first end of the 52nd transistor M52 are both connected to the second end of the 56th transistor M56. The first end of the 56th transistor M56 receives the eighth power signal. A control end of the 51st transistor M51 is connected to the second end of the 52nd transistor M52, and a control end of the 52nd transistor M52 is connected to the second end of the 51st transistor M51. A second end of the 51st transistor M51 is connected to the local data line 10, and a second end of the 52nd transistor M52 is connected to the complementary local data line ION. A first end of the 54th transistor M54 is connected to the complementary local data line ION, a first end of the 53rd transistor M53 is connected to the local data line 10, a control end of the 53rd transistor M53 is connected to the first end of the 54th transistor M54, and a control end of the 54th transistor M54 is connected to the first end of the 53rd transistor M53. The second end of the fifty-third transistor M53 and the second end of the fifty-fourth transistor M54 are both connected to the first end of the fifty-fifth transistor M55, and the second end of the fifty-fifth transistor M55 is grounded.

[0055] A control terminal of the fifty-fifth transistor M55 receives a read enable signal RdEn, which controls whether the fifty-fifth transistor M55 is turned on or off. A control terminal of the fifty-sixth transistor M56 receives a complementary read enable signal RdEnN, which controls whether the fifty-sixth transistor M56 is turned on or off. When the fifty-fifth transistor M55 and the fifty-sixth transistor M56 are turned on, the fifty-first transistor M51, the fifty-second transistor M52, the fifty-third transistor M53, and the fifty-fourth transistor M54 amplify a voltage difference between the local data line 10 and the complementary local data line ION.

[0056] The semiconductor memory also includes a sixty-first transistor M61, a sixty-second transistor M62, and a sixty-third transistor M63. The first end of the sixty-first transistor M61 is connected to the local data line IO, the second end of the sixty-first transistor M61 receives the tenth power signal, the first end of the sixty-second transistor M62 receives the tenth power signal, the second end of the sixty-second transistor M62 is connected to the complementary local data line ION, the first end of the sixty-third transistor M63 is connected to the local data line IO, the second end of the sixty-third transistor M63 is connected to the complementary local data line ION, the control end of the sixty-first transistor M61, the control end of the sixty-second transistor M62, and the control end of the sixty-third transistor M63 receive the second complementary equalization control signal EqION, and under the control of the second complementary equalization control signal EqION, the voltages on the local data line IO and the complementary local data line ION are driven to a third pre-charge voltage, which is the voltage of the tenth power signal.

[0057] The second amplifying module 80 further includes a 57th transistor M57 and a 58th transistor M58. A first end of the 57th transistor M57 is connected to the global data line YIO, a second end of the 57th transistor M57 is connected to the first end of the 58th transistor M58, a second end of the 58th transistor M58 is grounded, a control end of the 58th transistor M58 receives a read enable signal RdEn, and a control end of the 57th transistor M57 receives a local data line 10. Under the control of the read enable signal RdEn, the voltage on the local data line 10 is amplified and then output to the global data line YIO.

[0058] The second amplification module 80 further includes a 59th transistor M59, a 60th transistor M60, and a 64th transistor M64. The first end of the 59th transistor M59 is connected to the complementary local data line ION, the second end of the 59th transistor M59 is connected to the complementary global data line YION, the control end of the 60th transistor M60 is connected to the complementary global data line YION, the first end of the 60th transistor M60 is connected to the local data line IO, the second end of the 60th transistor M60 is connected to the first end of the 64th transistor M64, the second end of the 64th transistor M64 is grounded, and the control end of the 64th transistor M64 receives a write enable signal WrEn. The control end of the 59th transistor M59 receives the write enable signal WrEn. Under the control of the write enable signal WrEn, the voltage on the complementary global data line YION is amplified and output to the local data line IO. The voltage on the complementary global data line YION is then transmitted to the complementary local data line ION via the 59th transistor M59.

[0059] FIG5 is a layout of a semiconductor memory. As shown in FIG5 , the semiconductor memory includes a memory bank (Bank), which includes two half-memory banks 10 and a second control area 20. A row decoding circuit is provided in the second control area 20. The row decoding circuit is used to decode the row address of the memory bank to generate a word line signal. The word line signal is used to control the storage cells in the two half-memory banks to read and write data.

[0060] When arranging the first and second amplifying modules 70, 80, a portion of the second amplifying module 80 is typically placed in the area where the first amplifying module is located, while the remaining portion is placed in other areas. Figure 6 illustrates an exemplary semiconductor memory layout. As shown in Figure 6, a first partial area 30 is located within half of the memory bank. The first partial area 30 includes a second storage area (MAT) 304, a second amplifying area 301, a third control area 302, and a fourth control area 303. A second amplifying area 301 is located between two second storage areas 304 arranged along the second direction Y. Within the second amplifying area 301 lies the first amplifying module (MSA).

[0061] Part of the circuit of the second amplifying module (LSA) is also arranged in the second amplifying area 301. A third driving circuit (PCS / NCS) is also provided in the second amplifying area 301. The third driving circuit is used to provide power signals to the first amplifying module 70 and / or the second amplifying module 80.

[0062] A third control region 302 is disposed between two second amplification regions 301 arranged along the first direction X. Partial circuitry of the second amplification module (LSA) is housed in the third control region 302. A first control circuit (SWC) is also disposed in the third control region 302. The first control circuit (SWC) is used to control one or more combinations of circuits within the second amplification regions 301 or other circuits within the third control region 302.

[0063] A fourth control region 303 is arranged between two second storage regions 304 arranged along the first direction X. A second control circuit (SWD) is arranged in the fourth control region 303 . The second control circuit is used to drive word lines in the second storage regions 304 .

[0064] Since the circuit structure of the first amplifying module 70 shown in FIG1 is different from the circuit structure of the second amplifying module 80 shown in FIG3 and FIG4 , the layout of the first amplifying module 70 is different from the layout of the second amplifying module 80 , and the process flows used are different, the process difficulty of the device will be increased.

[0065] FIG7 is a circuit schematic diagram of a semiconductor memory provided by some embodiments of the present application. As shown in FIG7 , some embodiments of the present application provide a semiconductor memory including: a first amplifying module 70 , a second amplifying module 80 , a first control transistor T1 , and a second control transistor T2 .

[0066] At least a portion of the circuit structure of the first amplifying module 70 is the same as at least a portion of the circuit structure of the second amplifying module 80 .

[0067] The first amplifier module 70 is connected to the bit line BL and the complementary bit line BLB, and is used to amplify the voltage difference between the bit line BL and the complementary bit line BLB. The second amplifier module 80 is connected to the local data line IO and the complementary local data line ION, and is used to amplify the voltage difference between the local data line IO and the complementary local data line ION.

[0068] The local data line IO is connected to the bit line BL through the first control transistor T1, and the complementary local data line ION is connected to the complementary bit line BLB through the second control transistor T2. The control terminals of the first control transistor T1 and the second control transistor T2 receive the column selection signal CSL.

[0069] Among them, at least part of the circuit structure of the first amplifier module 70 is identical to at least part of the circuit structure of the second amplifier module 80. Specifically, this means that: a first partial structure formed by replacing some transistors of the first amplifier module 70 with wires or removing some transistors in the first amplifier module 70 is identical to the circuit structure of the second amplifier module 80; or, a first partial structure formed by replacing some transistors of the first amplifier module 70 with wires or removing some transistors in the first amplifier module 70 is identical to a second partial structure formed by replacing some transistors of the second amplifier module 80 with wires or removing some transistors. It should be noted that determining whether the circuit structures are identical only focuses on whether the types and positions of the transistors included in the circuit structures are identical, and does not focus on whether the signals received by the transistors are identical.

[0070] The column select signal CSL is used to control the on / off switching of the first control transistor T1. The column select signal CSL is also used to control the on / off switching of the second control transistor T2. When the first control transistor T1 and the second control transistor T2 are turned on, data on the local data line IO and the complementary local data line ION can be transferred to the bit line BL and the complementary bit line BLB, or vice versa.

[0071] The data on the bit line BL and the complementary bit line BLB is represented by the voltage difference between the bit line BL and the complementary bit line BLB. When the voltage of the bit line BL is greater than the voltage of the complementary bit line BLB, the data on the bit line BL and the complementary bit line BLB is 1. When the voltage of the bit line BL is less than the voltage of the complementary bit line BLB, the data on the bit line BL and the complementary bit line BLB is 0.

[0072] Similarly, the data on the local data line IO and the complementary local data line ION is represented by the voltage difference between the local data line IO and the complementary local data line ION. When the voltage of the local data line IO is greater than the voltage of the complementary local data line ION, it indicates that the data on the local data line IO and the complementary local data line ION is 1. When the voltage of the local data line IO is less than the voltage of the complementary local data line ION, it indicates that the data on the local data line IO and the complementary local data line ION is 0.

[0073] In the above technical solution, the semiconductor memory includes a first amplifier module 70, a second amplifier module 80, a first control transistor T1, and a second control transistor T2. The bit line BL and the local data line IO are connected via the first control transistor T1, and the complementary bit line BLB and the complementary local data line ION are connected via the second control transistor T2. This enables transmission of data on the bit line BL and the complementary bit line BLB with data on the local data line IO and the complementary local data line ION. The first amplifier module 70 is used to amplify the voltage difference between the bit line BL and the complementary bit line BLB, and the second amplifier module 80 is used to amplify the voltage difference between the local data line IO and the complementary local data line ION. This makes the first amplifier module 70 and the second amplifier module 80 functionally continuous and thus physically adjacent. By arranging at least a portion of the circuit structure of the first amplifier module 70 and at least a portion of the circuit structure of the second amplifier module 80 to be identical, the layout structure of the first amplifier module 70 and the layout structure of the second amplifier module 80 are similar, allowing the device to be manufactured using a unified manufacturing process, reducing process difficulty.

[0074] In some embodiments, Figure 8 is a circuit schematic diagram of a semiconductor memory provided in some embodiments of the present application. As shown in Figure 8, the semiconductor memory further includes a third control tube T3 and a fourth control tube T4. The local data line IO is connected to the global data line YIO through the third control tube T3, and the complementary local data line ION is connected to the complementary global data line YION through the fourth control tube T4. The control end of the third control tube T3 and the control end of the fourth control tube T4 both receive a read-write control signal RW, wherein the read-write control signal RW is generated when the semiconductor memory receives a read data instruction or a write data instruction.

[0075] Here, the third transistor T3 and the fourth transistor T4 are N-type transistors as an example. When the semiconductor memory receives a read data instruction, a read / write control signal RW is generated. When the read / write control signal RW is at a high level, the third control transistor T3 and the fourth control transistor T4 are turned on to control the data on the local data line IO and the complementary local data line ION to be transferred to the global data line YIO and the complementary global data line YION. When the semiconductor memory receives a write data instruction and generates a read / write control signal RW, when the read / write control signal RW is at a high level, the third control transistor T3 and the fourth control transistor T4 are turned on to control the data on the global data line YIO and the complementary global data line YION to be transferred to the local data line IO and the complementary local data line ION. By providing a third control transistor T3 connecting the local data line IO and the global data line YIO, and a fourth control transistor T4 connecting the complementary local data line ION and the complementary global data line YION, data on the local data line IO and the global data line YIO can be transmitted with data on the complementary local data line ION and the complementary global data line YION. That is, the third control transistor T3 and the fourth control transistor T4 are used to transmit data between the local data line IO and the complementary local data line ION and the global data line YIO and the complementary global data line YION, similar to the functions of the first control transistor T1 and the second control transistor T2. Consequently, the relative positional relationship between the third control transistor T3 and the second amplifying module 80 is similar to the relative positional relationship between the first control transistor T1 and the first amplifying module 70, and the relative positional relationship between the fourth control transistor T4 and the second amplifying module 80 is similar to the relative positional relationship between the second control transistor T2 and the first amplifying module 70. This helps to improve the symmetry of the layout at the location of the first amplifying module 70 and the layout at the location of the second amplifying module 80. A unified manufacturing process can be used for device manufacturing, reducing the process difficulty.

[0076] In some embodiments, the semiconductor memory further includes a plurality of third control transistors T3 connected in parallel and a plurality of fourth control transistors T4 connected in parallel, wherein one end of the plurality of third control transistors T3 is connected to the same local data line IO, and the other end of the plurality of third control transistors T3 is connected to the same global data line YIO, one end of the plurality of fourth control transistors T4 is connected to the same complementary local data line ION, and the other end of the plurality of fourth control transistors T4 is connected to the same complementary global data line YION. By arranging the transistors in parallel, the driving capability can be improved, the data transmission speed between the local data line IO and the global data line YIO and the complementary local data line ION and the complementary global data line YION can be improved, and the read and write performance of the semiconductor memory can be improved.

[0077] In some embodiments, Figure 9 is a circuit diagram of a semiconductor memory provided in other embodiments of the present application. As shown in Figure 9, the semiconductor memory further includes a third control transistor T3, a fifth control transistor T5, and a sixth control transistor T6. The local data line IO is connected to the global data line YIO through the third control transistor T3, and the complementary local data line ION is grounded through the fifth control transistor T5 and the sixth control transistor T6, and the fifth control transistor T5 and the sixth control transistor T6 are connected in series.

[0078] The control terminal of the third control transistor T3 receives a read / write control signal RW, the control terminal of the fifth control transistor T5 is connected to the global data line YIO, and the control terminal of the sixth control transistor T6 receives a write enable signal WrEn. The read / write control signal RW is generated when the semiconductor memory receives a read data instruction or a write data instruction, and the write enable signal WrEn is generated when the semiconductor memory receives a write data instruction.

[0079] Here, using the example of the third transistor T3, the fifth transistor T5, and the sixth transistor T6 being N-type transistors, when the semiconductor memory receives a data write instruction and generates a read / write control signal RW and a write enable signal WrEn, and when both the read / write control signal RW and the write enable signal WrEn are high, the third control transistor T3 and the sixth control transistor T6 are turned on. If the voltage on the global data line YIO is high, the fifth control transistor T5 is turned on, grounding the complementary local data line ION and driving the local data line IO to a high level, thereby writing data to the local data line IO and the complementary local data line ION. If the voltage on the global data line YIO is low, the fifth control transistor T5 is turned off, maintaining the complementary local data line ION at the fourth precharge voltage, and driving the local data line IO to a low level. By setting the fourth precharge voltage to be greater than the low level and satisfying the voltage difference requirement, data can be written to the local data line IO and the complementary local data line ION.

[0080] The series connection order of the fifth control transistor T5 and the sixth control transistor T6 is not limited herein. As one feasible solution, the first end of the fifth control transistor T5 is connected to the complementary local data line ION, the second end of the fifth control transistor T5 is connected to the first end of the sixth control transistor T6, and the second end of the sixth control transistor T6 is grounded. As another feasible solution, the first end of the sixth control transistor T6 is connected to the complementary local data line ION, the second end of the sixth control transistor T6 is connected to the first end of the fifth control transistor T5, and the second end of the fifth control transistor T5 is grounded.

[0081] That is, the third control transistor T3 implements signal transmission between the local data line IO and the global data line YIO, and the fifth control transistor T5 implements signal transmission between the complementary local data line ION and the global data line YIO, which are similar to the functions of the first control transistor T1 and the second control transistor T3. As a result, the relative positional relationship between the third control transistor T3 and the second amplifying module 80 is similar to the relative positional relationship between the first control transistor T1 and the first amplifying module 70, and the relative positional relationship between the fifth control transistor T5 and the second amplifying module 80 is similar to the relative positional relationship between the second control transistor T2 and the first amplifying module 70. This helps to improve the symmetry of the layout at the location of the first amplifying module and the layout at the location of the second amplifying module, and can use a unified manufacturing process for device manufacturing, reducing the process difficulty.

[0082] In some embodiments, the semiconductor memory includes multiple second amplification modules 80, and the multiple second amplification modules 80 are connected to the same local data line IO and the same complementary local data line ION. In this way, the multiple second amplification modules 80 can simultaneously amplify the voltage difference on the same pair of local data lines IO and complementary local data lines ION, thereby increasing the voltage difference amplification rate and improving the data reading and writing rate.

[0083] In some embodiments, FIG10 is a circuit diagram of a semiconductor memory provided in other embodiments of the present application. As shown in FIG10 , the second amplifying module 80 includes a first transistor M1 , a second transistor M2 , a seventh transistor M7 , and an eighth transistor M8 .

[0084] A first end of the first transistor M1 and a first end of the second transistor M2 receive a first power signal PCS_L, and a second end of the seventh transistor M7 and a second end of the eighth transistor M8 receive a second power signal NCS_L.

[0085] The second end of the first transistor M1 is connected to the first end of the seventh transistor M7, the control end of the first transistor M1 is connected to the second end of the second transistor M2, the second end of the second transistor M2 is connected to the first end of the eighth transistor M8, the control end of the second transistor M2 is connected to the second end of the first transistor M1, the control end of the seventh transistor M7 is connected to the first end of the eighth transistor M8, and the control end of the eighth transistor M8 is connected to the first end of the seventh transistor M7.

[0086] Among them, the first amplifying module 70 can be the structure shown in Figure 1, so that the local circuit structure of the first amplifying module 70 is the same as the circuit structure of the second amplifying module 80. That is, the second amplifying module 80 is the structure of Figure 1 except that the thirteenth transistor M13 and the fourteenth transistor M14 are replaced by wires, and the fifteenth transistor M15 and the sixteenth transistor M16 are removed, so that the local circuit structure of the first amplifying module 70 is the same as the circuit structure of the second amplifying module 80.

[0087] In other embodiments, the structure of the first amplifying module may be a structure in which only the thirteenth transistor M13 and the fourteenth transistor M14 are replaced with wires on the basis of FIG1 , or a circuit structure in which only the fifteenth transistor M15 and the sixteenth transistor M16 are removed on the basis of FIG1 . In this way, it is also possible to achieve that part of the circuit structure of the first amplifying module 70 is the same as the circuit structure of the second amplifying module 80.

[0088] In other embodiments, the structure of the first amplifying module can also be a circuit structure based on Figure 1, except that the thirteenth transistor M13 and the fourteenth transistor M14 are replaced by wires, and the fifteenth transistor M15 and the sixteenth transistor M16 are removed. In this way, the circuit structure of the first amplifying module 70 can be completely identical to the circuit structure of the second amplifying module 80.

[0089] In some embodiments, Figure 11 is a circuit schematic diagram of a semiconductor memory provided in some other embodiments of the present application. As shown in Figure 11, Figure 8 and Figure 9, the second amplification module 80 also includes a fifth transistor M5 and a sixth transistor M6. The first end of the fifth transistor M5 is connected to the control end of the seventh transistor M7, and the second end of the fifth transistor M5 is connected to the first end of the seventh transistor M7; the first end of the sixth transistor M6 is connected to the first end of the eighth transistor M8, and the second end of the sixth transistor M6 is connected to the control end of the eighth transistor M8.

[0090] In some embodiments, a control terminal of the fifth transistor M5 receives a first equalization control signal EqIO, and a control terminal of the sixth transistor M6 receives the first equalization control signal EqIO. The first equalization control signal EqIO is used to control the fifth transistor M5 and the sixth transistor M6 to be turned on or off. The first equalization control signal EqIO is also used to control the equalization circuit to precharge the local data line IO and the complementary local data line ION.

[0091] Among them, the first amplifying module 70 can be the structure shown in Figure 1, so that the partial circuit structure of the first amplifying module 70 is the same as the circuit structure of the second amplifying module 80, that is, the second amplifying module 80 is the result of replacing the thirteenth transistor M13 and the fourteenth transistor M14 with wires on the basis of Figure 1, so that the partial circuit structure of the first amplifying module 70 is the same as the circuit structure of the second amplifying module 80.

[0092] In other embodiments, the structure of the first amplifying module 70 can also be a structure based on Figure 1, except that the thirteenth transistor M13 and the fourteenth transistor M14 are replaced by wires, and the fifteenth transistor M15 and the sixteenth transistor M16 are removed, so that part of the circuit structure of the first amplifying module 70 is the same as the circuit structure of the second amplifying module 80.

[0093] In other embodiments, the structure of the first amplifying module 70 can also be a structure in which the thirteenth transistor M13 and the fourteenth transistor M14 are replaced by wires based on FIG. 1 , so that the circuit structure of the first amplifying module 70 is completely identical to the circuit structure of the second amplifying module 80 .

[0094] By using the first equalization control signal EqIO to control the fifth transistor M5 and the sixth transistor M6, it is ensured that the fifth transistor M5 and the sixth transistor M6 are in a conductive state when the equalization circuit is precharging, which is beneficial to precharging the local data line IO and the complementary local data line ION and can also simplify the structure of the equalization circuit.

[0095] In some embodiments, as shown in Figures 8 and 9, the balancing circuit is connected to the first end of the eighth transistor M8. The balancing circuit also receives a third power signal. The balancing circuit receives a first balancing control signal EqIO, which is used to control the first end of the eighth transistor M8 to receive the third power signal. The voltage of the third power signal is within the range of [0.5V, 0.55V]. In other embodiments, the voltage of the third power signal is within the range of [1V, 1.08V]. When the first balancing control signal EqIO causes the first end of the eighth transistor M8 to receive the third power signal, the fifth transistor M5 and the sixth transistor M6 are turned on, which facilitates precharging of the local data line IO and the complementary local data line ION, simplifying the structure of the balancing circuit.

[0096] In some embodiments, the balancing circuit is connected to the first end of the seventh transistor M7 and further receives a third power signal. The balancing circuit also receives a first balancing control signal EqIO, which is used to control the first end of the seventh transistor M7 to receive the third power signal. When the first balancing control signal EqIO causes the first end of the seventh transistor M7 to receive the third power signal, the fifth transistor M5 and the sixth transistor M6 are turned on, which facilitates precharging of the local data line IO and the complementary local data line ION, simplifying the structure of the balancing circuit.

[0097] In some embodiments, the balancing circuit includes a ninth transistor M9, wherein a first end of the ninth transistor M9 is connected to a first end of the eighth transistor M8, a second end of the ninth transistor M9 receives a third power supply signal, and a control end of the ninth transistor M9 receives a first balancing control signal EqIO. When the first balancing control signal EqIO turns on the ninth transistor M9, the first end of the eighth transistor M8 receives the third power supply signal, and the fifth transistor M5 and the sixth transistor M6 are in a turned-on state, thereby precharging the local data line IO and the complementary local data line ION, thereby simplifying the structure of the balancing circuit.

[0098] In some embodiments, as shown in Figures 7 and 8, the second amplification module 80 includes a third transistor M3 and a fourth transistor M4, the control end of the seventh transistor M7 is connected to the first end of the eighth transistor M8 through the third transistor M3, and the control end of the eighth transistor M8 is connected to the first end of the seventh transistor M7 through the fourth transistor M4.

[0099] The third transistor M3 and the fourth transistor M4 are in a long-term on state, or the third transistor M3 and the fourth transistor M4 are turned on or off according to the read / write control signal RW, or the third transistor M3 and the fourth transistor M4 are turned on or off according to the isolation control signal ISO. The isolation control signal ISO is also used to control the first amplification module 70 to amplify the voltage difference between the bit line BL and the complementary bit line BLB.

[0100] The first amplifying module 70 may be of the structure shown in FIG. 1 , so that the circuit structure of the first amplifying module 70 is the same as the circuit structure of the second amplifying module 80 .

[0101] In other embodiments, the structure of the first amplifying module 70 is the same as that of Figure 1 except that the thirteenth transistor M13 and the fourteenth transistor M14 are replaced with wires, and the fifteenth transistor M15 and the sixteenth transistor M16 are removed, so that part of the circuit structure of the first amplifying module 70 is the same as the circuit structure of the second amplifying module 80.

[0102] In other embodiments, the structure of the first amplifying module 70 is a structure in which the thirteenth transistor M13 and the fourteenth transistor M14 are replaced with wires based on FIG. 1 , so that part of the circuit structure of the first amplifying module 70 is the same as the circuit structure of the second amplifying module 80 .

[0103] As a possible implementation, the third transistor M3 and the fourth transistor M4 are in a long-term on state, allowing the second amplification module 80 to amplify the voltage difference between the local data line 10 and the complementary local data line ION. Specifically, when the third transistor M3 and the fourth transistor M4 are N-type transistors, a high level is connected to the control terminals of the third transistor M3 and the fourth transistor M4. When the third transistor M3 and the fourth transistor M4 are P-type transistors, a low level is connected to the control terminals of the third transistor M3 and the fourth transistor M4.

[0104] As a possible implementation, the third transistor M3 and the fourth transistor M4 are turned on or off according to the read / write control signal RW. Taking the third transistor T3 and the fourth transistor T4 as N-type transistors as an example, when the read / write control signal RW is high, the third transistor M3 and the fourth transistor M4 are turned on, allowing the second amplifier module 80 to amplify the voltage difference between the local data line IO and the complementary local data line ION. When the read / write control signal RW is low, the third transistor M3 and the fourth transistor M4 are turned off, preventing the second amplifier module 80 from amplifying the voltage difference between the local data line IO and the complementary local data line ION. The third control transistor T3, the fourth control transistor T4, the third transistor M3, and the fourth transistor M4 are all controlled by the read / write control signal RW, which can simplify the control circuit and reduce the layout of the control signal lines.

[0105] As one possible implementation, the third transistor M3 and the fourth transistor M4 are turned on or off based on an isolation control signal ISO. The isolation control signal ISO is used to control the first amplifier module 70 to amplify the voltage difference between the bit line BL and the complementary bit line BLB. Taking the third transistor T3 and the fourth transistor T4 as N-type transistors as an example, when the isolation control signal ISO is high, the third transistor M3 and the fourth transistor M4 are turned on, enabling the second amplifier module 80 to amplify the voltage difference between the local data line IO and the complementary local data line ION. When the isolation control signal ISO is low, the third transistor M3 and the fourth transistor M4 are turned off, preventing the second amplifier module 80 from amplifying the voltage difference between the local data line IO and the complementary local data line ION. The first amplifier module 70 and the second amplifier module 80 share the isolation control signal ISO, which simplifies the control circuit and reduces the layout of control signal lines.

[0106] FIG12 illustrates a possible write timing control diagram for a semiconductor memory device provided by some embodiments of the present application. Using the circuit structures of FIG7 and FIG11 as examples, in the first stage S5, the second equalization control signal EqIO is low, and the equalization circuit stops precharging the local data line IO and the complementary local data line ION. The read / write control signal RW is high, turning on the third control transistor T3 and the fourth control transistor T4, and transmitting data from the global data line YIO and the complementary global data line YION to the local data line IO and the complementary local data line ION. The first power supply signal PCS_L is the power supply voltage, the second power supply signal NCS_L is the ground voltage, the second equalization control signal EqIO is low, the fifth transistor M5 and the sixth transistor M6 are off, and the second amplifier module amplifies the voltage difference between the local data line IO and the complementary local data line ION. The column select signal CSL is high, and the data on the local data line IO and the complementary local data line ION is transmitted to the bit line BL and the complementary bit line BLB, enabling data to be written into the memory cell when the word line is enabled.

[0107] FIG13 illustrates a possible read timing control diagram for a semiconductor memory device provided in some embodiments of the present application. Using the circuit structures of FIG7 and FIG9 as examples, in the second stage S6, the second equalization control signal EqIO is low, and the equalization circuit stops precharging the local data line IO and the complementary local data line ION. The column select signal CSL is high, and data on the bit line BL and the complementary bit line BLB are transferred to the local data line IO and the complementary local data line ION. The first power supply signal PCS_L is the power supply voltage, the second power supply signal NCS_L is the ground voltage, the second equalization control signal EqIO is low, the fifth transistor M5 and the sixth transistor M6 are turned off, and the second amplifier module amplifies the voltage difference between the local data line IO and the complementary local data line ION. The read / write control signal RW is high, turning on the third control transistor T3, and the data on the local data line IO is transferred to the global data line YIO.

[0108] In some embodiments, Figure 14 illustrates a layout of a semiconductor memory device provided in some embodiments of the present application. As shown in Figure 14 , the semiconductor memory device includes a first control region 50, with half of a memory bank 10 disposed on either side of the first control region 50. A row decoding circuit is disposed within the first control region 50 for decoding the row address of the memory bank. The semiconductor memory device also includes a first driver circuit, which is connected to the first amplifier module and configured to provide power signals. For example, the first driver circuit may provide a fifth power signal and a sixth power signal. The first driver circuit is located within the first control region 50. For example, Figure 16 illustrates a layout of a semiconductor memory device provided in some embodiments of the present application. Figure 16 only illustrates a portion of the semiconductor memory device structure. As shown in Figure 16 , a first region 606 is disposed within the first control region 50 for accommodating the first driver circuit. This configuration can reduce the area of ​​the first amplification region. Furthermore, because there are a large number of first amplification regions within a memory bank, reducing the height of each first amplification region can reduce the height of the entire memory bank.

[0109] In some embodiments, FIG15 is a layout diagram of a semiconductor memory provided in some embodiments of the present application. FIG15 shows only a portion of the structure of the semiconductor memory, that is, only the second portion 60 in FIG14 . As shown in FIG15 , the semiconductor memory includes multiple first amplification regions 601, each of which is provided with a first amplification module. An intermediate region 602 is disposed between two adjacent first amplification regions 601 in a first direction X, and a second amplification module is disposed within the intermediate region 602. Because at least a portion of the circuit structure of the first amplification module and at least a portion of the circuit structure of the second amplification module are identical, the first amplification module and the second amplification module can be fabricated simultaneously within the first amplification region 601 and the intermediate region 602, reducing process complexity.

[0110] In some embodiments, the semiconductor memory further includes a first storage area 604 and a fifth control area 603, wherein the fifth control area 603 is arranged between the two first storage areas 604 arranged along the first direction X, and a third control circuit is arranged in the fifth control area 603, and the third control circuit is used to drive the word line in the first storage area 604.

[0111] In some embodiments, Figure 16 is a layout of a semiconductor memory provided by some embodiments of the present application. Figure 16 only shows a part of the structure of the semiconductor memory. As shown in Figure 16, a driving area 605 is arranged on the side of half of the storage memory away from the first control area 50. The semiconductor memory includes a first driving circuit and a second driving circuit. The first driving circuit is connected to the first amplifying module. The first driving circuit is located in the first control area 50. The second driving circuit is connected to the first amplifying module. The second driving circuit is arranged in the driving area 605. The first driving circuit and the second driving circuit are both used to provide power signals to the first amplifying module. This can improve the driving capability, improve the amplification rate of the first amplifying module to the voltage difference on the bit line and the complementary bit line, and improve the read and write performance of the semiconductor memory.

[0112] In some embodiments, the second driving circuit can provide a power signal to the nearby first amplifying modules, which is beneficial to enhancing the power supply of the first amplifying modules at the edge and improving the read and write performance of the semiconductor memory.

[0113] As one feasible solution, the second drive circuit and the first drive circuit can be connected to the same power supply, and the power signal is provided to the first amplification module based on the connected power supply. As another feasible solution, the second drive circuit can be connected to the first drive circuit, and the first drive circuit provides power to the second drive circuit, so that the second drive circuit provides the power signal to the first amplification module.

[0114] In some embodiments, the first driving circuit and the second driving circuit may further provide power signals to the second amplifying module. For example, the first driving circuit and the second driving circuit may both provide a first power signal and a second power signal.

[0115] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this application and include common knowledge or customary techniques in the art that are not disclosed herein.

[0116] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor memory, comprising: A first amplification module (70), a first control transistor (T1), a second control transistor (T2), and a second amplification module (80); At least part of the circuit structure of the first amplification module (70) is the same as at least part of the circuit structure of the second amplification module (80); The first amplification module (70) is connected to a bit line (BL) and a complementary bit line (BLB), and is configured to amplify the voltage difference between the bit line (BL) and the complementary bit line (BLB); The second amplification module (80) is connected to a local data line (IO) and a complementary local data line (ION), and is configured to amplify the voltage difference between the local data line (IO) and the complementary local data line (ION); The local data line (IO) is connected to the bit line (BL) through the first control transistor (T1), the complementary local data line (ION) is connected to the complementary bit line (BLB) through the second control transistor (T2), and the control terminals of the first control transistor (T1) and the second control transistor (T2) receive a column selection signal (CSL).

2. The semiconductor memory according to claim 1, wherein the semiconductor memory includes a plurality of first amplification regions (601), and the first amplification module (70) is disposed in the first amplification regions (601); An intermediate region (602) is arranged between two adjacent first amplification regions (601) in a first direction (X), and the second amplification module (80) is arranged in the intermediate region (602).

3. The semiconductor memory according to claim 2, wherein the semiconductor memory further includes a first driving circuit, the first driving circuit is connected to the first amplification module (70), and the first driving circuit is configured to provide a power signal; The semiconductor memory further includes a first amplification region (50), with half of a memory bank disposed on each side of the first amplification region (50). A row decoding circuit is disposed in the first amplification region (50) for decoding the row address of the memory bank, and the first driving circuit is located in the first amplification region (50).

4. The semiconductor memory according to claim 3, wherein the semiconductor memory further includes a second driving circuit, the second driving circuit is connected to the first amplification module (70); A driving region (605) is arranged on a side of the half memory bank away from the first amplification region (50), and the second driving circuit is arranged in the driving region (605).

5. The semiconductor memory according to claim 1, wherein the semiconductor memory further includes a third control transistor (T3) and a fourth control transistor (T4); The local data line (IO) is connected to a global data line (YIO) through the third control transistor (T3), and the complementary local data line (ION) is connected to a complementary global data line (YION) through the fourth control transistor (T4); The control terminals of the third control transistor (T3) and the fourth control transistor (T4) both receive a read / write control signal (RW), and generate the read write control signal (RW) when the semiconductor memory receives a read data instruction or a write data instruction.

6. The semiconductor memory according to claim 5, wherein the semiconductor memory includes a plurality of parallel-connected third control transistors (T3) and a plurality of parallel-connected fourth control transistors (T4); One ends of the plurality of third control transistors (T3) are connected to the same local data line (IO), and the other ends of the plurality of third control transistors (T3) are connected to the same global data line (YIO); One ends of the plurality of fourth control transistors (T4) are connected to the same complementary local data line (ION), and the other ends of the plurality of fourth control transistors (T4) are connected to the same complementary global data line (YION).

7. The semiconductor memory according to claim 1, wherein the semiconductor memory further includes a third control transistor (T3), a fifth control transistor (T5), and a sixth control transistor (T6); The local data line (IO) is connected to the global data line (YIO) through the third control transistor (T3); The complementary local data line (ION) is grounded through the fifth control transistor (T5) and the sixth control transistor (T6), and the fifth control transistor (T5) and the sixth control transistor (T6) are connected in series; Among them, The control terminal of the third control transistor (T3) receives the read / write control signal (RW), the control terminal of the fifth control transistor (T5) is connected to the global data line (YIO), and the control terminal of the sixth control transistor (T6) receives a write enable signal (WrEn); The read / write control signal (RW) is generated when the semiconductor memory receives a read data instruction or a write data instruction, and the write enable signal (WrEn) is generated when the semiconductor memory receives a write data instruction.

8. The semiconductor memory according to claim 1, wherein the semiconductor memory includes a plurality of the second amplification modules (80), and the plurality of second amplification modules (80) are connected to the same local data line (IO) and the same complementary local data line (ION).

9. The semiconductor memory according to claim 8, wherein the second amplification module (80) includes a first transistor (M1), a second transistor (M2), a seventh transistor (M7), and an eighth transistor (M8); The first ends of the first transistor (M1) and the second transistor (M2) receive a first power supply signal (PCS_L), and the second ends of the seventh transistor (M7) and the eighth transistor (M8) receive a second power supply signal (NCS_L); The second end of the first transistor (M1) is connected to the first end of the seventh transistor (M7), the control end of the first transistor (M1) is connected to the second end of the second transistor (M2), the second end of the second transistor (M2) is connected to the first end of the eighth transistor (M8), the control end of the second transistor (M2) is connected to the second end of the first transistor (M1), the control end of the seventh transistor (M7) is connected to the first end of the eighth transistor (M8), and the control end of the eighth transistor (M8) is connected to the first end of the seventh transistor (M7).

10. The semiconductor memory according to claim 9, wherein the second amplification module (80) further comprises a fifth transistor (M5) and a sixth transistor (M6); The first end of the fifth transistor (M5) is connected to the control end of the seventh transistor (M7), and the second end of the fifth transistor (M5) is connected to the first end of the seventh transistor (M7); the first end of the sixth transistor (M6) is connected to the first end of the eighth transistor (M8), and the second end of the sixth transistor (M6) is connected to the control end of the eighth transistor (M8); The control ends of the fifth transistor (M5) and the sixth transistor (M6) both receive a first equalization control signal (EqIO); The first equalization control signal (EqIO) is used to control the fifth transistor (M5) and the sixth transistor (M6) to conduct or cut off.

11. The semiconductor memory according to claim 10, wherein the second amplification module (80) comprises a third transistor (M3) and a fourth transistor (M4); The control end of the seventh transistor (M7) is connected to the first end of the eighth transistor (M8) through the third transistor (M3), and the control end of the eighth transistor (M8) is connected to the first end of the seventh transistor (M7) through the fourth transistor (M4); The third transistor (M3) and the fourth transistor (M4) are in a long-term conducting state, and the third transistor (M3) and the fourth transistor (M4) conduct or cut off according to a read / write control signal (RW), or the third transistor (M3) and the fourth transistor (M4) conduct or cut off according to an isolation control signal (ISO); The isolation control signal (ISO) is used to control the first amplification module (70) to amplify the voltage difference on the bit line (BL) and the complementary bit line (BLB).

12. The semiconductor memory according to claim 9, wherein the semiconductor memory further comprises an equalization circuit; The equalization circuit is connected to the first end of the seventh transistor (M7), or the equalization circuit is connected to the first end of the eighth transistor (M8); The equalization circuit further receives a third power supply signal, and the equalization circuit receives the first equalization control signal (EqIO) for controlling the first end of the seventh transistor (M7) or the first end of the eighth transistor (M8) to connect to the third power supply signal.

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