Low-noise amplifier and radio frequency chip

Abstract

The present invention is applicable to the technical field of wireless communications, and in particular relates to a low-noise amplifier and a radio frequency chip. Compared with the prior art, the low-noise amplifier of the present invention comprises a signal input end, an input matching network, a first gain attenuation unit, a second gain attenuation unit, a power amplification unit, an output matching network, and a signal output end. In the second gain attenuation unit, a gate of a first switch transistor, a gate of a second switch transistor, a gate of a third switch transistor, and a gate of a fourth switch transistor are connected to an external logic control circuit, a source of the first switch transistor, a source of the second switch transistor, a source of the third switch transistor, and a source of the fourth switch transistor are respectively grounded, and a first end of a second inductor is connected to an input end of the power amplification unit. In this way, the low-noise amplifier of the present invention can give considerations to IIP3 and noise figure while the gain is reduced.

Description

A low-noise amplifier and radio frequency chip Technical Field

[0001] The present invention is applicable to the field of wireless communication technology, and in particular relates to a low-noise amplifier and a radio frequency chip. Background Art

[0002] As a key component of a receiver, the performance of a low-noise amplifier (LNA) directly impacts the overall performance of the receiver (gain, power consumption, noise figure, linearity, area, etc.). In smart terminal applications, LNAs are often required to have gain adjustment capabilities to handle signals of varying antenna strengths.

[0003] There are many ways to reduce gain, such as attenuating the input resistor. This method can greatly optimize the input third-order intercept point (IIP3) and reduce current, but it significantly deteriorates the noise figure (NF). Attenuating the output resistor does not affect the NF but cannot optimize IIP3 and current. Switching the common-source transistor area generates some nonlinear capacitance when the common-source transistor is turned off, making it impossible to optimize IIP3 at low gain levels.

[0004] Therefore, a new low-noise amplifier and radio frequency chip are urgently needed to solve the above problems. Summary of the Invention

[0005] The present invention provides a low noise amplifier and a radio frequency chip, aiming to solve the problem that it is difficult for existing low noise amplifiers to improve IIP3 as much as possible and deteriorate the noise figure with minimal gain reduction.

[0006] In a first aspect, the present invention provides a low noise amplifier, comprising a signal input terminal, an input matching network, a first gain attenuation unit, a second gain attenuation unit, a power amplification unit, an output matching network, and a signal output terminal;

[0007] The signal input terminal is connected to the input terminal of the input matching network; the output terminal of the input matching network is connected to the input terminal of the first gain attenuation unit; the output terminal of the first gain attenuation unit is connected to the first input terminal of the power amplification unit; the first terminal of the second gain attenuation unit is used to be connected to the external logic control circuit, the second terminal of the second gain attenuation unit is grounded, and the third terminal of the second gain attenuation unit is connected to the second input terminal of the power amplification unit; the output terminal of the power amplification unit is connected to the input terminal of the output matching network; the output terminal of the output matching network is connected to the signal output terminal;

[0008] The second gain attenuation unit includes a first inductor, a second inductor, a first resistor, a second resistor, and a first switching transistor, a second switching transistor, a third switching transistor and a fourth switching transistor for acting as switches; the gate of the first switching transistor, the gate of the second switching transistor, the gate of the third switching transistor and the gate of the fourth switching transistor collectively serve as the first end of the second gain attenuation unit, the source of the first switching transistor, the source of the second switching transistor, the source of the third switching transistor and the source of the fourth switching transistor are interconnected and collectively serve as the second end of the second gain attenuation unit, the first end of the second inductor serves as the third end of the second gain attenuation unit, and the second end of the second inductor is connected to the drain of the first switching transistor; the first end of the first inductor is connected to the drain of the first switching transistor, the drain of the second switching transistor, the first end of the first resistor and the first end of the second resistor are respectively connected to the second end of the first inductor, the drain of the third switching transistor is connected to the second end of the first resistor, and the drain of the fourth switching transistor is connected to the second end of the second resistor.

[0009] Preferably, the first gain attenuation unit includes a first capacitor, a second capacitor, a third capacitor, and a fifth switching transistor and a sixth switching transistor for acting as switches; the first end of the first capacitor, the first end of the second capacitor and the first end of the third capacitor are interconnected and collectively connected to the output end of the input matching network as the input end of the first gain attenuation unit, and the first end of the first capacitor, the first end of the second capacitor and the first end of the third capacitor are interconnected and connected to the first input end of the power amplification unit as the first output end of the first gain attenuation unit; the second end of the second capacitor is connected to the drain of the fifth switching transistor, the second end of the third capacitor is connected to the drain of the sixth switching transistor, the gate of the fifth switching transistor and the gate of the sixth switching transistor are respectively used to connect to an external logic control circuit, the second end of the first capacitor, the source of the fifth switching transistor and the source of the sixth switching transistor are interconnected and collectively connected to the second input end of the power amplification unit as the second output end of the first gain attenuation unit.

[0010] Preferably, the power amplifying unit includes a first MOS transistor and a second MOS transistor; the gate of the first MOS transistor serves as the first input terminal of the power amplifying unit, and the source of the first MOS transistor serves as the second input terminal of the power amplifying unit;

[0011] The source of the second MOS transistor is connected to the drain of the first MOS transistor, the drain of the second MOS transistor serves as the output end of the power amplification unit, and the gate of the second MOS transistor is used to connect to an external bias circuit.

[0012] Preferably, the output matching network includes a fourth capacitor and a third inductor; the first end of the third inductor is used to connect to the power supply voltage, the second end of the third inductor and the first end of the fourth capacitor are connected and serve as the input end of the output matching network, and the second end of the fourth capacitor serves as the output end of the output matching network.

[0013] Preferably, the input matching network includes a fourth inductor; a first end of the fourth inductor serves as an input end of the input matching network, and a second end of the fourth inductor serves as an output end of the input matching network.

[0014] Preferably, the input matching network further includes a fifth capacitor, a first end of the fifth capacitor is connected to the second end of the fourth inductor, and a second end of the fifth capacitor serves as an output end of the input matching network.

[0015] In a second aspect, the present invention further provides a radio frequency chip, characterized in that the radio frequency chip includes a low noise amplifier as described in any one of the above embodiments.

[0016] Compared to the prior art, the low-noise amplifier of the present invention includes a signal input terminal, an input matching network, a first gain attenuation unit, a second gain attenuation unit, a power amplifier unit, an output matching network, and a signal output terminal. The gates of the first, second, third, and fourth switching transistors of the second gain attenuation unit are connected to an external logic control circuit, the sources of the first, second, third, and fourth switching transistors are grounded, the first end of the second inductor is connected to the input terminal of the power amplifier unit, the drain of the first switching transistor is connected to the first end of the first inductor and the second end of the second inductor, the drain of the second switching transistor, the first end of the first resistor, and the first end of the second resistor are connected to the second end of the first inductor, the drain of the third switching transistor is connected to the second end of the first resistor, the drain of the fourth switching transistor is connected to the second end of the second resistor, and the first end of the second inductor serves as the third end of the second gain attenuation unit. Thus, the low-noise amplifier of the present invention can achieve both IIP3 and noise figure while reducing gain. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made with reference to the following drawings. In the accompanying drawings:

[0018] FIG1 is a schematic structural diagram of a low noise amplifier provided by an embodiment of the present invention.

[0019] In the figure, 100 is a low noise amplifier, 1 is a signal input terminal, 2 is an input matching network, 3 is a first gain attenuation unit, 4 is a second gain attenuation unit, 5 is a power amplification unit, 6 is an output matching network, and 7 is a signal output terminal. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0021] Example 1

[0022] 1 , the present invention provides a low noise amplifier 100, which includes a signal input terminal 1, an input matching network 2, a first gain attenuation unit 3, a second gain attenuation unit 4, a power amplification unit 5, an output matching network 6, and a signal output terminal 7;

[0023] The signal input terminal 1 is connected to the input terminal of the input matching network 2; the output terminal of the input matching network 2 is connected to the input terminal of the first gain attenuation unit 3; the output terminal of the first gain attenuation unit 3 is connected to the first input terminal of the power amplification unit 5; the first terminal of the second gain attenuation unit 4 is used to be connected to the external logic control circuit, the second terminal of the second gain attenuation unit 4 is grounded GND1, and the third terminal of the second gain attenuation unit 4 is connected to the second input terminal of the power amplification unit 5; the output terminal of the power amplification unit 5 is connected to the input terminal of the output matching network 6; the output terminal of the output matching network 6 is connected to the signal output terminal 7;

[0024] The second gain attenuation unit 4 includes a first inductor L1, a second inductor L2, a first resistor R1, a second resistor R2, and a first switch transistor S1, a second switch transistor S2, a third switch transistor S3 and a fourth switch transistor S4 used to act as switches; the gate of the first switch transistor S1, the gate of the second switch transistor S2, the gate of the third switch transistor S3 and the gate of the fourth switch transistor S4 jointly serve as the first end of the second gain attenuation unit 4, and the source of the first switch transistor S1, the source of the second switch transistor S2, the source of the third switch transistor S3 and the source of the fourth switch transistor S4 are connected to each other and jointly serve as The second end of the second gain attenuation unit 4 and the first end of the second inductor L2 are connected to the input end of the power amplification unit 5 as the third end of the second gain attenuation unit 4, and the second end of the second inductor L2 is connected to the drain of the first switching transistor S1; the first end of the first inductor L1 is connected to the drain of the first switching transistor S1, the drain of the second switching transistor S2, the first end of the first resistor R1 and the first end of the second resistor R2 are respectively connected to the second end of the first inductor L1, the drain of the third switching transistor S3 is connected to the second end of the first resistor R1, and the drain of the fourth switching transistor S4 is connected to the second end of the second resistor R2.

[0025] In an embodiment of the present invention, the first gain attenuation unit 3 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fifth switching transistor S5 and a sixth switching transistor S6 for acting as switches; the first end of the first capacitor C1, the first end of the second capacitor C2, and the first end of the third capacitor C3 are interconnected and commonly connected to the output end of the input matching network 2 as the input end of the first gain attenuation unit 3, and the first end of the first capacitor C1, the first end of the second capacitor C2, and the first end of the third capacitor C3 are interconnected as the first output end of the first gain attenuation unit 3 and connected to the first input end of the power amplification unit 5; the second end of the second capacitor C2 is connected to the drain of the fifth switching transistor S5, the second end of the third capacitor C3 is connected to the drain of the sixth switching transistor S6, the gate of the fifth switching transistor S5 and the gate of the sixth switching transistor S6 are respectively used to connect to an external logic control circuit, the second end of the first capacitor C1, the source of the fifth switching transistor S5, and the source of the sixth switching transistor S6 are interconnected and commonly connected to the second output end of the first gain attenuation unit 3 as the second output end of the first gain attenuation unit 3 and are respectively connected to the second input end of the power amplification unit 5.

[0026] In the embodiment of the present invention, the power amplification unit 5 includes a first MOS transistor M1 and a second MOS transistor M2; the gate of the first MOS transistor M1 serves as the first input terminal of the power amplification unit 5 and is connected to the first output terminal of the first gain attenuation unit 3; the source of the first MOS transistor M1 serves as the second input terminal of the power amplification unit 5 and is respectively connected to the second output terminal of the first gain attenuation unit 3 and the third terminal of the second gain attenuation unit 4;

[0027] The source of the second MOS transistor M2 is connected to the drain of the first MOS transistor M1. The drain of the second MOS transistor M2 is connected to the input of the output matching network 6 as the output end of the power amplification unit 5. The gate of the second MOS transistor M2 is used to connect to an external bias circuit.

[0028] In an embodiment of the present invention, the output matching network 6 includes a fourth capacitor C4 and a third inductor L3; the first end of the third inductor L3 is used to connect to the power supply voltage VDD, the second end of the third inductor L3 and the first end of the fourth capacitor C4 are connected and serve as the input end of the output matching network 6 and are respectively connected to the output end of the power amplification unit 5, and the second end of the fourth capacitor C4 serves as the output end of the output matching network 6 and is connected to the signal output end 7.

[0029] In an embodiment of the present invention, the input matching network 2 includes a fourth inductor L4; the first end of the fourth inductor L4 is connected to the signal input end 1 as the input end of the input matching network 2, and the second end of the fourth inductor L4 is connected to the input end of the first gain attenuation unit 3 as the output end of the input matching network 2.

[0030] In an embodiment of the present invention, the input matching network 2 further includes a fifth capacitor C5, a first end of the fifth capacitor C5 is connected to the second end of the fourth inductor L4, and a second end of the fifth capacitor C5 is connected to the input end of the first gain attenuation unit 3 as the output end of the input matching network 2.

[0031] The present invention achieves gain reduction by adding series resistors (i.e., first resistor R1 and second resistor R2) to the source of the first MOS transistor M1. The gain reduction is controlled by switching between different resistance values ​​using switches (e.g., second switching transistor S2, third switching transistor S3, and fourth switching transistor S4). Furthermore, the frequency deviation of parameter S11 caused by the first and second resistors R1 and R2 is compensated by controlling the capacitance values ​​(first capacitor C1, second capacitor C2, and third capacitor C3) using switches (fifth switching transistor S5 and sixth switching transistor S6).

[0032] Specifically, one factor contributing to nonlinearity is the nonlinear relationship between leakage current and overdrive voltage. The presence of the source series resistor (Rs), composed of the first resistor R1 and the second resistor R2, can divide the input voltage, thereby weakening this nonlinear relationship and optimizing IIP3. Another factor contributing to nonlinearity is the nonlinearity of the common source transistor's parasitic capacitance. The introduction of a linear access capacitor (Cgs) network, composed of the first capacitor C1, the second capacitor C2, and the third capacitor C3, to compensate for frequency deviation reduces the proportion of nonlinear capacitance in the overall capacitance, thereby further optimizing IIP3.

[0033] Regarding noise figure, if the gain of the common-source stage is Av, the source series resistor (Rs) is equivalent to a resistance of Rs / Av at the input. Therefore, compared to direct input attenuation, the effect of this resistor on the noise figure is only 1 / Av. Therefore, the present invention can balance IIP3 and noise figure while reducing gain.

[0034] Compared to the prior art, the low-noise amplifier of the present invention includes a signal input terminal, an input matching network, a first gain attenuation unit, a second gain attenuation unit, a power amplifier unit, an output matching network, and a signal output terminal. The gates of the first, second, third, and fourth switching transistors of the second gain attenuation unit are connected to an external logic control circuit, the sources of the first, second, third, and fourth switching transistors are grounded, the first end of the second inductor is connected to the input terminal of the power amplifier unit, the drain of the first switching transistor is connected to the first end of the first inductor and the second end of the second inductor, the drain of the second switching transistor, the first end of the first resistor, and the first end of the second resistor are connected to the second end of the first inductor, the drain of the third switching transistor is connected to the second end of the first resistor, the drain of the fourth switching transistor is connected to the second end of the second resistor, and the first end of the second inductor serves as the third end of the second gain attenuation unit. Thus, the low-noise amplifier of the present invention can achieve both IIP3 and noise figure while reducing gain.

[0035] Example 2

[0036] The present invention further provides a radio frequency chip, which includes the low noise amplifier as described in the above embodiment. The technical effects achieved by the radio frequency chip are the same as those of the low noise amplifier in the above embodiment, and will not be described in detail here.

[0037] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0038] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only a preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A low-noise amplifier, characterized in that, The low-noise amplifier includes a signal input terminal, an input matching network, a first gain attenuation unit, a second gain attenuation unit, a power amplification unit, an output matching network, and a signal output terminal; The signal input terminal is connected to the input end of the input matching network; the output end of the input matching network is connected to the input end of the first gain attenuation unit; the output end of the first gain attenuation unit is connected to the first input end of the power amplification unit; the first end of the second gain attenuation unit is used to be connected to an external logic control circuit, the second end of the second gain attenuation unit is grounded, and the third end of the second gain attenuation unit is connected to the second input end of the power amplification unit; the output end of the power amplification unit is connected to the input end of the output matching network; the output end of the output matching network is connected to the signal output terminal; The second gain attenuation unit includes a first inductor, a second inductor, a first resistor, a second resistor, and first, second, third, and fourth switching transistors serving as switches; the gates of the first, second, third, and fourth switching transistors together serve as the first end of the second gain attenuation unit, the sources of the first, second, third, and fourth switching transistors are connected to each other and together serve as the second end of the second gain attenuation unit, the first end of the second inductor serves as the third end of the second gain attenuation unit, and the second end of the second inductor is connected to the drain of the first switching transistor; the first end of the first inductor is connected to the drain of the first switching transistor, the drains of the second switching transistor, the first end of the first resistor, and the first end of the second resistor are respectively connected to the second end of the first inductor, the drain of the third switching transistor is connected to the second end of the first resistor, and the drain of the fourth switching transistor is connected to the second end of the second resistor.

2. The low-noise amplifier according to claim 1, wherein The first gain attenuation unit includes a first capacitor, a second capacitor, a third capacitor, a fifth switching transistor and a sixth switching transistor serving as switches; a first end of the first capacitor, a first end of the second capacitor and a first end of the third capacitor are connected to each other and jointly serve as an input end of the first gain attenuation unit, and the first end of the first capacitor, the first end of the second capacitor and the first end of the third capacitor are connected to each other and serve as a first output end of the first gain attenuation unit; a second end of the second capacitor is connected to a drain of the fifth switching transistor, a second end of the third capacitor is connected to a drain of the sixth switching transistor, gates of the fifth switching transistor and the sixth switching transistor are respectively used for connecting to an external logic control circuit, a second end of the first capacitor, a source of the fifth switching transistor and a source of the sixth switching transistor are connected to each other and jointly serve as a second output end of the first gain attenuation unit and are connected to a second input end of the power amplification unit.

3. The low-noise amplifier according to claim 2, wherein The power amplification unit includes a first MOS transistor and a second MOS transistor; a gate of the first MOS transistor serves as a first input end of the power amplification unit, and a source of the first MOS transistor serves as a second input end of the power amplification unit; A source of the second MOS transistor is connected to a drain of the first MOS transistor, a drain of the second MOS transistor serves as an output end of the power amplification unit, and a gate of the second MOS transistor is used for connecting to an external bias circuit.

4. The low-noise amplifier according to claim 1, wherein The output matching network includes a fourth capacitor and a third inductor; a first end of the third inductor is used for connecting to a power supply voltage, a second end of the third inductor and a first end of the fourth capacitor are connected and jointly serve as an input end of the output matching network, and a second end of the fourth capacitor serves as an output end of the output matching network.

5. The low-noise amplifier according to claim 1, wherein, The input matching network includes a fourth inductor; a first end of the fourth inductor serves as an input end of the input matching network, and a second end of the fourth inductor serves as an output end of the input matching network.

6. The low-noise amplifier according to claim 5, wherein The input matching network further includes a fifth capacitor, a first end of the fifth capacitor is connected to a second end of the fourth inductor, and a second end of the fifth capacitor serves as an output end of the input matching network.

7. A radio frequency chip, characterized in that, The radio frequency chip includes the low-noise amplifier according to any one of claims 1-6.

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