A robust circuit for pulse width control for short pulse applications

Abstract

The invention relates to an apparatus for pulse width control in a Vertical Cavity Surface Emitting Laser (VCSEL) driver, configured to control the pulse width of current pulses in a Time-of-Flight (ToF) application, and comprising two poles and one zero configuring a two-poles, one-zero system, and wherein the apparatus comprises - a high gain amplifier H_int configured to reduce gain error and stabilize the complete loop, and - a delay cell H_delay, wherein a capacitor Cint is provided in the feedback path of the high gain amplifier H_int at a first pole of the high gain amplifier H_int, to stabilize the system.

Description

[0001] A Robust Circuit for Pulse Width Control for Short Pulse Applications

[0002] DESCRIPTION

[0003] TECHNICAL FIELD

[0004] The invention relates to an apparatus for pulse width control in a Vertical Cavity Surface Emitting Laser (VCSEL ) , and a method for pulse width control in a VCSEL driver .

[0005] BACKGROUND

[0006] In the field of Time-of-Flight ( ToF) applications , pulse width control loops are essential for ensuring the stability of short current pulses that are passed through a diode at a speci fic frequency . These current pulses can have a pulse width that varies from l O OpS to InS and a frequency ranging from 160MHz to 200MHz . A pulse width control loop is required to ensure that the pulse width does not vary across process , voltage , and temperature ( PVT ) variations .

[0007] Traditionally, a 3-pole 1-zero architecture has been used to solve this problem . However, this architecture has several drawbacks , including the need for a large capacitance to produce a zero and stabili ze the design, low area ef ficiency, and the requirement for a single-stage operational transconductance ampli fier ( OTA) with low gain for system stability, which may cause gain error . Additionally, increasing gain may bring the third pole inside the loop bandwidth, further exacerbating the problem .

[0008] In other words , in the prior art a 3-pole 1-Zero architecture is known having a general need for big capacitance to produce a zero and to make the design stable . This setup is not area ef ficient and needs a single stage OTA with low gain for a stable system which may cause gain error . Thereby, an increase in gain will bring the third pole inside the loopbandwidth .

[0009] Therefore , the obj ective of the present invention was to provide an improved Time-of-Flight application, and speci fically having an improved controlling of the pulse width of short current pulses that are passed through a diode at a speci fic frequency . A further obj ective of the present invention is to provide an improved control loop to ensure less variation of the pulse width across process , voltage , and temperature ( PVT ) variations .

[0010] SUMMARY

[0011] The above obj ects of the invention are achieved by an apparatus for pulse width control in a Vertical Cavity Surface Emitting Laser (VCSEL ) , and a method for pulse width control in a VCSEL driver according to the annexed claims .

[0012] Preferred embodiments may be taken from the dependent claims , and, beyond that , from the following description, in particular comprising various embodiments as covered and described in the annexed claims .

[0013] The skilled person will understand that any embodiment described in the following description is covered and comprised by the subj ect matter covered by the annexed claims .

[0014] The embodiments , features and combination of features as described herein in connection with the invention, as well as the combination of features as given in the annexed claims , but also any combination of features as mentioned and described in connection with the embodiments shall be considered as being disclosed herein, at least , however, shall be considered to be derivable by the skilled person . In particular, each feature and each combination of features in the embodiments as described herein may for example be claimed in a di f ferent combination, in particular di f ferent claim category, at least because the skilled person will recogni ze that each and every combination of the features mentioned herein is suitable for contributing to solving the underlying problem .

[0015] Further, each feature and each combination of features in the claims and used in the description below may be used and claimed independently from the respective claimed subj ect matter, independently from claim dependencies and back- references , and independently from the claim category in which the feature is claimed . For example in an arbitrary combination selected from one or more claims , one or more embodiments as set forth herein below and / or from the annexed figures may be envisaged .

[0016] An apparatus for pulse width control in a Vertical Cavity Surface Emitting Laser (VCSEL ) driver according to the present invention is configured to control the pulse width of current pulses in a Time-of-Flight ( ToF) application and comprises two poles and one zero configuring a two-poles , one- zero system . Thereby, the apparatus comprises

[0017] - a high gain ampli fier H_int configured to reduce gain error and stabili ze the complete loop, and

[0018] - a delay cell H_delay, wherein a capacitor Cintis provided in the feedback path of the high gain ampli fier H_int at a first pole of the high gain ampli fier H_int , to stabili ze the system .

[0019] The present inventors have surprisingly found that such Two pole-one zero system according to the present invention, and particularly when compared to the known three pole-one zero system, advantageously provides a higher stability without the need for using big capacitance . It provides furthermore an area ef ficient solution and a reduced gain error . The use of the high gain ampli fier also contributes beneficially to stabili ze the complete loop . All described embodiments of the invention address the drawbacks of the prior art by introducing a two-pole one-zero system instead of the three-pole one-zero system known in the art. Thereby, the system is advantageously stable without the need for a large capacitance, offering a more area-efficient solution. Another significant improvement of the apparatus according to the present invention is the advantageous reduction of gain error through the use of a high gain amplifier, which also ensures the stability of the complete loop. This new architecture differs from the prior art by providing a more efficient and stable solution for pulse width control in Time-of-Flight applications.

[0020] In a further aspect of the present invention, a method for pulse width control in a VCSEL driver is provided.

[0021] The inventive method comprising at least the following steps:

[0022] - providing a high gain amplifier (H_int) configured to reduce gain error and stabilize the complete loop;

[0023] - providing a delay cell (H_delay) ; and

[0024] - providing a capacitor (Cint) in the feedback path of the high gain amplifier (H_int) at a first pole of the high gain amplifier (H_int) , to stabilize the system.

[0025] Thereby, the present invention also provides a novel method for pulse width control in Vertical Cavity Surface Emitting Laser (VCSEL) drivers by employing a two-pole one-zero system that addresses the limitations and drawbacks of the prior art. The invention offers an area-efficient and stable solution without the need for large capacitance, resulting in improved performance and reduced gain error.

[0026] It shall be noted, that the steps given above do not necessarily have to be carried out in the given order. The provided steps may be carried out in any other suitable order .

[0027] However, the order as given above may apply for particular variants of the method .

[0028] It will be immediately acknowledged by a person skilled in the art that a feature , embodiment , ef fect or advantage described herein in connection with the inventive apparatus , particularly the two-pole one- zero system, may also be a feature , embodiment , ef fect or advantage of the inventive method, respectively, and vice versa .

[0029] Thereby, the capacitor in the feedback path of the high gain ampli fier advantageously replaces a large capacitance used in the prior art to stabili ze the system . This advantageously allows for a more compact and ef ficient design . By replacing the large capacitance used in the prior art with a capacitor in the feedback path of the high gain ampli fier, the system can achieve stability while saving signi ficant area . This configuration also simpli fies the system, reducing the complexity and potential for errors , and contributes to the overall performance and ef ficiency of the system .

[0030] Due to reduced space requirements inclusion of additional features or components in the same physical space are made possible . Further the inventive apparatus and / or method may be configured to provide a pulse width of the current pulses varying from l O OpS to InS and / or a frequency of the current pulses varying from 160MHz to 200MHz .

[0031] In an advantageous embodiment of the inventive apparatus or method, the apparatus , particularly the two-pole one- zero system, comprises an Rzeroprovided in series to the capacitor Cmt .

[0032] Having an Rzero provided in series to the capacitor Cint in the two-pole one- zero system is advantageous in generating a zero , capable of nulli fying the impact of a pole from the delay cell (H_delay) . This configuration can improve the stability of the system by counteracting the phase shift introduced by the pole, thereby enhancing the overall performance of the Vertical Cavity Surface Emitting Laser (VCSEL) driver

[0033] In an advantageous embodiment of the inventive apparatus or method, in the apparatus, particularly in the two-pole one- zero system, the delay cell is provided in series to the amplifier H_int, and preferably no capacitor is provided between the delay cell and the amplifier H_int .

[0034] This advantageously allows to reduce the complexity of the system and potentially improve the stability and response time. By directly connecting the delay cell to the amplifier, the signal path is simplified, which can lead to less signal distortion and faster response times. This configuration can also reduce the number of components, potentially leading to cost and space savings.

[0035] In a further advantageous embodiment of the inventive method or apparatus, the capacitor Cint, and preferably Rzero, if present, are configured to generate one zero, capable of nullifying a pole impact of the delay cell.

[0036] The two-pole one-zero system preferably is configured to nullify the effect of a pole coming from a delay cell. This is particularly of advantage in relationto system stability and performance. In control systems, poles can significantly influence the system's stability and transient response. A pole from a delay cell can introduce phase delay or phase shift, which can potentially destabilize the system, especially if it falls within the system's bandwidth.

[0037] By configuring the two-pole one-zero system to nullify this effect, the system can maintain stability even with the presence of the delay cell. This means the system can handle faster response times and higher frequencies without risk of instability . This configuration also allows for greater flexibility in system design, as it can accommodate delay cells that might be necessary for other aspects of system performance. It can lead to improved overall system performance, reliability, and efficiency.

[0038] In a further advantageous embodiment of the inventive method or apparatus, the apparatus, particularly the two-pole one- zero system, is provided as a differential system.

[0039] Providing the two-pole one-zero system implemented in a differential manner offers several advantages. It can significantly improve the system's immunity to common-mode noise, leading to a cleaner, more accurate signal. Additionally, it can provide better signal quality and increased dynamic range, which is particularly beneficial in high-precision applications. Thereby, the term "differential manner" as used herein, preferably means that the system processes two complementary, or opposite, signals simultaneously. In this context, it preferably further refers to the method of operation, where the two-pole one-zero system uses two inputs - a positive and a negative. The system then may advantageously amplify the difference between these two signals, effectively doubling the signal strength while rejecting any common noise that might be present on both signals.

[0040] In a further advantageous embodiment of the inventive method or apparatus, preferably provided as a differential system, the apparatus, particularly the two-pole one-zero system, comprises a further amplifier H_zero_amp, preferably provided in series to the amplifier H_int .

[0041] The advantage of including a further amplifier H_zero_amp, preferably provided in series to the amplifier H_int, in the two-pole one-zero system is that it can enhance the overall gain of the system. This can be particularly beneficial in situations where the signal strength needs to be increased . The further ampli fier H_zero_amp can ampli fy the signal after it has been processed by the first ampli fier H_int , thereby ensuring that the signal is strong enough for subsequent stages of the system . This can lead to improved performance of the Vertical Cavity Surface Emitting Laser (VCSEL ) driver .

[0042] In a further advantageous embodiment of the inventive method or apparatus , preferably provided as a di f ferential system, the apparatus , particularly the two-pole one- zero system, comprises a further capacitor C_int in the feedback path of the high gain ampli fier H_int at a second pole of the high gain ampli fier H_int .

[0043] The advantage of including a further capacitor C_int in the feedback path of the high gain ampli fier H_int at a second pole of the high gain ampli fier H_int , particularly in the two-pole one- zero system, is that it can provide additional stability to the system . This further capacitor C_int can help in controlling the gain and phase characteristics of the system at di f ferent frequencies . It can also help in reducing the ef fects of noise and other disturbances , thereby improving the overall performance and reliability of the Vertical Cavity Surface Emitting Laser (VCSEL ) driver .

[0044] In a further advantageous embodiment of the inventive method or apparatus , the apparatus , particularly the two-pole one- zero system, is provided as a single-ended system .

[0045] Implementing the two-pole one- zero system according to the present invention in a single-ended manner of fers advantages in terms of simplicity and cost-ef fectiveness . Such single- ended system according to the present invention requires fewer components and less complex circuitry than di f ferential systems , leading to lower manufacturing costs . Additionally, the system is easier to design and implement , making the invention a practical choice for certain applications . The term "single-ended" as used herein, preferably refers to a system configuration where the signal is carried on a single conductor with the other terminal grounded. This particularly may be understood best, in contrast to a differential system of the prior art, where the signal is carried on two conductors with equal and opposite voltages. In a single-ended system according to the present invention, the signal preferably is referenced to a fixed ground potential, making the system simpler and less expensive to implement .

[0046] In a further advantageous embodiment of the inventive method or apparatus, preferably provided as a single-ended system, the apparatus, particularly the two-pole one-zero system, comprises a register, capable of generating a zero, and wherein the register is provided in series to the capacitor Cint, preferably in the feedback loop of the amplifier H_int .

[0047] This advantageously provides additional control over the system's response. The register can be used to adjust the value of the zero that is generated, allowing for fine-tuning of the system's behaviour. This can be particularly useful in applications where the system's response needs to be adjusted based on specific requirements or conditions. This configuration can lead to improved flexibility and performance of the Vertical Cavity Surface Emitting Laser (VCSEL) driver.

[0048] In a further advantageous embodiment of the inventive method or apparatus, the apparatus, particularly the two-pole one- zero system, is configured to nullify the effect of a pole coming from the delay cell.

[0049] This advantageously can improve the stability and performance of the system. Poles in a system can introduce phase shifts and can potentially destabilize the system. By configuring the apparatus to nullify the effect of such a pole, the system can maintain its stability and performance even in the presence of the delay cell . This can lead to more reliable and consistent operation of the Vertical Cavity Surface Emitting Laser (VCSEL ) driver .

[0050] In a further advantageous embodiment of the inventive method or apparatus , the high gain ampli fier H_int is configured to have a high gain ( ~ 80dB ) .

[0051] Configuring the high gain ampli fier to have a high gain at very low frequencies provides several advantages .

[0052] Particularly, the Signal-to-Noise Ratio can be improved . This is because the ampli fier can boost the signal strength relative to the noise , making the signal easier to detect and process . Furthermore , the high gain at low frequencies can enhance the sensitivity of the system to small signals . This can be particularly beneficial in applications where the input signal is very weak . Still further, some applications , such as certain types of communication or sensor systems , operate primarily at low frequencies . In these cases , having a high gain at low frequencies can improve the overall performance of the system . Also distortion can be advantageously reduced and overall stability improved .

[0053] In a further advantageous embodiment of the inventive method or apparatus , the apparatus , particularly the two-pole one- zero system, is configured to generate a zero that can be programmed based on the system' s operation frequency .

[0054] Configuring the active network to generate a programmable zero based on the operating frequency enhances system flexibility and stability . It allows the system to adapt to di f ferent frequencies and manage potential destabili zing poles . This leads to optimi zed performance , reduced signal distortion, and a customi zable system response .

[0055] In a further advantageous embodiment of the inventive method or apparatus , the two-pole one- zero system provides a reduced area compared to a three-pole one- zero system, as used in the prior art .

[0056] The advantage of the two-pole one- zero system providing a reduced area compared to a three-pole one- zero system used in the prior art lies in its ef ficiency and cost-ef fectiveness . A reduced area implies a more compact design, which can lead to cost savings in materials and manufacturing . Additionally, a smaller footprint can make the system more suitable for applications where space is at a premium or allow for the

[0057] All described embodiments of the invention address the drawbacks of the prior art by introducing a two-pole one- zero system instead of the three-pole one- zero system, providing several advantages over the prior art . The system is designed to be stable without the need for a large capacitance , of fering a more area-ef ficient solution . This design can cover a large range of pulse widths ( 160pS - InS ) for its inherent stable behavior .

[0058] Another signi ficant improvement of fered by the invention is the reduction of gain error through the use of a high gain ampli fier, which also ensures the stability of the complete loop . This new architecture di f fers from the prior art by providing a more ef ficient and stable solution for pulse width control in Time-of-Flight applications .

[0059] Advantageously, the inventive apparatus , and particularly the inventive two-pole one- zero system, can replace a three-pole one- zero system used in the prior art . This advantageously allows for a more area-ef ficient and stable solution for pulse width control in Time-of-Flight applications . By replacing the three-pole one- zero system with a two-pole one- zero system, the need for a large capacitance to produce a zero and stabili ze the design is eliminated . This results in a more compact and ef ficient system . Additionally, the two- pole one- zero system reduces the risk of gain error associated with the low gain of a single-stage operational transconductance ampli fier ( OTA) used in the three-pole one- zero system . This leads to improved system stability and performance .

[0060] Further advantageously, the inventive apparatus , and particularly the inventive two-pole one- zero system, can be configured to cancel a non-dominant pole generated by a filter with the zero , resulting in a one-pole system .

[0061] This advantageously allows for the creation of a more stable system . By configuring the active network to cancel a nondominant pole generated by a filter with the zero , a one-pole system is achieved . This simpli fies the system and enhances its stability, as a one-pole system is inherently more stable than a system with multiple poles . This configuration also contributes to the area ef ficiency of the system, as it eliminates the need for additional components to manage multiple poles .

[0062] Further advantageously, the inventive apparatus , and particularly the inventive two-pole one- zero system, can be configured to generate a zero by using a capacitor in the feedback path of the high gain ampli fier .

[0063] This advantageously allows for the stabili zation of the system without the need for a large capacitance . By configuring the active network to generate a zero using a capacitor in the feedback path of the high gain ampli fier, the system can achieve stability while saving area . This configuration also contributes to the reduction of gain error, further enhancing the overall performance and ef ficiency of the system .

[0064] In summary, the present invention provides a novel method for pulse width control in Vertical Cavity Surface Emitting Laser (VCSEL ) drivers by employing a two-pole one- zero system that addresses the limitations and drawbacks of the prior art . The invention of fers an area-ef ficient and stable solution without the need for large capacitance , resulting in improved performance and reduced gain error . BRIEF DESCRIPTION OF DRAWINGS

[0065] The present invention will be described in further detail with reference to the drawings from which further features , embodiments and advantages may be taken, and in which :

[0066] Fig . 1 shows a topography of an apparatus having a three pole system for pulse width control in a Vertical Cavity Surface Emitting Laser (VCSEL ) driver according to the prior art ;

[0067] Fig . 2 shows further details of an apparatus having a three pole system for pulse width control in a Vertical Cavity Surface Emitting Laser (VCSEL ) driver according to the prior art ;

[0068] Fig . 3 depicts schematical gain over frequency graphs of the three pole system apparatus according to the prior art ;

[0069] Fig . 4 depicts schematical gain over frequency graphs of the two pole , one zero system apparatus according to the present invention;

[0070] Fig . 5 shows a schematical topography of a first embodiment of the present invention and particularly, a two pole , one zero system apparatus according to the present invention;

[0071] Fig . 6 shows a schematical topography of a second embodiment of the present invention and particularly, of a two pole , one zero system apparatus in a di f ferential architecture according to the present invention;

[0072] Fig . 7 shows a schematical topography of a third embodiment of the present invention and particularly, of a two pole , one zero system apparatus in a di f ferential architecture according to the present invention;

[0073] Fig . 8 shows a schematical topography of a fourth embodiment of the present invention and particularly, of a two pole , one zero system apparatus in a single ended solution architecture according to the present invention;

[0074] Fig . 9 shows a table with test data comparing a three pole system of the prior art ( old design) with a two-pole , one zero apparatus according to the present invention .

[0075] DETAILED DESCRIPTION

[0076] The features of the present invention disclosed in the speci fication, the claims , examples and / or the figures may both separately and in any combination thereof be material for reali zing the invention in various forms thereof . In the embodiments shown in the figures , elements similar or identic in function are designated with like reference signs . It is noted, that the figures may not be true to scale with respect to each other .

[0077] Fig . 1 shows a topography of an apparatus according to the present invention configured in a classical three pole system for pulse width control in a Vertical Cavity Surface Emitting Laser (VCSEL ) driver . As shown The current Ivcsei is passing the diode in an interval as depicted in the pulse-width diagram shown on the left side of the Figure . A person skilled in the art will acknowledge that the pulse widths are relatively small or can may vary, particularly between l O Ops to Ins . A controlled clock is provided . As a main component an ampli fier A is provided . The two currents Iref_pls l and Iref_pls2 are generating basically the pulses of the system . Current Iref_Pls2 thereby is connected to a register R . The register R is programmed to a predetermined value to generate a reference voltage VREF PLS. I f current Iref-pls2 is changed, also the voltage VREF PLSand thus the pulse width of the IVCSEL will vary . Similarly, i f current Iref_pls l , VMEAN PLSwill accordingly vary, too . Turning again to ampli fier A, it can be taken from the Figure that both, VMEAN PLSand VREF PLSare connected to the ampli fier poles . The ampli fier A secures that VMEANpLSequals VREF PLS. Accordingly, depending on the voltage VREF PLS, in average the same voltage is generated as VMEAN PLS - Based on this, a pulse is generated as VPisresulting in IPuise width being equal to the reference voltage. As can be seen from Fig. 2 showing further details of a topology of an apparatus of the prior art configured as a three poles and one zero system. Thereby the following equations apply:

[0078] • 1stPole =1 / (rO* (C1 + C2) ) = wpl

[0079] • 2nd pole = 1 / R2*C2 = wp2

[0080] • 3rd Pole from delay cell with C4 = wp3

[0081] • 1stZero = 1 / R1*C1 = wz2

[0082] • 1stpole~^2ndpole~^lstzero~^3rdpole

[0083] It can be recognized that thus capacitor Cl is relatively big in order to create a zero that is close to the 2ndpole.

[0084] There are several problems found by the present inventors in relation to such setup as shown in Figs. 1 and 2.

[0085] At first, a high gain amplifier A is needed, and in order to stabilize it capacitor Cl has to be very big to generate a zero in order to stabilze the system. As can be taken from Fig. 2, this is due to the network around the first pole. The average value again will be equal.

[0086] As shown on the left side of Fig. 2 a pole relating to R2 and C2 will cause instability of the system. In order to nullify the respective impact, a big capacitor Cl is to be provided and it is kind of blowing up the overall area, resulting in the incapability to increase the gain of this amplifier Gm after a certain level without causing unstability. In general, a very high gain is needed in such system to make sure that the two input voltages Vinp and Vinm, the inputs of these two amplifier, which track each other.

[0087] A skilled person will thus acknowledge that in such setup according to the prior art the gain of this system cannot be increased beyond a certain threshold - otherwise the system will become unstable. Secondly, a rather big capacitor is needed to provide stability as such.

[0088] Turning to Fig. 3 that shows schematical gain over frequency graphs of the three pole system apparatus according to the prior art. Referring to Fig. 2 R2 and C2 are providing H_filter of Fig. 3, while H_amplifier depicts the respective response of amplifier Gm. A pole wpl and a zero, here w=wz, shown in the dottet circle is provided.

[0089] In the first figure (left picture) , the system is stable. The zero generated by the system comes on top of the pole to nullify its effect, maintaining the stability of the system. The delay cell, which also has a pole (w3) , is outside the bandwidth of the system, so it does not affect the stability.

[0090] In the second figure (right picture) , the gain of the amplifier is increased. This causes the pole from the delay cell to move within the bandwidth of the system. As a result, the system becomes unstable. The figures demonstrate that increasing the amplifier gain beyond a certain limit can lead to instability in the system.

[0091] The figures 1 to 3 illustrate the problem that in such prior art 3-pole 1-Zero architecture a big capacitance is needed to produce a zero and to make the design stable. Such system is not very area efficient. A single stage OTA is needed with low gain for a stable system which may cause gain error. However, increasing gain will bring the third pole inside the loop-bandwidth .

[0092] Turning to the solution provided by the present invention a two pole, one zero architecture can advantageously be used instead of said three pole architecture of the prior art. Thereby, the big capacitance of the prior art is no longer needed . According to the present invention an apparatus for pulse width control in a Vertical Cavity Surface Emitting Laser (VCSEL ) driver that is configured to control the pulse width of current pulses in a Time-of-Flight ( ToF) application, and comprises inventively two poles and one zero configuring a two-poles , one- zero system, further comprises a high gain ampli fier H_int configured to reduce gain error and stabili ze the complete loop, and a delay cell H_delay . Thereby, the capacitor Cint is provided in the feedback path of the high gain ampli fier H_int at a first pole of the high gain ampli fier H_int , to stabili ze the system .

[0093] This provides a stable system without using big capacitance and advantageously of fers a more area ef ficient solution compared to the prior art . A high gain ampli fier is used to stabili ze the complete loop . Hence , compared to the prior art an apparatus according to the present invention comprises only two poles and one zero instead of three pole and one zero . Thereby, a non-dominant pole is cancelled by the zero to make the system stable ( one-pole ) . It is obvious to the skilled person that a zero is required to nulli fy the impact of the pole generated by the filter . I f the zero is generated from the active network, it will save a lot of area .

[0094] In Fig . 4 a gain over frequency graph of the two pole , one zero system apparatus according to the present invention is depicted showing the trans fer characteristics of the inventive solution . The figure demonstrates that by increasing the gain of the ampli fier, the position of the zero also shi fts , but it continues to cancel out the pole from the delay cell , ensuring the system remains stable .

[0095] In Fig . 5 the respective schematical topography of a first embodiment of the present invention and particularly, a two pole , one zero system apparatus according to the present invention is shown .

[0096] Between the poles a saw tooth kind of waveform of Vref is schematically depicted having an average value equal to Vref connected to the ampli fier . As can be immediately seen from Fig. 5, the two-pole one-zero system, comprises an Rzero provided in series to the capacitor Cint. Thereby, capacitor Cint is provided in the feedback path of the high gain amplifier H_int (egrator) at a first pole of the high gain amplifier H_int, to stabilize the system.

[0097] In other words, in the prior art, an integrating capacitor Cint no mechanism is in place to nullify the pole coming from the delay cell, which can lead to instability in the system. As shown in Fig. 5, in the present invention, the integrating capacitor Cint has been moved to a new position, where it serves two purposes. First, in conjunction with the zero register Rzero, it stabilizes the amplifier. Second, it eliminates the need for the large Czero capacitor that was previously required to nullify the effect of the pole. Fig. 5 also shows that there is no capacitor between the amplifier and the delay cell in the new configuration. The amplifier, now acting as an integrator (H_integrator ) , can have a very high gain at low frequencies because it operates as a one- pole system. The integrating capacitor Cint and the zero register Rzero generate a zero that nullifies the impact of the pole from the delay cell. The graph below the figure shows the response of the H_integrator . The response starts high, then falls down to a zero, which is generated by the Cint and Rzero. This zero can be programmed to cancel out the pole from the delay cell, resulting in an overall response that resembles a one-pole system.

[0098] Overall, Figure 6 provides a visual representation of how the invention can be implemented in a differential architecture, highlighting the roles of various components in ensuring system stability and performance . As can be seen from Fig. 6 that presents a schematic topography of a second embodiment of the invention, specifically a two-pole, one-zero system apparatus in a differential architecture, the present invention can be used in a differential design. Here, the integrator part, denoted as H_int, is shown. The capacitor C_int is connected directly in the feedback loop of the amplifier, which is a key part of this design. Following this, another amplifier, denoted as H_zero_amp, is added. This amplifier plays a crucial role in generating a zero. The components Rzero and Czero are positioned on top of the delay generating network. These components can be programmed based on the operating frequency, providing flexibility in system operation .

[0099] The pole that arises from the delay generating network is effectively managed to ensure overall system stability. This is achieved by the strategic placement and programming of the components Rzero and Czero.

[0100] Figure 7 presents a schematic topography of a third embodiment of the invention, specifically a two-pole, one- zero system apparatus in a differential architecture.

[0101] In this design, a register, shown in the dotted line, is introduced. This register is capable of generating a zero, which contributes to the overall stability of the system.

[0102] The figure shows that the register can be placed in series with the capacitor. This configuration also generates a zero, similar to the structure H_zero_amp shown in the previous figure .

[0103] This figure demonstrates the flexibility of the system design, where different components (like a register or the H_zero_amp structure) can be used to generate a zero and ensure system stability. The figure highlights the differential implementation of the system, showing how the invention can be adapted to different configurations.

[0104] Figure 8 presents a schematic topography of a fourth embodiment of the invention, specifically a two-pole, one- zero system apparatus in a single-ended solution architecture. This figure 8 represents a single-ended solution. The figure provides a visual representation of how the two-pole, one-zero system apparatus can be implemented in a single-ended solution architecture , demonstrating the versatility of the invention in di f ferent configurations .

[0105] Figure 9 presents a table with test data comparing a three- pole system of the prior art ( old design) with a two-pole , one- zero apparatus according to the present invention (new design) . The table provides a clear comparison between the present invention and the prior art . It shows that the stability, which is largely determined by the phase , is consistently around 80- 90 ° in the apparatus according to the present invention . In contrast , the phase in the apparatus of the prior art is marginal , indicating less stability . The table also shows that the gain in the apparatus according to the present invention can be increased twofold compared to the prior art . This demonstrates the improved performance of the apparatus according to the present invention . The figure 9 concludes that the present invention of fers signi ficant advantages over the prior art design, including the elimination of the need for the MOS , reduced area, and increased stability .

[0106] It shall be noted that the above described embodiments in the figures may relate to preferred embodiments , while all elements and features described in connection with embodiments may be used, as far as appropriate , in combination with any other embodiment and feature as discussed herein, in particular related to any other embodiment discussed further above .

Claims

CLAIMS1. An apparatus for pulse width control in a Vertical Cavity Surface Emitting Laser (VCSEL) driver, configured to control the pulse width of current pulses in a Time-of-Flight (ToF) application, and comprising two poles and one zero configuring a two- poles, one-zero system, and wherein the apparatus comprises- a high gain amplifier H_int configured to reduce gain error and stabilize the complete loop, and- a delay cell H_delay, wherein a capacitor Cintis provided in the feedback path of the high gain amplifier H_int at a first pole of the high gain amplifier H_int, to stabilize the system.

2. The apparatus according to claim 1, wherein the apparatus, particularly the two-pole one-zero system, comprises an Rzeroprovided in series to the capacitor Cmt.

3. The apparatus according to claim 1 or 2, wherein in the apparatus, particularly in the two-pole one-zero system, the delay cell is provided in series to the amplifier H_int, and preferably no capacitor is provided between the delay cell and the amplifier H_int .

4. The apparatus according to any one of claims 1 to 3, wherein the capacitor Cint, and preferably Rzero, ifpresent, are configured to generate one zero, capable of nullifying a pole impact of the delay cell.

5. The apparatus according to any one of claims 1 to 4, wherein the apparatus, particularly the two-pole one- zero system, is provided as a differential system.

6. The apparatus according to any one of claims 1 to 5, preferably according to claim 5, wherein the apparatus, particularly the two-pole one-zero system, comprises a further amplifier H_zero_amp, preferably provided in series to the amplifier H_int .

7. The apparatus according to any one of claims 1 to 6, preferably according to claim 5 or 6, wherein the apparatus, particularly the two-pole one-zero system, comprises a further capacitor C_int in the feedback path of the high gain amplifier H_int at a second pole of the high gain amplifier H_int .

8. The apparatus according to any one of claims 1 to 7, wherein the apparatus, particularly the two-pole one- zero system, is provided as a a single-ended system.

9. The apparatus according to any one of claims 1 to 8, preferably according to claim 8, wherein the apparatus, particularly the two-pole one-zero system, comprises a register, capable of generating a zero, and wherein the register is provided in series to the capacitor Cint, preferably in the feedback loop of the amplifier H_int .

10. The apparatus according to any one of claims 1 to 9, wherein the apparatus, particularly the two-pole one- zero system, is configured to nullify the effect of a pole coming from the delay cell.

11. The apparatus according to any one of claims 1 to 10, wherein the high gain amplifier H_int is configured to have a high gain (80dB) .

12. The apparatus according to any one of claims 1 to 11, wherein the apparatus, particularly the two-pole one- zero system, is configured to generate a zero that can be programmed based on the system' s operation frequency .

13. A method for pulse width control in a Vertical Cavity Surface Emitting Laser (VCSEL) driver, the method comprising :- providing a high gain amplifier (H_int) configured to reduce gain error and stabilize the complete loop;- providing a delay cell (H_delay) ; and- providing a capacitor (Cint) in the feedback path of the high gain amplifier (H_int) at a first pole of the high gain amplifier (H_int) , to stabilize the system.

14. The method of claim 13, further comprising providing an Rzero in series to the capacitor (Cint) .

15. The method of claim 13 or 14, wherein the delay cell (H_delay) is provided in series to the amplifier (H_int) , and no capacitor is provided between the delay cell (H_delay) and the amplifier (H_int) .

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