Semiconductor device

Abstract

A semiconductor device according to one embodiment of the present disclosure has a substrate and first and second semiconductor chips. The first and the second semiconductor chips each have one or more function blocks and one or more block power source control circuits. Each of the one or more block power source control circuits is electrically connected to at least one function block among the one or more function blocks, and controls supply of the power source voltage to the at least one function block. The second semiconductor chip further has an arbitration circuit for outputting, on the basis of a turning-on request signal which is outputted from at least one block power source control circuit among the plurality of block power source control circuits included in the first and the second semiconductor chips and which is for requesting to start supplying the power source voltage for at least one function block to be controlled by the at least one block power source control circuit, and also on the basis of a score based on parasitic capacitance, a permission signal that permits the at least one block power source control circuit, which outputted the turning-on request signal, to start supplying the power source voltage.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, there is a technology for mounting multiple semiconductor chips on a single substrate or package to manufacture chiplet products or multi-chip package products. In such products incorporating multiple semiconductor chips, when controlling the power supply voltage of each semiconductor chip, it is necessary to consider the power supply status to other semiconductor chips. For example, in multiple semiconductor chips sharing a power domain, if power supply voltage is simultaneously supplied to multiple functional blocks, there is a risk of malfunction or failure due to inrush current.

[0003] US Patent No. 11467655 JP 2023-075588 A

[0004] However, there is room for improvement in the timing control of power supply voltage supply across multiple semiconductor chips, such as the fact that a power supply control circuit that controls the power supply voltage supply to a certain functional block cannot grasp the timing of power supply voltage supply to other functional blocks by other power supply voltage supply circuits.

[0005] An object of the present disclosure is to appropriately control the timing of supplying power supply voltages across multiple semiconductor chips.

[0006] A semiconductor device according to an embodiment of the present disclosure includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on the substrate. Each of the first semiconductor chip and the second semiconductor chip includes at least one functional block and at least one block power supply control circuit. Each of the at least one block power supply control circuit is electrically connected to one or more of the at least one functional block and controls the supply of a power supply voltage to each of the one or more functional blocks. The second semiconductor chip further includes an arbitration circuit. The arbitration circuit outputs an on-request signal from one or more of the block power supply control circuits included in the first semiconductor chip and the second semiconductor chip, the on-request signal requesting the start of supply of a power supply voltage for the one or more functional blocks to be controlled, based on a score based on parasitic capacitance. The on-request signal is output from each of the one or more block power supply control circuits to request the start of supply of a power supply voltage for the one or more functional blocks to be controlled. The score is based on parasitic capacitance.

[0007] According to an embodiment of the present disclosure, it is possible to appropriately control the timing of supplying power supply voltages across a plurality of semiconductor chips.

[0008] FIG. 1 is a diagram illustrating an example of the configuration of a semiconductor device according to a first embodiment. FIG. 2 is a diagram illustrating an example of the configuration of an arbitration circuit of FIG. 1. FIG. 3 is a flowchart illustrating an example of the operation flow of the arbitration circuit of FIG. 2. FIG. 4 is a flowchart illustrating an example of the flow of an enqueue entry operation of FIG. 3. FIG. 5 is a flowchart illustrating an example of the flow of a request storage operation of FIG. 3. FIG. 6 is a flowchart illustrating an example of the flow of a simultaneous permission determination operation of FIG. 3. FIG. 7 is a diagram illustrating an example of the configuration of a semiconductor device according to a second embodiment. FIG. 8 is a diagram illustrating an example of the configuration of a semiconductor device according to a third embodiment. FIG. 9 is a diagram illustrating an example of the configuration of a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating an example of the configuration of a semiconductor device according to a fifth embodiment. FIG. 11 is a diagram illustrating an example of the configuration of a semiconductor device according to a sixth embodiment. FIG. 12 is a diagram illustrating an example of the configuration of a semiconductor device according to a seventh embodiment. FIG. 13 is a diagram illustrating an example of the configuration of a semiconductor device according to an eighth embodiment.

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor device will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0010] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals, and redundant explanations are provided only when necessary. The embodiments can be appropriately combined with other embodiments, modifications, and / or conventional techniques.

[0011] In the description of the present disclosure, components having the same or substantially the same functions may be distinguished by adding an alphanumeric character to the end of the reference symbol. Alternatively, when multiple components having the same or substantially the same functions are not distinguished, they may be collectively described by omitting the alphanumeric character at the end of the reference symbol.

[0012] In the description of the present disclosure, "determining whether it is A" may mean "determining that it is A," "determining that it is not A," or "determining whether it is A or not."

[0013] In each embodiment of the present disclosure, a semiconductor device called a SoC (System on a Chip) or SiP (System in Package) in which multiple semiconductor chips are mounted on a single substrate or package will be exemplified as the semiconductor device.

[0014] 1 is a diagram showing an example of the configuration of a semiconductor device 1a according to a first embodiment. As shown in FIG. 1, the semiconductor device 1a includes a power management IC (Integrated Circuit) 3 and a plurality of semiconductor chips 5.

[0015] The power management IC 3 and the multiple semiconductor chips 5 are provided on a substrate 2. The substrate 2 is formed of, for example, silicon or resin. The substrate 2 is, for example, a Si interposer substrate, but various circuit boards for semiconductor devices, such as other printed circuit boards, can be used as appropriate. The power management IC 3 is a composite power circuit that generates a power supply voltage to be supplied to each of the multiple semiconductor chips 5. A wiring pattern that constitutes a power domain 4 is formed on the substrate 2. The power domain 4 is a group of power supplies to which power is supplied from the power management IC 3.

[0016] 1 illustrates semiconductor chips 5a and 5b as examples of multiple semiconductor chips 5. The semiconductor chips 5a and 5b belong to a common power domain 4 and are each electrically connected to a power management IC 3. The semiconductor chips 5a and 5b have circuit groups 6a and 6b, respectively. Each of the circuit groups 6a and 6b has at least one switch 13, at least one function block 15, and at least one block power control circuit 17. The semiconductor chip 5a also has an arbitration circuit 19. Here, the semiconductor chip 5a is an example of a second semiconductor chip arranged on a substrate. The semiconductor chip 5b is an example of a first semiconductor chip arranged on a substrate.

[0017] Each of the at least one block power supply control circuits 17 is electrically connected to an arbitration circuit 19. In the example of Fig. 1, each block power supply control circuit 17 of the semiconductor chip 5a is electrically connected to the arbitration circuit 19 inside the same semiconductor chip 5a. Also, each block power supply control circuit 17 of the semiconductor chip 5b is electrically connected to the arbitration circuit 19 outside the semiconductor chip 5b, i.e., the arbitration circuit 19 of the semiconductor chip 5a.

[0018] Each of the at least one block power supply control circuit 17 is provided in the always-on area 9a, 9b which is always supplied with a power supply voltage from the power supply domain 4. Each of the at least one block power supply control circuit 17 is electrically connected to at least one functional block 15 in the same semiconductor chip 5. Each of the at least one block power supply control circuit 17 controls the supply of a power supply voltage from the power management IC 3 for the corresponding at least one functional block 15.

[0019] Specifically, for each of at least one connected functional block 15, each block power supply control circuit 17 outputs a power supply voltage ON request signal and a score to the arbitration circuit 19 based on the operating state of that functional block 15. Furthermore, each block power supply control circuit 17 controls the ON / OFF of the power supply voltage to that functional block 15 and the supply sequence of that power supply voltage based on the power supply voltage ON permission signal from the arbitration circuit 19. The score will be described later.

[0020] Note that, although the present disclosure illustrates an example in which a transition from a power-off state to an on state is controlled for each of at least one functional block 15, the present disclosure is not limited to this. For example, the present disclosure may be applied to a case in which a transition of an operation mode for each of at least one functional block 15 is controlled from a first operation mode to a second operation mode having a higher operating voltage (or operating frequency) than that of the first operation mode, or to a combination of these.

[0021] Each of the at least one functional block 15 is electrically connected to a corresponding switch 13. Specifically, each of the at least one functional block 15 is connected to the power supply domain 4 via the corresponding switch 13. Each of the at least one functional block 15 is at least one processor, and is driven using a power supply voltage from the power management IC 3.

[0022] As an example, each of the at least one functional block 15 is a CPU (Central Processing Unit) core, but may be another processor. Each of the at least one functional block 15 may be a processor that realizes a predetermined function by executing a program loaded from a ROM (internal memory) or the like to a RAM (internal memory), or may be a processor constructed as a dedicated circuit to realize a predetermined function. Each circuit group 6 may be provided with two or more functional blocks 15 of two or more types. The functions of the two or more functional blocks 15 may be the same or different.

[0023] Each of the at least one switch 13 is controlled by a corresponding block power control circuit 17 to switch between conduction and communication between the corresponding functional block 15 and the power management IC 3 (power domain 4).

[0024] 1 illustrates, for each semiconductor chip 5, three block power supply control circuits 17 that control the supply of power supply voltage to one functional block 15, and one block power supply control circuit 17 that controls the supply of power supply voltage to each of two functional blocks 15. The number of block power supply control circuits 17 in each semiconductor chip 5 is arbitrary and may be designed as appropriate. The number of functional blocks 15 to which one block power supply control circuit 17 controls the supply of power supply voltage is arbitrary and may be designed as appropriate. The numbers of functional blocks 15 and block power supply control circuits 17 may be the same or different among two or more semiconductor chips 5.

[0025] The arbitration circuit 19 is provided in the always-on region 9 a. The arbitration circuit 19 has an internal register. The arbitration circuit 19 outputs a power supply voltage on permission signal to each block power supply control circuit 17 based on the threshold value stored in the internal register and the power supply voltage on request signal and score received from each block power supply control circuit 17.

[0026] Here, the "score" is a value based on the parasitic capacitance of the functional block 15 receiving power supply and the resistance value of the switch 13 connected to the functional block 15. The score of each functional block 15 is, for example, predetermined and stored in the internal memory of each functional block 15 or the block power supply control circuit 17.

[0027] As an example, the score value may be designed so that the response time when the switch 13 is turned on, i.e., the time required to reach a steady state, is a time constant that satisfies the required specifications. For example, this time constant "τ" is expressed as "τ = CR," where "C" is the capacitance value of the parasitic capacitance of the functional block 15 and "R" is the resistance value of the corresponding switch 13. In the transient state from when the switch 13 is turned on until the parasitic capacitance of the functional block 15 reaches a steady state, the inrush current is maximized at the point where the change per unit time in the time series of the potential "V" (dV / dt) is maximized. Therefore, the score value can be calculated by multiplying the maximum "dV / dt" in the transient state by "1 / R," i.e., the value of "dI / dt." This score value is a circuit-specific value that depends on the operating frequency, operating voltage, circuit size, and the like.

[0028] The "threshold" is a value based on the amount of drop in power supply voltage (or power supply current) that will not cause malfunction of each semiconductor chip 5 and the allowable current value of the power supply management IC 3. This threshold is, for example, predetermined for each power supply management IC 3 and semiconductor chip 5 and stored in an internal register (memory) of the arbitration circuit 19.

[0029] As an example, dynamic voltage drop (DVD) occurs in proportion to the amount of rush current. Therefore, the threshold value may be expressed as "Min(X, Y)" where "X" is the dynamic voltage drop amount (≒ rush current amount) within a range that does not cause malfunction and is specified for each process (sign-off condition), and "Y" is the allowable current value (allowable current amount) specified for the power management IC 3. Furthermore, the threshold value for multiple semiconductor chips 5 sharing the power domain 4 may be expressed as "Min(X-A, X-B, Y)" where "X" is the dynamic voltage drop amount of semiconductor chip "A" and semiconductor chip "B," respectively.

[0030] The arbitration circuit 19 compares the sum of the scores (total score) of at least one functional block 15 for which an on-request has been made with a threshold. If the total score is equal to or less than the threshold, the arbitration circuit 19 grants all of the received on-requests. On the other hand, if the total score is greater than the threshold, the arbitration circuit 19 repeats the process of granting on-requests with a predetermined high priority within the range where the total score falls within the threshold until the total score of the received on-requests falls below the threshold.

[0031] Fig. 2 is a diagram showing an example of the configuration of the arbitration circuit 19 shown in Fig. 1. As shown in Fig. 2, the arbitration circuit 19 includes a request receiving circuit 191, a request storage memory 193, a simultaneous permission determination circuit 195, and a simultaneous permission sending circuit 197.

[0032] The request receiving circuit 191 performs an enqueue entry operation. For example, the request receiving circuit 191 sequentially receives turn-on requests and scores for at least one functional block 15 of the semiconductor chips 5a and 5b from at least one block power control circuit 17 of the semiconductor chips 5a and 5b, and stores these requests and scores in the enqueue entry 201. As shown in FIG. 2 , the enqueue entry 201 has an area for each of at least one functional block 15 to be controlled.

[0033] The request acceptance circuit 191 also performs a request storage operation. For example, the request acceptance circuit 191 stores the data stored in the enqueue entry 201 in the request storage memory 193 as enqueue data 203, for example, at a predetermined cycle. The request storage memory 193 is, for example, a FIFO (First In, First Out) memory. As shown in FIG. 2 , the enqueue data 203 has an area for each of at least one function block 15 to be controlled.

[0034] Note that the priority of power supply to the functional blocks 15 may be adjusted by determining the storage location in the request storage memory 193 based on a predetermined priority. In other words, the calculation of the total score, which will be described later, may be performed based on the priority set for each of the multiple functional blocks 15 of the multiple semiconductor chips 5. This adjustment may be performed by setting the storage location in the enqueue entry 201 and the enqueue data 203, or by setting the start position for reading (searching) from the enqueue data 203 in the simultaneous permission determination, which will be described later, or by a combination of these.

[0035] The simultaneous permission determination circuit 195 performs a simultaneous permission determination operation. For example, the simultaneous permission determination circuit 195 determines whether to supply power to each functional block 15 in response to an on-request for at least one functional block 15 in the semiconductor chips 5a and 5b, which is sequentially received from at least one block power control circuit 17 in the semiconductor chips 5a and 5b. Specifically, the simultaneous permission determination circuit 195 calculates a total score (a sum of the scores) of at least one functional block 15 for which an on-request has been made during a predetermined period, based on the on-requests and scores stored in the request storage memory 193. The simultaneous permission determination circuit 195 also determines whether to supply power to the functional block 15 for which an on-request has been made, based on the comparison result between the total score and a threshold value. The simultaneous permission determination circuit 195 then stores the determination result in the simultaneous permission flag 205. As shown in FIG. 2 , the simultaneous permission flag 205 has an area for each of at least one functional block 15 to be controlled.

[0036] The simultaneous permission sending circuit 197 performs a simultaneous permission sending operation. For example, the simultaneous permission sending circuit 197 refers to the simultaneous permission flag 205 and sends a permission for at least one functional block 15 that has been permitted to receive power supply by the simultaneous permission determination circuit 195 to at least one block power control circuit 17 of the semiconductor chips 5 a and 5 b.

[0037] The simultaneous permission determination circuit 195 repeatedly permits power supply starting from the highest priority on-request if a priority is set, or in the order of readout if a priority is not set, within the range in which the total score does not exceed the threshold. At this time, the simultaneous permission determination circuit 195 stores the determination result in the simultaneous permission flag 205 each time it determines whether or not to supply power, and supplies a startup notification to the simultaneous permission transmission circuit 197. Furthermore, each time the simultaneous permission transmission circuit 197 receives a startup notification from the simultaneous permission determination circuit 195, the simultaneous permission transmission circuit 197 refers to the simultaneous permission flag 205 in response to the startup notification and transmits permission.

[0038] Next, the flow of control processing executed by the semiconductor device 1a configured as above will be described.

[0039] 3 is a flowchart showing an example of the operation flow of the arbitration circuit 19 according to the embodiment. In the semiconductor device 1a, it is assumed that each of the plurality of block power supply control circuits 17 of the semiconductor chips 5a and 5b outputs an on-request and a score for at least one functional block 15 at any time and at any desired timing.

[0040] The arbitration circuit 19 performs an enqueue entry operation (S101). Fig. 4 is a flowchart showing an example of the flow of the enqueue entry operation of Fig. 3. The arbitration circuit 19 sequentially stores and holds the on-requests and scores for at least one functional block 15 received sequentially from at least one block power control circuit 17, for example, in one cycle, in the corresponding areas of the enqueue entry 201 (S201).

[0041] The arbitration circuit 19 performs a request storage operation (S102). FIG. 5 is a flowchart showing an example of the flow of the request storage operation of FIG. 3. The arbitration circuit 19 determines whether at least one valid ON request exists in the enqueue entry 201, for example, in any cycle period equal to or greater than one cycle period (S301). If at least one valid ON request exists in the enqueue entry 201 (S301: Yes), the arbitration circuit 19 stores the data stored in the enqueue entry 201 as enqueue data 203 in the request storage memory 193 (S302). If at least one valid ON request does not exist in the enqueue entry 201 (S301: No), or after the processing of S302, the request storage operation for that time ends.

[0042] The arbitration circuit 19 performs a simultaneous permission determination operation (S103). Fig. 6 is a flowchart showing an example of the flow of the simultaneous permission determination operation of Fig. 3 .

[0043] The arbitration circuit 19 determines whether the request storage memory 193 is empty, i.e., no enqueue data 203 is stored therein (S401). If the request storage memory 193 is empty (S401: Yes), the simultaneous permission determination operation ends, and the process returns to S401. On the other hand, if the request storage memory 193 is not empty, i.e., if the enqueue data 203 is stored therein (S401: No), the arbitration circuit 19 initializes the total score and the simultaneous permission flag 205 (S402), and then scans the request storage memory 193 in an arbitrary order, and permits power supply starting from the order in which the request was stored or the highest priority, as long as the total score does not exceed the threshold, until the total score of the received power-on requests becomes equal to or less than the threshold (S403 to S408).

[0044] Specifically, the arbitration circuit 19 refers to the request storage memory 193, and if the flag valid request [i] of the on request in the scanning area "i" of the enqueue data 203 is "1" (S403: Yes), it determines whether the total score obtained by adding the score [i] of the scanning area "i" to the current total score is below a threshold value (S404).

[0045] If the total score is greater than the threshold value (S404: No), the arbitration circuit 19 simultaneously asserts permission [*] in the simultaneous permission flag 205 at that time, where the simultaneous permission flag [* (* is arbitrary)] is "1", and sends it to the corresponding block power supply control circuit 17 (S405). After assertion, the arbitration circuit 19 initializes the total score and the simultaneous permission flag 205 (S406).

[0046] If the total score is below the threshold (S404: Yes), or after assertion and initialization, the arbitration circuit 19 adds the score [i] to update the total score, and also sets the simultaneous permission flag 205 of the scanning area "i", i.e., the simultaneous permission flag [i], to "1" (S407).

[0047] If the on-request flag valid request [i] is not "1" (S403: No), or after processing S407, the arbitration circuit 19 updates "i" indicating the scanning area (S408) and performs processing for the next scanning area "i+1" (or scanning area "i-1").

[0048] Thereafter, the arbitration circuit 19 determines whether there are any areas in the simultaneous permission flag 205 at that time where the simultaneous permission flag [*] is "1" (S409).

[0049] If there is an area where the simultaneous permission flag [*] is "1" (S409: No), the arbitration circuit 19 simultaneously asserts the permission [*] of the simultaneous permission flag [*] "1" and sends it to the corresponding block power supply control circuit 17 (S410).

[0050] If there is no area where the simultaneous permission flag [*] is "1" (S409: Yes), or after the processing of S410, the arbitration circuit 19 outputs (discharges) the enqueue data 203 to be processed this time from the request storage memory 193 (S411). After that, the simultaneous permission determination operation for that time ends, and the process returns to the processing of S401.

[0051] As described above, the semiconductor device 1a according to this embodiment has an arbitration circuit 19 that arbitrates on-request signals from each of the multiple block power supply control circuits 17 across the multiple semiconductor chips 5. Specifically, in the semiconductor device 1 according to this embodiment, the arbitration circuit 19 outputs a permission signal that permits the start of supply of power supply voltage to one or more block power supply control circuits 17 that have output an on-request signal, based on an on-request signal that requests the start of supply of power supply voltage for one or more functional blocks 15 to be controlled, output from each of the one or more block power supply control circuits 17 among the multiple block power supply control circuits 17 included in the semiconductor chips 5a and 5b, and a score based on parasitic capacitance.

[0052] According to this configuration, when an ON request is made to simultaneously supply power supply voltage to multiple functional blocks 15 in multiple semiconductor chips 5a and 5b, the timing of supplying power supply voltage to the multiple semiconductor chips 5 can be controlled based on the scores, thereby suppressing a drop in power supply voltage and the resulting malfunction.

[0053] Second Embodiment A semiconductor device 1 according to a second embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1a according to the first embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. FIG. 7 is a diagram showing an example of the configuration of a semiconductor device 1b according to the second embodiment. The semiconductor device 1b according to the second embodiment has multiple power domains 4. FIG. 7 illustrates power domains 4a and 4b as examples of the multiple power domains 4.

[0054] The power supply domains 4a and 4b are power supply domains with different power supply voltages. Here, the power supply domain 4a is an example of a first power supply voltage domain that operates at a first power supply voltage. The power supply domain 4b is an example of a second power supply voltage domain that operates at a second power supply voltage different from the first power supply voltage.

[0055] 7 has semiconductor chips 5a and 5b as the plurality of semiconductor chips 5. The semiconductor chips 5a and 5b belong to two power supply domains 4a and 4b, and are electrically connected to the power supply management IC 3, respectively.

[0056] The semiconductor chip 5a includes circuit groups 6a and 6d, which are connected to the power supply domains 4a and 4b, respectively. The semiconductor chip 5b includes circuit groups 6b and 6e, which are connected to the power supply domains 4a and 4b, respectively.

[0057] Each of the circuit groups 6 a , 6 b , 6 d , and 6 e includes at least one switch 13 , at least one function block 15 , and at least one block power supply control circuit 17 .

[0058] In circuit groups 6a and 6b, at least one block power supply control circuit 17 is provided in always-on regions 9a and 9b that are constantly supplied with power supply voltage from power domain 4a. In circuit groups 6d and 6e, at least one block power supply control circuit 17 is provided in always-on regions 9d and 9e that are constantly supplied with power supply voltage from power domain 4b.

[0059] 7 includes arbitration circuits 19a and 19d as the arbitration circuits 19 for each power domain 4. The semiconductor device 1b of FIG.

[0060] The arbitration circuit 19a is provided in the always-on region 9a. The arbitration circuit 19a outputs a power supply voltage on permission signal to each block power supply control circuit 17 of the circuit groups 6a and 6b based on a threshold value stored in an internal register and the power supply voltage on request signal and score received from each block power supply control circuit 17 of the circuit groups 6a and 6b. The arbitration circuit 19d is provided in the always-on region 9d. The arbitration circuit 19d outputs a power supply voltage on permission signal to each block power supply control circuit 17 of the circuit groups 6d and 6e based on a threshold value stored in an internal register and the power supply voltage on request signal and score received from each block power supply control circuit 17 of the circuit groups 6d and 6e.

[0061] In this way, the semiconductor device 1 according to this embodiment has an arbitration circuit 19 for each system of the power supply domain 4. This configuration can accommodate cases where power supply domains 4 a and 4 b with different power supply voltages are provided, or where it is desired to suppress fluctuations in the power supply voltage.

[0062] Third Embodiment A semiconductor device 1 according to a third embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1a according to the first embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. FIG. 8 is a diagram showing an example of the configuration of a semiconductor device 1c according to the third embodiment. The semiconductor device 1c according to the third embodiment further includes at least one clock control circuit 21. Each of the at least one clock control circuit 21 includes a frequency control circuit configured to be able to change the frequency.

[0063] The circuit groups 7a and 7b of the semiconductor device 1c have a configuration in which the circuit groups 6a and 6b according to the first embodiment are further provided with at least one clock control circuit 21. Specifically, each of the at least one clock control circuit 21 is electrically connected between the functional block 15 and the block power supply control circuit 17, and outputs a clock signal CK to the connected functional block 15.

[0064] In the semiconductor device 1c, each of the at least one block power supply control circuits controls not only the connected functional block 15 but also the connected clock control circuit 21. After the supply of power supply voltage starts, each of the at least one block power supply control circuit outputs a clock control signal that controls the connected clock control circuit 21 based on the operating state of the connected functional block 15. Specifically, each of the at least one block power supply control circuit controls the connected clock control circuit 21 to control the on / off of the input of the clock signal CK to the controlled functional block 15 and the frequency of the input clock signal CK.

[0065] According to this configuration, after the supply of power supply voltage begins, the on / off and frequency of the clock signal CK can be controlled based on the operating state of the connected functional block 15, thereby reducing the power consumption of the functional block 15 to be controlled.

[0066] (Modification of Third Embodiment) The configuration according to this embodiment can be appropriately combined with at least one of the semiconductor device 1 according to each of the above-described embodiments and modifications.

[0067] For example, in the configuration of a semiconductor device 1 b in which an arbitration circuit 19 is provided for each power domain 4 , a clock control circuit 21 may be provided between the functional block 15 and the block power control circuit 17 .

[0068] Fourth Embodiment A semiconductor device 1 according to a fourth embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1a according to the first embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. FIG. 9 is a diagram showing an example of the configuration of a semiconductor device 1d according to the fourth embodiment. The semiconductor device 1d according to the fourth embodiment has a plurality of serial / parallel conversion circuits 23. FIG. 9 illustrates serial / parallel conversion circuits 23a and 23b as the plurality of serial / parallel conversion circuits 23.

[0069] The semiconductor device 1d of FIG. 9 includes a serial / parallel conversion circuit 23 in each of a plurality of semiconductor chips 5. The semiconductor device 1d of FIG. 9 includes semiconductor chips 5a and 5b as the plurality of semiconductor chips 5. The serial / parallel conversion circuit 23a is provided in the always-on region 9a of the semiconductor chip 5a and is electrically connected to the arbitration circuit 19 via a signal line for parallel communication. The serial / parallel conversion circuit 23b is provided in the always-on region 9b of the semiconductor chip 5b and is electrically connected to at least one block power supply control circuit 17 of the circuit group 6b via a signal line for parallel communication. The serial / parallel conversion circuits 23a and 23b are electrically connected to each other via a signal line for serial communication. Here, the serial / parallel conversion circuit 23a is an example of a second serial / parallel conversion circuit. The serial / parallel conversion circuit 23b is an example of a first serial / parallel conversion circuit.

[0070] The serial / parallel conversion circuit 23b provided in the semiconductor chip 5b converts into serial signals the on-request signals and scores output from at least one of the block power supply control circuits 17. The serial / parallel conversion circuit 23b provided in the semiconductor chip 5b also outputs the converted serial signals to the semiconductor chip 5a.

[0071] The serial / parallel conversion circuit 23a provided in the semiconductor chip 5a converts the serial signals of the on-request signal and the score from the serial / parallel conversion circuit 23b provided in the semiconductor chip 5b into parallel signals. The serial / parallel conversion circuit 23a provided in the semiconductor chip 5a outputs each of the converted parallel signals to the arbitration circuit 19. The serial / parallel conversion circuit 23a provided in the semiconductor chip 5a converts the enable signal (parallel signal) from the arbitration circuit 19 into a serial signal. The serial / parallel conversion circuit 23a provided in the semiconductor chip 5a outputs the converted serial signal of the enable signal to the serial / parallel conversion circuit 23b provided in the semiconductor chip 5b.

[0072] The serial / parallel conversion circuit 23b provided in the semiconductor chip 5b converts the serial signal of the enable signal from the serial / parallel conversion circuit 23a provided in the semiconductor chip 5a into a parallel signal, and outputs each of the converted parallel signals to at least one block power supply control circuit 17 that output the on-request signal.

[0073] In this way, the semiconductor device 1 according to this embodiment uses serial signals for communication between the multiple semiconductor chips 5. This configuration makes it possible to reduce the number of wirings between the multiple semiconductor chips 5, i.e., the number of wirings provided across the multiple semiconductor chips 5 or dies.

[0074] (Modification of Fourth Embodiment) The configuration according to this embodiment can be appropriately combined with at least one of the semiconductor device 1 according to each of the above-described embodiments and modifications.

[0075] For example, in the configuration of the semiconductor device 1 b in which the arbitration circuit 19 is provided for each power supply domain 4 , a serial / parallel conversion circuit 23 may be further provided for each power supply domain 4 .

[0076] For example, in the configuration of the semiconductor device 1c in which the clock control circuit 21 is provided between the functional block 15 and the block power supply control circuit 17, a serial / parallel conversion circuit 23 may be further provided to make communication between the semiconductor chips 5a and 5b serial communication.

[0077] For example, an arbitration circuit 19 and a serial / parallel conversion circuit 23 may be provided for each power domain 4 , and a clock control circuit 21 may be provided between the function block 15 and the block power control circuit 17 .

[0078] Fifth Embodiment A semiconductor device 1 according to a fifth embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1d according to the fourth embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. FIG. 10 is a diagram showing an example of the configuration of a semiconductor device 1e according to the fifth embodiment. The semiconductor device 1e according to the fifth embodiment further includes a semiconductor chip 5c as one of the multiple semiconductor chips 5. The semiconductor chip 5c has a configuration similar to that of, for example, the semiconductor chip 5b. Of course, in the circuit groups 6c and 6f of the semiconductor chip 5c, the number of functional blocks 15 and block power supply control circuits 17 may be the same as or different from those of the other semiconductor chips 5.

[0079] Furthermore, the semiconductor device 1e according to the fifth embodiment has a time division multiplexing circuit 25 for each power supply domain 4. In the example of Fig. 10, time division multiplexing circuits 25a and 25b are provided for the power supply domains 4a and 4b, respectively.

[0080] The time division multiplexing circuit 25a is provided in the always-on area 9b of the semiconductor chip 5b and is electrically connected by serial communication signal lines to the serial / parallel conversion circuit 23a in the always-on area 9a of the semiconductor chip 5a, the serial / parallel conversion circuit 23b in the always-on area 9b of the semiconductor chip 5b, and the serial / parallel conversion circuit 23c in the always-on area 9c of the semiconductor chip 5c. The time division multiplexing circuit 25b is provided in the always-on area 9e of the semiconductor chip 5b and is electrically connected by serial communication signal lines to the serial / parallel conversion circuit 23d in the always-on area 9d of the semiconductor chip 5a, the serial / parallel conversion circuit 23e in the always-on area 9e of the semiconductor chip 5b, and the serial / parallel conversion circuit 23f in the always-on area 9f of the semiconductor chip 5c. Here, the serial / parallel conversion circuits 23c and 23f are examples of third serial / parallel conversion circuits.

[0081] The time division multiplexing circuits 25 a and 25 b time division multiplex the on request signal and the score serial signal output from at least one block power control circuit 17 for each power domain 4 .

[0082] In this way, the semiconductor device 1 according to this embodiment time-division multiplexes communications between the multiple semiconductor chips 5. With this configuration, when the number of semiconductor chips 5 to be controlled increases to three or more, the number of connection wires between the semiconductor chips 5 increases with each increase in the number of chips. However, by multiplexing the request signals and score serial signals from each semiconductor chip 5, it is possible to suppress an increase in the number of signal wires to the semiconductor chip 5a having the arbitration circuit 19.

[0083] (Modification of Fifth Embodiment) The configuration according to this embodiment can be appropriately combined with the semiconductor device 1d according to the fourth embodiment and at least one of the modifications of the fourth embodiment.

[0084] Sixth Embodiment A semiconductor device 1 according to a sixth embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1e according to the fifth embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. FIG. 11 is a diagram showing an example of the configuration of a semiconductor device 1f according to the sixth embodiment. Unlike the semiconductor device 1e according to the fifth embodiment, the semiconductor device 1f according to the sixth embodiment does not include a time division multiplexing circuit 25, but does include a communication master circuit 27 and at least one communication slave circuit 29.

[0085] 11 illustrates a communication slave circuit 29a provided on the semiconductor chip 5b and a communication slave circuit 29b provided on the semiconductor chip 5c as at least one communication slave circuit 29. The communication master circuit 27, the communication slave circuit 29a, and the communication slave circuit 29b are connected in series using signal lines for serial communication.

[0086] The communication master circuit 27 is provided in the always-on area 9a of the semiconductor chip 5a and is electrically connected by serial communication signal lines to the serial / parallel conversion circuit 23a in the always-on area 9a of the semiconductor chip 5a and the serial / parallel conversion circuit 23d in the always-on area 9d of the semiconductor chip 5a. The communication slave circuit 29a is provided in the always-on area 9b of the semiconductor chip 5b and is electrically connected by serial communication signal lines to the serial / parallel conversion circuit 23b in the always-on area 9b of the semiconductor chip 5b and the serial / parallel conversion circuit 23e in the always-on area 9e of the semiconductor chip 5b. The communication slave circuit 29b is provided in the always-on area 9c of the semiconductor chip 5c and is electrically connected by serial communication signal lines to the serial / parallel conversion circuit 23c in the always-on area 9c of the semiconductor chip 5c and the serial / parallel conversion circuit 23f in the always-on area 9f of the semiconductor chip 5f.

[0087] 11, the communication master circuit 27, the multiple communication slave circuits 29a and 29b, and the multiple serial / parallel conversion circuits 23a to 23f are connected in series using signal lines for serial communication. Here, the communication master circuit 27 is an example of a second communication circuit. The communication slave circuit 29a is an example of a first communication circuit.

[0088] Furthermore, in the semiconductor device 1f according to the sixth embodiment, an ID is assigned to each power supply domain 4 of each semiconductor chip 5 to uniquely identify it.

[0089] For example, an ID for uniquely identifying the semiconductor chip 5 and power domain 4 of the own circuit is predetermined and stored in the internal memory of each of the at least one block power control circuit 17. Then, each of the at least one block power control circuit 17 outputs the ID assigned to the own circuit together with an on-request signal and a score to the next stage connected in series.

[0090] 11 in which a serial / parallel conversion circuit 23 is provided for each power supply domain 4 of each semiconductor chip 5, the storage of the predetermined ID in the internal memory and the output thereof may be realized by the serial / parallel conversion circuit 23 in the next stage of the block power supply control circuit 17 that outputs the serial signals of the on-request signal and the score, or may be realized by each of the communication master circuit 27, communication slave circuit 29a, and communication slave circuit 29b that receive the serial signals. In this case, an ID may be used to uniquely identify the serial / parallel conversion circuit 23 that outputs the serial signals of the on-request signal and the score.

[0091] Also, for example, the arbitration circuit 19 temporarily holds the ID attached to the ON request signal and the score, and outputs the held ID together with the permission signal to the next stage connected in series.

[0092] In this way, the semiconductor device 1 according to this embodiment connects the signal wiring for the on request and the score of each semiconductor chip 5 in series. Furthermore, in the semiconductor device 1 according to this embodiment, when there is data to be transmitted (output), each semiconductor chip 5 transmits the assigned ID along with the data to the next stage, and when there is no data to be transmitted (output), it transfers the data and ID from the previous stage to the next stage. Specifically, the communication master circuit 27 and each of the multiple communication slave circuits 29 a, 29 b determine whether to receive or transfer data based on the ID. The ID may be a destination ID indicating the destination, or a source ID indicating the source.

[0093] According to this configuration, request signals and score serial signals can be transmitted and received between the semiconductor chips 5 via signal lines for one-way serial communication, which prevents an increase in the number of signal wires to the semiconductor chip 5a having the arbitration circuit 19 and further reduces the number of signal wires between the semiconductor chips 5. Furthermore, when the number of semiconductor chips 5 to be controlled increases to three or more, the number of connection wires between the semiconductor chips 5 increases with each increase in the number of chips, but this increase can be prevented.

[0094] (Modification of Sixth Embodiment) The configuration according to this embodiment can be appropriately combined with at least one of the semiconductor devices 1d and 1e according to the fourth and fifth embodiments and the modifications of the fourth and fifth embodiments.

[0095] Seventh Embodiment A semiconductor device 1 according to a seventh embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1a according to the first embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. Figure 12 is a diagram showing an example of the configuration of a semiconductor device 1g according to the seventh embodiment.

[0096] 12, an arbitration circuit 19 may be provided in a semiconductor chip 5a near (for example, closest to) the power management IC 3 on the substrate 2. The arbitration circuit 19 provided in this semiconductor chip 5a receives on-request signals and scores from the plurality of block power supply control circuits 17 of the semiconductor chips 5a to 5d, and outputs permission signals to the plurality of block power supply control circuits 17 based on the score of each block power supply control circuit 17.

[0097] (Modification of Seventh Embodiment) The configuration according to this embodiment can be appropriately combined with at least one of the semiconductor device 1 according to each of the above-described embodiments and modifications.

[0098] Eighth Embodiment A semiconductor device 1 according to an eighth embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1g according to the seventh embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. Figure 13 is a diagram showing an example of the configuration of a semiconductor device 1h according to the eighth embodiment.

[0099] 13 has multiple power management ICs 3a and 3b on a substrate 2. Thus, the semiconductor device 1g may have a different power management IC 3 for each power domain 4. In this case, for example, an arbitration circuit 19 may be provided in each of the semiconductor chips 5a and 5d that are located near (e.g., closest to) the power management ICs 3a and 3b. The arbitration circuit 19 provided in the semiconductor chip 5a receives, for example, on-request signals and scores from the multiple block power control circuits 17 of the semiconductor chips 5a and 5b, and outputs enable signals to the multiple block power control circuits 17 based on the scores of each block power control circuit 17. The arbitration circuit 19 provided in the semiconductor chip 5d receives, for example, on-request signals and scores from the multiple block power control circuits 17 of the semiconductor chips 5c and 5d, and outputs enable signals to the multiple block power control circuits 17 based on the scores of each block power control circuit 17.

[0100] (Modification of Eighth Embodiment) The configuration according to this embodiment can be appropriately combined with at least one of the semiconductor device 1 according to each of the above-described embodiments and modifications.

[0101] In each of the above-described embodiments, part or all of each circuit may be configured with hardware, or may be configured with information processing software (programs) executed by a CPU, etc. In addition, in each of the above-described embodiments, when multiple memories store data, each of the multiple memories may store only a portion of the data, or may store the entire data.

[0102] As described above, according to at least one embodiment of the present disclosure, it is possible to appropriately control the timing of supplying power supply voltages across multiple semiconductor chips.

[0103] Although the embodiments of the present disclosure have been described in detail above, these embodiments are presented as examples and are not intended to be limiting. Each embodiment can be modified by various additions, changes, substitutions, partial deletions, combinations, etc., without departing from the technical spirit of the present invention. These embodiments and their modifications are included within the scope of the invention described in the claims and their equivalents.

[0104] REFERENCE SIGNS LIST 1 semiconductor device 2 substrate 3 power management IC 4 power domain 5 semiconductor chip 6, 7 circuit group 9 always-on area 13 switch 15 functional block 17 block power control circuit 19 arbitration circuit 21 clock control circuit 23 serial / parallel conversion circuit 25 time division multiplexing circuit 27 communication master circuit 29 communication slave circuit 191 request acceptance circuit 193 request storage memory 195 simultaneous permission determination circuit 197 simultaneous permission transmission circuit 201 enqueue entry 203 enqueue data 205 simultaneous permission flag

Claims

1. A semiconductor device, comprising a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on the substrate, wherein each of the first semiconductor chip and the second semiconductor chip has at least one functional block and at least one block power control circuit that is electrically connected to one or more of the at least one functional block and controls supply of a power voltage to each of the one or more functional blocks, and the second semiconductor chip further has an arbitration circuit that outputs a permission signal for permitting supply of a power voltage to one or more block power control circuits that output the on-request signal, based on an on-request signal for requesting start of supply of a power voltage to one or more functional blocks to be controlled, each of which is output from one or more of the block power control circuits included in the first semiconductor chip and the second semiconductor chip, and a score based on parasitic capacitance.

2. The semiconductor device according to claim 1, wherein the first semiconductor chip is electrically connected to each of the at least one block power control circuit included in the first semiconductor chip, converts the on-request signal and the score output from each of the one or more block power control circuits into a serial signal and outputs the serial signal to the second semiconductor chip, and further has a first serial / parallel conversion circuit that outputs the permission signal to each of the one or more block power control circuits that output the on-request signal upon receiving the permission signal from the second semiconductor chip.

3. The semiconductor device according to claim 2, wherein the second semiconductor chip is electrically connected between the arbitration circuit and the first serial / parallel conversion circuit, converts the serial signal of the on-request signal and the score from the first serial / parallel conversion circuit into a parallel signal and outputs the parallel signal to the arbitration circuit, and further has a second serial / parallel conversion circuit that converts the permission signal from the arbitration circuit into a serial signal and outputs the serial signal to the first serial / parallel conversion circuit.

4. The semiconductor device according to claim 1, wherein the arbitration circuit calculates a total value of the scores input during a set period and outputs the permission signal based on a comparison result between the total value and a predetermined threshold value.

5. The semiconductor device according to claim 4, wherein the arbitration circuit calculates the total value based on priorities set for the plurality of functional blocks included in the first semiconductor chip and the second semiconductor chip.

6. Each of the first semiconductor chip and the second semiconductor chip has a first power supply voltage region operating at a first power supply voltage and a second power supply voltage region operating at a second power supply voltage different from the first power supply voltage, and the second semiconductor chip has the arbitration circuit in each of the first power supply voltage region and the second power supply voltage region. The semiconductor device according to claim 1.

7. Each of the at least one block power supply control circuit controls, for each of the one or more functional blocks to be controlled, the on / off and the frequency of an input clock signal based on an operating state. The semiconductor device according to claim 1.

8. Each of the first semiconductor chip and the second semiconductor chip has a first power supply voltage region operating at a first power supply voltage and a second power supply voltage region operating at a second power supply voltage different from the first power supply voltage, the first semiconductor chip has the first serial / parallel conversion circuit in each of the first power supply voltage region and the second power supply voltage region, and the second semiconductor chip has the second serial / parallel conversion circuit and the arbitration circuit in each of the first power supply voltage region and the second power supply voltage region. The semiconductor device according to claim 3.

9. The semiconductor device further includes a third semiconductor chip disposed on the substrate. The third semiconductor chip includes at least one functional block, at least one block power control circuit electrically connected to one or more of the at least one functional block and controlling supply of a power voltage to each of the one or more functional blocks, and a third serial / parallel conversion circuit electrically connected to each of the at least one block power control circuit included in the third semiconductor chip, converting the on-request signal and the score output from each of the one or more block power control circuits included in the third semiconductor chip into a serial signal, outputting the serial signal to the second semiconductor chip, and outputting the permission signal received from the second semiconductor chip to each of the one or more block power control circuits that output the on-request signal included in the third semiconductor chip. The first semiconductor chip is electrically connected between each of the first serial / parallel conversion circuit and the third serial / parallel conversion circuit and the second serial / parallel conversion circuit, and further includes a time-division multiplexing circuit that time-division multiplexes the serial signals of the on-request signal and the score from each of the first serial / parallel conversion circuit and the third serial / parallel conversion circuit and outputs the multiplexed signals to the arbitration circuit of the second semiconductor chip. The semiconductor device according to claim 3.

10. The first semiconductor chip is electrically connected to the first serial / parallel conversion circuit, and further includes a first communication circuit that transfers the on-request signal from the first serial / parallel conversion circuit and the serial signal of the score to the second semiconductor chip via a signal line for serial communication. The second semiconductor chip is electrically connected to the arbitration circuit, converts the on-request signal from the first serial / parallel conversion circuit and the serial signal of the score into a parallel signal and outputs the parallel signal to the arbitration circuit, and converts the permission signal from the arbitration circuit into a serial signal and outputs the serial signal. The second semiconductor chip further includes a second serial / parallel conversion circuit and a second communication circuit that transfers the serial signal of the permission signal from the second serial / parallel conversion circuit to the first semiconductor chip via the signal line for serial communication, and receives the on-request signal from the first serial / parallel conversion circuit and the serial signal of the score and outputs the signals to the second serial / parallel conversion circuit. The semiconductor device according to claim 2.

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