Semiconductor device

Abstract

A semiconductor device according to one embodiment of the present disclosure comprises a substrate and first and second semiconductor chips. The first and second semiconductor chips each include at least one functional block and at least one block power-supply control circuit. The first semiconductor chip further includes an aggregation circuit that: aggregates on-request signals and scores, the on-request signals being from the at least one block power-supply control circuit and requesting the start of supply of a power supply voltage and the scores being based on parasitic capacitance; and outputs an aggregate on-request signal and an aggregate score. The second semiconductor chip further includes a main arbitration circuit that, on the basis of the aggregate on-request signal and the aggregate score from the aggregation circuit and on the basis of on-request signals from a plurality of block power-supply control circuits which are included in the second semiconductor chip and which request the start of supply of a power supply voltage and scores based on parasitic capacitance, outputs a permission signal permitting the start of supply of a power supply voltage to one or more block power-supply control circuits of the first and second semiconductor chips that have output the on-request signal.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, there is a technology for mounting multiple semiconductor chips on a single substrate or package to manufacture chiplet products or multi-chip package products. In such products incorporating multiple semiconductor chips, when controlling the power supply voltage of each semiconductor chip, it is necessary to consider the power supply status to other semiconductor chips. For example, in multiple semiconductor chips sharing a power domain, if power supply voltage is simultaneously supplied to multiple functional blocks, there is a risk of malfunction or failure due to inrush current.

[0003] US Patent No. 11467655 JP 2023-075588 A

[0004] However, there is room for improvement in timing control of power supply voltage supply across multiple semiconductor chips, such as the fact that a power supply control circuit that controls the power supply voltage supply to a certain functional block cannot grasp the timing of power supply voltage supply to other functional blocks by other power supply voltage supply circuits.

[0005] An object of the present disclosure is to appropriately control the timing of supplying power supply voltages across multiple semiconductor chips.

[0006] According to an embodiment of the present disclosure, a semiconductor device includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on the substrate. Each of the first semiconductor chip and the second semiconductor chip includes at least one functional block and at least one block power control circuit electrically connected to one or more of the at least one functional block and controlling supply of power supply voltage to each of the one or more functional blocks. The first semiconductor chip further includes an aggregation circuit configured to aggregate on-request signals output from one or more of the block power control circuits included in the first semiconductor chip, the on-request signals requesting start of supply of power supply voltage for the one or more functional blocks to be controlled, and scores based on parasitic capacitance, for the one or more functional blocks to be controlled, and to output an aggregated on-request signal and an aggregated score. The second semiconductor chip further includes a main arbitration circuit that outputs a permission signal to the one or more block power supply control circuits that output the on request signal of the first semiconductor chip and the second semiconductor chip to permit the start of supply of power supply voltage, based on the aggregated on request signal and the aggregated score from the aggregated circuit, and on request signals requesting the start of supply of power supply voltage and scores based on parasitic capacitance, for the one or more functional blocks to be controlled, output from each of the one or more block power supply control circuits among the plurality of block power supply control circuits included in the second semiconductor chip.

[0007] According to an embodiment of the present disclosure, it is possible to appropriately control the timing of supplying power supply voltages across a plurality of semiconductor chips.

[0008] FIG. 1 is a diagram illustrating an example of the configuration of a semiconductor device according to a first embodiment. FIG. 2 is a diagram illustrating an example of the configuration of a main arbitration circuit of FIG. 1. FIG. 3 is a diagram illustrating an example of the configuration of a division circuit and an aggregation circuit of FIG. 1. FIG. 4 is a flowchart illustrating an example of the operation flow of the main arbitration circuit of FIG. 2. FIG. 5 is a flowchart illustrating an example of the operation flow of an enqueue entry operation of FIG. 4. FIG. 6 is a flowchart illustrating an example of the operation flow of a request storage operation of FIG. 4. FIG. 7 is a flowchart illustrating an example of the operation flow of a simultaneous permission determination operation of FIG. 4. FIG. 8 is a flowchart illustrating an example of the operation flow of an aggregation entry operation of the aggregation circuit of FIG. 3. FIG. 9 is a flowchart illustrating an example of the operation flow of an aggregation request storage operation of the aggregation circuit of FIG. 3. FIG. 10 is a flowchart illustrating an example of the operation flow of a division operation of the division circuit of FIG. 3. FIG. 11 is a diagram illustrating an example of the configuration of a semiconductor device according to a second embodiment. FIG. 12 is a diagram illustrating an example of the configuration of a semiconductor device according to a third embodiment. FIG. 13 is a diagram illustrating an example of the configuration of a semiconductor device according to a fourth embodiment. FIG. 14 is a diagram illustrating an example of the configuration of a semiconductor device according to a fifth embodiment. FIG. 15 is a diagram illustrating an example of the configuration of a semiconductor device according to a sixth embodiment. FIG. 16 is a diagram illustrating an example of the configuration of a semiconductor device according to a seventh embodiment. 17 is a diagram showing an example of the configuration of a semiconductor device according to an eighth embodiment. FIG. 18 is a diagram showing an example of the configuration of a semiconductor device according to a ninth embodiment.

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor device will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0010] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals, and redundant explanations are provided only when necessary. The embodiments can be appropriately combined with other embodiments, modifications, and / or conventional techniques.

[0011] In the description of the present disclosure, components having the same or substantially the same functions may be distinguished by adding an alphanumeric character to the end of the reference symbol. Alternatively, when multiple components having the same or substantially the same functions are not distinguished, they may be collectively described by omitting the alphanumeric character at the end of the reference symbol.

[0012] In the description of the present disclosure, "determining whether it is A" may mean "determining that it is A," "determining that it is not A," or "determining whether it is A or not."

[0013] In each embodiment of the present disclosure, a semiconductor device called a SoC (System on a Chip) or SiP (System in Package) in which multiple semiconductor chips are mounted on a single substrate or package will be exemplified as the semiconductor device.

[0014] 1 is a diagram showing an example of the configuration of a semiconductor device 1a according to a first embodiment. As shown in FIG. 1, the semiconductor device 1a includes a power management IC (Integrated Circuit) 3 and a plurality of semiconductor chips 5.

[0015] The power management IC 3 and the multiple semiconductor chips 5 are provided on a substrate 2. The substrate 2 is formed of, for example, silicon or resin. The substrate 2 is, for example, a Si interposer substrate, but various circuit boards for semiconductor devices, such as other printed circuit boards, can be used as appropriate. The power management IC 3 is a composite power circuit that generates a power supply voltage to be supplied to each of the multiple semiconductor chips 5. A wiring pattern that constitutes a power domain 4 is formed on the substrate 2. The power domain 4 is a group of power supplies to which power is supplied from the power management IC 3.

[0016] FIG. 1 illustrates semiconductor chips 5a and 5b as examples of multiple semiconductor chips 5. The semiconductor chips 5a and 5b belong to a common power domain 4 and are each electrically connected to a power management IC 3. The semiconductor chips 5a and 5b each have a circuit group 6a and 6b, respectively. Each of the circuit groups 6a and 6b has at least one switch 13, at least one functional block 15, and at least one block power control circuit 17. The semiconductor chip 5a also has a main arbitration circuit 18. The semiconductor chip 5b also has a sub-arbitration circuit 19, a dividing circuit 31, and a consolidation circuit 33. Here, the semiconductor chip 5a is an example of a second semiconductor chip arranged on a substrate. The semiconductor chip 5b is an example of a first semiconductor chip arranged on a substrate.

[0017] Each of the at least one block power supply control circuits 17 is electrically connected to a main arbitration circuit 18. In the example of Fig. 1, each block power supply control circuit 17 of the semiconductor chip 5a is electrically connected to the main arbitration circuit 18 in the same semiconductor chip 5a. Also, each block power supply control circuit 17 of the semiconductor chip 5b is electrically connected to a sub-arbitration circuit 19 in the semiconductor chip 5b.

[0018] Each of the at least one block power supply control circuit 17 is provided in the always-on area 9a, 9b that is always supplied with a power supply voltage from the power supply domain 4. Each of the at least one block power supply control circuit 17 is electrically connected to at least one functional block 15 in the same semiconductor chip 5. Each of the at least one block power supply control circuit 17 controls the supply of a power supply voltage from the power management IC 3 for the corresponding at least one functional block 15.

[0019] Specifically, each block power control circuit 17 of the semiconductor chip 5a outputs a power supply voltage ON request signal and a score to the main arbitration circuit 18 for each of at least one connected functional blocks 15 based on the operating state of the functional block 15. Furthermore, each block power control circuit 17 of the semiconductor chip 5a controls the ON / OFF of the power supply voltage to the functional block 15 and the supply sequence of the power supply voltage based on a power supply voltage ON permission signal from the main arbitration circuit 18. Furthermore, each block power control circuit 17 of the semiconductor chip 5b outputs a power supply voltage ON request signal and a score to the aggregation circuit 33 for each of at least one connected functional block 15 based on the operating state of the functional block 15. Furthermore, each block power control circuit 17 of the semiconductor chip 5b controls the ON / OFF of the power supply voltage to the functional block 15 and the supply sequence of the power supply voltage based on a power supply voltage ON permission signal from the sub-arbitration circuit 19. The score will be described later.

[0020] Note that, although the present disclosure illustrates an example in which a transition from a power-off state to an on state is controlled for each of at least one functional block 15, the present disclosure is not limited to this. For example, the present disclosure may be applied to a case in which a transition of an operation mode for each of at least one functional block 15 is controlled from a first operation mode to a second operation mode having a higher operating voltage (or operating frequency) than that of the first operation mode, or to a combination of these.

[0021] Each of the at least one functional block 15 is electrically connected to a corresponding switch 13. Specifically, each of the at least one functional block 15 is connected to the power supply domain 4 via the corresponding switch 13. Each of the at least one functional block 15 is at least one processor, and is driven using a power supply voltage from the power management IC 3.

[0022] As an example, each of the at least one functional block 15 is a CPU (Central Processing Unit) core, but may be another processor. Each of the at least one functional block 15 may be a processor that realizes a predetermined function by executing a program loaded from a ROM (internal memory) or the like to a RAM (internal memory), or may be a processor constructed as a dedicated circuit to realize a predetermined function. Each circuit group 6 may be provided with two or more functional blocks 15 of two or more types. The functions of the two or more functional blocks 15 may be the same or different.

[0023] Each of the at least one switch 13 is controlled by a corresponding block power control circuit 17 to switch between conduction and communication between the corresponding functional block 15 and the power management IC 3 (power domain 4).

[0024] 1 illustrates, for each semiconductor chip 5, three block power supply control circuits 17 that control the supply of power supply voltage to one functional block 15, and one block power supply control circuit 17 that controls the supply of power supply voltage to each of two functional blocks 15. The number of block power supply control circuits 17 in each semiconductor chip 5 is arbitrary and may be designed as appropriate. The number of functional blocks 15 to which one block power supply control circuit 17 controls the supply of power supply voltage is arbitrary and may be designed as appropriate. The numbers of functional blocks 15 and block power supply control circuits 17 may be the same or different among two or more semiconductor chips 5.

[0025] The main arbitration circuit 18 is provided in the always-on area 9 a. The main arbitration circuit 18 has an internal register. The main arbitration circuit 18 outputs a power supply voltage on permission signal to each block power supply control circuit 17 based on the threshold values ​​for the semiconductor chips 5 a, 5 b stored in the internal register and the power supply voltage on request signals and scores received from each block power supply control circuit 17.

[0026] Here, the "score" is a value based on the parasitic capacitance of the functional block 15 receiving power supply and the resistance value of the switch 13 connected to the functional block 15. The score of each functional block 15 is, for example, predetermined and stored in the internal memory of each functional block 15 or the block power supply control circuit 17.

[0027] As an example, the score value may be designed so that the response time when the switch 13 is turned on, i.e., the time required to reach a steady state, is a time constant that satisfies the required specifications. For example, this time constant "τ" is expressed as "τ = CR," where "C" is the capacitance value of the parasitic capacitance of the functional block 15 and "R" is the resistance value of the corresponding switch 13. In the transient state from when the switch 13 is turned on until the parasitic capacitance of the functional block 15 reaches a steady state, the inrush current is maximized at the point where the change per unit time in the time series of the potential "V" (dV / dt) is maximized. Therefore, the score value can be calculated by multiplying the maximum "dV / dt" in the transient state by "1 / R," i.e., the value of "dI / dt." This score value is a circuit-specific value that depends on the operating frequency, operating voltage, circuit size, and the like.

[0028] The "threshold" is a value based on the amount of drop in power supply voltage (or power supply current) that will not cause malfunction of each semiconductor chip 5 and the allowable current value of the power supply management IC 3. This threshold is, for example, predetermined for each power supply management IC 3 and semiconductor chip 5 and stored in the internal registers (memories) of the main arbitration circuit 18 and the sub-arbitration circuit 19.

[0029] As an example, dynamic voltage drop (DVD) occurs in proportion to the amount of rush current. Therefore, the threshold value may be expressed as "Min(X, Y)" where "X" is the dynamic voltage drop amount (≒ rush current amount) within a range that does not cause malfunction and is specified for each process (sign-off condition), and "Y" is the allowable current value (allowable current amount) specified for the power management IC 3. Furthermore, the threshold value for multiple semiconductor chips 5 sharing the power domain 4 may be expressed as "Min(X-A, X-B, Y)" where "X" is the dynamic voltage drop amount for semiconductor chip "A" and semiconductor chip "B," respectively. For example, in the semiconductor device 1 according to this embodiment, the threshold value for semiconductor chip 5b used by the sub-arbitration circuit 19 is expressed as "Min(X-B, Y)." Furthermore, for example, the threshold value for the system, ie, the semiconductor chips 5a and 5b, used by the main arbitration circuit 18 is expressed as "Min("XA", "XB", Y)."

[0030] The main arbitration circuit 18 compares the sum of the scores (total score) of at least one functional block 15 that has received an on-request with a threshold. If the total score is equal to or less than the threshold, the main arbitration circuit 18 grants all of the received on-requests. On the other hand, if the total score is greater than the threshold, the main arbitration circuit 18 repeats the process of granting on-requests with a predetermined high priority within the range where the total score falls within the threshold, until the total score of the received on-requests falls below the threshold.

[0031] Fig. 2 is a diagram showing an example of the configuration of the main arbitration circuit 18 of Fig. 1. As shown in Fig. 2, the main arbitration circuit 18 has a request acceptance circuit 191, a request storage memory 193, a simultaneous permission determination circuit 195, and a simultaneous permission transmission circuit 197.

[0032] The request receiving circuit 191 performs an enqueue entry operation. For example, the request receiving circuit 191 sequentially receives turn-on requests and scores for at least one functional block 15 of the semiconductor chips 5a and 5b from at least one block power control circuit 17 of the semiconductor chips 5a and 5b, and stores these requests and scores in the enqueue entry 201. As shown in FIG. 2 , the enqueue entry 201 has an area for each of at least one functional block 15 to be controlled.

[0033] The request acceptance circuit 191 also performs a request storage operation. For example, the request acceptance circuit 191 stores the data stored in the enqueue entry 201 in the request storage memory 193 as enqueue data 203, for example, at a predetermined cycle. The request storage memory 193 is, for example, a FIFO (First In, First Out) memory. As shown in FIG. 2 , the enqueue data 203 has an area for each of at least one function block 15 to be controlled.

[0034] Note that the priority of power supply to the functional blocks 15 may be adjusted by determining the storage location in the request storage memory 193 based on a predetermined priority. In other words, the calculation of the total score, which will be described later, may be performed based on the priority set for each of the multiple functional blocks 15 of the multiple semiconductor chips 5. This adjustment may be performed by setting the storage location in the enqueue entry 201 and the enqueue data 203, or by setting the start position for reading (searching) from the enqueue data 203 in the simultaneous permission determination, which will be described later, or by a combination of these.

[0035] The simultaneous permission determination circuit 195 performs a simultaneous permission determination operation. For example, the simultaneous permission determination circuit 195 determines whether to supply power to each functional block 15 in response to a power-on request for at least one functional block 15 in the semiconductor chips 5a and 5b, which is sequentially received from at least one block power control circuit 17 in the semiconductor chips 5a and 5b. Specifically, the simultaneous permission determination circuit 195 calculates a total score (a sum of the scores) of at least one functional block 15 for which a power-on request has been made during a predetermined period, based on the power-on requests and scores stored in the request storage memory 193. The simultaneous permission determination circuit 195 also determines whether to supply power to the functional block 15 for which a power-on request has been made, based on the comparison result between the total score and a threshold value for the semiconductor chips 5a and 5b. The simultaneous permission determination circuit 195 then stores the determination result in the simultaneous permission flag 205. As shown in FIG. 2 , the simultaneous permission flag 205 has an area for each of at least one functional block 15 to be controlled.

[0036] The simultaneous permission sending circuit 197 performs a simultaneous permission sending operation. For example, the simultaneous permission sending circuit 197 refers to the simultaneous permission flag 205 and sends a permission for at least one functional block 15 that has been permitted to receive power supply by the simultaneous permission determination circuit 195 to at least one block power supply control circuit 17 of the semiconductor chip 5a and / or the divided circuit 31 of the semiconductor chip 5b. The permission sent to the divided circuit 31 of the semiconductor chip 5b relates to at least one block power supply control circuit 17 of the semiconductor chip 5b.

[0037] The simultaneous permission determination circuit 195 repeatedly permits power supply starting from the highest priority on-request if a priority is set, or in the order of readout if a priority is not set, within the range in which the total score does not exceed the threshold. At this time, the simultaneous permission determination circuit 195 stores the determination result in the simultaneous permission flag 205 each time it determines whether or not to supply power, and supplies a startup notification to the simultaneous permission transmission circuit 197. Furthermore, each time the simultaneous permission transmission circuit 197 receives a startup notification from the simultaneous permission determination circuit 195, the simultaneous permission transmission circuit 197 refers to the simultaneous permission flag 205 in response to the startup notification and transmits permission.

[0038] The aggregation circuit 33 is provided in the always-on region 9b. The aggregation circuit 33 is electrically connected to the main arbitration circuit 18 of the semiconductor chip 5a and to each of at least one block power supply control circuit 17 of the semiconductor chip 5b. The aggregation circuit 33 receives on-request signals and scores from each block power supply control circuit 17 of the semiconductor chip 5b, and outputs an aggregated on-request signal and aggregated score (total score) to the main arbitration circuit 18.

[0039] The division circuit 31 is provided in the always-on region 9b. The division circuit 31 is electrically connected to the main arbitration circuit 18 of the semiconductor chip 5a and the sub-arbitration circuit 19 of the semiconductor chip 5b. When an enable signal is input from the main arbitration circuit 18, the division circuit 31 extracts the block power supply control circuit 17 of the semiconductor chip 5b that corresponds to the enable signal, and outputs the enable signal and score corresponding to the extracted block power supply control circuit 17 to the sub-arbitration circuit 19.

[0040] The sub-arbitration circuit 19 is provided in the always-on region 9b. The sub-arbitration circuit 19 is electrically connected to the division circuit 31 and each of at least one block power supply control circuit 17. The sub-arbitration circuit 19 has a configuration similar to that of the main arbitration circuit 18. For example, the sub-arbitration circuit 19 has an internal register and outputs an authorization signal permitting each block power supply control circuit 17 of the semiconductor chip 5b to turn on its power supply voltage, based on a threshold value for the semiconductor chip 5b stored in the internal register and a power supply voltage on request signal and score from the division circuit 31 for each block power supply control circuit 17 of the semiconductor chip 5b.

[0041] 3 is a diagram showing an example of the configuration of the splitting circuit 31 and the aggregation circuit 33 of FIG. 1. As shown in FIG. 3, the splitting circuit 31 has a split permission sending circuit 311. The aggregation circuit 33 has a request receiving circuit 331 and an aggregation request sending circuit 333. Either the splitting circuit 31 or the aggregation circuit 33 has an aggregation request storage memory 32. The aggregation request storage memory 32 may be an external memory of the splitting circuit 31 and the aggregation circuit 33.

[0042] The request receiving circuit 331 performs an aggregation entry operation. For example, the request receiving circuit 331 sequentially receives from at least one block power control circuit 17 of the semiconductor chip 5b on requests and scores for at least one functional block 15 of the semiconductor chip 5b, and stores these requests and scores in the aggregation entry 202. As shown in FIG. 3 , the aggregation entry 202 has an area for each of at least one functional block 15 of the semiconductor chip 5b to be controlled.

[0043] The request receiving circuit 331 and the aggregation request sending circuit 333 also perform aggregation request storage operations. For example, the request receiving circuit 331 stores the data stored in the aggregation entry 202 in the aggregation request storage memory 32 as enqueue data 204, for example, at a predetermined cycle. As shown in FIG. 3 , the enqueue data 204 has an area for each of at least one functional block 15 of the semiconductor chip 5b to be controlled. The request receiving circuit 331 also stores the on-request and score in the aggregation request storage memory 32, and the aggregation request sending circuit 333 references the aggregation entry 202 and outputs the aggregate on-request and aggregation score (total score) to the main arbitration circuit 18.

[0044] The priority of power supply to the functional blocks 15 of the semiconductor chip 5b may be adjusted by determining the storage location in the aggregation request storage memory 32 based on a predetermined priority. In other words, the calculation of the aggregation score, which will be described later, may be performed based on the priority set for each of at least one functional block 15 of the semiconductor chip 5b. This adjustment may be performed by setting the storage location in the aggregation entry 202 and the enqueue data 204, by setting the start position for reading (searching) from the aggregation entry 202 in the above-mentioned aggregation request storage operation, by setting the start position for reading (searching) from the enqueue data 203 in the above-mentioned simultaneous permission determination, or by a combination of these.

[0045] The division circuit 31 performs a division operation. For example, when a permission signal for turning on the power supply voltage is input from the main arbitration circuit 18, the division circuit 31 references the aggregation request storage memory 32 to extract at least one block power supply control circuit 17 of the semiconductor chip 5 b that corresponds to the permission signal, and outputs an on request signal and a score corresponding to the extracted one or more block power supply control circuits 17 to the sub-arbitration circuit 19 via the division permission sending circuit 311.

[0046] Next, the flow of control processing executed by the semiconductor device 1a configured as above will be described.

[0047] 4 is a flowchart showing an example of the operation flow of the main arbitration circuit 18 according to the embodiment. In the semiconductor device 1a, it is assumed that each of the plurality of block power supply control circuits 17 of the semiconductor chips 5a and 5b outputs an on-request and a score for at least one functional block 15 at any time and at any desired timing.

[0048] The main arbitration circuit 18 performs an enqueue entry operation (S101). Fig. 5 is a flowchart showing an example of the flow of the enqueue entry operation of Fig. 4. The main arbitration circuit 18 sequentially stores and holds, in a corresponding area in the enqueue entry 201, on-requests and scores for at least one functional block 15 that are sequentially received, for example, in one cycle, from at least one block power control circuit 17 directly or via the aggregation circuit 33 (S201).

[0049] The main arbitration circuit 18 performs a request storage operation (S102). FIG. 6 is a flowchart showing an example of the flow of the request storage operation of FIG. 4. The main arbitration circuit 18 determines whether at least one valid ON request exists in the enqueue entry 201, for example, in any cycle period equal to or greater than one cycle period (S301). If at least one valid ON request exists in the enqueue entry 201 (S301: Yes), the main arbitration circuit 18 stores the data stored in the enqueue entry 201 in the request storage memory 193 as enqueue data 203 (S302). If at least one valid ON request does not exist in the enqueue entry 201 (S301: No), or after the processing of S302, the request storage operation for that time ends.

[0050] The main arbitration circuit 18 performs a simultaneous permission determination operation (S103). Fig. 7 is a flowchart showing an example of the flow of the simultaneous permission determination operation of Fig. 4 .

[0051] The main arbitration circuit 18 determines whether the request storage memory 193 (e.g., a FIFO memory) is empty, i.e., no enqueue data 203 is stored therein (S401). If the request storage memory 193 is empty (S401: Yes), the simultaneous permission determination operation ends, and the process returns to S401. On the other hand, if the request storage memory 193 is not empty, i.e., if the enqueue data 203 is stored therein (S401: No), the main arbitration circuit 18 initializes the total score and simultaneous permission flag 205 (S402), and then scans the request storage memory 193 in an arbitrary order, permitting power supply starting with the highest priority on-request, as long as the total score does not exceed a threshold, until the total score of the received on-requests becomes equal to or less than the threshold (S403 to S408).

[0052] Specifically, the main arbitration circuit 18 refers to the request storage memory 193, and if the flag valid request [i] of the on request in the scanning area "i" of the enqueue data 203 is "1" (S403: Yes), it determines whether the total score obtained by adding the score [i] of the scanning area "i" to the current total score is below a threshold value (S404).

[0053] If the total score is greater than the threshold value (S404: No), the main arbitration circuit 18 simultaneously asserts permission [*] in the simultaneous permission flag 205 at that time, where the simultaneous permission flag [* (* is arbitrary)] is "1", and sends it to the corresponding block power supply control circuit 17 or division circuit 31 (S405). After assertion, the main arbitration circuit 18 initializes the total score and the simultaneous permission flag 205 (S406).

[0054] If the total score is below the threshold (S404: Yes), or after assertion and initialization, the main arbitration circuit 18 adds the current score [i] to update the total score, and also sets the simultaneous permission flag 205 of the scanning area "i", i.e., the simultaneous permission flag [i], to "1" (S407).

[0055] If the on-request flag valid request [i] is not "1" (S403: No), or after processing S407, the main arbitration circuit 18 updates "i" indicating the scanning area (S408) and performs processing for the next scanning area "i+1" (or scanning area "i-1").

[0056] Thereafter, the main arbitration circuit 18 determines whether there are any areas in the simultaneous permission flag 205 at that time where the simultaneous permission flag [*] is "1" (S409).

[0057] If there is an area where the simultaneous permission flag [*] is "1" (S409: No), the main arbitration circuit 18 simultaneously asserts the permission [*] where the simultaneous permission flag [*] is "1" and sends it to the corresponding block power supply control circuit 17 or division circuit 31 (S410).

[0058] If there is no area where the simultaneous permission flag [*] is "1" (S409: Yes), or after the processing of S410, the main arbitration circuit 18 outputs (discharges) the enqueue data 203 to be processed this time from the request storage memory 193 (S411). Thereafter, the simultaneous permission determination operation ends, and the process returns to the processing of S401.

[0059] Fig. 8 is a flowchart showing an example of the flow of the aggregation entry operation of the aggregation circuit 33 of Fig. 3. The aggregation circuit 33 sequentially stores and holds, in a corresponding area in the aggregation entry 202, on-requests and scores for at least one functional block 15 sequentially received from at least one block power control circuit 17 of the semiconductor chip 5b, for example, in one cycle (S501).

[0060] 9 is a flowchart showing an example of the flow of the aggregation request storage operation of the aggregation circuit 33 of FIG. 3 . The aggregation circuit 33 determines whether at least one valid ON request exists in the aggregation entry 202, for example, at any cycle period equal to or greater than one cycle period (S601). If at least one valid ON request exists in the aggregation entry 202 (S601: Yes), the aggregation circuit 33 stores the data stored in the aggregation entry 202 as enqueue data 204 in the aggregation request storage memory 32 (S602). If at least one valid ON request does not exist in the aggregation entry 202 (S601: No), or after processing S602, the aggregation circuit 33 calculates the sum of the scores of the valid ON requests in the aggregation entry 202 (aggregation score) and sends the aggregated score of the valid ON requests, i.e., the aggregated valid ON requests and aggregation score, to the main arbitration circuit 18 as an aggregated request (aggregated request) (S603). The aggregation request storage operation for that round then ends.

[0061] 10 is a flowchart showing an example of the flow of the splitting operation of the splitting circuit 31 of FIG. 3. The splitting circuit 31 determines whether it has received an aggregation permission (post-aggregation permission) including the permission signal and score asserted in the processing of S405 or S410 of FIG. 7 and sent from the main arbitration circuit 18 (S701). If the aggregation permission has not been received (S701: No), the splitting operation for that time ends, and the process returns to S701. On the other hand, if the aggregation permission has been received (S701: Yes), the splitting circuit 31 simultaneously asserts valid requests in the aggregation entry 202 and sends them to the sub-arbitration circuit 19 (S702). After asserting, the splitting circuit 31 outputs (discharges) the enqueue data 204 to be processed this time from the aggregation request storage memory 32 (S703). Then, the splitting operation for that time ends, and the process returns to S701.

[0062] The operation of the sub-arbitration circuit 19 is similar to that of the main arbitration circuit 18 described above, and therefore a description thereof will be omitted here.

[0063] As described above, the semiconductor device 1a according to this embodiment has a sub-arbitration circuit 19 that arbitrates on-request signals from at least one block power supply control circuit 17 in its own semiconductor chip 5b, and a main arbitration circuit 18 that arbitrates on-request signals from each of the plurality of block power supply control circuits 17 across the plurality of semiconductor chips 5 including its own semiconductor chip 5a and the other semiconductor chip 5b. Specifically, in the semiconductor device 1 according to this embodiment, the main arbitration circuit 18 outputs a permission signal that permits the start of supply of power supply voltage to the one or more block power supply control circuits 17 that output the on-request signal, based on an on-request signal that requests the start of supply of power supply voltage for one or more functional blocks 15 to be controlled, output from each of the one or more block power supply control circuits 17 among the plurality of block power supply control circuits 17 included in the semiconductor chips 5a, 5b, and a score based on parasitic capacitance. In addition, the sub-arbitration circuit 19 outputs a permission signal to one or more block power supply control circuits 17 that have output an on-request signal, based on the permission signal and score from the main arbitration circuit 18 for one or more functional blocks 15 to be controlled, which are output from each of one or more block power supply control circuits 17 among the at least one block power supply control circuit 17 included in the semiconductor chip 5 b. The permission signal and score are output from the main arbitration circuit 18 for one or more functional blocks 15 to be controlled.

[0064] According to this configuration, when an ON request is made to simultaneously supply power supply voltage to multiple functional blocks 15 in multiple semiconductor chips 5a and 5b, the timing of supplying power supply voltage to the multiple semiconductor chips 5 can be controlled based on the scores, thereby suppressing a drop in power supply voltage and the resulting malfunction.

[0065] Furthermore, in the semiconductor device 1a according to this embodiment, one semiconductor chip 5b among the plurality of semiconductor chips 5 is provided with an aggregation circuit 33 that aggregates power supply voltage on requests from at least one functional block 15 in that semiconductor chip 5b. This configuration makes it possible to reduce the number of signal lines between the plurality of semiconductor chips 5a and 5b. Furthermore, even if the number of semiconductor chips 5 increases, it is possible to suppress an increase in the processing load of the main arbitration circuit 18.

[0066] Furthermore, in the semiconductor device 1a according to this embodiment, each of the plurality of semiconductor chips 5 is provided with either a main arbitration circuit 18 that makes a simultaneous permission determination for the plurality of functional blocks 15 across the plurality of semiconductor chips 5, or a sub-arbitration circuit 19 that makes a simultaneous permission determination for at least one functional block 15 within that semiconductor chip 5b. With this configuration, even if the number of semiconductor chips 5 increases, it is possible to suppress an increase in the processing load of the main arbitration circuit 18 that controls all of the plurality of semiconductor chips 5.

[0067] Second Embodiment A semiconductor device 1 according to a second embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1a according to the first embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. FIG. 11 is a diagram showing an example of the configuration of a semiconductor device 1b according to the second embodiment. The semiconductor device 1b according to the second embodiment has multiple power domains 4. FIG. 11 illustrates power domains 4a and 4b as examples of the multiple power domains 4.

[0068] The power supply domains 4a and 4b are power supply domains with different power supply voltages. Here, the power supply domain 4a is an example of a first power supply voltage domain that operates at a first power supply voltage. The power supply domain 4b is an example of a second power supply voltage domain that operates at a second power supply voltage different from the first power supply voltage.

[0069] 11 has semiconductor chips 5a and 5b as the multiple semiconductor chips 5. The semiconductor chips 5a and 5b belong to two power supply domains 4a and 4b, and are electrically connected to the power supply management IC 3, respectively.

[0070] The semiconductor chip 5a includes circuit groups 6a and 6d, which are connected to the power supply domains 4a and 4b, respectively. The semiconductor chip 5b includes circuit groups 6b and 6e, which are connected to the power supply domains 4a and 4b, respectively.

[0071] Each of the circuit groups 6 a , 6 b , 6 d , and 6 e includes at least one switch 13 , at least one function block 15 , and at least one block power supply control circuit 17 .

[0072] In circuit groups 6a and 6b, at least one block power supply control circuit 17 is provided in always-on regions 9a and 9b that are constantly supplied with power supply voltage from power domain 4a. In circuit groups 6d and 6e, at least one block power supply control circuit 17 is provided in always-on regions 9d and 9e that are constantly supplied with power supply voltage from power domain 4b.

[0073] Furthermore, the semiconductor chip 5a has a main arbitration circuit 18 for each power supply domain 4. The semiconductor device 1b in Fig. 11 has main arbitration circuits 18a and 18d as the main arbitration circuits 18 for each power supply domain 4. The main arbitration circuits 18a and 18d are provided in the always-on regions 9a and 9d, respectively.

[0074] Furthermore, semiconductor chip 5b has a sub-arbitration circuit 19, a dividing circuit 31, and a consolidating circuit 33 for each power domain 4. Semiconductor device 1b in Fig. 11 has sub-arbitration circuits 19b and 19e, dividing circuits 31b and 31e, and consolidating circuits 33b and 33e as the sub-arbitration circuit 19, dividing circuit 31, and consolidating circuit 33 for each power domain 4. Sub-arbitration circuits 19b and 19e, dividing circuits 31b and 31e, and consolidating circuits 33b and 33e are provided in always-on regions 9b and 9e, respectively.

[0075] The main arbitration circuit 18a outputs an on-permission signal to each block power supply control circuit 17 of the circuit group 6a, and outputs an aggregated permission signal and an aggregated score to the sub-arbitration circuit 19b of the semiconductor chip 5b, based on the threshold value stored in the internal register, the power supply voltage on-request signals and scores received from each block power supply control circuit 17 of the circuit group 6a, and the aggregated on-request signal and aggregated score received from the aggregation circuit 33b of the semiconductor chip 5b. The main arbitration circuit 18d outputs an on-permission signal to each block power supply control circuit 17 of the circuit group 6d, and outputs an aggregated permission signal and an aggregated score to the sub-arbitration circuit 19e of the semiconductor chip 5b, based on the threshold value stored in the internal register, the power supply voltage on-request signals and scores received from each block power supply control circuit 17 of the circuit group 6d, and the aggregated on-request signal and aggregated score received from the aggregation circuit 33e of the semiconductor chip 5b.

[0076] As described above, the semiconductor device 1 according to this embodiment has the main arbitration circuit 18, the sub-arbitration circuit 19, the dividing circuit 31, and the consolidation circuit 33 for each system of the power supply domain 4. This configuration can accommodate cases where power supply domains 4 a, 4 b with different power supply voltages are provided, or where it is desired to suppress fluctuations in the power supply voltage.

[0077] Third Embodiment A semiconductor device 1 according to a third embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1a according to the first embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. FIG. 12 is a diagram showing an example of the configuration of a semiconductor device 1c according to the third embodiment. The semiconductor device 1c according to the third embodiment further includes at least one clock control circuit 21. Each of the at least one clock control circuit 21 includes a frequency control circuit configured to be able to change the frequency.

[0078] The circuit groups 7a and 7b of the semiconductor device 1c have a configuration in which the circuit groups 6a and 6b according to the first embodiment are further provided with at least one clock control circuit 21. Specifically, each of the at least one clock control circuit 21 is electrically connected between the functional block 15 and the block power supply control circuit 17, and outputs a clock signal CK to the connected functional block 15.

[0079] In the semiconductor device 1c, each of the at least one block power supply control circuits controls not only the connected functional block 15 but also the connected clock control circuit 21. After the supply of power supply voltage starts, each of the at least one block power supply control circuit outputs a clock control signal that controls the connected clock control circuit 21 based on the operating state of the connected functional block 15. Specifically, each of the at least one block power supply control circuit controls the connected clock control circuit 21 to control the on / off of the input of the clock signal CK to the controlled functional block 15 and the frequency of the input clock signal CK.

[0080] According to this configuration, after the supply of power supply voltage begins, the on / off and frequency of the clock signal CK can be controlled based on the operating state of the connected functional block 15, thereby reducing the power consumption of the functional block 15 to be controlled.

[0081] (Modification of Third Embodiment) The configuration according to this embodiment can be appropriately combined with at least one of the semiconductor device 1 according to each of the above-described embodiments and modifications.

[0082] For example, in the configuration of a semiconductor device 1 b in which a main arbitration circuit 18 is provided for each power domain 4 , a clock control circuit 21 may be provided between the functional block 15 and the block power control circuit 17 .

[0083] Fourth Embodiment A semiconductor device 1 according to a fourth embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1a according to the first embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. FIG. 13 is a diagram showing an example of the configuration of a semiconductor device 1d according to the fourth embodiment. In the semiconductor device 1d according to the fourth embodiment, the semiconductor chips 5a and 5b further include sub-arbitration circuits 19a and 19b, division circuits 31a and 31b, and aggregation circuits 33a and 33b in addition to the circuit groups 6a and 6b, similar to the semiconductor chip 5b of the semiconductor device 1a according to the first embodiment.

[0084] 13, the main arbitration circuit 18 is electrically connected to the aggregation circuit 33a of the semiconductor chip 5a and the aggregation circuit 33b of the semiconductor chip 5b. The main arbitration circuit 18 outputs an on-permission signal for the power supply voltage based on threshold values ​​for the semiconductor chips 5a and 5b stored in an internal register, the aggregation-on request signal and aggregation score received from the aggregation circuit 33a of the semiconductor chip 5a, and the aggregation-on request signal and aggregation score received from the aggregation circuit 33b of the semiconductor chip 5b.

[0085] In the main arbitration circuit 18 of the semiconductor device 1a according to the first embodiment, the on request signals from the block power control circuits 17 in the semiconductor chip 5a and the aggregated on request signal from the aggregated circuit 33 in the semiconductor chip 5b are handled at the same level. On the other hand, in the semiconductor device 1b according to the present embodiment, the aggregated on request signal is also output from the semiconductor chip 5a to the main arbitration circuit 18, so that the aggregated on request signals from both the semiconductor chips 5a and 5b can be handled at the same level in the main arbitration circuit 18.

[0086] (Modification of Fourth Embodiment) The configuration according to this embodiment can be appropriately combined with at least one of the semiconductor device 1 according to each of the above-described embodiments and modifications.

[0087] For example, in the configuration of semiconductor device 1b in which, for each power domain 4, a main arbitration circuit 18 is provided on semiconductor chip 5a, and a sub-arbitration circuit 19, a division circuit 31, and an aggregation circuit 33 are provided on semiconductor chip 5b, a sub-arbitration circuit 19, a division circuit 31, and an aggregation circuit 33 may further be provided on semiconductor chip 5a for each power domain 4.

[0088] For example, in the configuration of the semiconductor device 1c in which the clock control circuit 21 is provided between the functional block 15 and the block power supply control circuit 17, the sub-arbitration circuit 19, the dividing circuit 31, and the consolidation circuit 33 may be further provided on the semiconductor chip 5a.

[0089] For example, for each power domain 4, a main arbitration circuit 18, a sub-arbitration circuit 19, a division circuit 31, and an aggregation circuit 33 may be provided on the semiconductor chip 5a, and a sub-arbitration circuit 19, a division circuit 31, and an aggregation circuit 33 may be provided on the semiconductor chip 5b, and a clock control circuit 21 may be provided between the functional block 15 and the block power control circuit 17.

[0090] Fifth Embodiment A semiconductor device 1 according to a fifth embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1b according to the second embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. FIG. 14 is a diagram showing an example of the configuration of a semiconductor device 1e according to the fifth embodiment. The semiconductor device 1e according to the fifth embodiment further includes a semiconductor chip 5c as one of the multiple semiconductor chips 5. The semiconductor chip 5c has a configuration similar to that of, for example, the semiconductor chip 5b. Of course, in the circuit groups 6c and 6f of the semiconductor chip 5c, the number of functional blocks 15 and block power supply control circuits 17 may be the same as or different from those of the other semiconductor chips 5.

[0091] Furthermore, the semiconductor device 1e according to the fifth embodiment has a time division multiplexing circuit 25 for each power supply domain 4. In the example of Fig. 14, time division multiplexing circuits 25a and 25b are provided for the power supply domains 4a and 4b, respectively.

[0092] The time division multiplexing circuit 25a is provided in the always-on area 9b of the semiconductor chip 5b and is electrically connected to the main arbitration circuit 18a of the semiconductor chip 5a and the dividing circuits 31b and 31c and consolidating circuits 33b and 33c of the semiconductor chips 5b and 5c. The time division multiplexing circuit 25b is provided in the always-on area 9e of the semiconductor chip 5b and is electrically connected to the main arbitration circuit 18d of the semiconductor chip 5a and the dividing circuits 31e and 31f and consolidating circuits 33e and 33f of the semiconductor chips 5b and 5c.

[0093] The time division multiplexing circuits 25 a and 25 b time division multiplex the aggregation-on request signals and aggregation score signals output from each aggregation circuit 33 for each power domain 4 .

[0094] In this way, the semiconductor device 1 according to this embodiment time-division multiplexes communications between the multiple semiconductor chips 5. With this configuration, when the number of semiconductor chips 5 to be controlled increases to three or more, the number of connection wires between the semiconductor chips 5 increases with each increase in the number of chips. However, by multiplexing the request signals and score signals from each semiconductor chip 5, it is possible to suppress an increase in the number of signal wires to the semiconductor chip 5a having the main arbitration circuit 18.

[0095] (Modification of Fifth Embodiment) The configuration according to this embodiment can be appropriately combined with at least one of the semiconductor device 1 according to each of the above-described embodiments and modifications.

[0096] For example, for multiple semiconductor chips 5a to 5c connected to only one power domain 4, the main arbitration circuit 18 of the semiconductor chip 5a and the division circuits 31b, 31c and aggregation circuits 33b, 33 of the semiconductor chips 5b, 5c may each be connected via a time division multiplexing circuit 25.

[0097] For example, in a configuration in which a main arbitration circuit 18 is provided on semiconductor chip 5a together with a sub-arbitration circuit 19, a division circuit 31, and an aggregation circuit 33 in relation to multiple semiconductor chips 5a to 5c, each of the division circuits 31a to 31c and aggregation circuits 33a to 33c of the multiple semiconductor chips 5a to 5c may be connected via a time division multiplexing circuit 25.

[0098] For example, in the configuration of the semiconductor device 1 c in which the clock control circuit 21 is provided between the functional block 15 and the block power supply control circuit 17 , the semiconductor chips 5 may be connected via a time division multiplexing circuit 25 .

[0099] Sixth Embodiment A semiconductor device 1 according to a sixth embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1e according to the fifth embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. FIG. 15 is a diagram showing an example of the configuration of a semiconductor device 1f according to the sixth embodiment. Unlike the semiconductor device 1e according to the fifth embodiment, the semiconductor device 1f according to the sixth embodiment does not include a time division multiplexing circuit 25, but does include a communication master circuit 27 and at least one communication slave circuit 29.

[0100] 15 illustrates at least one communication slave circuit 29, which includes a communication slave circuit 29a provided on semiconductor chip 5b and a communication slave circuit 29b provided on semiconductor chip 5c. The communication master circuit 27, the communication slave circuit 29a, and the communication slave circuit 29b are connected in series using signal lines for serial communication. Here, the communication master circuit 27 is an example of a second communication circuit. The communication slave circuit 29a is an example of a first communication circuit.

[0101] The communication master circuit 27 is provided in the always-on area 9a of the semiconductor chip 5a and is electrically connected by serial communication signal lines to the main arbitration circuit 18a in the always-on area 9a of the semiconductor chip 5a and the main arbitration circuit 18d in the always-on area 9d of the semiconductor chip 5a. The communication slave circuit 29a is provided in the always-on area 9b of the semiconductor chip 5b and is electrically connected by serial communication signal lines to the divided circuit 31b and the aggregated circuit 33b in the always-on area 9b of the semiconductor chip 5b and to the divided circuit 31e and the aggregated circuit 33e in the always-on area 9e of the semiconductor chip 5b. In addition, the communication slave circuit 29b is provided in the always-on area 9c of the semiconductor chip 5c, and is electrically connected by signal lines for serial communication to each of the split circuit 31c and aggregation circuit 33c in the always-on area 9c of the semiconductor chip 5c, and to each of the split circuit 31f and aggregation circuit 33f in the always-on area 9f of the semiconductor chip 5f.

[0102] Therefore, in the example of Figure 15, the communication master circuit 27, the multiple communication slave circuits 29a and 29b, the dividing circuits 31b, 31c, 31e, and 31f, and the consolidating circuits 33b, 33c, 33e, and 33f are connected in series using signal lines for serial communication.

[0103] Furthermore, in the semiconductor device 1f according to the sixth embodiment, an ID is assigned to each power supply domain 4 of each semiconductor chip 5 to uniquely identify it.

[0104] For example, an ID for uniquely identifying the semiconductor chip 5 and power domain 4 of the own circuit is predetermined and stored in the internal memory of each of the at least one block power control circuit 17. Then, each of the at least one block power control circuit 17 outputs the ID assigned to the own circuit together with an on-request signal and a score to the next stage connected in series.

[0105] For example, the storage of the predetermined ID in the internal memory and its output may be realized by the aggregation circuit 33 at the next stage of the block power supply control circuit 17 that output the on-request signal and the serial signal of the score, or may be realized by each of the communication master circuit 27, the communication slave circuit 29a, and the communication slave circuit 29b that received the serial signal. In this case, an ID may be used to uniquely identify the aggregation circuit 33 that output the on-request signal (or aggregated on-request signal) and the serial signal of the score.

[0106] Also, for example, the main arbitration circuit 18 temporarily holds the on request signal (or aggregate on request signal) and the ID attached to the score, and outputs the held ID together with the permission signal (or aggregate permission signal) to the next stage connected in series.

[0107] In this way, the semiconductor device 1 according to this embodiment connects the signal wiring for the on request and the score of each semiconductor chip 5 in series. Furthermore, in the semiconductor device 1 according to this embodiment, when there is data to be transmitted (output), each semiconductor chip 5 transmits the assigned ID along with the data to the next stage, and when there is no data to be transmitted (output), it transfers the data and ID from the previous stage to the next stage. Specifically, the communication master circuit 27 and each of the multiple communication slave circuits 29 a, 29 b determine whether to receive or transfer data based on the ID. The ID may be a destination ID indicating the destination, or a source ID indicating the source.

[0108] According to this configuration, request signals and score serial signals can be transmitted and received between the semiconductor chips 5 via signal lines for one-way serial communication, which prevents an increase in the number of signal wires to the semiconductor chip 5a having the main arbitration circuit 18 and further reduces the number of signal wires between the semiconductor chips 5. Furthermore, when the number of semiconductor chips 5 to be controlled increases to three or more, the number of connection wires between the semiconductor chips 5 increases with each increase in the number of chips, but this increase can be prevented.

[0109] (Modification of Sixth Embodiment) The configuration according to this embodiment can be appropriately combined with at least one of the semiconductor device 1 according to each of the above-described embodiments and modifications.

[0110] Seventh Embodiment A semiconductor device 1 according to a seventh embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1a according to the first embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. Figure 16 is a diagram showing an example of the configuration of a semiconductor device 1g according to the seventh embodiment.

[0111] 16 may have a main arbitration circuit 18 provided in a semiconductor chip 5a near (for example, closest to) the power management IC 3 on the substrate 2. The main arbitration circuit 18 provided in this semiconductor chip 5a receives on-request signals and scores from each block power supply control circuit 17 in the semiconductor chip 5a and aggregated on-request signals and scores from each aggregated circuit 33 in the semiconductor chips 5b to 5d, and outputs a permission signal and an aggregated permission signal based on the score of each block power supply control circuit 17.

[0112] (Modification of Seventh Embodiment) The configuration according to this embodiment can be appropriately combined with at least one of the semiconductor device 1 according to each of the above-described embodiments and modifications.

[0113] Eighth Embodiment A semiconductor device 1 according to an eighth embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1g according to the seventh embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. FIG. 17 is a diagram showing an example of the configuration of a semiconductor device 1h according to the eighth embodiment.

[0114] The semiconductor device 1g in FIG. 17 has multiple power management ICs 3a and 3b on a substrate 2. Thus, the semiconductor device 1g may have a different power management IC 3 for each power domain 4. In this case, for example, a main arbitration circuit 18 may be provided in each of the semiconductor chips 5a and 5d that are near (e.g., closest to) the power management ICs 3a and 3b. The main arbitration circuit 18a provided in the semiconductor chip 5a receives on-request signals and scores from each block power control circuit 17 of the semiconductor chip 5a and aggregated on-request signals and scores from each aggregated circuit 33 of the semiconductor chips 5b to 5d, and outputs a permission signal and an aggregated permission signal based on the scores of each block power control circuit 17. The main arbitration circuit 18d provided in the semiconductor chip 5d receives on-request signals and scores from each block power control circuit 17 of the semiconductor chip 5d and aggregated on-request signals and scores from each aggregated circuit 33 of the semiconductor chip 5c, and outputs a permission signal and an aggregated permission signal based on the scores of each block power control circuit 17.

[0115] (Modification of Eighth Embodiment) The configuration according to this embodiment can be appropriately combined with at least one of the semiconductor device 1 according to each of the above-described embodiments and modifications.

[0116] Ninth Embodiment A semiconductor device 1 according to a ninth embodiment of the present disclosure will be described. Here, differences from the semiconductor device 1g according to the seventh embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate. Figure 18 is a diagram showing an example of the configuration of a semiconductor device 1i according to the ninth embodiment.

[0117] 18, the semiconductor chips 5a and 5c may be provided with a main arbitration circuit 18 and a sub-arbitration circuit 19, and the semiconductor chips 5b and 5d may be provided with a sub-arbitration circuit 19. The power supply domain 4a supplies a power supply voltage across a portion of the semiconductor chip 5a and a portion of the semiconductor chip 5b. The power supply domain 4b supplies a power supply voltage across a portion of the semiconductor chip 5a, a portion of the semiconductor chip 5b, a portion of the semiconductor chip 5c, and a portion of the semiconductor chip 5d. The power supply domain 4c supplies a power supply voltage across a portion of the semiconductor chip 5c and a portion of the semiconductor chip 5d. The main arbitration circuit 18a provided in the semiconductor chip 5a controls the power supply domains 4a and 4b. The main arbitration circuit 18c provided in the semiconductor chip 5c controls the power supply domain 4c.

[0118] (Modification of the Ninth Embodiment) The configuration according to this embodiment can be appropriately combined with at least one of the semiconductor device 1 according to each of the above-described embodiments and modifications.

[0119] In each of the above-described embodiments, part or all of each circuit may be configured with hardware, or may be configured with information processing software (programs) executed by a CPU, etc. In addition, in each of the above-described embodiments, when multiple memories store data, each of the multiple memories may store only a portion of the data, or may store the entire data.

[0120] As described above, according to at least one embodiment of the present disclosure, it is possible to appropriately control the timing of supplying power supply voltages across multiple semiconductor chips.

[0121] Although the embodiments of the present disclosure have been described in detail above, these embodiments are presented as examples and are not intended to be limiting. Each embodiment can be modified by various additions, changes, substitutions, partial deletions, combinations, etc., without departing from the technical spirit of the present invention. These embodiments and their modifications are included within the scope of the invention described in the claims and their equivalents.

[0122] REFERENCE SIGNS LIST 1 semiconductor device 2 substrate 3 power management IC 4 power domain 5 semiconductor chip 6, 7 circuit group 9 always-on area 13 switch 15 functional block 17 block power control circuit 18 main arbitration circuit 19 sub-arbitration circuit 21 clock control circuit 25 time division multiplexing circuit 27 communication master circuit 29 communication slave circuit 31 division circuit 32 aggregation request storage memory 33 aggregation circuit 191 request acceptance circuit 193 request storage memory 195 simultaneous permission determination circuit 197 simultaneous permission transmission circuit 201 enqueue entry 202 aggregation entry 203 enqueue data 204 enqueue data 205 simultaneous permission flag 311 division permission transmission circuit 331 request acceptance circuit 333 aggregation request transmission circuit

Claims

1. A semiconductor device, comprising: a substrate; a first semiconductor chip disposed on the substrate; and a second semiconductor chip disposed on the substrate, wherein each of the first semiconductor chip and the second semiconductor chip includes at least one functional block and at least one block power control circuit that is electrically connected to one or more of the at least one functional block and controls supply of a power voltage to each of the one or more functional blocks, the first semiconductor chip further includes an aggregation circuit that aggregates an on-request signal requesting start of supply of a power voltage for each of the one or more functional blocks to be controlled, which is output from each of one or more of the block power control circuits included in the first semiconductor chip, and a score based on parasitic capacitance, and outputs an aggregated on-request signal and an aggregated score, and the second semiconductor chip further includes a main arbitration circuit that outputs a permission signal permitting start of supply of a power voltage to the one or more block power control circuits that output the on-request signals of the first semiconductor chip and the second semiconductor chip, based on the aggregated on-request signal and the aggregated score from the aggregation circuit, and on-request signals requesting start of supply of a power voltage for each of the one or more functional blocks to be controlled, and scores based on parasitic capacitance, which are output from each of one or more of the block power control circuits included in the second semiconductor chip.

2. The semiconductor device according to claim 1, wherein the first semiconductor chip further includes a division circuit that receives the permission signal from the second semiconductor chip and outputs the permission signal and the score corresponding to a block power control circuit to be permitted among the at least one block power control circuit included in the first semiconductor chip, based on the permission signal, and a sub-arbitration circuit that outputs a permission signal permitting start of supply of a power voltage to the one or more block power control circuits that output the on-request signals in the first semiconductor chip, based on the permission signal and the score output from the division circuit.

3. A semiconductor device having a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on the substrate, each of the first semiconductor chip and the second semiconductor chip having at least one functional block, at least one block power control circuit electrically connected to one or more of the at least one functional block and controlling the supply of a power voltage to each of the one or more functional blocks, and an aggregation circuit that aggregates an on-request signal for requesting the start of supply of a power voltage for each of the one or more functional blocks to be controlled, output from each of one or more of the plurality of block power control circuits included in each, and a score based on parasitic capacitance, to output an aggregated on-request signal and an aggregated score, the second semiconductor chip further having a main arbitration circuit that outputs a permission signal for permitting the start of supply of a power voltage to the one or more block power control circuits that output the on-request signal, based on the aggregated on-request signal and the aggregated score from the aggregation circuits of the first semiconductor chip and the second semiconductor chip.

4. Each of the first semiconductor chip and the second semiconductor chip further has a division circuit that receives the permission signal from the main arbitration circuit and outputs the permission signal and the score corresponding to the block power control circuit to be permitted among the at least one block power control circuit included in each, based on the permission signal, and a sub-arbitration circuit that outputs a permission signal for permitting the start of supply of a power voltage to the one or more block power control circuits that output the on-request signal included in the first semiconductor chip, based on the permission signal and the score output from the division circuit. The semiconductor device according to claim 3.

5. The main arbitration circuit of the semiconductor device according to claim 1 calculates the total value of the scores input during a set period and outputs the permission signal based on the comparison result between the total value and a predetermined threshold value.

6. The main arbitration circuit of the semiconductor device according to claim 5 calculates the total value based on the priorities set for the plurality of functional blocks included in the first semiconductor chip and the second semiconductor chip.

7. Each of the first semiconductor chip and the second semiconductor chip has a first power supply voltage region operating at a first power supply voltage and a second power supply voltage region operating at a second power supply voltage different from the first power supply voltage. The second semiconductor chip has the main arbitration circuit in each of the first power supply voltage region and the second power supply voltage region. The semiconductor device according to claim 1.

8. Each of the at least one block power control circuit has a clock control circuit that controls on / off and frequency of a clock signal input to the one or more functional blocks based on an operating state of the one or more functional blocks to be controlled. The semiconductor device according to claim 1.

9. Further comprising a third semiconductor chip disposed on the substrate. The third semiconductor chip has at least one functional block, at least one block power control circuit each electrically connected to one or more functional blocks of the at least one functional block and controlling supply of a power supply voltage to each of the one or more functional blocks, and an aggregation circuit that aggregates an on request signal requesting start of supply of a power supply voltage for each of the one or more functional blocks to be controlled and output from each of one or more of the block power control circuits included in the third semiconductor chip, and a score based on parasitic capacitance, and outputs an aggregated on request signal and an aggregated score. The first semiconductor chip is electrically connected between each of the aggregation circuits of the first semiconductor chip and the second semiconductor chip and the main arbitration circuit of the second semiconductor chip, and further has a time division multiplexing circuit that time division multiplexes signals of the aggregated on request signal and the aggregated score from each of the aggregation circuits of the first semiconductor chip and the second semiconductor chip and outputs the multiplexed signals to the main arbitration circuit of the second semiconductor chip. The semiconductor device according to claim 1.

10. The first semiconductor chip is electrically connected to the integrated circuit, and further includes a first communication circuit that transfers the integrated on-request signal and the serial signal of the integrated score from the integrated circuit to the second semiconductor chip via a signal line for serial communication. The second semiconductor chip is electrically connected to the main arbitration circuit, transfers the permission signal from the main arbitration circuit to the first semiconductor chip via the signal line for serial communication, and further includes a second communication circuit that receives the integrated on-request signal and the serial signal of the integrated score from the first semiconductor chip and outputs them to the main arbitration circuit. The semiconductor device according to claim 2.

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