Semiconductor device and method for producing same

Abstract

This semiconductor device is provided with: an external terminal in which a first portion, a second portion, and a third portion are connected in order, and the third portion includes a connection surface that orients to the opposite direction from the surface facing the second portion; a semiconductor chip that is connected to the connection surface of the external terminal; a wiring line that is disposed on the same plane level as the third portion of the external terminal; and a sealing resin that covers the semiconductor chip, the external terminal, and the wiring line. When viewed from the thickness direction in which the first portion, the second portion, and the third portion are connected, the area of the connection surface is smaller than the area of the first portion.

Description

Semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0002] The characteristics of semiconductor chips containing semiconductor elements such as transistors and diodes are affected by surface contamination and static electricity. For this reason, molded packages are used, in which the semiconductor chip and its surroundings are covered with a sealing resin, which is a resin-based insulating material.

[0003] Japanese Patent Application Laid-Open No. 2021-93454

[0004] [Summary] In a molded package semiconductor device, terminals (hereinafter also referred to as "external terminals") connecting a semiconductor chip inside the molded package to the outside of the molded package pass through the inside of the encapsulating resin. Furthermore, wiring is arranged inside the encapsulating resin so as not to come into contact with the external terminals. An object of the present disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device that can improve the degree of freedom in the layout of wiring arranged inside the encapsulating resin.

[0005] One aspect of the present disclosure is a semiconductor device comprising: an external terminal in which a first part, a second part, and a third part are connected in order, the third part including a connection surface facing opposite to the surface facing the second part; a semiconductor chip connected to the connection surface of the external terminal; wiring arranged at the same plane level as the third part of the external terminal; and a sealing resin covering the semiconductor chip, the external terminal, and the wiring, wherein the area of ​​the connection surface when viewed from the thickness direction in which the first part, second part, and third part are connected is smaller than the area of ​​the first part.

[0006] Another aspect of the present disclosure is a method for manufacturing a semiconductor device, including forming a first portion of an external terminal on an upper surface of a substrate, forming a second portion of the external terminal on an upper surface of the first portion with at least a wider spacing between the upper surfaces than the first portion, covering the first and second portions with a first sealing resin, exposing an upper surface of the second portion from the first sealing resin, forming a third portion of the external terminal on an upper surface of the second portion with a wider spacing than the first portion, forming wiring on the upper surface of the first sealing resin at a position separated from the third portion, placing a semiconductor chip above the first sealing resin so as to connect to the third portion, forming a second sealing resin so as to cover the first sealing resin, and covering the semiconductor chip, the wiring, and the third portion with the second sealing resin.

[0007] FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to an embodiment. FIG. 2 is a schematic plan view showing the structure of a semiconductor device according to an embodiment. FIG. 3 is a schematic cross-sectional view showing the structure of a semiconductor device according to a comparative example. FIG. 4A is a schematic conceptual view showing an example of the arrangement of external terminals and wiring in a semiconductor device according to an embodiment. FIG. 4B is a schematic conceptual view showing another example of the arrangement of external terminals and wiring in a semiconductor device according to an embodiment. FIG. 5A is a schematic conceptual view showing an example of the arrangement of external terminals and wiring in a semiconductor device according to a comparative example. FIG. 5B is a schematic conceptual view showing another example of the arrangement of external terminals and wiring in a semiconductor device according to a comparative example. FIG. 6A is a perspective view showing an example of the appearance of a semiconductor device according to an embodiment. FIG. 6B is a perspective view showing an example of the appearance of a semiconductor device according to an embodiment, as viewed from another direction. FIG. 7A is a perspective view showing another example of the appearance of a semiconductor device according to an embodiment. FIG. 7B is a perspective view showing another example of the appearance of a semiconductor device according to an embodiment, as viewed from another direction. FIG. 8 is a schematic view showing an example of the configuration of a semiconductor device having a printed circuit board. FIG. 9A is a schematic cross-sectional view showing an example of connecting a wiring pattern on a printed circuit board to an external electrode. 9B is a schematic cross-sectional view showing another example of connecting a wiring pattern of a printed circuit board to an external electrode. FIG. 9C is a schematic cross-sectional view showing yet another example of connecting a wiring pattern of a printed circuit board to an external electrode. FIG. 9D is a schematic cross-sectional view showing yet another example of connecting a wiring pattern of a printed circuit board to an external electrode. FIG. 10 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment (part 1). FIG. 11 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment (part 2). FIG. 12 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment (part 3). FIG. 13 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment (part 4). FIG. 14 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment (part 5). FIG. 15 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment (part 6). FIG. 16 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment (part 7).FIG. 17 is a schematic cross-sectional view (part 8) illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 18 is a schematic cross-sectional view (part 9) illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 19 is a schematic cross-sectional view (part 10) illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 20 is a schematic cross-sectional view (part 11) illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 21 is a schematic cross-sectional view (part 12) illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 22A is a schematic plan view illustrating an example of a positional relationship between the first portion and the third portion of a semiconductor device according to an embodiment. FIG. 22B is a schematic plan view illustrating another example of a positional relationship between the first portion and the third portion of a semiconductor device according to an embodiment. FIG. 23 is a schematic cross-sectional view illustrating another example of a relationship between the cross-sectional areas of the second portion and the third portion of a semiconductor device according to an embodiment. FIG. 24A is a schematic cross-sectional view illustrating another example of a shape of the second portion of a semiconductor device according to an embodiment. FIG. 24B is a schematic cross-sectional view illustrating yet another example of a shape of the second portion of a semiconductor device according to an embodiment. FIG. 25 is a schematic cross-sectional view illustrating a structure of a semiconductor device including multilayer wiring. FIG. 26 is a schematic cross-sectional view showing an example of the structure of a semiconductor device in which a plurality of semiconductor chips are covered with a sealing resin.

[0008] [Detailed Description] Next, embodiments will be described with reference to the drawings. In the following description of the drawings, identical or similar parts are designated by identical or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each part, etc. may differ from the actual ones. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships or ratios.

[0009] Furthermore, the embodiments described below are merely examples of devices or methods for embodying the technical ideas, and are not intended to limit the shape, structure, arrangement, etc. of the components to those described below. Various modifications can be made to these embodiments within the scope of the claims.

[0010] As shown in FIG. 1 , the semiconductor device 1 according to the embodiment includes an external terminal 10, a semiconductor chip 20, wiring 30, and a sealing resin 40. The external terminal 10 includes a first portion 11, a second portion 12, and a third portion 13 connected in this order. The third portion 13 includes a connection surface 100 facing away from the surface facing the second portion 12. The semiconductor chip 20 connects to the connection surface 100 of the external terminal 10. The wiring 30 is disposed at the same plane level as the third portion 13 of the external terminal 10. The sealing resin 40 covers the external terminal 10, the semiconductor chip 20, and the wiring 30. In the semiconductor device 1, the area of ​​the connection surface 100 when viewed from the thickness direction in which the first portion 11, the second portion 12, and the third portion 13 are connected is set to be smaller than the area of ​​the first portion 11. Hereinafter, the area of ​​a cross section perpendicular to the thickness direction of the external terminal 10 will also be referred to as the "cross-sectional area." The cross-sectional area is the area of ​​a cross section parallel to the connection surface 100 of the external terminal 10 .

[0011] As shown in FIG. 1 , the thickness direction of the sealing resin 40 and the external terminals 10 is the Z direction. In FIG. 1 , the Z direction is the up-down direction on the paper. The plane perpendicular to the Z direction is the XY plane defined by the X and Y directions. The connection surface 100 is parallel to the XY plane. In FIG. 1 , the X direction is the left-right direction on the paper, and the Y direction is the depth direction on the paper. In this disclosure, in the Z direction, the direction in which the semiconductor chip 20 is located as viewed from the external terminals 10 is the upward direction, and the direction in which the external terminals 10 are located as viewed from the semiconductor chip 20 is the downward direction. With regard to the components of the semiconductor device 1, the upward facing surface is also referred to as the upper surface, and the downward facing surface is also referred to as the lower surface. For example, the connection surface 100 is the upper surface of the external terminal 10. The surface facing the external terminal 10 is the lower surface of the semiconductor chip 20. The surface connecting the upper and lower surfaces is also referred to as the side surface.

[0012] The second portion 12 of the external terminal 10 is an intermediate portion of the external terminal 10 that connects the first portion 11 and the third portion 13. The side surface of the second portion 12 shown in FIG. 1 is parallel to the axial direction of the external terminal 10 extending from the first portion 11 toward the third portion 13 when viewed from the Y direction.

[0013] A portion of the surface of the first portion 11 of the external terminal 10 is exposed from the sealing resin 40. In the semiconductor device 1 shown in FIG. 1 , the bottom surface of the first portion 11 facing away from the top surface connected to the second portion 12 is exposed from the sealing resin 40. The semiconductor chip 20 can also be electrically or thermally connected to the outside of the sealing resin 40 via the external terminal 10. For this reason, a conductive material may be used for the external terminal 10.

[0014] For example, the electrode terminals of the semiconductor chip 20 may be electrically connected to signal terminals, ground terminals, or power supply terminals of a device arranged outside the sealing resin 40 via the conductive external terminals 10. Alternatively, heat generated in the semiconductor chip 20 may be dissipated to the outside of the sealing resin 40 via the external terminals 10.

[0015] The sealing resin 40 has a laminated structure of a first sealing resin 41 and a second sealing resin 42. The first portion 11 and the second portion 12 of the external terminal 10 are covered with the first sealing resin 41. The semiconductor chip 20, the wiring 30, and the third portion 13 of the external terminal 10 are covered with the second sealing resin 42. The wiring 30 is disposed on the surface of the first sealing resin 41 that faces the second sealing resin 42. In addition, the interface between the second portion 12 and the third portion 13 of the external terminal 10 is at the same plane level as the boundary between the first sealing resin 41 and the second sealing resin 42.

[0016] The semiconductor device 1 may include a plurality of external terminals 10. The wiring 30 is disposed between the external terminals 10. The semiconductor device 1 shown in FIG. 1 includes two external terminals 10 when viewed in the Y direction, but it goes without saying that the semiconductor device 1 may have more than two external terminals 10. The wiring 30 electrically connects, for example, an electrode terminal of the semiconductor chip 20 to an external electrode (not shown in FIG. 1 ) whose surface is partially exposed outside the sealing resin 40. For example, input / output signals of the semiconductor chip 20 may be transmitted via the wiring 30.

[0017] 2 shows a plan view of the semiconductor device 1 as viewed from the Z direction. In FIG. 2, the first portion 11 and the third portion 13 of the external terminal 10 are shown through the semiconductor chip 20. The wiring 30 electrically connects the electrode terminal (not shown) arranged on the underside of the semiconductor chip 20 to the external electrode 60 exposed to the outside of the sealing resin 40. As described above, the semiconductor chip 20 can be electrically connected to a device external to the semiconductor device 1 via the wiring 30.

[0018] 2 shows an example in which the external terminals 10 are arranged at the four corners of the semiconductor chip 20 when viewed from the Z direction (hereinafter also referred to as "plan view"), but the positions of the external terminals 10 are not limited to the four corners of the semiconductor chip 20. For example, the external terminals 10 may be arranged in the central region of the semiconductor chip 20. Also, an example in which the external electrodes 60 are arranged on the side surfaces of the sealing resin 40 is shown, but the positions at which the external electrodes 60 are arranged can be set arbitrarily, and they may be arranged above or below the semiconductor chip 20, for example.

[0019] As already mentioned, the cross-sectional area of ​​the external terminal 10 is narrower in the third portions 13 than in the first portions 11. In other words, as shown in FIG. 2 , the spacing between the third portions 13 is wider than the spacing between the first portions 11 in a plan view. In the semiconductor device 1, the wiring 30 passes between the third portions 13 of the external terminals 10. Therefore, the number of wirings 30 can be made larger in the semiconductor device 1 than in a comparative semiconductor device that includes external terminals with a constant cross-sectional area (hereinafter also referred to as "comparative terminals 10M") as shown in FIG. 3 . In the comparative semiconductor device shown in FIG. 3 , the spacing between the comparative terminals 10M is constant, equal to the spacing between the first portions 11 of the external terminals 10.

[0020] The number of wirings that can be arranged in each of the semiconductor device 1 and the semiconductor device of the comparative example will be compared below with reference to FIGS. 4A and 4B and FIGS. 5A and 5B.

[0021] 4A and 4B are schematic conceptual diagrams showing the positional relationship between the external terminals 10 and the wirings 30 in a plan view of the semiconductor device 1. As shown in FIGS. 4A and 4B, the wirings 30 can also be arranged in a region that overlaps with the first portion 11 in a plan view. For example, in the arrangement shown in FIG. 4A, two wirings 30 extending in the Y direction can be arranged adjacent to each other along the X direction between the external terminals 10. Furthermore, as shown in FIG. 4B, the portions of two wirings 30 that extend in the X direction and whose direction changes from the Y direction to the X direction can also be arranged adjacent to each other along the Y direction between the external terminals 10.

[0022] 5A and 5B are schematic conceptual diagrams showing the positional relationship between external terminals (comparison terminals 10M) and wiring 30 of a semiconductor device of a comparative example. As shown in FIG. 5A, only one wiring 30 extending in the Y direction can be placed between the comparison terminals 10M. Also, as shown in FIG. 5B, only one wiring 30 whose direction changes from the Y direction to the X direction can be placed between the comparison terminals 10M. In other words, the number of wirings 30 that can be placed between the comparison terminals 10M is fewer than the number of wirings 30 that can be placed between the external terminals 10 shown in FIGS. 4A and 4B.

[0023] As described above, by arranging the wiring 30 between the third portions 13, which have a cross-sectional area relatively narrower than that of the first portions 11, the number of wirings 30 can be increased compared to arranging the wirings 30 between the first portions 11.

[0024] As described above, in the semiconductor device 1, the cross-sectional area of ​​the external terminal 10 is made narrower in the third portion 13 than in the first portion 11, and the wiring 30 is arranged at the same planar level as the third portion 13. This allows the semiconductor device 1 to increase the degree of freedom in the layout of the wiring 30 arranged inside the sealing resin 40.

[0025] 6A and 6B show examples of the external appearance of the semiconductor device 1. The external electrodes 60 of the semiconductor device 1 shown in Figures 6A and 6B are electrically connected to the semiconductor chip 20 by wiring 30 arranged inside the sealing resin 40. The external terminals 10 shown in Figure 6B may be used, for example, as ground electrodes of the semiconductor chip 20, or as heat dissipation components thermally connected to the semiconductor chip.

[0026] 6A and 6B show an example in which the external electrodes 60 are arranged from the main surface to the side surfaces at the outer edge of the sealing resin 40. Alternatively, as shown in Figures 7A and 7B, the external electrodes 60 may be arranged only on the main surface at the outer edge of the sealing resin 40. In other words, it is possible to arbitrarily set in which region of the sealing resin 40 the external electrodes 60 are arranged.

[0027] 8 shows an example of the configuration of a semiconductor device 1 having a printed circuit board 70. The printed circuit board 70 includes a wiring pattern 71 that is electrically connected to the external electrodes 60. The wiring pattern 71 extends outward from the side surface of the sealing resin 40. For example, the external electrodes 60 arranged on the outer edge of the sealing resin 40 are electrically connected to the wiring pattern 71 by a bonding material 80. The semiconductor chip 20 can be electrically connected to an external device via the wiring pattern 71 of the printed circuit board 70. For example, the semiconductor chip 20 can be electrically connected to a device mounted on the printed circuit board 70.

[0028] FIG. 9A shows an example in which an external electrode 60 and a wiring pattern 71 of a printed circuit board 70 are connected by a bonding material 80. The bonding material 80 may be, for example, solder. In FIG. 9A , the side surfaces of the external electrode 60 protrude outward from the side surfaces of the sealing resin 40, and the bottom surface of the external electrode 60 protrudes downward from the bottom surface of the sealing resin 40. However, the positional relationship between the side surfaces and bottom surfaces of the external electrode 60 and the sealing resin 40 is not limited to the above. For example, as shown in FIG. 9B , the side surfaces of the external electrode 60 and the sealing resin 40 may be flush with each other, and the bottom surface of the external electrode 60 and the sealing resin 40 may also be flush with each other. As shown in FIG. 9C , the side surfaces of the sealing resin 40 may protrude outward from the side surfaces of the external electrode 60, and the bottom surface of the sealing resin 40 may protrude downward from the bottom surface of the external electrode 60. Alternatively, as shown in FIG. 9D , the side surfaces of the sealing resin 40 may protrude outward from the side surfaces of the external electrode 60, and the bottom surface of the external electrode 60 and the bottom surface of the sealing resin 40 may be flush with each other. In this way, the positional relationship between the side and bottom surfaces of the external electrodes 60 and the sealing resin 40 is arbitrary.

[0029] A method for manufacturing the semiconductor device 1 according to the embodiment will be described below with reference to the drawings. Note that the method for manufacturing the semiconductor device 1 described below is one example, and the semiconductor device 1 can be manufactured by various other manufacturing methods, including variations thereof. The following describes, as an example, a case where a copper (Cu) film is used for the external terminals 10 and the wiring 30.

[0030] First, as shown in FIG. 10 , a seed film 300 is formed on the upper surface of a substrate 200. For example, the seed film 300 is formed by sputtering. For example, a silicon (Si) substrate may be used for the substrate 200. For example, a glass substrate or a sapphire substrate may be used for the substrate 200. For example, a titanium (Ti) / Cu laminated film may be used for the seed film 300. The Ti layer adheres the resin and the Cu layer. Instead of the Ti layer, a titanium tungsten (TiW) alloy film or a tantalum (Ta) film may be used.

[0031] 11 , a plurality of first resist films 401 are formed at first intervals D1 on the upper surface of the seed film 300. For example, the first resist film 401 is applied to the entire surface of the seed film 300, and then the first resist film 401 is patterned by photolithography. A dry film resist (DFR) may be used as the first resist film 401.

[0032] 12 , the first portions 11 of the external terminals 10 are formed between the first resist films 401. For example, a Cu plated film is formed as the first portions 11 using the Cu layer of the seed film 300 as a seed film for electrolytic plating. As a result, the first portions 11 of the external terminals 10 are formed on the upper surface of the substrate 200.

[0033] 13 , a plurality of second resist films 402 are formed on the upper surfaces of the first resist film 401 and the first portions 11 at second intervals D2 narrower than the first intervals D1 so that a portion of the upper surface of the first portions 11 is exposed between the second resist films 402. For example, the second resist film 402 is applied to the entire surface, and then the second resist film 402 is patterned by photolithography. DFR may be used for the second resist film 402.

[0034] 14 , second portions 12 that connect to the first portions 11 are formed between the second resist films 402. For example, a Cu plating film is formed as the second portions 12. As a result, the second portions 12 of the external terminals 10 are formed on the upper surfaces of the first portions 11 with a narrower spacing parallel to the upper surface of the substrate 200 than the first portions 11. At this time, the second portions 12 are formed on the upper surfaces of the first portions 11 with a wider spacing at least on the upper surfaces than the first portions 11.

[0035] 15 , the first resist film 401, the second resist film 402, and the seed film 300 are removed. That is, after the first portion 11 and the second portion 12 are formed while the first resist film 401 and the second resist film 402 remain, the first resist film 401 and the second resist film 402 are simultaneously removed. This reduces the number of steps compared to removing the first resist film 401 and the second resist film 402 separately. As a result, the first portion 11 and the second portion 12 of the external terminal 10 are formed on the upper surface of the substrate 200.

[0036] Next, a first sealing resin 41 is formed to cover the first portion 11 and the second portion 12 of the external terminal 10. Then, as shown in FIG. 16 , the upper surface of the first sealing resin 41 is ground so that the upper surface of the second portion 12 is exposed.

[0037] 17 , the third portion 13 of the external terminal 10 and the wiring 30 are formed. The third portion 13 of the external terminal 10 is formed on the upper surface of the second portion 12 at a narrower distance parallel to the upper surface of the substrate 200 than the first portion 11. For example, the third portion 13 and the wiring 30 may be formed by the same process as the method for forming the second portion 12, including the steps of patterning a resist film, Cu plating, and peeling the resist film. As a result, the wiring 30 is formed at a position separated from the third portion 13 on the upper surface of the first sealing resin 41. The boundary between the second portion 12 and the third portion 13 of the external terminal 10 is flush with the upper surface of the first sealing resin 41. The third portion 13 may be formed so that the outer edge of the second portion 12 is located inside the outer edge of the third portion 13 when viewed from the normal direction of the connection surface 100.

[0038] A conductive bump 50 is formed on the third portion 13 of the external terminal 10. For example, as shown in FIG. 18 , the bump 50 is formed on the upper surface of the third portion 13, i.e., the connection surface 100. The bump 50 may be, for example, a nickel (Ni) / tin-silver (SnAg) laminate film. For example, the bump 50 may be formed by the steps of patterning a resist film, Ni / SnAg plating, and peeling off the resist film. If there is no need to electrically connect the external terminal 10 and the semiconductor chip 20, the bump 50 does not need to be conductive. For example, the external terminal 10 may be used as a heat dissipation terminal, and the semiconductor chip 20 may be thermally connected to a heat dissipation member or substrate disposed outside the sealing resin 40 via the external terminal 10. When the external terminal 10 is used for heat dissipation, the bump 50 is made of a material with good thermal conductivity, and it does not matter whether it is conductive or not.

[0039] 19 , the semiconductor chip 20 is disposed above the first sealing resin 41 so as to be connected to the third portion 13. For example, the third portion 13 and the semiconductor chip 20 are electrically connected via bumps 50. At this time, electrodes (not shown) of the semiconductor chip 20 may be electrically connected to the wiring 30.

[0040] 20, a second sealing resin 42 is formed so as to cover the first sealing resin 41. As a result, the semiconductor chip 20, the wiring 30, and the third portion 13 are covered with the second sealing resin 42.

[0041] After the second sealing resin 42 is formed, the substrate 200 is removed to expose a portion of the surface of the first portion 11. For example, the lower surface of the first portion 11 is exposed at the lower surface of the first sealing resin 41. Thereafter, as shown in FIG. 21 , the second sealing resin 42 and the first sealing resin 41 are separated to separate the semiconductor device 1. In this manner, the semiconductor device 1 is completed.

[0042] The above description exemplifies a case in which multiple semiconductor devices 1 are simultaneously formed on one substrate 200. That is, multiple external terminals 10 are formed on the substrate 200, and multiple semiconductor chips 20 that connect to any of the multiple external terminals 10 are placed above a first sealing resin 41. Then, after the multiple semiconductor chips 20 are covered with a second sealing resin 42, the second sealing resin 42 and the first sealing resin 41 are separated.

[0043] Any resin such as an epoxy resin or a silicone resin can be used for the first sealing resin 41 and the second sealing resin 42. The first sealing resin 41 and the second sealing resin 42 may be made of the same material or different materials.

[0044] In the above description of the manufacturing method, the external terminals 10 and the wiring 30 are formed by electrolytic plating, but the external terminals 10 and the wiring 30 may also be formed by electroless plating. Furthermore, instead of a Cu plating film, other conductive films may be used for the external terminals 10 and the wiring 30. For example, films that can be formed by plating methods other than Cu films may be used for the external terminals 10 and the wiring 30. Examples of films that can be formed by plating methods include gold (Au) films, aluminum (Al) films, Ni films, palladium (Pd) films, and antimony (Sb) films.

[0045] Forming the external terminals 10 using a plating method makes it easy to form the external terminals 10 with a large thickness. For example, the thickness of the first portion 11 and the second portion 12 may be approximately several tens of μm to several hundreds of μm. The thickness of the wiring 30 may be approximately 10 μm to 50 μm.

[0046] Furthermore, although an example in which a DFR is used for the resist film has been described, a liquid resist may be used for the resist film.

[0047] Although the method of forming the bump 50 on the third portion 13 of the external terminal 10 has been described above, in the case of a semiconductor chip 20 including a bump, the third portion 13 and the semiconductor chip 20 may be connected via the bump of the semiconductor chip 20.

[0048] Incidentally, it is also conceivable to form the external terminal 10 including the first portion 11, the second portion 12, and the third portion 13 by repeating a series of steps including seed film formation, a resist film patterning step, a plating step, a resist film removal step, and seed film removal. However, repeating the above series of steps requires repeating the steps of seed film formation, resist film removal, and seed film removal. In contrast, according to the manufacturing method described with reference to FIGS. 10 to 20 , the steps of seed film formation, resist film removal, and seed film removal can be reduced. This allows the manufacturing cost and manufacturing process time of the semiconductor device 1 to be reduced.

[0049] 2 shows the external terminal 10 configured such that the outer edge of the third portion 13 does not extend beyond the outer edge of the first portion 11 when viewed from the normal direction of the connection surface 100. For example, the center position of the first portion 11 and the center position of the third portion 13 may coincide with each other in plan view.

[0050] Alternatively, as shown in Fig. 22A , the center position of the first portion 11 and the center position of the third portion 13 do not have to coincide. In other words, the position of the third portion 13 may be shifted from the center position of the first portion 11 toward the outer edge in a planar view. For example, as shown in Fig. 22B , a part of the outer edge of the first portion 11 may overlap a part of the outer edge of the third portion 13. As described above, the relative position of the third portion 13 with respect to the first portion 11 in a planar view may be set arbitrarily depending on the layout of the wiring 30, etc.

[0051] 1 , the cross-sectional area of ​​the second portion 12 of the external terminal 10 is smaller than that of the third portion 13. That is, when viewed from the normal direction of the connection surface 100, the outer edge of the second portion 12 is located more inward than the outer edge of the third portion 13. Therefore, the boundary between the side surface of the second portion 12 and the first sealing resin 41 is blocked by the third portion 13, which can prevent an etching agent from penetrating this boundary. Furthermore, the third portion 13 acts as a stopper, preventing the external terminal 10 from coming off the sealing resin 40 during or after the process of removing the substrate 200 from the sealing resin 40.

[0052] 23 , when viewed from the normal direction of the connection surface 100, the outer edge of the second portion 12 may coincide with the outer edge of the third portion 13. In other words, the cross-sectional area of ​​the second portion 12 may be the same as the cross-sectional area of ​​the third portion 13. Increasing the cross-sectional area of ​​the second portion 12 can reduce the electrical resistance and thermal resistance from the top surface to the bottom surface of the external terminal 10. However, to prevent a short circuit between the external terminal 10 and the wiring 30, the cross-sectional area of ​​the second portion 12 is made narrower than the cross-sectional area of ​​the first portion 11.

[0053] In the above example, in a cross section perpendicular to the connection surface 100 of the external terminal 10, the side surface of the second portion 12 connecting the first portion 11 and the third portion 13 is perpendicular to the connection surface 100. However, the side surface of the second portion 12 may have a tapered shape that intersects the connection surface 100 at an angle. For example, as shown in FIG. 24A , the cross-sectional area of ​​the second portion 12 may gradually narrow from the region connected to the first portion 11 toward the region connected to the third portion 13. Alternatively, as shown in FIG. 24B , the cross-sectional area of ​​the second portion 12 may gradually widen from the region connected to the first portion 11 toward the region connected to the third portion 13. In this way, by forming the second portion 12 using a resist film and plating, the shape of the second portion 12 can be set as desired.

[0054] Although the embodiments have been described above, the descriptions and drawings that form part of this disclosure should not be understood to limit the embodiments. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0055] For example, as shown in FIG. 25 , the wiring 30 may be arranged in multiple layers. The semiconductor device 1 shown in FIG. 25 has a structure in which the second portion 12, which connects the first portion 11 and the third portion 13, connects the first region 12A, the second region 12B, and the third region 12C. The first portion 11 and the first region 12A are covered with a first layer 41A of a first sealing resin 41. The second region 12B and the third region 12C are covered with a second layer 41B of the first sealing resin 41. The third portion 13 and the semiconductor chip 20 are covered with a second sealing resin 42. The wiring 30 is arranged on the upper surface of the first layer 41A and the upper surface of the second layer 41B of the first sealing resin 41. The semiconductor device 1 in which the wiring 30 is arranged in multiple layers can further increase the degree of freedom in the layout of the wiring 30.

[0056] Furthermore, multiple semiconductor chips 20 may be covered with the sealing resin 40. Fig. 26 shows an example in which a first semiconductor chip 20A and a second semiconductor chip 20B are covered with a common sealing resin 40. By covering multiple semiconductor chips 20 with a single sealing resin 40, the size of the semiconductor device 1 can be reduced. The semiconductor chips 20 can be electrically connected to each other by the wiring 30 arranged inside the sealing resin 40.

[0057] Although the present disclosure has been described in detail above, it will be apparent to those skilled in the art that the present disclosure is not limited to the embodiments described herein. One or more elements of one embodiment can be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure, as defined by the claims. Therefore, the description of the present disclosure is intended to be illustrative and explanatory, and is not intended to be limiting of the present disclosure.

[0058] [Notes] The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each note should not be limited to the components indicated by the reference symbols.

[0059] [Supplementary Note 1] The semiconductor device 1 includes an external terminal 10 in which a first portion 11, a second portion 12, and a third portion 13 are sequentially connected, the third portion 13 including a connection surface 100 facing away from the surface facing the second portion 12, a semiconductor chip 20 connected to the connection surface 100 of the external terminal 10, wiring 30 arranged at the same plane level as the third portion 13 of the external terminal 10, and a sealing resin 40 covering the semiconductor chip 20, the external terminal 10, and the wiring 30. When viewed in the thickness direction in which the first portion 11, the second portion 12, and the third portion 13 are connected, the area of ​​the connection surface 100 in the third portion 13 is smaller than the area of ​​the first portion 11. According to the semiconductor device 1 described in Supplementary Note 1, by arranging the wiring 30 at the same plane level as the third portion 13 in which the spacing between the external terminals 10 is wide, the degree of freedom in the layout of the wiring 30 arranged inside the sealing resin 40 can be increased.

[0060] [Supplementary Note 2] In the semiconductor device 1 described in Supplementary Note 1, a part of the surface of the first portion 11 is exposed from the sealing resin 40. According to the semiconductor device 1 described in Supplementary Note 2, the semiconductor chip 20 can be electrically or thermally connected to the outside of the sealing resin 40 via the external terminals 10.

[0061] [Supplementary Note 3] In the semiconductor device 1 described in Supplementary Note 1 or 2, the outer edge of the third portion 13 does not extend beyond the outer edge of the first portion 11 when viewed from the normal direction of the connection surface 100. According to the semiconductor device 1 described in Supplementary Note 3, the distance between the third portions 13 can be wider than the distance between the first portions 11.

[0062] [Supplementary Note 4] The semiconductor device 1 described in any one of Supplementary Notes 1 to 3 includes a plurality of external terminals 10, and the wiring 30 is arranged between the third portions 13 of the external terminals 10. According to the semiconductor device 1 described in Supplementary Note 4, by arranging the wiring 30 in the relatively wide spaces between the third portions 13, it is possible to increase the degree of freedom in the layout of the wiring 30.

[0063] [Supplementary Note 5] In the semiconductor device 1 described in any one of Supplementary Notes 1 to 4, the sealing resin 40 has a structure in which a first sealing resin 41 and a second sealing resin 42 are laminated. The first portion 11 and the second portion 12 of the external terminal 10 are covered with the first sealing resin 41. The semiconductor chip 20, the wiring 30, and the third portion 13 are covered with the second sealing resin 42.

[0064] [Appendix 6] In the semiconductor device 1 described in Appendix 5, the wiring 30 is arranged on the surface of the first sealing resin 41 facing the second sealing resin 42. According to the semiconductor device 1 described in Appendix 6, the wiring 30 is arranged at the same plane level as the third portion 13 in which the spacing between the external terminals 10 is wide.

[0065] [Supplementary Note 7] In the semiconductor device 1 according to any one of Supplementary Notes 1 to 6, the external terminals 10 are conductive. According to the semiconductor device 1 according to Supplementary Note 7, the semiconductor chip 20 can be electrically connected to the outside of the sealing resin 40 via the external terminals 10.

[0066] [Supplementary Note 8] In the semiconductor device 1 described in any one of Supplementary Notes 1 to 7, the outer edge of the second portion 12 is located more inward than the outer edge of the third portion 13 when viewed from the normal direction of the connection surface 100. The semiconductor device 1 described in Supplementary Note 8 can prevent the etching agent from penetrating into the boundary between the second portion 12 and the first sealing resin 41. In addition, the external terminals 10 can be prevented from coming out of the sealing resin 40.

[0067] [Supplementary Note 9] In the semiconductor device 1 described in any one of Supplementary Notes 1 to 7, the outer edge of the second portion 12 and the outer edge of the third portion 13 coincide with each other when viewed from the normal direction of the connection surface 100. According to the semiconductor device 1 described in Supplementary Note 9, the cross-sectional area of ​​the second portion 12 can be increased, thereby reducing the electrical resistance and thermal resistance of the external terminal 10.

[0068] [Supplementary Note 10] In the semiconductor device 1 according to any one of Supplementary Notes 1 to 9, the semiconductor chips 20 are covered with a sealing resin 40. According to the semiconductor device 1 according to Supplementary Note 10, the size of the semiconductor device 1 can be reduced.

[0069] [Supplementary Note 11] In the semiconductor device 1 described in any one of Supplementary Notes 1 to 10, the wiring 30 electrically connects the semiconductor chip to the external electrode 60, the surface of which is partially exposed from the sealing resin 40. According to the semiconductor device 1 described in Supplementary Note 11, the semiconductor chip 20 can be electrically connected to a device or power source external to the semiconductor device 1 via the wiring 30.

[0070] [Supplementary Note 12] The semiconductor device 1 described in Supplementary Note 11 further includes a printed circuit board 70 including a wiring pattern 71 electrically connected to the external electrode 60. According to the semiconductor device 1 described in Supplementary Note 12, the semiconductor chip 20 can be electrically connected to another device via the wiring pattern 71 of the printed circuit board 70.

[0071] [Supplementary Note 13] In the semiconductor device 1 described in any one of Supplementary Notes 1 to 12, the cross section of the second portion 12 perpendicular to the connection surface 100 has a tapered shape in which the side surface connecting the first portion 11 and the third portion 13 obliquely intersects with the connection surface 100. The shape of the second portion 12 can be set arbitrarily.

[0072] [Supplementary Note 14] The manufacturing method of a semiconductor device includes the following steps: forming first portions 11 of external terminals 10 on the upper surface of substrate 200; forming second portions 12 of external terminals 10 on the upper surface of first portions 11 with at least a wider gap between their upper surfaces than first portions 11; covering first portions 11 and 12 with first sealing resin 41, and exposing the upper surfaces of second portions 12 from first sealing resin 41; forming third portions 13 of external terminals 10 on the upper surfaces of second portions 12 with a wider gap between them than first portions 11; forming wiring 30 on the upper surface of first sealing resin 41 at a position separated from third portion 13; and placing semiconductor chip 20 above first sealing resin 41 so as to connect to third portion 13; forming second sealing resin 42 so as to cover first sealing resin 41; and covering semiconductor chip 20, wiring 30, and third portion 13 with second sealing resin 42. According to the manufacturing method of Appendix 14, by arranging the wiring 30 at the same plane level as the third part 13 in which the spacing between the external terminals 10 is wide, the degree of freedom in the layout of the wiring 30 to be arranged inside the sealing resin 40 can be increased.

[0073] [Appendix 15] In the method for manufacturing a semiconductor device described in Appendix 14, after forming the second sealing resin 42, the substrate 200 is removed to expose a part of the surface of the first portion 11. According to the method for manufacturing a semiconductor device described in Appendix 15, the semiconductor chip 20 can be electrically or thermally connected to the outside of the sealing resin 40 via the external terminals 10.

[0074] [Supplementary Note 16] In the method for manufacturing a semiconductor device described in Supplementary Note 14 or 15, bumps 50 are formed on the third portions 13 of the external terminals 10, and the third portions 13 and the semiconductor chip 20 are connected via the bumps 50. According to the method for manufacturing a semiconductor device described in Supplementary Note 16, the external electrodes 60 and the semiconductor chip 20 can be electrically or thermally connected via the bumps 50.

[0075] [Supplementary Note 17] In the method for manufacturing a semiconductor device according to Supplementary Note 14 or 15, the semiconductor chip 20 includes bumps, and the third portion 13 and the semiconductor chip 20 are connected via the bumps. According to the method for manufacturing a semiconductor device according to Supplementary Note 17, the step of forming the bumps 50 on the third portion 13 can be omitted.

[0076] [Appendix 18] In the method for manufacturing a semiconductor device described in any one of Appendices 14 to 17, a plurality of first resist films 401 are formed on the upper surface of the substrate 200 at a first interval D1, and first portions 11 of the external terminals 10 are formed between the first resist films 401. A plurality of second resist films 402 are formed on the upper surfaces of the first resist films 401 and the first portions 11 at a second interval D2 narrower than the first interval D1, so that a portion of the upper surface of the first portions 11 is exposed between the second resist films 402. A second portion 12 connecting to the first portions 11 is formed between the second resist films 402. According to the method for manufacturing a semiconductor device described in Appendices 18, the first portions 11 and the second portions 12 are formed while the first resist film 401 and the second resist film 402 remain. Therefore, the first resist film 401 and the second resist film 402 can be removed simultaneously, reducing the number of manufacturing steps.

[0077] [Appendix 19] In the method for manufacturing a semiconductor device described in any one of Appendices 14 to 18, a plurality of external terminals 10 are formed on a substrate 200, and a plurality of semiconductor chips 20 connected to any of the plurality of external terminals 10 are placed above a first sealing resin 41. The plurality of semiconductor chips 20 are covered with a second sealing resin 42, and the second sealing resin 42 and the first sealing resin 41 are divided and singulated. In the method for manufacturing a semiconductor device described in Appendix 19, a plurality of semiconductor devices 1 are simultaneously formed on one substrate 200, and then the semiconductor devices 1 are singulated.

[0078] [Supplementary Note 20] In the method for manufacturing a semiconductor device according to any one of Supplements 14 to 19, the third portion 13 is formed so that the outer edge of the second portion 12 is located more inward than the outer edge of the third portion 13 when viewed from the normal direction of the connection surface 100. The method for manufacturing a semiconductor device according to Supplementary Note 20 can prevent the etching agent from penetrating the boundary between the second portion 12 and the first sealing resin 41. In addition, it can prevent the external terminals 10 from coming out of the sealing resin 40.

[0079] [Supplementary Note 21] In the method for manufacturing a semiconductor device according to any one of Supplements 14 to 20, the external terminals 10 are made of a conductive material. According to the method for manufacturing a semiconductor device according to Supplementary Note 21, the semiconductor chip 20 can be electrically connected to the outside of the sealing resin 40 via the external terminals 10.

[0080] [Supplementary Note 22] In the method for manufacturing a semiconductor device according to any one of Supplementary Notes 14 to 21, the external terminals 10 are formed by plating. According to the method for manufacturing a semiconductor device according to Supplementary Note 22, it is easy to form the external terminals 10 to have a large thickness.

[0081] REFERENCE SIGNS LIST 1 semiconductor device 10 external terminal 11 first portion 12 second portion 13 third portion 20 semiconductor chip 30 wiring 40 sealing resin 41 first sealing resin 42 second sealing resin 50 bump 60 external electrode 70 printed circuit board 71 wiring pattern 80 bonding material 100 connection surface 200 substrate 300 seed film 401 first resist film 402 second resist film D1 first distance D2 second distance

Claims

1. A semiconductor device comprising: an external terminal included in a third portion, the third portion having a connection surface facing away from a surface facing the second portion, the first portion, the second portion, and the third portion being sequentially connected; a semiconductor chip connected to the connection surface of the external terminal; a wiring disposed at the same planar level as the third portion of the external terminal; and a sealing resin covering the semiconductor chip, the external terminal, and the wiring, wherein an area of the connection surface when viewed from a thickness direction in which the first portion, the second portion, and the third portion are connected is narrower than an area of the first portion.

2. The semiconductor device according to claim 1, wherein a part of a surface of the first portion is exposed from the sealing resin.

3. The semiconductor device according to claim 1 or 2, wherein an outer edge of the third portion does not exceed an outer edge of the first portion when viewed in a normal direction of the connection surface.

4. The semiconductor device according to any one of claims 1 to 3, comprising a plurality of the external terminals, wherein the wiring is disposed between the third portions of the external terminals.

5. The semiconductor device according to any one of claims 1 to 4, wherein the sealing resin has a structure in which a first sealing resin and a second sealing resin are laminated, the first portion and the second portion of the external terminal are covered with the first sealing resin, and the semiconductor chip, the wiring, and the third portion are covered with the second sealing resin.

6. The semiconductor device according to claim 5, wherein the wiring is disposed on a surface of the first sealing resin facing the second sealing resin.

7. The semiconductor device according to any one of claims 1 to 6, wherein the external terminal has conductivity.

8. The semiconductor device according to any one of claims 1 to 7, wherein an outer edge of the second portion is inside an outer edge of the third portion when viewed in a normal direction of the connection surface.

9. The semiconductor device according to any one of claims 1 to 7, wherein an outer edge of the second portion coincides with an outer edge of the third portion when viewed in a normal direction of the connection surface.

10. The semiconductor device according to any one of claims 1 to 9, wherein a plurality of the semiconductor chips are covered by the sealing resin.

11. The semiconductor device according to any one of claims 1 to 10, wherein the wiring electrically connects an external electrode, a part of the surface of which is exposed from the sealing resin, and the semiconductor chip.

12. The semiconductor device according to claim 11, further comprising a printed circuit board including a wiring pattern electrically connected to the external electrode.

13. The semiconductor device according to any one of claims 1 to 12, wherein a cross-section perpendicular to the connection surface of the second part has a tapered shape in which a side surface connecting the first part and the third part intersects the connection surface obliquely.

14. A method of manufacturing a semiconductor device, comprising: forming a first part of an external terminal on an upper surface of a substrate; forming a second part of the external terminal on an upper surface of the first part with at least an upper surface interval wider than that of the first part; coating the first part and the second part with a first encapsulation resin; exposing an upper surface of the second part from the first encapsulation resin; forming a third part of the external terminal on the upper surface of the second part with a wider interval than that of the first part; forming a wiring at a position separated from the third part on an upper surface of the first encapsulation resin; disposing a semiconductor chip above the first encapsulation resin so as to be connected to the third part; and forming a second encapsulation resin so as to cover the first encapsulation resin to cover the semiconductor chip, the wiring, and the third part with the second encapsulation resin.

15. The method of manufacturing a semiconductor device according to claim 14, wherein the substrate is removed after forming the second encapsulation resin to expose a part of a surface of the first part.

16. The method of manufacturing a semiconductor device according to claim 14 or 15, comprising: forming a bump on the third part of the external terminal; and connecting the third part and the semiconductor chip via the bump.

17. The method of manufacturing a semiconductor device according to claim 14 or 15, wherein the semiconductor chip includes a bump, and the third part and the semiconductor chip are connected via the bump.

18. The method of manufacturing a semiconductor device according to any one of claims 14 to 17, comprising: forming a plurality of first resist films at a first interval on an upper surface of the substrate; forming the first part of the external terminal between the first resist films; forming a plurality of second resist films at a second interval narrower than the first interval on upper surfaces of the first resist film and the first part so that a part of an upper surface of the first part is exposed between them; and forming the second part connected to the first part between the second resist films.

19. A method of manufacturing a semiconductor device according to any one of claims 14 to 18, comprising: forming a plurality of the external terminals on the substrate; disposing a plurality of the semiconductor chips connected to any one of the plurality of the external terminals above the first encapsulating resin; coating the plurality of the semiconductor chips with the second encapsulating resin; and dividing the second encapsulating resin and the first encapsulating resin to form individual pieces.

20. A method of manufacturing a semiconductor device according to any one of claims 14 to 19, comprising: forming the third portion such that an outer edge of the second portion is located inside an outer edge of the third portion when viewed from a normal direction of an upper surface of the second portion.

21. A method of manufacturing a semiconductor device according to any one of claims 14 to 20, wherein the external terminal is made of a conductive material.

22. A method of manufacturing a semiconductor device according to any one of claims 14 to 21, comprising: forming the external terminal by a plating method.

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