Semiconductor device

Abstract

This semiconductor device includes: a well region that is provided, in an outer peripheral region of a chip, in a surface layer section of a first main surface so as to partition an IGBT region and the outer peripheral region, which is provided in a peripheral edge section of the first main surface of the chip; a plurality of field regions of a first conductivity type that are provided to the well region and to the peripheral edge side of the chip, with a gap therebetween, and that are arranged spaced apart from each other; and a cathode region that is provided in a surface layer section of a second main surface in the outer peripheral region, and that constitutes the well region and a diode. The cathode region is disposed at a position that is farther on the peripheral edge side of the chip than the well region and that faces at least one of the plurality of field regions in the thickness direction of the chip.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses a semiconductor device including a reverse conducting-insulating gate bipolar transistor (RC-IGBT).

[0003] JP 2018-120990 A

[0004] [Summary] There is a demand for improved electrical characteristics of semiconductor devices.

[0005] A semiconductor device according to one aspect of the present disclosure includes a chip having a first main surface and a second main surface opposite to the first main surface, a peripheral region provided on a peripheral edge of the first main surface, an IGBT region provided inside the peripheral region in the first main surface, a well region of a first conductivity type provided in a surface layer portion of the first main surface in the peripheral region so as to partition the IGBT region, a plurality of field regions of the first conductivity type provided at intervals from the well region on the peripheral side of the chip in the surface layer portion of the first main surface in the peripheral region and arranged apart from each other, and a cathode region of a second conductivity type provided in a surface layer portion of the second main surface of the well region and constituting a diode together with the well region; an insulating film covering at least the well region; an emitter electrode arranged on the insulating film so as to be electrically connected to the well region; and a collector electrode provided on the second main surface so as to be electrically connected to the cathode region, the cathode region being located closer to the periphery of the chip than the well region and at a position facing at least one of the plurality of field regions in the thickness direction of the chip.

[0006] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. FIG. 2 is a schematic plan view showing an example of the layout within the first main surface of a chip. FIG. 3 is a schematic plan view showing an example of the layout of well regions, field regions, channel stop regions, and gate wiring. FIG. 4 is a schematic plan view enlarging the dashed-dotted frame A in FIG. 3. FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. 4. FIG. 6 is a schematic cross-sectional view of the semiconductor device taken along line F6-F6 in FIG. 4. FIG. 7 is a schematic cross-sectional view of the semiconductor device taken along line F7-F7 in FIG. 4. FIG. 8 is a schematic cross-sectional view of the peripheral portion of a chip taken along line F8-F8 in FIG. 3. FIG. 9 is a graph showing the relationship between the position of the peripheral portion of the chip and the electric field strength when a collector-emitter voltage is applied in a first example. FIG. 10 is a graph showing the relationship between the position of the peripheral portion of the chip and the electric field strength when a collector-emitter voltage is applied in a second example. FIG. 11 is a graph showing the relationship between the position of the periphery of the chip and the electric field strength when a collector-emitter voltage is applied in the third example. FIG. 12 is a graph showing the relationship between the placement position of the cathode region and the forward current. FIG. 13 is a schematic cross-sectional view of the periphery of the chip in the semiconductor device of the second embodiment. FIG. 14 is a schematic cross-sectional view showing the cross-sectional structure of the periphery of the chip together with the inner cathode region according to the first layout example. FIG. 15 is a graph showing the relationship between the forward voltage and the forward current when the placement position of the inner cathode region is changed. FIG. 16 is a graph showing the relationship between the placement position of the inner cathode region and the forward current, and is a graph for explaining a first setting example of the prohibited range, the first allowed range, and the second allowed range. FIG. 17 is a graph showing the relationship between the placement position of the inner cathode region and the forward current, and is a graph for explaining a second setting example of the prohibited range, the first allowed range, and the second allowed range. Fig. 18 is a graph showing the relationship between peak surge current and forward voltage when the placement position of the inner cathode region is adjusted. Fig. 19 is a schematic cross-sectional view showing the cross-sectional structure of the peripheral portion of the chip together with the inner cathode region according to a second layout example. Fig. 20 is a schematic cross-sectional view showing the cross-sectional structure of the peripheral portion of the chip together with the inner cathode region according to a third layout example. Fig. 21 is a schematic cross-sectional view of the peripheral portion of the chip in a semiconductor device according to a modified example.Fig. 22 is a schematic cross-sectional view of a peripheral portion of a chip in a semiconductor device of a modified example. Fig. 23 is a schematic cross-sectional view of a peripheral portion of a chip in a semiconductor device of a modified example. Fig. 24 is a schematic cross-sectional view of a peripheral portion of a chip in a semiconductor device of a modified example. Fig. 25 is a schematic cross-sectional view of a peripheral portion of a chip in a semiconductor device of a modified example. Fig. 26 is a schematic cross-sectional view of a peripheral portion of a chip in a semiconductor device of a modified example.

[0007] DETAILED DESCRIPTION Hereinafter, several embodiments of semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" as used herein means "one or more" of the desired options. As an example, the phrase "at least one" as used herein means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used herein means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used herein, the terms "the dimensions (depth, width, length, height) of A are equal to the dimensions (depth, width, length, height) of B" or "the dimensions (depth, width, length, height) of A and the dimensions (depth, width, length, height) of B are equal to each other" also include a relationship in which the difference between the dimensions (depth, width, length, height) of A and the dimensions (depth, width, length, height) of B is within 10% of the dimensions (depth, width, length, height) of A, for example. Also, as used herein, the terms "the concentration of A is equal to the concentration of B" or "the concentrations of A and B are equal to each other" also include a relationship in which the difference between the concentrations of A and B is within 10% of the concentration of A, for example.

[0011] First Embodiment [Overall Configuration of Semiconductor Device] The overall configuration of a semiconductor device 10 according to a first embodiment will be described with reference to FIGS. 1 to 8. FIG. 1 schematically illustrates the planar structure of the semiconductor device 10 according to the first embodiment. FIG. 2 schematically illustrates an example of the layout of various wirings in the semiconductor device 10 of FIG. 1. FIG. 3 schematically illustrates an example of the layout of a well region 54, a plurality of field regions 56, gate line wiring 70, and a cathode region 110, which will be described later. Note that FIG. 2 omits a field electrode 102 and a channel stop electrode 106, which will be described later. For convenience, FIG. 3 collectively illustrates a plurality of field regions 56 as a single region.

[0012] Fig. 4 shows a planar structure of a portion of the chip 12. Fig. 5 shows a schematic cross-sectional structure of the semiconductor device taken along line F5-F5 in Fig. 4. Fig. 6 shows a schematic cross-sectional structure of the semiconductor device taken along line F6-F6 in Fig. 4. Fig. 7 shows a schematic cross-sectional structure of the semiconductor device taken along line F7-F7 in Fig. 4. Fig. 8 shows a schematic cross-sectional structure of the peripheral portion of the chip 12, which will be described later.

[0013] 1 to 3, the semiconductor device 10 is an RC-IGBT (Reverse Conducting-IGBT) semiconductor device that includes an RC-IGBT (Insulated Gate Bipolar Transistor) that is integrated with an IGBT and a diode. The diode is a freewheeling diode for the IGBT. Such an RC-IGBT semiconductor device may also be referred to as a semiconductor switching device.

[0014] As shown in FIG. 1 , the semiconductor device 10 includes a hexahedral chip 12. The chip 12 can also be said to be formed in a flat plate shape with the Z direction as its thickness direction. The chip 12 may also be referred to as a "semiconductor chip." In the first embodiment, the chip 12 has a single-layer structure formed of a silicon single crystal substrate (semiconductor substrate). The chip 12 has a first main surface 12A, a second main surface 12B (see FIG. 5 ) opposite the first main surface 12A, and first to fourth side surfaces 12C to 12F connecting the first main surface 12A and the second main surface 12B. Hereinafter, a view of the semiconductor device 10 from the Z direction will be referred to as a "planar view." Furthermore, directions perpendicular to the Z direction that are perpendicular to each other will be referred to as the "X direction" and the "Y direction."

[0015] Both the first main surface 12A and the second main surface 12B are formed in a quadrangular shape in a plan view. The first side surface 12C and the second side surface 12D constitute both end surfaces of the chip 12 in the Y direction. Both the first side surface 12C and the second side surface 12D extend in the X direction in a plan view. The third side surface 12E and the fourth side surface 12F constitute both end surfaces of the chip 12 in the X direction. Both the third side surface 12E and the fourth side surface 12F extend in the Y direction in a plan view.

[0016] As shown in FIG. 2, the semiconductor device 10 includes an IGBT region 14 provided in an inner portion of the first main surface 12A. The IGBT region 14 is a region having an IGBT structure and may be referred to as an "active region." In one example, the IGBT region 14 is formed in a polygonal shape having four sides parallel to the first to fourth side surfaces 12C to 12F in a plan view. In the example shown in FIG. 2, the IGBT region 14 includes a recess recessed from the center in the Y direction of the side along the third side surface 12E toward the fourth side surface 12F in a plan view. The recess is recessed in a polygonal shape in a plan view. In the example shown in FIG. 2, the recess is recessed in a quadrangular shape in a plan view.

[0017] The semiconductor device 10 includes a pad region 16 provided in a region defined by a recess in the IGBT region 14 on the first main surface 12A, and an outer periphery region 18 provided on the periphery of the chip 12. The pad region 16 is formed in a polygonal shape in a plan view. In the example shown in FIG. 2, the pad region 16 is formed in a quadrangular shape in a plan view. The outer periphery region 18 is provided in an annular shape extending along the first to fourth side surfaces 12C to 12F so as to surround the IGBT region 14 in a plan view. In the example shown in FIG. 2, the outer periphery region 18 is formed in a quadrangular annular shape in a plan view. The portion of the outer periphery region 18 extending along the third side surface 12E is connected to the pad region 16. It can be said that the IGBT region 14 is provided inside the outer periphery region 18 on the first main surface 12A.

[0018] 5 , the semiconductor device 10 includes an n-type (second conductivity type) drift region 20 formed inside the chip 12. The drift region 20 is formed throughout the entire interior of the chip 12. In the first embodiment, the chip 12 is configured of an n-type semiconductor substrate (an n-type semiconductor chip). The drift region 20 is formed by utilizing the chip 12.

[0019] The semiconductor device 10 includes an n-type buffer region 22 formed in a surface layer portion of the second main surface 12B. In the first embodiment, the buffer region 22 is formed in a layer shape extending along the entire area of ​​the second main surface 12B. The buffer region 22 is exposed from the first to fourth side surfaces 12C to 12F (see FIG. 2). The buffer region 22 has a higher n-type impurity concentration than the drift region 20. The presence or absence of the buffer region 22 is optional, and a configuration without the buffer region 22 may also be adopted.

[0020] The semiconductor device 10 includes a p-type (first conductivity type) collector region 24 formed in a surface layer portion of the second main surface 12B. The collector region 24 is formed in a surface layer portion on the second main surface 12B side of the buffer region 22. In the first embodiment, the collector region 24 is formed in a layer shape extending along the second main surface 12B over substantially the entire area of ​​the second main surface 12B.

[0021] The semiconductor device 10 includes a trench isolation structure 26 formed in the first main surface 12A to partition the IGBT region 14. A gate potential is applied to the trench isolation structure 26. The trench isolation structure 26 surrounds the IGBT region 14 and separates the IGBT region 14 from the outer periphery region 18 and the pad region 16 (see FIG. 2 ). In the first embodiment, the trench isolation structure 26 is formed in a polygonal ring shape having four sides parallel to the first to fourth side surfaces 12C to 12F in a plan view.

[0022] The trench isolation structure 26 may have a width of 0.5 μm or more and 5 μm or less. Here, the width of the trench isolation structure 26 can be defined by the dimension in a direction perpendicular to the direction in which the trench isolation structure 26 extends in a plan view. The width of the trench isolation structure 26 is preferably 1 μm or more and 2.5 μm or less. The trench isolation structure 26 may have a depth of 1 μm or more and 20 μm or less. Here, the depth of the trench isolation structure 26 can be defined by the dimension in the Z direction of the trench isolation structure 26, in other words, the distance in the Z direction between the first main surface 12A and the bottom wall of an isolation trench 28 described below. The depth of the trench isolation structure 26 is preferably 4 μm or more and 10 μm or less.

[0023] The trench isolation structure 26 includes an isolation trench 28, an isolation insulating film 30, and an isolation buried electrode 32. The isolation trench 28 is dug down from the first main surface 12A toward the second main surface 12B, and defines the wall surface of the trench isolation structure 26. The isolation insulating film 30 is formed in the shape of a film along the wall surface of the isolation trench 28. The isolation insulating film 30 defines a recess space within the isolation trench 28.

[0024] The isolation insulating film 30 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The isolation insulating film 30 preferably has a single-layer structure formed of a single insulating film. It is particularly preferable that the isolation insulating film 30 include a silicon oxide film formed of an oxide of the chip 12.

[0025] The isolated buried electrode 32 is buried in the isolation trench 28 with the isolation insulating film 30 sandwiched therebetween. In the first embodiment, the isolated buried electrode 32 is made of conductive polysilicon. A gate potential is applied to the isolated buried electrode 32.

[0026] The semiconductor device 10 includes an IGBT structure 34 formed in the IGBT region 14. The IGBT structure 34 may also be referred to as a "FET (Field Effect Transistor) structure." The IGBT structure 34 includes a p-type base region 36 formed in the IGBT region 14 in a surface layer portion of the first main surface 12A. The base region 36 may also be referred to as a "body region" or a "channel region." The base region 36 is formed shallower than the trench isolation structure 26. That is, the base region 36 has a bottom located closer to the first main surface 12A than the bottom wall of the trench isolation structure 26. The base region 36 extends in a layered manner along the first main surface 12A. The base region 36 contacts the inner circumferential wall of the trench isolation structure 26.

[0027] The IGBT structure 34 includes a plurality of trench gate structures 38 formed in the first main surface 12A in the IGBT region 14. A gate potential is applied to the plurality of trench gate structures 38. The plurality of trench gate structures 38 penetrate the base region 36 to reach the drift region 20. As shown in FIG. 2 , the plurality of trench gate structures 38 are arranged at intervals in the X direction in a plan view. Each trench gate structure 38 is formed in a band shape extending in the Y direction in a plan view. In other words, the plurality of trench gate structures 38 are arranged in stripes extending in the Y direction.

[0028] Each trench gate structure 38 includes a first end 38A on one side (the first side surface 12C side) and a second end 38B on the other side (the second side surface 12D side) in the longitudinal direction (Y direction). The first end 38A and the second end 38B are mechanically and electrically connected to the trench isolation structure 26.

[0029] That is, the plurality of trench gate structures 38, together with the trench isolation structure 26, constitute one ladder-shaped trench gate structure 38. The connection portion connecting the trench isolation structure 26 and the trench gate structure 38 may be considered as part of the trench isolation structure 26 or may be considered as part of the trench gate structure 38.

[0030] The multiple trench gate structures 38 may be arranged at intervals of 0.5 μm to 5 μm in the X direction. The intervals between the multiple trench gate structures 38 are preferably 1 μm to 3 μm. Each trench gate structure 38 may have a width of 0.5 μm to 5 μm. Here, the width of the trench gate structure 38 can be defined by the dimension in a direction perpendicular to the direction in which each trench gate structure 38 extends in a plan view.

[0031] The width of each trench gate structure 38 is preferably 1 μm or more and 2.5 μm or less. The width of each trench gate structure 38 is preferably equal to the width of the trench isolation structure 26. Each trench gate structure 38 may have a depth of 1 μm or more and 20 μm or less. Here, the depth of each trench gate structure 38 can be defined by the dimension of the trench gate structure 38 in the Z direction. The depth of each trench gate structure 38 is preferably 4 μm or more and 10 μm or less. The depth of each trench gate structure 38 is preferably equal to the depth of the trench isolation structure 26. Here, the depth of the trench gate structure 38 can be defined by the dimension of the trench gate structure 38 in the Z direction, in other words, the distance in the Z direction between the first main surface 12A and the bottom wall of a gate trench 40 described below.

[0032] One trench gate structure 38 will be described below. As shown in FIG. 5 , the trench gate structure 38 includes a gate trench 40, a gate insulating film 42, and a buried gate electrode 44. The gate trench 40 is dug downward from the first main surface 12A toward the second main surface 12B to define the wall surface of the trench gate structure 38. In the first embodiment, the gate trench 40 communicates with the isolation trench 28 at both longitudinal ends thereof, that is, a first end 38A and a second end 38B (both see FIG. 2 ). Specifically, as shown in FIG. 4 , the sidewall of the gate trench 40 communicates with the sidewall of the isolation trench 28, and the bottom wall of the gate trench 40 communicates with the bottom wall of the isolation trench 28.

[0033] As shown in FIGS. 4 and 5 , the gate insulating film 42 is formed in the form of a film along the wall surface of the gate trench 40. The gate insulating film 42 defines a recess space within the gate trench 40. The gate insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The gate insulating film 42 preferably has a single-layer structure formed of a single insulating film. It is particularly preferable that the gate insulating film 42 includes a silicon oxide film formed of an oxide of the chip 12. In the first embodiment, the gate insulating film 42 is formed of the same insulating film as the isolation insulating film 30. The gate insulating film 42 is connected to the isolation insulating film 30 at the communicating portion between the isolation trench 28 and the gate trench 40.

[0034] The buried gate electrode 44 is buried in the gate trench 40 with the gate insulating film 42 sandwiched therebetween. In the first embodiment, the buried gate electrode 44 is made of conductive polysilicon. A gate potential is applied to the buried gate electrode 44. The buried gate electrode 44 is connected to the isolation buried electrode 32 at the communicating portion between the isolation trench 28 and the gate trench 40.

[0035] 5 , the IGBT structure 34 includes a plurality of n-type emitter regions 46 formed in a surface layer portion of the base region 36 in a region along the plurality of trench gate structures 38. The plurality of emitter regions 46 are arranged on both sides of the plurality of trench gate structures 38. Each emitter region 46 is formed in a strip shape extending along the plurality of trench gate structures 38 in a plan view. Each emitter region 46 has a higher n-type impurity concentration than the drift region 20. It is preferable that the emitter regions 46 are not formed in a region sandwiched between the trench isolation structure 26 and the trench gate structure 38 in the surface layer portion of the base region 36.

[0036] The IGBT structure 34 includes a plurality of contact holes 48 formed in the first main surface 12A to expose the emitter regions 46. The plurality of contact holes 48 are respectively formed in regions between pairs of adjacent trench gate structures 38 spaced apart from one another among the plurality of trench gate structures 38. In the first embodiment, each contact hole 48 is formed so that the opening width is constant from the opening toward the bottom wall. Note that each contact hole 48 may be formed so that the opening width narrows from the opening toward the bottom wall.

[0037] In the first embodiment, the multiple contact holes 48 penetrate the emitter region 46 to reach the base region 36. Note that the multiple contact holes 48 may be spaced from the bottom of the emitter region 46 toward the first main surface 12A so as not to reach the base region 36. Each contact hole 48 is formed in a strip shape extending along the multiple trench gate structures 38 in a plan view. As shown in FIG. 7 , the multiple contact holes 48 are arranged spaced apart in the longitudinal direction (Y direction) from the trench isolation structure 26. Therefore, the multiple contact holes 48 are shorter in the longitudinal direction (Y direction) than the multiple trench gate structures 38 (see FIG. 6 ).

[0038] 5, the IGBT structure 34 includes a plurality of p-type contact regions 50 formed in regions different from the plurality of emitter regions 46 in the surface layer portion of the base region 36. The plurality of contact regions 50 are each formed in a strip shape extending along the corresponding contact hole 48 in a plan view. The bottom of each of the plurality of contact regions 50 is formed in a region between the bottom wall of the corresponding contact hole 48 and the bottom of the base region 36. Each contact region 50 has a higher p-type impurity concentration than the base region 36.

[0039] As shown in FIG. 3 , the semiconductor device 10 includes a p-type pad well region 52 formed in the surface layer portion of the first main surface 12A in the pad region 16. The pad well region 52 is formed to partition the IGBT region 14. The pad well region 52 may also be referred to as a "pad anode region." In the first embodiment, the pad well region 52 has a higher p-type impurity concentration than the base region 36 (see FIG. 5 ). Note that the pad well region 52 may also have a lower p-type impurity concentration than the base region 36.

[0040] The pad well region 52 is formed in the pad region 16 at a distance from the periphery of the chip 12 toward the IGBT region 14. The pad well region 52 is formed in a polygonal shape (a square shape in the first embodiment) that matches the pad region 16 in a plan view. The pad well region 52 contacts the trench isolation structure 26 (see FIG. 2). The pad well region 52 is formed deeper than the base region 36. Specifically, the pad well region 52 is formed deeper than the trench isolation structure 26 (the plurality of trench gate structures 38). The pad well region 52 has a portion that covers the bottom wall of the trench isolation structure 26.

[0041] The pad well region 52 has a peripheral portion that extends from the pad region 16 into the IGBT region 14. The peripheral portion of the pad well region 52 has a portion that crosses the trench isolation structure 26 and covers the bottom walls of the plurality of trench gate structures 38. The peripheral portion of the pad well region 52 covers the sidewalls of the trench isolation structure 26 and the sidewalls of the plurality of trench gate structures 38 in the IGBT region 14, and is connected to the base region 36 in the surface layer portion of the first main surface 12A. In other words, the pad well region 52 is electrically connected to the base region 36 and the plurality of emitter regions 46 in the IGBT region 14.

[0042] As shown in FIGS. 5 to 8 , the semiconductor device 10 includes a p-type well region 54 formed in a surface layer portion of the first main surface 12A in the peripheral region 18. The well region 54 is formed so as to separate the IGBT region 14 from the peripheral region 18. The well region 54 may also be referred to as an "anode region." In the first embodiment, the well region 54 has a higher p-type impurity concentration than the base region 36. Note that the well region 54 may also have a lower p-type impurity concentration than the base region 36. It is preferable that the well region 54 has the same p-type impurity concentration as the pad well region 52.

[0043] The well region 54 is formed at a distance from the periphery of the chip 12 toward the IGBT region 14. The well region 54 is formed in a layer shape extending along the first main surface 12A. The well region 54 is exposed from the first main surface 12A. The well region 54 is formed in a band shape extending along the IGBT region 14 in a plan view. Specifically, as shown in FIG. 3 , the well region 54 is formed in a ring shape surrounding the IGBT region 14 in a plan view. The well region 54 has four sides parallel to the periphery of the chip 12. The well region 54 has an inner edge 54A on the IGBT region 14 side and an outer edge 54B on the periphery of the chip 12.

[0044] The well region 54 is formed integrally with the pad well region 52 in a portion extending along the third side surface 12E. In other words, the well region 54 integrally includes the pad well region 52 extending from the outer periphery region 18 side to the pad region 16. The width of the well region 54 may be 10 μm or more and 100 μm or less. The width of the well region 54 is preferably 40 μm or more and 80 μm or less. Here, the width of the well region 54 can be defined by the dimension in a direction perpendicular to the direction in which the well region 54 extends in a plan view.

[0045] 5, the well region 54 is formed deeper than the base region 36. Specifically, the well region 54 is formed deeper than the trench isolation structure 26 (the plurality of trench gate structures 38). The well region 54 is in contact with the trench isolation structure 26. The well region 54 has a portion that covers the bottom wall of the trench isolation structure 26. The well region 54 is drawn out from the outer periphery region 18 into the IGBT region 14. Therefore, an inner edge 54A of the well region 54 is located within the IGBT region 14.

[0046] 6 and 7 , the well region 54 has a portion that crosses the trench isolation structure 26 and covers the bottom walls of the plurality of trench gate structures 38. The well region 54 covers the sidewalls of the trench isolation structure 26 and the sidewalls of the plurality of trench gate structures 38 in the IGBT region 14, and is connected to the base region 36 in the surface layer portion of the first main surface 12A. In other words, as shown in FIGS. 5 and 7 , an inner edge 54A of the well region 54 is electrically connected to the base region 36 and the emitter region 46 in the IGBT region 14.

[0047] As shown in FIG. 8 , the semiconductor device 10 includes at least one p-type field region 56 formed in the surface layer portion of the first main surface 12A in the peripheral region 18. In one example, a plurality of field regions 56 (four in the first embodiment) are provided. The number of field regions 56 is arbitrary and may be 1 to 20 (typically 3 to 10). Each field region 56 may have a higher p-type impurity concentration than the base region 36. Each field region 56 may have the same p-type impurity concentration as the well region 54. Each field region 56 is formed in an electrically floating state.

[0048] A plurality of field regions 56 are formed between the periphery of the chip 12 and the well region 54, with spaces between them. Each field region 56 is formed in a strip shape extending along the well region 54 in plan view. In one example, as shown in FIG. 3 , each field region 56 is formed in a ring shape (a square ring shape in the first embodiment) surrounding the well region 54 in plan view.

[0049] 8, the multiple field regions 56 include an outermost field region 56D that is closest to the periphery of the chip 12, and inner field regions 56A to 56C that are arranged closer to the well region 54 than the outermost field region 56D. In the following description, when there is no need to distinguish between the outermost field region 56D and the inner field regions 56A to 56C, they may be simply referred to as field regions 56.

[0050] Each field region 56 is preferably formed deeper than the base region 36. Each field region 56 is preferably formed shallower than the well region 54. Each field region 56 is preferably formed shallower than the well region 54 by a depth of 0.1 μm to 1 μm (preferably 0.5 μm or less) relative to the depth position of the bottom of the well region 54, for example.

[0051] Each field region 56 is preferably formed to a constant depth. In the width direction of the field regions 56, the distance between adjacent field regions 56 (hereinafter referred to as the "spacing between field regions 56") is preferably arranged so that it gradually increases toward the periphery of the chip 12. Note that the spacing between the multiple field regions 56 may be equal to one another.

[0052] Each field region 56 preferably has a width smaller than that of the well region 54. The widths of the inner field regions 56A-56C are equal to one another. The width of the outermost field region 56D is equal to that of the inner field regions 56A-56C. Hereinafter, when there is no need to distinguish between the widths of the inner field regions 56A-56C and the width of the outermost field region 56D, they will simply be referred to as the "width WF of the field region 56." Furthermore, the width WF of the field region 56 (the width of the inner field regions 56A-56C and the width of the outermost field region 56D) can be defined by the dimension in a direction perpendicular to the extension direction of the field region 56 in a plan view.

[0053] The width WF of each field region 56 may be 1 μm or more and 50 μm or less. The width WF of each field region 56 may be set to a value within any of the following ranges: 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, and 40 μm or more and 50 μm or less. The width WF of each field region 56 is preferably 10 μm or more and 30 μm or less.

[0054] The spacing between the field regions 56 may be 10 μm or more and 30 μm or less. The spacing between the field regions 56 may be 10 μm or more and 20 μm or less. The spacing between the field regions 56 may be 10 μm or more and 15 μm or less.

[0055] The semiconductor device 10 includes an n-type channel stop region 58 formed in a surface layer portion of the first main surface 12A at an interval from the plurality of field regions 56 toward the periphery of the chip 12 in the peripheral region 18. The channel stop region 58 has a higher n-type impurity concentration than the drift region 20. The channel stop region 58 may be exposed from the first to fourth side surfaces 12C to 12F (see FIG. 3 ).

[0056] 3, the channel stop region 58 is formed in a band shape extending along the periphery of the chip 12 in a plan view. In one example, the channel stop region 58 is formed in a ring shape (the square ring shape in the first embodiment) surrounding the plurality of field regions 56 in a plan view. The channel stop region 58 is formed in an electrically floating state.

[0057] As shown in FIGS. 5 to 8 , the semiconductor device 10 includes an insulating film 60 that selectively covers the first main surface 12A. In the first embodiment, the insulating film 60 has a layered structure including a main surface insulating film 62 and an interlayer insulating film 64. The main surface insulating film 62 selectively covers the first main surface 12A in the IGBT region 14, the peripheral region 18, and the pad region 16 (see FIG. 3 ). The main surface insulating film 62 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The main surface insulating film 62 preferably has a single-layer structure composed of a single insulating film.

[0058] It is particularly preferable that the main surface insulating film 62 includes a silicon oxide film made of an oxide of the chip 12. In one example, as shown in Figures 5 and 6, the main surface insulating film 62 is made of the same insulating film as the gate insulating film 42. The main surface insulating film 62 covers the first main surface 12A so as to expose the trench isolation structure 26 and the plurality of trench gate structures 38.

[0059] Specifically, the main surface insulating film 62 is connected to the isolation insulating film 30 and the gate insulating film 42. On the other hand, the main surface insulating film 62 exposes the isolation buried electrode 32 and the gate buried electrode 44. The main surface insulating film 62 covers the pad well region 52 (see FIG. 3 ), the well region 54, the plurality of field regions 56, and the channel stop region 58 in the pad region 16 and the peripheral region 18.

[0060] The interlayer insulating film 64 covers the main surface insulating film 62. The interlayer insulating film 64 is thicker than the main surface insulating film 62. The interlayer insulating film 64 may have a single-layer structure composed of a single insulating film, or a stacked structure including multiple insulating films. The interlayer insulating film 64 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The interlayer insulating film 64 may include at least one of a non-doped silicate glass (NSG) film, a phosphorus silicate glass (PSG) film, and a boron phosphorus silicate glass (BPSG) film, which are examples of silicon oxide films.

[0061] The interlayer insulating film 64 covers the main surface insulating film 62 in the IGBT region 14, the peripheral region 18, and the pad region 16. The interlayer insulating film 64 covers the main surface insulating film 62, the trench isolation structure 26, and the plurality of trench gate structures 38 in the IGBT region 14. As shown in FIG. 8 , the interlayer insulating film 64 covers the pad well region 52, the well region 54, the plurality of field regions 56, and the channel stop region 58 with the main surface insulating film 62 sandwiched between them in the pad region 16 (see FIG. 3 ) and the peripheral region 18.

[0062] 3, the semiconductor device 10 includes a gate wiring 66 arranged in the form of a film inside the insulating film 60. In the first embodiment, the gate wiring 66 is made of a conductive polysilicon film. In one example, as shown in FIGS. 3 and 6, the gate wiring 66 includes a gate pad wiring 68, a gate line wiring 70, and a plurality of gate connection wirings 72. The gate line wiring 70 may also be referred to as a "gate finger wiring."

[0063] As shown in FIG. 3 , the gate pad wiring 68 is disposed within a portion of the insulating film 60 that covers the pad region 16. The gate pad wiring 68 faces the pad well region 52 in the thickness direction (Z direction) of the chip 12. Specifically, the gate pad wiring 68 is disposed in the form of a film on the main surface insulating film 62 and is covered by the interlayer insulating film 64 (see FIG. 6 ). The gate pad wiring 68 is formed in a polygonal shape (a quadrangular shape in the first embodiment) that matches the pad region 16 in a plan view. The peripheral portion of the gate pad wiring 68 may be located within the pad region 16.

[0064] The peripheral portion of the gate pad wiring 68 may be drawn from the pad region 16 toward the IGBT region 14. In this case, the peripheral portion of the gate pad wiring 68 may be drawn from above the main surface insulating film 62 onto a portion of the trench isolation structure 26 (see FIG. 6) that defines the pad region 16, and may be connected to the isolated buried electrode 32 (see FIG. 6). The peripheral portion of the gate pad wiring 68 may also cover a portion (first end 38A and second end 38B (see FIG. 2)) of the plurality of trench gate structures 38, and may be connected to the plurality of buried gate electrodes 44 (see FIG. 6).

[0065] The gate line wiring 70 is disposed inside a portion of the insulating film 60 that covers the outer periphery region 18. As shown in FIGS. 5 to 7 , the gate line wiring 70 faces the well region 54 in the thickness direction (Z direction) of the chip 12. Specifically, the gate line wiring 70 is disposed in the form of a film on the main surface insulating film 62 and is covered by the interlayer insulating film 64. In the first embodiment, the gate line wiring 70 is disposed only in the portion that covers the well region 54. That is, the gate line wiring 70 faces the inner portion of the well region 54, spaced apart from the outer edge 54B and the inner edge 54A of the well region 54 in a plan view. Moreover, the entire area of ​​the gate line wiring 70 faces the well region 54 across the main surface insulating film 62.

[0066] As shown in FIG. 3 , the gate line wiring 70 extends in a strip shape along the well region 54 in a plan view. The gate line wiring 70 preferably defines the IGBT region 14 in multiple directions in a plan view. In the first embodiment, the gate line wiring 70 is formed in a strip shape extending along the first to fourth side surfaces 12C to 12F in a plan view. The gate line wiring 70 defines the IGBT region 14 in four directions. The gate line wiring 70 may be formed in an endless strip shape or a strip shape with edges so as to surround the IGBT region 14. In one example, the gate line wiring 70 is formed in a ring shape (a square ring shape in the first embodiment) surrounding the IGBT region 14.

[0067] The gate line wiring 70 is formed integrally with the gate pad wiring 68 at a portion extending along the third side surface 12E. In other words, the gate line wiring 70 integrally includes the gate pad wiring 68 drawn from the peripheral region 18 to the pad region 16. The gate line wiring 70 has a width less than the width of the well region 54. The width of the gate line wiring 70 may be 10 μm or more and 100 μm or less. The width of the gate line wiring 70 is preferably 15 μm or more and 60 μm or less. Here, the width of the gate line wiring 70 can be defined by the dimension in a direction perpendicular to the direction in which the gate line wiring 70 extends in a plan view.

[0068] 4 and 6 , the plurality of gate connection wirings 72 are disposed inside the insulating film 60 so as to electrically connect the gate line wiring 70 to the plurality of trench gate structures 38. The plurality of gate connection wirings 72 are drawn from a portion of the gate line wiring 70 extending along the first side surface 12C (see FIG. 3 ) toward the first ends 38A (see FIG. 2 ) of the plurality of trench gate structures 38. The plurality of gate connection wirings 72 are drawn from a portion of the gate line wiring 70 extending along the second side surface 12D (see FIG. 3 ) toward the second ends 38B (see FIG. 2 ) of the plurality of trench gate structures 38.

[0069] The plurality of gate connection wirings 72 are arranged at intervals along the gate line wiring 70 on the first side surface 12C side. Each gate connection wiring 72 on the first side surface 12C side is drawn out toward the trench isolation structure 26. The plurality of gate connection wirings 72 are preferably arranged at equal intervals in the X direction. The plurality of gate connection wirings 72 are drawn out from above the main surface insulating film 62 onto the trench isolation structure 26 on the first side surface 12C side and connected to the isolation buried electrode 32. In the first embodiment, the plurality of gate connection wirings 72 respectively cover the first ends 38A of the plurality of trench gate structures 38 and are connected to the plurality of gate buried electrodes 44.

[0070] The plurality of gate connection wirings 72 are arranged at intervals along the gate line wiring 70 on the second side surface 12D side. Each gate connection wiring 72 on the second side surface 12D side is drawn out toward the trench isolation structure 26. The plurality of gate connection wirings 72 are preferably arranged at equal intervals in the X direction. The plurality of gate connection wirings 72 are drawn out from above the main surface insulating film 62 onto the trench isolation structure 26 on the second side surface 12D side and connected to the isolated buried electrode 32.

[0071] In the first embodiment, the plurality of gate connection wirings 72 respectively cover the second ends 38B of the plurality of trench gate structures 38 and are connected to the plurality of gate buried electrodes 44. In the first embodiment, the gate wiring 66 is made of the same conductive material as the isolated buried electrode 32 and the plurality of gate buried electrodes 44. The gate wiring 66 includes lead-out portions that are led out from the isolated buried electrode 32 and the plurality of gate buried electrodes 44 onto the main surface insulating film 62 (see FIG. 6 ).

[0072] 5, the semiconductor device 10 has a plurality of emitter openings 74 that expose the plurality of emitter regions 46 in a portion of the insulating film 60 that covers the IGBT region 14. The plurality of emitter openings 74 are formed in a one-to-one correspondence with the plurality of contact holes 48. The plurality of emitter openings 74 are each connected to the corresponding contact holes 48. The plurality of emitter openings 74 are each formed in a strip shape that extends along the corresponding contact hole 48 in a plan view.

[0073] The semiconductor device 10 includes a plurality of emitter connection electrodes 76 embedded in the insulating film 60 so as to be electrically connected to the plurality of emitter regions 46. The plurality of emitter connection electrodes 76 are embedded in the plurality of emitter openings 74. The plurality of emitter connection electrodes 76 extend from the plurality of emitter openings 74 into the plurality of contact holes 48, thereby being electrically connected to the emitter regions 46 and the contact region 50.

[0074] Each emitter-connecting electrode 76 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, each emitter-connecting electrode 76 has a stacked structure including a Ti-based metal film and a W-based metal film. The Ti-based metal may include at least one of a pure Ti film (a Ti film with a purity of 99% or more) and a Ti alloy film. The Ti alloy film may be a TiN film. The W-based metal may include at least one of a pure W film (a W film with a purity of 99% or more) and a W alloy film.

[0075] The Al-based metal film may include at least one of a pure Al film (an Al film with a purity of 99% or more) and an Al alloy film. The Al alloy film may include at least one of an AlCu alloy, an AlSi alloy, and an AlSiCu alloy. The Cu-based metal may include at least one of a pure Cu film (a Cu film with a purity of 99% or more) and a Cu alloy film. In the following description, the Ti-based metal film, the W-based metal film, the Al-based metal film, and the Cu-based metal film include the above.

[0076] The semiconductor device 10 includes at least one gate opening 78 (a plurality of gate openings in the first embodiment) that selectively exposes the gate line wiring 70 in a portion of the insulating film 60 that covers the gate line wiring 70. The number of gate openings 78 can be changed as desired. In one example, a single gate opening 78 may be formed in the insulating film 60.

[0077] 4 and 5 , the gate openings 78 are spaced apart from the inner and outer edges of the gate line wiring 70 to expose the inner portions of the gate line wiring 70. The gate openings 78 are formed at intervals from one another from the IGBT region 14 toward the peripheral edge of the chip 12. Each gate opening 78 extends in a strip shape along the gate line wiring 70. Each gate opening 78 may be formed in an endless strip shape or a strip shape with edges so as to surround the IGBT region 14. In one example, each gate opening 78 is formed in a ring shape (a square ring shape in the first embodiment) surrounding the IGBT region 14.

[0078] Although specific illustrations are omitted, the semiconductor device 10 may include at least one gate opening 78 (multiple in the first embodiment) that selectively exposes the gate pad wiring 68 in the portion of the insulating film 60 that covers the gate pad wiring 68.

[0079] The semiconductor device 10 includes at least one gate connection electrode 80 (multiple in the first embodiment) embedded in the insulating film 60 so as to be electrically connected to the gate line wiring 70. Each gate connection electrode 80 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, each gate connection electrode 80 has a stacked structure including a Ti-based metal film and a W-based metal film.

[0080] The plurality of gate connection electrodes 80 are embedded in the plurality of gate openings 78 in a one-to-one correspondence, respectively. The plurality of gate connection electrodes 80 are electrically connected to the gate line wiring 70 in the corresponding gate openings 78. When a gate opening 78 that exposes the gate pad wiring 68 is formed in the insulating film 60, the gate connection electrode 80 may be formed in the gate opening 78 so as to be electrically connected to the gate pad wiring 68.

[0081] The semiconductor device 10 includes a plurality of well openings 82 that selectively expose the well region 54 in a portion of the insulating film 60 that covers the peripheral region 18. The plurality of well openings 82 include at least one (multiple in the first embodiment) first well opening 82A that exposes the well region 54 on the IGBT region 14 side and at least one (multiple in the first embodiment) second well opening 82B that exposes the well region 54 on the peripheral edge side of the chip 12. The number of first well openings 82A and the number of second well openings 82B can be changed as desired. In one example, a single first well opening 82A may be formed in the insulating film 60. In another example, a single second well opening 82B may be formed in the insulating film 60.

[0082] The multiple first well openings 82A are formed at intervals from the middle of the well region 54 in the width direction toward the inner edge 54A of the well region 54. The multiple first well openings 82A selectively expose the region of the well region 54 on the inner edge 54A side. Specifically, the multiple first well openings 82A are formed at intervals from the gate line wiring 70 toward the inner edge 54A of the well region 54, thereby selectively exposing the inner edge portion of the well region 54.

[0083] 4 and 5 , the multiple first well openings 82A are formed at intervals from one another from the IGBT region 14 side toward the peripheral edge of the chip 12. Each first well opening 82A extends in a strip shape along the well region 54. Each first well opening 82A has a portion extending in the X direction along the well region 54 and a portion extending in the Y direction along the well region 54.

[0084] 4 , each first well opening 82A includes a plurality of segment openings 82AA formed at intervals so as to expose regions between the plurality of gate connection wirings 72 in a portion extending in the X direction. In other words, the plurality of segment openings 82AA are formed at intervals from the plurality of gate connection wirings 72 so as not to expose the plurality of gate connection wirings 72. The plurality of segment openings 82AA are arranged in a region surrounded by the trench isolation structure 26 (the plurality of trench gate structures 38), the gate line wirings 70, and the plurality of gate connection wirings 72. The plurality of segment openings 82AA are each formed in a strip shape extending in the X direction.

[0085] 5, the plurality of second well openings 82B are formed at intervals from the middle of the well region 54 in the width direction toward the outer edge 54B of the well region 54. The plurality of second well openings 82B selectively expose the region of the well region 54 on the outer edge 54B side. Specifically, the plurality of second well openings 82B are formed at intervals from the gate line wiring 70 toward the outer edge 54B of the well region 54, thereby selectively exposing the outer edge portion of the well region 54.

[0086] 4 and 5 , the multiple second well openings 82B are formed at intervals from one another from the IGBT region 14 toward the peripheral edge of the chip 12. Each second well opening 82B extends in a strip shape along the well region 54. Each second well opening 82B may be formed in an endless strip shape or a strip shape with edges so as to surround the IGBT region 14. In one example, each second well opening 82B is formed in a ring shape (a square ring shape in the first embodiment) surrounding the IGBT region 14.

[0087] 5, the semiconductor device 10 includes a plurality of well connection electrodes 84 embedded in the insulating film 60 so as to be electrically connected to the well regions 54. Each well connection electrode 84 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, each well connection electrode 84 has a stacked structure including a Ti-based metal film and a W-based metal film.

[0088] The multiple well-connecting electrodes 84 include at least one (multiple in the first embodiment) first well-connecting electrode 84A and at least one (multiple in the first embodiment) second well-connecting electrode 84B. Each first well-connecting electrode 84A is connected to the well region 54 on the inner edge 54A side of the well region 54 (toward the IGBT region 14). Each second well-connecting electrode 84B is connected to the well region 54 on the outer edge 54B side of the well region 54 (toward the peripheral edge of the chip 12). The number of first well-connecting electrodes 84A and the number of second well-connecting electrodes 84B can be changed as desired. In one example, there may be a single first well-connecting electrode 84A. In another example, there may be a single second well-connecting electrode 84B.

[0089] The plurality of first well connection electrodes 84A are embedded in the plurality of first well openings 82A in a one-to-one correspondence. That is, the plurality of first well connection electrodes 84A are formed at intervals from the middle of the well region 54 in the width direction toward the inner edge 54A of the well region 54. The plurality of first well connection electrodes 84A are electrically connected to a region of the well region 54 on the inner edge 54A side. Specifically, the plurality of first well connection electrodes 84A are formed at intervals from the gate line wiring 70 in a region on the inner edge 54A side of the well region 54, thereby being electrically connected to the inner edge of the well region 54.

[0090] The second well connection electrodes 84B are embedded in the second well openings 82B in a one-to-one correspondence. That is, the second well connection electrodes 84B are formed at intervals from the middle of the well region 54 in the width direction toward the outer edge 54B of the well region 54. Here, the width direction of the well region 54 can be defined as a direction perpendicular to the direction in which the well region 54 extends in a plan view. The second well connection electrodes 84B are electrically connected to a region of the well region 54 on the outer edge 54B side. Specifically, the second well connection electrodes 84B are formed at intervals in a region on the outer edge 54B side of the well region 54 from the gate line wiring 70, thereby electrically connecting to the outer edge of the well region 54.

[0091] As shown in FIG. 1 , the semiconductor device 10 includes a gate electrode 86 disposed on the insulating film 60. The gate electrode 86 is made of a conductive material different from that of the gate wiring 66 (see FIG. 3 ). In the first embodiment, the gate electrode 86 is made of a metal film. The gate electrode 86 has a lower resistance value than the gate wiring 66. The gate electrode 86 may be referred to as a "gate metal." The gate electrode 86 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, the gate electrode 86 has a stacked structure including a Ti-based metal film and an Al-based metal film.

[0092] 1 and 2 , the gate electrode 86 includes a gate pad electrode 88 and a gate line electrode 90. The gate line electrode 90 may also be referred to as a "gate finger electrode." The gate pad electrode 88 is disposed on a portion of the insulating film 60 that covers the gate pad wiring 68. In one example, the gate pad electrode 88 is formed in a polygonal shape (a quadrangular shape in the first embodiment) that matches the pad region 16 in a plan view.

[0093] The gate pad electrode 88 faces the gate pad wiring 68 (see FIG. 3 ) across a part of the insulating film 60 (interlayer insulating film 64) in the thickness direction of the chip 12. The gate pad electrode 88 faces the pad well region 52 (see FIG. 3 ) across the insulating film 60 and the gate pad wiring 68 in the thickness direction of the chip 12. When the gate connection electrode 80 is connected to the gate pad wiring 68, the gate pad electrode 88 is electrically connected to the gate pad wiring 68 via the gate connection electrode 80 (see FIG. 5 ).

[0094] The gate pad electrode 88 may have a planar area equal to or larger than the planar area of ​​the pad region 16, or may have a planar area smaller than the planar area of ​​the pad region 16. The gate pad electrode 88 may have a planar area equal to or larger than the planar area of ​​the gate pad wiring 68, or may have a planar area smaller than the planar area of ​​the gate pad wiring 68.

[0095] 5 to 7 , the gate line electrode 90 is disposed on the insulating film 60 on a portion thereof covering the gate line wiring 70. The gate line electrode 90 is formed integrally with the gate pad electrode 88 (see FIG. 2 ). The gate line electrode 90 is drawn out in a strip shape from the gate pad electrode 88 onto the insulating film 60. In the first embodiment, the gate line electrode 90 is drawn out from the gate pad electrode 88 onto the insulating film 60 to a region between the first well connecting electrode 84A and the second well connecting electrode 84B.

[0096] The gate line electrode 90 is disposed at a distance from the first well connection electrode 84A and the second well connection electrode 84B. The gate line electrode 90 covers the multiple gate connection electrodes 80. That is, the gate line electrode 90 is disposed at a distance from the first well connection electrode 84A toward the outer edge 54B of the well region 54 (toward the periphery of the chip 12). The gate line electrode 90 is disposed at a distance from the second well connection electrode 84B toward the inner edge 54A of the well region 54 (toward the IGBT region 14). The gate line electrode 90 is electrically connected to the gate line wiring 70 via the multiple gate connection electrodes 80.

[0097] The gate line electrode 90 faces the gate line electrode 90 in the thickness direction of the chip 12, with a part of the insulating film 60 sandwiched therebetween. The gate line electrode 90 faces the well region 54 in the thickness direction of the chip 12, with the insulating film 60 and the gate line wiring 70 sandwiched therebetween. The gate line electrode 90 has a width less than the width of the well region 54. It is preferable that the gate line electrode 90 has a width less than the width of the gate line wiring 70. The width of the gate line electrode 90 can be changed as desired, and may be, for example, greater than or equal to the width of the gate line wiring 70.

[0098] As shown in FIGS. 1 and 2 , the gate line electrode 90 extends in a strip shape along the gate line wiring 70 in a plan view. The gate line electrode 90 preferably defines the IGBT region 14 from multiple directions in a plan view. In the first embodiment, the gate line electrode 90 is formed in a strip shape extending along the first to fourth side surfaces 12C to 12F in a plan view. The gate line electrode 90 defines the IGBT region 14 from four directions. The gate line electrode 90 may be formed in an endless strip shape or a strip shape with edges so as to surround the IGBT region 14. In one example, the gate line electrode 90 is formed in a ring shape (a quadrangular ring shape in the first embodiment) surrounding the IGBT region 14, and has a pair of open ends 90A in the portion extending along the fourth side surface 12F.

[0099] The semiconductor device 10 includes an emitter electrode 92 disposed on the insulating film 60 and spaced apart from the gate electrode 86. The emitter electrode 92 is made of a different conductive material than the gate wiring 66. In the first embodiment, the emitter electrode 92 is made of a metal film. The emitter electrode 92 has a lower resistance than the gate wiring 66 (see FIG. 3). The emitter electrode 92 may also be referred to as an "emitter metal." The emitter electrode 92 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, the emitter electrode 92 has a layered structure including a Ti-based metal film and an Al-based metal film. In other words, the emitter electrode 92 is made of the same material as the gate electrode 86.

[0100] The emitter electrode 92 includes an emitter pad electrode 94 and an emitter line electrode 96. The emitter line electrode 96 may also be referred to as an "emitter finger electrode." The emitter pad electrode 94 is disposed on a portion of the insulating film 60 that covers the IGBT region 14. In one example, the emitter pad electrode 94 is disposed spaced apart from the gate pad electrode 88 and the gate line electrode 90. The emitter pad electrode 94 is formed in a polygonal shape having a recess that is recessed along the gate pad electrode 88 in a plan view.

[0101] 5 , the emitter pad electrode 94 collectively covers the plurality of trench gate structures 38 and the plurality of emitter connecting electrodes 76. The emitter pad electrode 94 faces the plurality of trench gate structures 38 with the insulating film 60 sandwiched therebetween. The emitter pad electrode 94 is electrically connected to the plurality of emitter regions 46 via the plurality of emitter connecting electrodes 76. The emitter pad electrode 94 includes an emitter leading portion 94A that is led from the IGBT region 14 to the outer periphery region 18 across the region immediately above the trench isolation structure 26 so as to face the well region 54 in the thickness direction of the chip 12.

[0102] The emitter lead-out portion 94A covers the region on the inner edge 54A side of the well region 54 with respect to the middle portion in the width direction of the well region 54. Specifically, the emitter lead-out portion 94A covers the inner edge portion of the well region 54 at a distance from the gate line electrode 90 toward the IGBT region 14, and also collectively covers the plurality of first well connection electrodes 84A. As a result, the emitter pad electrode 94 is electrically connected to the inner edge portion of the well region 54 via the plurality of first well connection electrodes 84A.

[0103] 1 and 5, the emitter line electrode 96 is formed integrally with the emitter pad electrode 94. The emitter line electrode 96 is drawn out from the emitter pad electrode 94 onto the insulating film 60. Specifically, the emitter line electrode 96 passes through the region between the pair of open ends 90A of the gate line electrode 90 on the insulating film 60 and is drawn out in a strip shape from the emitter pad electrode 94 to the outer circumferential region 18.

[0104] 5 to 7, the emitter line electrode 96 is routed over the portion of the insulating film 60 that covers the well region 54. In other words, the emitter line electrode 96 faces the well region 54 across the insulating film 60 in the thickness direction of the chip 12. The emitter line electrode 96 is arranged at a distance from the gate line electrode 90 toward the outer edge 54B of the well region 54 (toward the peripheral edge of the chip 12) so as to cover the multiple second well connection electrodes 84B. As a result, the emitter line electrode 96 is electrically connected to the outer edge of the well region 54 via the multiple second well connection electrodes 84B.

[0105] As shown in FIGS. 1 and 2 , the emitter line electrode 96 extends in a strip shape along the outer edge 54B of the well region 54 in a plan view. The emitter line electrode 96 preferably defines the IGBT region 14 from multiple directions in a plan view. In the first embodiment, the emitter line electrode 96 is formed in a strip shape extending along the first to fourth side surfaces 12C to 12F in a plan view. The emitter line electrode 96 defines the IGBT region 14 from four directions. The emitter line electrode 96 may be formed in an endless strip shape or a strip shape with edges so as to surround the IGBT region 14. In one example, the emitter line electrode 96 is formed in a ring shape (a square ring shape in the first embodiment) surrounding the IGBT region 14.

[0106] 8 , the insulating film 60 includes at least one field opening 98 (multiple in the first embodiment) that selectively exposes each field region 56 in the peripheral region 18. The multiple field openings 98 expose corresponding field regions 56 in a one-to-many correspondence. Alternatively, a single field opening 98 may expose corresponding field regions 56 in a one-to-one correspondence. The multiple field openings 98 are formed in a strip shape extending along the corresponding field regions 56. In one example, the multiple field openings 98 are formed in a ring shape (a square ring shape in the first embodiment) extending along the corresponding field regions 56.

[0107] The semiconductor device 10 includes at least one field connection electrode 100 (multiple in the first embodiment) embedded in an insulating film 60 so as to be electrically connected to a corresponding field region 56. Each field connection electrode 100 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, each field connection electrode 100 has a layered structure including a Ti-based metal film and a W-based metal film.

[0108] The plurality of field connection electrodes 100 are embedded in the plurality of field openings 98 in a one-to-one correspondence, respectively. The plurality of field connection electrodes 100 are electrically connected to the corresponding field regions 56 in the corresponding field openings 98. In the first embodiment, the plurality of field connection electrodes 100 are formed in an electrically floating state.

[0109] The semiconductor device 10 includes a plurality of field electrodes 102 formed on the insulating film 60 in the peripheral region 18. The plurality of field electrodes 102 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In one example, each field electrode 102 may have a stacked structure including a Ti-based metal film and a W-based metal film. The plurality of field electrodes 102 are formed in an electrically floating state.

[0110] The plurality of field electrodes 102 are formed in one-to-one correspondence with the corresponding field regions 56. Each field electrode 102 collectively covers the corresponding plurality of field connection electrodes 100. Each field electrode 102 is electrically connected to the corresponding field region 56 via the corresponding plurality of field connection electrodes 100.

[0111] The plurality of field electrodes 102 are formed in strip shapes extending along the corresponding field regions 56. In one example, the plurality of field electrodes 102 are formed in ring shapes (square ring shapes in the first embodiment) extending along the corresponding field regions 56.

[0112] The multiple field electrodes 102 include inner field electrodes 102A-102C corresponding to the inner field regions 56A-56C and an outermost field electrode 102D corresponding to the outermost field region 56D. The outermost field electrode 102D includes a field lead portion 102E extending toward the peripheral edge of the chip 12. Therefore, the width of the outermost field electrode 102D is greater than the width of the inner field electrodes 102A-102C. In one example, the widths of the inner field electrodes 102A-102C are equal to each other.

[0113] The insulating film 60 includes a channel stop opening 104 that exposes the channel stop region 58 in the peripheral region 18. The channel stop opening 104 is formed in a strip shape extending along the channel stop region 58. In one example, the channel stop opening 104 is formed in a ring shape (a square ring shape in the first embodiment) extending along the channel stop region 58. The channel stop opening 104 communicates with the peripheral edge of the chip 12.

[0114] The semiconductor device 10 includes a channel stop electrode 106 formed on the insulating film 60 in the peripheral region 18. The channel stop electrode 106 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, the channel stop electrode 106 may have a stacked structure including a Ti-based metal film and a W-based metal film. The channel stop electrode 106 is formed in an electrically floating state.

[0115] The channel stop electrode 106 is formed in a strip shape extending along the channel stop region 58. In one example, the channel stop electrode 106 is formed in a strip shape (a square ring shape in the first embodiment) extending along the channel stop region 58. The channel stop electrode 106 is electrically connected to the channel stop region 58 by extending from above the insulating film 60 into the channel stop opening 104. The channel stop electrode 106 may be formed at a distance from the periphery of the chip 12 toward the IGBT region 14 so as to expose the peripheral portion (channel stop region 58) of the first main surface 12A.

[0116] The semiconductor device 10 includes a collector electrode 108 provided on the second main surface 12B. In one example, the collector electrode 108 covers the second main surface 12B. The collector electrode 108 is electrically connected to the collector region 24 exposed from the second main surface 12B. The collector electrode 108 forms an ohmic contact with the collector region 24. The collector electrode 108 may cover the entire second main surface 12B so as to be continuous with the periphery of the chip 12 (the first to fourth side surfaces 12C to 12F).

[0117] The collector electrode 108 may have a single-film structure or a multilayer structure including at least one of a Ti film, a Ni film, a Pd film, an Au film, an Ag film, and an Al film. The collector electrode 108 preferably includes at least a Ti film that directly covers the second main surface 12B. The collector electrode 108 may have a multilayer structure including, for example, a Ti film, a Ni film, a Pd film, and an Au film that are stacked in this order from the second main surface 12B side.

[0118] 8, the semiconductor device 10 includes an n-type cathode region 110 formed in the surface layer portion of the second main surface 12B in the peripheral region 18. The cathode region 110 has a higher n-type impurity concentration than the p-type impurity concentration of the collector region 24. The cathode region 110 is a region in which the conductivity type of a portion of the collector region 24 is replaced from p-type to n-type. The cathode region 110 preferably has a higher n-type impurity concentration than the drift region 20 (buffer region 22).

[0119] The cathode region 110 extends in a layer shape along the second major surface 12B. The cathode region 110 is exposed from the second major surface 12B. The cathode region 110 penetrates the collector region 24 so as to be connected to the buffer region 22. The cathode region 110 is electrically connected to the collector electrode 108. The cathode region 110 forms an ohmic contact with the collector electrode 108. The cathode region 110 and the well region 54 form a diode 112. The diode 112 is configured as a freewheeling diode for the IGBT structure 34.

[0120] When a forward voltage VF of the diode 112 is applied between the emitter electrode 92 and the collector electrode 108, a forward current IF flows through the diode 112. The forward current IF flows from the second well-connecting electrode 84B to the cathode region 110, for example.

[0121] The cathode region 110 is disposed closer to the peripheral edge of the chip 12 than the well region 54 in a plan view. More specifically, the cathode region 110 is disposed closer to the peripheral edge of the chip 12 than the outer edge 54B of the well region 54 in a plan view. In other words, the cathode region 110 is disposed closer to the multiple field regions 56 than the well region 54 in a plan view.

[0122] In one example, the cathode region 110 is arranged at a distance from the well region 54 on the peripheral edge side of the chip 12 so as not to face the well region 54 in the thickness direction of the chip 12. In this way, it can be said that the cathode region 110 is arranged at a distance from the IGBT region 14 on the peripheral edge side of the chip 12 so as not to face the IGBT region 14 in the thickness direction of the chip 12. In other words, the cathode region 110 is formed only in the outer periphery region 18, and not in the IGBT region 14. In this case, it is possible to suppress the electrical influence from the IGBT region 14 to the diode 112, and also to suppress the electrical influence from the diode 112 to the IGBT region 14.

[0123] The cathode region 110 may be formed in an endless or ended band shape so as to surround the IGBT region 14 in a plan view. The cathode region 110 may be formed in an endless or ended band shape so as to surround the well region 54 in a plan view. In one example, the cathode region 110 is formed in a ring shape (a quadrangular ring shape in the first embodiment) so as to surround the well region 54. The cathode region 110 in the first embodiment is formed in a quadrangular ring shape with rounded corners in a plan view.

[0124] The width W1 of the cathode region 110 is smaller than the width WP of the well region 54. The width W1 of the cathode region 110 is smaller than the distance Dwc between the well region 54 and the channel stop region 58. The width W1 of the cathode region 110 is smaller than the total width WT of the multiple field regions 56. In the first embodiment, the width W1 of the cathode region 110 is equal to the width of the inner field region 56A. Note that in the first embodiment, the widths of the inner field regions 56B and 56C are equal to the width of the inner field region 56A, so the width W1 of the cathode region 110 can also be said to be equal to the widths of the inner field regions 56B and 56C. In other words, in the first embodiment, the width W1 of the cathode region 110 can be said to be equal to the width WF of the field region 56.

[0125] The width W1 of the cathode region 110 can be changed arbitrarily and may be greater than the width of the inner field region 56A, for example. In this case, the width W1 of the cathode region 110 is, for example, less than twice the width of the inner field region 56A. The width W1 of the cathode region 110 may be greater than the width WF of the field region 56. In this case, the width W1 of the cathode region 110 is, for example, less than twice the width WF of the field region 56.

[0126] The cathode region 110 is disposed in a position facing at least one of the plurality of field regions 56 in the thickness direction (Z direction) of the chip 12. The cathode region 110 is disposed at a distance from the channel stop region 58 toward the plurality of field regions 56 so as not to face the channel stop region 58 in the thickness direction of the chip 12. It can be said that the cathode region 110 is disposed in a position facing the position spaced apart from the channel stop region 58 toward the field region 56 in the thickness direction of the chip 12. In this way, the cathode region 110 is disposed closer to the periphery of the chip 12 than the well region 54 and closer to the well region 54 than the channel stop region 58 in a plan view. Therefore, both the IGBT region 14 and the well region 54 face the collector region 24 in the thickness direction of the chip 12.

[0127] In one example, the cathode region 110 may be disposed in a position facing one of the multiple field regions 56 closer to the well region 54 in the thickness direction of the chip 12. In other words, the cathode region 110 may be disposed in a position facing one of the inner field regions 56A to 56C in the thickness direction of the chip 12. In the first embodiment, the cathode region 110 is disposed in a position facing the inner field region 56B in the thickness direction of the chip 12. When the annular cathode region 110 faces one field region 56, it may face the field region 56 over the entire periphery in the thickness direction of the chip 12.

[0128] (Method of Setting the Position of the Cathode Region) A method of setting the position of the cathode region 110 will be described with reference to Figures 9 to 11. In the following description, for components in the semiconductor device 10 denoted by reference numerals, please refer to the reference numerals of the components of the semiconductor device 10 shown in Figures 1 to 8.

[0129] 9 to 11 are graphs showing the electric field strength in the peripheral region 18 when a predetermined collector-emitter voltage Vce is applied. The predetermined collector-emitter voltage Vce is, for example, 650V.

[0130] 9 to 11 show the electric field strength when the spacing between the multiple field regions 56 is changed. The graph in FIG. 9 shows, as a first example, the electric field strength in the outer periphery when the spacing between the multiple field regions 56 is a reference value. The graph in FIG. 10 shows, as a second example, the electric field strength in the outer periphery when the spacing between the multiple field regions 56 is a first spacing that is smaller than the reference value. The graph in FIG. 11 shows, as a third example, the electric field strength in the outer periphery when the spacing between the multiple field regions 56 is a second spacing that is smaller than the first spacing. Note that in the graphs in FIGS. 9 to 11, the width of each field region 56 is constant. Here, the width of each field region 56 is set to 10 μm.

[0131] Here, examples of reference values ​​are 18 μm for the distance between inner field region 56A and inner field region 56B, 21 μm for the distance between inner field region 56B and inner field region 56C, and 24 μm for the distance between inner field region 56C and outermost field region 56D. Also, the distance between outer edge 54B of well region 54 and inner field region 56A is 16 μm.

[0132] An example of the first distance is 15 μm between inner field region 56A and inner field region 56B, 18 μm between inner field region 56B and inner field region 56C, and 21 μm between inner field region 56C and outermost field region 56D. Also, the distance between outer edge 54B of well region 54 and inner field region 56A is 13 μm.

[0133] An example of the second distance is 13 μm between the inner field region 56A and the inner field region 56B, 16 μm between the inner field region 56B and the inner field region 56C, and 19 μm between the inner field region 56C and the outermost field region 56D. Also, the distance between the outer edge 54B of the well region 54 and the inner field region 56A is 11 μm.

[0134] The range RW on the horizontal axis in Figures 9 to 11 indicates the placement area of ​​the outer edge of the well region 54 within the outer periphery region 18. The range RA on the horizontal axis in Figures 9 to 11 indicates the placement area of ​​the inner field region 56A within the outer periphery region 18. The range RB on the horizontal axis in Figures 9 to 11 indicates the placement area of ​​the inner field region 56B within the outer periphery region 18. The range RC on the horizontal axis in Figures 9 to 11 indicates the placement area of ​​the inner field region 56C within the outer periphery region 18. The range RD on the horizontal axis in Figures 9 to 11 indicates the placement area of ​​the outermost field region 56D within the outer periphery region 18.

[0135] 9 to 11, peaks of electric field strength occur at the outer edge of the well region 54, the inner field regions 56A to 56C, and the outermost field region 56D. In other words, the electric field strength is low in the regions between adjacent field regions 56 among the multiple field regions 56. For this reason, it is preferable that the cathode region 110 is not disposed so as to face only the regions between adjacent field regions 56 among the multiple field regions 56 in the thickness direction. In other words, it is preferable that part or all of the cathode region 110 be disposed in a position facing the inner field regions 56A to 56C and the outermost field region 56D in the thickness direction.

[0136] As shown in Figure 9, in the first example, the position PK corresponding to the maximum electric field strength is located within the range RA corresponding to the inner field region 56A. As shown in Figure 10, in the second example, the position PK corresponding to the maximum electric field strength is located within the range RB corresponding to the inner field region 56B. As shown in Figure 11, in the third example, the position PK corresponding to the maximum electric field strength is located within the range RC corresponding to the inner field region 56C. In this way, as the spacing between the multiple field regions 56 is narrowed, the position PK of the maximum electric field strength moves toward the periphery of the chip 12. Therefore, it can be said that the position PK of the maximum electric field strength can be adjusted by adjusting the spacing between the multiple field regions 56.

[0137] Here, the plurality of field regions 56 includes a specific field region to which an electric field of maximum strength is applied when a collector-emitter voltage Vce is applied. In this case, the cathode region 110 is disposed in a position opposite the specific field region in the thickness direction of the chip 12.

[0138] 9, in the first example, the position PK corresponding to the maximum electric field strength is the inner field region 56A, and therefore the specific field region is the inner field region 56A. Therefore, the cathode region 110 is disposed directly below the inner field region 56A.

[0139] 10, in the second example, the position PK corresponding to the maximum electric field strength is the inner field region 56B, and therefore the specific field region is the inner field region 56B. Therefore, the cathode region 110 is disposed directly below the inner field region 56B.

[0140] 11, in the third example, the position PK corresponding to the maximum electric field strength is the inner field region 56C, and therefore the specific field region is the inner field region 56C. Therefore, the cathode region 110 is disposed directly below the inner field region 56C.

[0141] In this way, the spacing between the multiple field regions 56 is adjusted during design so that the position PK corresponding to the maximum electric field strength is at the desired position. In other words, by adjusting the spacing between the multiple field regions 56 during design, a specific field region including the position PK corresponding to the maximum electric field strength is set. Then, the cathode region 110 is placed at a position opposite the specific field region in the thickness direction. As a result, the cathode region 110 is placed at a position where the electric field strength is maximum when the collector-emitter voltage Vce is applied.

[0142] Next, a method for setting the position of the cathode region 110 in consideration of the diode characteristics will be described. FIG. 12 is a graph showing the relationship between the position of the cathode region 110 and the forward current IF of the diode 112. The vertical axis of FIG. 12 represents the forward current IF (A). The horizontal axis of FIG. 12 represents the position of the cathode region 110. The graph of FIG. 12 shows the change in forward current IF when the position of the cathode region 110 is changed from directly below the well region 54 to directly below the inner field region 56C. The width of the cathode region 110 is fixed to a constant value (10 μm in FIG. 12).

[0143] 12 , the first well reference position PW1 is a position directly below the first well connection electrode 84A. When a single first well connection electrode 84A is formed, the first well reference position PW1 is a position directly below the center of the single first well connection electrode 84A. When multiple first well connection electrodes 84A are formed, the first well reference position PW1 is a position directly below the midpoint between the innermost first well connection electrode 84A arranged on the IGBT region 14 side and the outermost first well connection electrode 84A arranged on the peripheral edge side of the chip 12. The first well reference position PW1 can also be said to be a position facing the first well connection electrode 84A in the thickness direction of the chip 12.

[0144] The second well reference position PW2 is a position directly below the second well connection electrode 84B. When a single second well connection electrode 84B is formed, the second well reference position PW2 is a position directly below the center of the single second well connection electrode 84B. When multiple second well connection electrodes 84B are formed, the second well reference position PW2 is a position directly below the midpoint between the innermost second well connection electrode 84B arranged on the IGBT region 14 side and the outermost second well connection electrode 84B arranged on the peripheral edge side of the chip 12. The second well reference position PW2 can also be said to be a position facing the second well connection electrode 84B in the thickness direction of the chip 12. Here, both the first well reference position PW1 and the second well reference position PW2 are examples of "well reference positions."

[0145] 12 , the forward current IF gradually decreases as the position of the cathode region 110 approaches the gate reference position PG from the first well reference position PW1. The forward current IF gradually increases as the position of the cathode region 110 approaches the second well reference position PW2 from the gate reference position PG. The forward current IF gradually decreases as the position of the cathode region 110 moves from the second well reference position PW2 toward the periphery of the chip 12. In other words, the forward current IF gradually decreases as the position of the cathode region 110 moves from the outer edge 54B of the well region 54 toward the channel stop region 58. In other words, the forward current IF gradually increases as the position of the cathode region 110 moves from the channel stop region 58 toward the outer edge 54B of the well region 54. For this reason, the forward current IF increases as the position of the cathode region 110 moves from the outermost field region 56D of the multiple field regions 56 toward the well region 54. That is, the forward current IF when the cathode region 110 is located directly below the inner field regions 56A-56C is greater than the forward current IF when the cathode region 110 is located directly below the outermost field region 56D. In addition, the forward current IF when the cathode region 110 is located directly below the inner field region 56B is greater than the forward current IF when the cathode region 110 is located directly below the inner field region 56C of the cathode region 110. The forward current IF when the cathode region 110 is located directly below the inner field region 56A is greater than the forward current IF when the cathode region 110 is located directly below the inner field region 56B of the cathode region 110.

[0146] For example, in the second example shown in Figure 10, the difference between the peak value of the electric field strength in the inner field region 56A and the peak value of the electric field strength in the inner field region 56B, which includes the position PK of maximum electric field strength, is small. Furthermore, the forward current I can be increased by positioning the cathode region 110 directly below the inner field region 56A rather than directly below the inner field region 56B. Thus, in the second example, by positioning the cathode region 110 directly below the inner field region 56A, the electric field in the inner field region 56A can be alleviated and the forward current I can be increased.

[0147] 11 , for example, the difference between the peak value of the electric field strength in the inner field region 56B and the peak value of the electric field strength in the inner field region 56C, which includes the position PK of maximum electric field strength, is small. Furthermore, the forward current I can be increased by positioning the cathode region 110 directly below the inner field region 56B rather than directly below the inner field region 56C. Thus, in the third example, by positioning the cathode region 110 directly below the inner field region 56B, the electric field in the inner field region 56B can be alleviated and the forward current I can be increased. As described above, the position of the cathode region 110 may be determined by considering the balance between alleviating electric field concentration in the outer circumferential region 18 and increasing the forward current I.

[0148] As another setting method, the spacing between the multiple field regions 56 is increased so that the position PK of maximum electric field strength is located in the inner field region 56A during design. In other words, the spacing between the multiple field regions 56 is set to a reference value. As a result, the cathode region 110 is positioned opposite in the thickness direction to the inner field region 56A that is closest to the well region 54 among the multiple field regions 56. This makes it possible to alleviate electric field concentration in the outer periphery region 18 and increase the forward current IF.

[0149] [Operations and Effects of the Embodiments] The semiconductor device 10 of the first embodiment provides the following operations and effects. (1-1) The semiconductor device 10 includes a chip 12 having a first main surface 12A and a second main surface 12B opposite to the first main surface 12A, a peripheral region 18 provided on the periphery of the first main surface 12A, an IGBT region 14 provided inside the peripheral region 18 on the first main surface 12A, a well region 54 of a first conductivity type provided in a surface layer portion of the first main surface 12A in the peripheral region 18 so as to define the IGBT region 14, and a well region 54 of a first conductivity type provided on the surface layer portion of the first main surface 12A of the peripheral region 18 at a distance from the well region 54 to the periphery of the chip 12. The peripheral region 18 includes a plurality of field regions 56 of a first conductivity type spaced apart from one another, a cathode region 110 of a second conductivity type provided in a surface layer portion of the second main surface 12B of the peripheral region 18 and constituting a diode 112 together with the well region 54, an insulating film 60 covering at least the well region 54, an emitter electrode 92 disposed on the insulating film 60 so as to be electrically connected to the well region 54, and a collector electrode 108 provided on the second main surface 12B so as to be electrically connected to the cathode region 110. The cathode region 110 is disposed closer to the periphery of the chip 12 than the well region 54 and at a position facing at least one of the plurality of field regions 56 in the thickness direction of the chip 12.

[0150] With this configuration, the cathode region 110 faces at least one of the field regions 56 in the thickness direction of the chip 12, thereby mitigating electric field concentration in the field regions 56. As a result, when a collector-emitter voltage Vce is applied, the voltage in the field regions 56 is less likely to reach a breakdown voltage (BV). This improves resistance to the breakdown voltage. In other words, the electrical characteristics of the semiconductor device 10 can be improved.

[0151] (1-2) The multiple field regions 56 include an outermost field region 56D that is closest to the periphery of the chip 12. The cathode region 110 is located opposite, in the thickness direction of the chip 12, the inner field regions 56A to 56C, which are located closer to the well region 54 than the outermost field region 56D among the multiple field regions 56.

[0152] Among the multiple field regions 56, the peak value of the electric field strength is likely to be higher in the inner field regions 56A-56C than in the outermost field region 56D. In consideration of this, the cathode region 110 is positioned opposite the inner field regions 56A-56C in the thickness direction of the chip 12. This reduces electric field concentration in the inner field regions 56A-56C, where the voltage of the multiple field regions 56 is likely to reach the breakdown voltage. This improves resistance to the breakdown voltage. In other words, the electrical characteristics of the semiconductor device 10 can be improved.

[0153] (1-3) The chip 12 includes a channel stop region 58 provided in a surface layer portion of the first main surface 12A of the peripheral region 18, spaced apart from the field region 56 toward the periphery of the chip 12. The cathode region 110 is disposed in a position facing the channel stop region 58 in the thickness direction of the chip 12, the position being spaced apart from the channel stop region 58 toward the field region 56.

[0154] With this configuration, the electric field strength in the channel stop region 58 is lower than that in the plurality of field regions 56. In other words, the channel stop region 58 is less likely to reach the breakdown voltage than the plurality of field regions 56. For this reason, the cathode region 110 is disposed in a position opposite, in the thickness direction of the chip 12, to the plurality of field regions 56 that are more likely to reach the breakdown voltage, thereby effectively alleviating electric field concentration.

[0155] (1-4) In plan view, the cathode region 110 is provided in a ring shape surrounding the well region 54. With this configuration, the cathode region 110 faces the multiple field regions 56 over the entire periphery in the thickness direction of the chip 12. This allows electric field concentration to be alleviated around the multiple field regions 56.

[0156] (1-5) The chip 12 includes a first conductivity type collector region 24 provided in a surface layer portion of the second main surface 12B. The cathode region 110 has a second conductivity type impurity concentration (n-type impurity concentration) that is higher than the first conductivity type impurity concentration (p-type impurity concentration) of the collector region 24. This configuration can enhance the effect of the cathode region 110 in mitigating electric field concentration in the multiple field regions 56.

[0157] (1-6) The plurality of field regions 56 includes a specific field region to which an electric field of maximum strength is applied when a collector-emitter voltage Vce is applied. The cathode region 110 is disposed at a position opposite the specific field region in the thickness direction of the chip 12.

[0158] With this configuration, cathode region 110 is positioned opposite, in the thickness direction of chip 12, a specific field region that was set during design, for example, by adjusting the spacing between multiple field regions. This ensures that cathode region 110 is positioned opposite, in the thickness direction, field region 56 to which the strongest electric field is applied. This effectively alleviates electric field concentration in field region 56 (specific field region) that is most likely to reach the breakdown voltage.

[0159] (1-7) The cathode region 110 faces one of the inner field regions 56A to 56C of the plurality of field regions 56, that is, the inner field region 56A or 56B closer to the well region 54, in the thickness direction of the chip 12.

[0160] This configuration shortens the current path between the cathode region 110 and the well region 54, thereby increasing the forward current I of the diode 112. When the cathode region 110 faces the inner field region 56A, which is closer to the well region 54 than the inner field region 56B in the thickness direction of the chip 12, the forward current I can be efficiently increased.

[0161] (1-8) The cathode region 110 is provided to face the opposing field region 56 over the entire periphery of the field region 56 in the thickness direction of the chip 12. This configuration allows the electric field concentration in the field region 56 to be alleviated over the entire periphery of the field region 56.

[0162] 13 to 20, a semiconductor device 10 according to a second embodiment will be described. The semiconductor device 10 according to the second embodiment differs from the semiconductor device 10 according to the first embodiment mainly in that an inner cathode region 120 is added. In the following description, components common to the semiconductor device 10 according to the first embodiment are designated by the same reference numerals, and description thereof will be omitted.

[0163] [Configuration and Arrangement of Inner Cathode Region] The configuration and arrangement of the inner cathode region 120 will be described with reference to Figures 13 and 14. Figures 13 and 14 schematically show the cross-sectional structure of a part of the IGBT region 14 and the outer circumferential region 18. The cross-sectional positions in Figures 13 and 14 are the same as the cross-sectional position in Figure 8. Figure 14 shows an enlarged view of the well region 54 and its surroundings in Figure 13.

[0164] As shown in FIG. 13 , the semiconductor device 10 of the second embodiment includes an n-type inner cathode region 120 formed in the outer peripheral region 18 in a surface layer portion of the second main surface 12B. The inner cathode region 120 has a higher n-type impurity concentration than the p-type impurity concentration of the collector region 24. Like the cathode region 110, the inner cathode region 120 is a region in which the conductivity type of a portion of the collector region 24 is changed from p-type to n-type. The inner cathode region 120 preferably has a higher n-type impurity concentration than the drift region 20 (buffer region 22). In one example, the n-type impurity concentration of the inner cathode region 120 is equal to the n-type impurity concentration of the cathode region 110. Note that the relationship between the n-type impurity concentrations of the inner cathode region 120 and the cathode region 110 can be changed as desired. In one example, the n-type impurity concentration of the inner cathode region 120 may be higher than the n-type impurity concentration of the cathode region 110. In one example, the n-type impurity concentration of the inner cathode region 120 may be lower than the n-type impurity concentration of the cathode region 110.

[0165] The inner cathode region 120 extends in a layer shape along the second major surface 12B. The inner cathode region 120 is exposed from the second major surface 12B. The inner cathode region 120 penetrates the collector region 24 so as to be connected to the buffer region 22. The inner cathode region 120 is electrically connected to the collector electrode 108. The inner cathode region 120 forms ohmic contact with the collector electrode 108.

[0166] The inner cathode region 120 is arranged at a distance from the cathode region 110 towards the IGBT region 14. More specifically, the inner cathode region 120 is arranged at a position facing the well region 54 in the thickness direction of the chip 12. The inner cathode region 120 faces the cathode region 110 in the surface layer portion of the second main surface 12B, with part of the collector region 24 sandwiched between them. The inner cathode region 120, together with the cathode region 110 and the well region 54, constitutes a diode 112.

[0167] The inner cathode region 120 may be formed in an endless band shape or an edged band shape in a plan view so as to surround the IGBT region 14. In one example, the inner cathode region 120 is formed in a ring shape (a square ring shape with rounded corners in the second embodiment) surrounding the IGBT region 14. The cathode region 110 surrounds the inner cathode region 120 in a plan view.

[0168] The inner cathode region 120 is arranged so that the well region 54 has a portion facing the inner cathode region 120 in the thickness direction of the chip 12 and a portion facing the collector region 24. In other words, the inner cathode region 120 is formed narrower than the well region 54 so as not to face the entire well region 54 in the thickness direction of the chip 12. The width W2 of the inner cathode region 120 may be 5 μm or more and 90 μm or less. The width W2 of the inner cathode region 120 may be 10 μm or more and 40 μm or less. Here, the width W2 of the inner cathode region 120 can be defined by the dimension in a direction perpendicular to the direction in which the inner cathode region 120 extends in a plan view.

[0169] The inner cathode region 120 is formed at a distance from the base region 36 on the peripheral edge side of the chip 12 so as not to face the base region 36 at least in the thickness direction of the chip 12. The inner cathode region 120 is arranged at a distance from the plurality of trench gate structures 38 on the peripheral edge side of the chip 12 so as not to face the plurality of trench gate structures 38 in the thickness direction of the chip 12. The inner cathode region 120 is arranged at a distance from the trench isolation structure 26 on the peripheral edge side of the chip 12 so as not to face the trench isolation structure 26 in the thickness direction of the chip 12.

[0170] In this way, the inner cathode region 120 is disposed at a distance from the IGBT region 14 toward the peripheral edge of the chip 12 so as not to face the IGBT region 14 in the thickness direction of the chip 12. In other words, the inner cathode region 120 is formed only in the outer circumferential region 18, but is not formed in the IGBT region 14. In this case, the electrical influence from the IGBT region 14 to the diode 112 can be suppressed, and the electrical influence from the diode 112 to the IGBT region 14 can also be suppressed.

[0171] In one example, the ratio of the planar area of ​​the inner cathode region 120 to the planar area of ​​the second main surface 12B is 0.1% to 10%. In another example, the ratio of the planar area of ​​the inner cathode region 120 to the planar area of ​​the second main surface 12B may fall within any one of the ranges of 0.1% to 1%, 1% to 2%, 2% to 4%, 4% to 6%, 6% to 8%, and 8% to 10%.

[0172] 15 to 17, a method for setting the position of the inner cathode region 120 will be described. Note that in the following description, for components in the semiconductor device 10 denoted by reference numerals, please refer to the reference numerals of the components of the semiconductor device 10 shown in FIGS.

[0173] When a forward voltage VF of the diode 112 is applied between the emitter electrode 92 and the collector electrode 108, a forward current IF flows through the diode 112. The forward current IF flows, for example, from the first well-connecting electrode 84A and the second well-connecting electrode 84B to the inner cathode region 120. The electrical characteristics of the diode 112 during forward operation vary depending on the position of the inner cathode region 120.

[0174] FIG. 15 shows the relationship between the forward current IF and the forward voltage VF depending on the position of the inner cathode region 120. The vertical axis of the graph in FIG. 15 represents the forward current IF (A). The horizontal axis of the graph in FIG. 15 represents the forward voltage VF (V). FIG. 15 shows a first characteristic S1, a second characteristic S2, and a third characteristic S3. The first characteristic S1 represents the characteristic when the inner cathode region 120 is located at the gate reference position PG. The second characteristic S2 represents the characteristic when the inner cathode region 120 is located at the first well reference position PW1. The third characteristic S3 represents the characteristic when the inner cathode region 120 is located at the second well reference position PW2.

[0175] The gate reference position PG is a position directly below the center of the gate line electrode 90. In one example, the gate reference position PG is a position directly below the center of the gate line wiring 70. The gate reference position PG can also be said to be a position facing the gate line electrode 90 in the thickness direction of the chip 12. The gate reference position PG can also be said to be a position facing the gate line wiring 70 in the thickness direction of the chip 12.

[0176] 15 , the forward current IF according to the second characteristic S2 is larger than the forward current IF according to the first characteristic S1. Furthermore, the forward current IF according to the third characteristic S3 is larger than the forward current IF according to the first characteristic S1. Thus, the inner cathode region 120 is preferably disposed so as to avoid the gate reference position PG in order to prevent a detour current path. Furthermore, the inner cathode region 120 is preferably disposed at either or both of the first well reference position PW1 and the second well reference position PW2.

[0177] 16 and 17 are graphs showing the relationship between the arrangement position of the inner cathode region 120 and the forward current IF. The horizontal axis of FIGS. 16 and 17 indicates the arrangement position of the inner cathode region 120. The vertical axis of FIGS. 16 and 17 indicates the magnitude of the forward current IF. Note that the graphs of FIGS. 16 and 17 are the same as the graph of FIG. 12. In the first embodiment, the region on the peripheral side of the chip 12 relative to the second well reference position PW2 was mainly described, but in the second embodiment, the region from the first well reference position PW1 to the second well reference position PW2 will be mainly described.

[0178] 16 and 17 , the forward current IF reaches a first maximum value v1 when the inner cathode region 120 is located at the first well reference position PW1. The forward current IF reaches a minimum value v2 when the inner cathode region 120 is located at the gate reference position PG. The forward current IF reaches a second maximum value v3 when the inner cathode region 120 is located at the second well reference position PW2.

[0179] When the inner cathode region 120 is located near the center between the first well reference position PW1 and the gate reference position PG, the forward current IF assumes a value near the intermediate value between the first maximum value v1 and the minimum value v2. The value near the intermediate value between the first maximum value v1 and the minimum value v2 is also a value near the first inflection point v4 between the first maximum value v1 and the minimum value v2.

[0180] When the inner cathode region 120 is located near the center between the gate reference position PG and the second well reference position PW2, the forward current IF assumes a value near the intermediate value between the minimum value v2 and the second maximum value v3. The value near the intermediate value between the minimum value v2 and the second maximum value v3 is also a value near the second inflection point v5 between the minimum value v2 and the second maximum value v3.

[0181] For the above reasons, it is preferable to set a prohibited range 122 on the second main surface 12B that prohibits the placement of the inner cathode region 120 near the gate reference position PG. It is also preferable to set a first allowed range 124 on the second main surface 12B that permits the placement of a part or the entire inner cathode region 120 near the first well reference position PW1. It is also preferable to set a second allowed range 126 that permits the placement of a part or the entire inner cathode region 120 near the second well reference position PW2.

[0182] Next, an explanation will be given of setting examples of the prohibited range 122, the first allowed range 124, and the second allowed range 126. Fig. 16 shows the first setting example, and Fig. 17 shows the second setting example. (First Setting Example) In the first setting example, the prohibited range 122, the first allowed range 124, and the second allowed range 126 are set separately for the distance between the first well reference position PW1 and the gate reference position PG, and the distance between the second well reference position PW2 and the gate reference position PG.

[0183] 16 , when the inner cathode region 120 is disposed in a region on the side of the first well reference position PW1, the prohibited range 122 and the first allowed range 124 may be set based on a first reference distance Da between the first well reference position PW1 and the gate reference position PG. Here, the first reference distance Da is an example of a "reference distance as the distance between the center of the gate line electrode and the well connecting electrode."

[0184] In this case, the prohibited range 122 is set within a range not exceeding half the first reference distance Da from the gate reference position PG. The prohibited range 122 is set on the IGBT region 14 side from the first well reference position PW1. In this case, the inner cathode region 120 is disposed at a distance of at least half the first reference distance Da from the gate reference position PG toward the first well reference position PW1. In other words, the inner cathode region 120 is not disposed within a range not exceeding half the first reference distance Da from the gate reference position PG toward the first well reference position PW1.

[0185] On the other hand, the first allowable range 124 is set within a range not exceeding half the first reference distance Da from the first well reference position PW1. The first allowable range 124 is set on the IGBT region 14 side and the gate reference position PG side from the first well reference position PW1. In this case, at least a portion of the inner cathode region 120 is disposed within a range not exceeding half the first reference distance Da from the first well reference position PW1. In other words, the inner cathode region 120 has a portion disposed within a range not exceeding half the first reference distance Da from the first well reference position PW1 directly below the first well connection electrode 84A.

[0186] Furthermore, when the inner cathode region 120 is disposed in a region on the side of the second well reference position PW2, the prohibited range 122 and the second allowed range 126 are set based on a second reference distance Db between the second well reference position PW2 and the gate reference position PG. Here, the second reference distance Db is an example of a "reference distance as the distance between the center of the gate line electrode and the well connecting electrode."

[0187] In this case, the prohibited range 122 is set within a range not exceeding half the second reference distance Db from the gate reference position PG. The prohibited range 122 is set toward the second well reference position PW2 from the gate reference position PG. In this case, the inner cathode region 120 is disposed at a distance of at least half the second reference distance Db from the gate reference position PG toward the second well reference position PW2. In other words, the inner cathode region 120 is not disposed within a range not exceeding half the first reference distance Da from the gate reference position PG toward the second well reference position PW2.

[0188] On the other hand, the second allowable range 126 is set within a range not exceeding half the second reference distance Db from the second well reference position PW2. The second allowable range 126 is set on the periphery of the chip 12 and toward the gate reference position PG from the second well reference position PW2. In this case, at least a portion of the inner cathode region 120 is positioned within a range not exceeding half the second reference distance Db from the second well reference position PW2. In other words, the inner cathode region 120 has a portion positioned within a range not exceeding half the first reference distance Da from the second well reference position PW2 directly below the second well connection electrode 84B.

[0189] When the inner cathode region 120 is positioned in both the region on the first well reference position PW1 side and the region on the second well reference position PW2 side, the prohibited range 122 is set to a range not exceeding 1 / 2 the first reference distance Da from the gate reference position PG toward the first well reference position PW1 side, and a range not exceeding 1 / 2 the second reference distance Db from the gate reference position PG toward the second well connection electrode 84B side.

[0190] On the other hand, the first allowable range 124 is set within a range not exceeding half the distance of the first reference distance Da with respect to the first well reference position PW1. The first allowable range 124 is set on the IGBT region 14 side and the gate reference position PG side with respect to the first well reference position PW1. On the other hand, the second allowable range 126 is set within a range not exceeding half the distance of the second reference distance Db with respect to the second well reference position PW2. The second allowable range 126 is set on the periphery side of the chip 12 and the gate reference position PG side with respect to the second well reference position PW2.

[0191] The first reference distance Da may be 1 μm or more and 50 μm or less. The first reference distance Da may be set to a value belonging to any of the following ranges: 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, and 45 μm or more and 50 μm or less. The first reference distance Da is preferably 10 μm or more and 30 μm or less. Furthermore, the first reference distance Da is preferably 10 μm or more and 20 μm or less.

[0192] The second reference distance Db may be less than the first reference distance Da or may be greater than or equal to the first reference distance Da. In one example, the second reference distance Db is greater than the first reference distance Da. The second reference distance Db may be greater than or equal to 1 μm and less than or equal to 100 μm. The second reference distance Db may be set to a value within any of the following ranges: greater than or equal to 1 μm and less than or equal to 5 μm, greater than or equal to 10 μm, greater than or equal to 10 μm, greater than or equal to 20 μm, greater than or equal to 20 μm and less than or equal to 30 μm, greater than or equal to 30 μm and less than or equal to 40 μm, greater than or equal to 40 μm and less than or equal to 50 μm, greater than or equal to 50 μm and less than or equal to 60 μm, greater than or equal to 60 μm and less than or equal to 70 μm, greater than or equal to 70 μm and less than or equal to 80 μm, greater than or equal to 80 μm and less than or equal to 90 μm, and greater than or equal to 90 μm and less than or equal to 100 μm. The second reference distance Db is preferably greater than or equal to 10 μm and less than or equal to 60 μm. The second reference distance Db is preferably 20 μm or more and 40 μm or less.

[0193] 17 , when the inner cathode region 120 is located at an intermediate reference position PW3 immediately below the midpoint between the first well reference position PW1 and the second well reference position PW2, the forward current IF becomes a value close to the minimum value v2.

[0194] The forward current IF becomes a value near the intermediate value between the first maximum value v1 and the minimum value v2 (a value near the first inflection point v4) when the inner cathode region 120 is located near the point immediately below the midpoint between the first well reference position PW1 and the intermediate reference position PW3. The forward current IF becomes a value near the intermediate value between the second maximum value v3 and the minimum value v2 (a value near the second inflection point v5) when the inner cathode region 120 is located near the point immediately below the midpoint between the second well reference position PW2 and the intermediate reference position PW3.

[0195] For the above reasons, the prohibited range 122, the first allowed range 124, and the second allowed range 126 may be set based on the third reference distance Dc between the first well reference position PW1 and the second well reference position PW2. The third reference distance Dc is also the sum of the first reference distance Da and the second reference distance Db (Dc = Da + Db) shown in FIG. 16 . That is, in the second setting example, the prohibited range 122, the first allowed range 124, and the second allowed range 126 are set based on the third reference distance Dc without using the first reference distance Da and the second reference distance Db. Here, the third reference distance Dc is an example of a "reference distance as the distance between the first well connecting electrode and the second well connecting electrode."

[0196] In this case, the prohibited range 122 may be set to a range not exceeding ¼ of the third reference distance Dc from an intermediate reference position PW3 immediately below the midpoint between the first well reference position PW1 and the second well reference position PW2. When the inner cathode region 120 is positioned in a region on the first well reference position PW1 side, the prohibited range 122 is set on the first well reference position PW1 side using the intermediate reference position PW3 as a reference. When the inner cathode region 120 is positioned in a region on the second well reference position PW2 side, the prohibited range 122 is set on the second well reference position PW2 side using the intermediate reference position PW3 as a reference.

[0197] On the other hand, the first allowable range 124 is set within a range not exceeding ¼ of the third reference distance Dc with respect to the first well reference position PW1. The first allowable range 124 is set toward the IGBT region 14 and the gate reference position PG with respect to the first well reference position PW1. On the other hand, the second allowable range 126 is set within a range not exceeding ¼ of the third reference distance Dc with respect to the second well reference position PW2. The second allowable range 126 is set toward the IGBT region 14 and the gate reference position PG with respect to the second well reference position PW2.

[0198] 17, the inner cathode region 120 is disposed at a distance from the intermediate reference position PW3. The inner cathode region 120 is preferably disposed in a region outside the prohibited range 122. In other words, the inner cathode region 120 is preferably not disposed within a range that does not exceed ¼ of the third reference distance Dc from the intermediate reference position PW3.

[0199] The inner cathode region 120 may be located in a region closer to the first well reference position PW1 than the intermediate reference position PW3. In this case, it is preferable that a portion or the entire inner cathode region 120 be located within the first allowable range 124. In other words, it is preferable that the inner cathode region 120 is not located within a range from the intermediate reference position PW3 toward the first well connection electrode 84A that does not exceed ¼ of the third reference distance Dc. Furthermore, it is preferable that the inner cathode region 120 has a portion located within a range from the first well reference position PW1 toward the intermediate reference position PW3 that does not exceed ¼ of the third reference distance Dc. In this case, it is preferable that the inner cathode region 120 be located at the first well reference position PW1. In other words, it is preferable that the inner cathode region 120 faces the first well connection electrode 84A in the thickness direction of the chip 12.

[0200] The inner cathode region 120 may also be located in a region closer to the second well reference position PW2 than the intermediate reference position PW3. In this case, it is preferable that a portion or the entire inner cathode region 120 be located within the second allowable range 126. That is, it is preferable that the inner cathode region 120 is not located within a range from the intermediate reference position PW3 toward the second well connection electrode 84B that does not exceed ¼ of the third reference distance Dc. It is also preferable that the inner cathode region 120 has a portion located within a range from the second well reference position PW2 toward the intermediate reference position PW3 that does not exceed ¼ of the third reference distance Dc. In this case, it is preferable that the inner cathode region 120 be located at the second well reference position PW2. That is, it is preferable that the inner cathode region 120 faces the second well connection electrode 84B in the thickness direction of the chip 12.

[0201] (Peak Surge Current IFSM) The relationship between the position of the inner cathode region 120 and the peak surge current IFSM will be described with reference to Fig. 18. Fig. 18 is a graph showing the relationship between the peak surge current IFSM and the forward voltage VF when the position of the inner cathode region 120 is adjusted. The vertical axis of Fig. 18 represents the peak surge current IFSM (A), and the horizontal axis of Fig. 18 represents the forward voltage VF (V). The peak surge current IFSM is the peak value of a commercial sinusoidal half-wave current (50 Hz or 60 Hz) of one cycle or more that is permissible without causing breakdown.

[0202] 18 shows first to sixth plot points P1 to P6. The first to third plot points P1 to P3 show the characteristics when the inner cathode region 120 is arranged at a distance from the well region 54 towards the periphery of the chip 12. The arrangement positions of the inner cathode regions 120 approach the well region 54 in the order of the first plot point P1, the second plot point P2, and the third plot point P3.

[0203] The fourth to sixth plot points P4 to P6 show the characteristics when the inner cathode region 120 is arranged in a position facing the well region 54. The arrangement positions of the inner cathode region 120 approach the second well reference position PW2 from the outer edge 54B side of the well region 54 in the order of the fourth plot point P4, the fifth plot point P5, and the sixth plot point P6. The sixth plot point P6 shows the characteristics when the inner cathode region 120 is arranged at the second well reference position PW2. At the first to sixth plot points P1 to P6, the width of the inner cathode region 120 is fixed to a constant value (here, 10 μm).

[0204] With reference to the first to sixth plot points P1 to P6, the peak surge currents IFSM associated with the fourth to sixth plot points P4 to P6 are greater than the peak surge currents IFSM associated with the first to third plot points P1 to P3. The peak surge current IFSM associated with the sixth plot point P6 is also greater than the peak surge currents IFSM associated with the first to fifth plot points P1 to P5. Therefore, from the viewpoint of the peak surge currents IFSM, it is preferable that the inner cathode region 120 be disposed in a region immediately below the well region 54. In particular, it is preferable that the inner cathode region 120 be disposed at the second well reference position PW2.

[0205] (Layout of the Inner Cathode Region) Next, first to third layout examples will be described as layout examples of the inner cathode region 120.

[0206] 14, the semiconductor device 10 may include, as the inner cathode region 120, an inner cathode region 120 according to a first layout example formed in consideration of the results of the above-described FIGS. 15 to 18. The inner cathode region 120 is arranged along the second main surface 12B at a distance from the gate reference position PG. Specifically, the inner cathode region 120 is arranged along the second main surface 12B at a distance from the gate reference position PG toward the second well reference position PW2.

[0207] The inner cathode region 120 is located in the second allowed range 126, but is not located in the prohibited range 122. Here, the prohibited range 122 and the second allowed range 126 according to the first or second setting example may be applied. The inner cathode region 120 is located at the second well reference position PW2. The inner cathode region 120 faces a plurality of second well connection electrodes 84B in the thickness direction of the chip 12. The inner cathode region 120 is located at a distance from the gate line electrode 90 toward the second well reference position PW2 so as not to face the gate line electrode 90 in the thickness direction of the chip 12.

[0208] The inner cathode region 120 is arranged at a distance from a position directly below the center of the gate line wiring 70 toward the second well reference position PW2. The inner cathode region 120 is arranged at a distance from a position directly below the plurality of gate connection electrodes 80 toward the second well reference position PW2 so as not to face the plurality of gate connection electrodes 80 in the thickness direction of the chip 12. The inner cathode region 120 is arranged at a distance from the gate line wiring 70 toward the second well reference position PW2 so as not to face the gate line wiring 70 in the thickness direction of the chip 12.

[0209] The inner cathode region 120 has a width that is less than the width of the emitter line electrode 96. The inner cathode region 120 may have a width that is equal to or greater than the width of the emitter line electrode 96. The inner cathode region 120 is arranged at a distance from a position directly below the outer edge 54B of the well region 54 toward the second well reference position PW2. The inner cathode region 120 is arranged only in a region that faces the well region 54 in the thickness direction of the chip 12 in the surface layer portion of the second main surface 12B.

[0210] 19 shows the cross-sectional structure of the peripheral portion of the chip 12 together with the inner cathode region 120 according to the second layout example. As shown in FIG. 19, the semiconductor device 10 may include the inner cathode region 120 according to the second layout example as the inner cathode region 120. The inner cathode region 120 is disposed at a distance from the gate reference position PG along the second main surface 12B. Specifically, the inner cathode region 120 is disposed at a distance from the gate reference position PG toward the first well reference position PW1 (toward the IGBT region 14) along the second main surface 12B.

[0211] The inner cathode region 120 is located in the first allowed range 124, but is not located in the prohibited range 122. Here, the prohibited range 122 and the first allowed range 124 according to the first setting example or the second setting example may be applied. The inner cathode region 120 is located at the first well reference position PW1. The inner cathode region 120 faces a plurality of first well connection electrodes 84A in the thickness direction of the chip 12. The inner cathode region 120 is located at a distance from the gate line electrode 90 toward the first well reference position PW1 so as not to face the gate line electrode 90 in the thickness direction of the chip 12.

[0212] The inner cathode region 120 is arranged at a distance from a position directly below the center of the gate line wiring 70 toward the first well reference position PW1. The inner cathode region 120 is arranged at a distance from a position directly below the plurality of gate connection electrodes 80 toward the first well reference position PW1 so as not to face the plurality of gate connection electrodes 80 in the thickness direction of the chip 12. The inner cathode region 120 is arranged at a distance from the gate line wiring 70 toward the first well reference position PW1 so as not to face the gate line wiring 70 in the thickness direction of the chip 12.

[0213] The inner cathode region 120 is preferably disposed at a distance from a position directly below the inner edge 54A of the well region 54 toward the first well reference position PW1, regardless of the first allowable range 124. In other words, the inner cathode region 120 is disposed only in a region facing the well region 54 in the thickness direction of the chip 12 in the surface layer portion of the second main surface 12B.

[0214] Furthermore, the inner cathode region 120 is preferably arranged at a distance from the plurality of trench gate structures 38 on the peripheral edge side of the chip 12 so as not to face the plurality of trench gate structures 38 in the thickness direction of the chip 12. The inner cathode region 120 is preferably arranged at a distance from the trench isolation structure 26 on the peripheral edge side of the chip 12 so as not to face the trench isolation structure 26 in the thickness direction of the chip 12.

[0215] That is, it is preferable that the inner cathode region 120 is disposed at a distance from the IGBT region 14 toward the peripheral edge of the chip 12 so as not to face the IGBT region 14 in the thickness direction of the chip 12. That is, it is preferable that the inner cathode region 120 is disposed only in the outer periphery region 18, and not in the IGBT region 14. In this case, it is possible to suppress the electrical influence from the IGBT region 14 to the diode 112, and also to suppress the electrical influence from the diode 112 to the IGBT region 14.

[0216] 20 shows the cross-sectional structure of the peripheral portion of the chip 12 together with the inner cathode region 120 according to the third layout example. As shown in Fig. 20, the semiconductor device 10 may include the inner cathode region 120 according to the third layout example as the inner cathode region 120. The inner cathode region 120 includes a first inner cathode region 120A arranged on the side of the first well reference position PW1 and a second inner cathode region 120B arranged on the side of the second well reference position PW2.

[0217] The first inner cathode region 120A is formed in a layout similar to that of the inner cathode region 120 according to the second layout example shown in FIG. 19 . In one example, the first inner cathode region 120A is arranged at a distance from the intermediate reference position PW3 toward the first well connection electrode 84A. The second inner cathode region 120B is formed in a layout similar to that of the inner cathode region 120 according to the first layout example shown in FIG. 18 . In one example, the second inner cathode region 120B is arranged at a distance from the intermediate reference position PW3 toward the second well connection electrode 84B. The second inner cathode region 120B faces the first inner cathode region 120A in the surface layer portion of the second main surface 12B, with a portion of the collector region 24 sandwiched therebetween.

[0218] In the first to third layout examples, a portion of the collector region 24 faces the gate line wiring 70, the gate connection electrode 80, and the gate line electrode 90 in the thickness direction of the chip 12. It is preferable that a portion of the collector region 24 faces the entire gate line electrode 90 in the thickness direction of the chip 12. It is preferable that a portion of the collector region 24 faces the entire gate line wiring 70 in the thickness direction of the chip 12.

[0219] [Effects of Second Embodiment] According to the semiconductor device 10 of the second embodiment, the following effects can be obtained in addition to the effects of the first embodiment.

[0220] (2-1) The semiconductor device 10 includes a well region 54 and an inner cathode region 120 of the second conductivity type (n-type) that constitutes a diode 112. The inner cathode region 120 is provided at a distance from the gate reference position PG directly below the center of the gate line electrode 90 toward the well connection electrode 84 so as to face the well region 54 in the surface layer portion of the second main surface 12B of the chip 12.

[0221] This configuration can prevent the formation of a current detour path that goes around to the region immediately below the gate line electrode 90 in the region between the well-connecting electrode 84 and the inner cathode region 120. This allows the inner cathode region 120 to increase the forward current IF of the diode 112.

[0222] In addition, because the inner cathode region 120 can increase the forward current I of the diode 112, the position of the cathode region 110 can be set without having to consider the forward current I of the diode 112. In other words, the degree of freedom in designing the spacing between the multiple field regions 56 is improved. For example, because the spacing between the multiple field regions 56 can be reduced, the semiconductor device 10 can be made smaller.

[0223] (2-2) The inner cathode region 120 is formed in the surface layer portion of the second main surface 12B in the outer circumferential region 18 so as to face the well connection electrode 84 in the thickness direction of the chip 12. The inner cathode region 120 forms a diode 112 together with the well region 54.

[0224] This configuration allows the formation of a current path that linearly connects the well connection electrode 84 and the inner cathode region 120. This increases the forward current IF of the diode 112 during forward operation, thereby improving the electrical characteristics of the semiconductor device 10.

[0225] (2-3) The inner cathode region 120 does not face the gate line electrode 90 in the thickness direction of the chip 12. This configuration appropriately prevents the formation of a detour current path that goes around to the region directly below the gate line electrode 90.

[0226] (2-4) The well connection electrode 84 may include at least one of a first well connection electrode 84A arranged on the inner edge 54A side of the well region 54 and a second well connection electrode 84B arranged on the outer edge 54B side of the well region 54.

[0227] According to this configuration, when the well connection electrode 84 includes the first well connection electrode 84A, the gate line electrode 90 is disposed at a distance from the first well connection electrode 84A toward the outer edge 54B of the well region 54 (toward the periphery of the chip 12). In this case, the inner cathode region 120 is disposed at a distance from a position directly below the center of the gate line electrode 90 along the second main surface 12B toward the inner edge 54A of the well region 54 (toward the IGBT region 14). This allows the formation of a current path that linearly connects the first well connection electrode 84A and the inner cathode region 120.

[0228] In this case, the semiconductor device 10 preferably includes an emitter pad electrode 94. The emitter pad electrode 94 is disposed on the insulating film 60 at a distance from the gate line electrode 90 toward the IGBT region 14 so as to be electrically connected to the well region 54 via the first well connection electrode 84A. The inner cathode region 120 faces the emitter pad electrode 94 in the thickness direction of the chip 12. This allows the formation of a current path that linearly connects the emitter pad electrode 94 and the inner cathode region 120.

[0229] Furthermore, when the well connection electrode 84 includes the second well connection electrode 84B, the gate line electrode 90 may be disposed at a distance from the second well connection electrode 84B to the inner edge 54A (toward the IGBT region 14) of the well region 54. In this case, the inner cathode region 120 is disposed at a distance from a position directly below the center of the gate line electrode 90 along the second main surface 12B to the outer edge 54B side of the well region 54 (toward the peripheral edge of the chip 12). This allows the formation of a current path that linearly connects the second well connection electrode 84B and the inner cathode region 120.

[0230] In this case, the semiconductor device 10 preferably includes an emitter line electrode 96. The emitter line electrode 96 is disposed on the insulating film 60 at a distance from the gate line electrode 90 toward the periphery of the chip 12 so as to be electrically connected to the well region 54 via the second well-connecting electrode 84B. The inner cathode region 120 faces the emitter line electrode 96 in the thickness direction of the chip 12. This allows the formation of a current path that linearly connects the emitter line electrode 96 and the inner cathode region 120.

[0231] (2-5) The semiconductor device 10 includes a gate line wiring 70 and a gate connection electrode 80. The gate line wiring 70 is disposed inside the insulating film 60 so as to face the well region 54 in the thickness direction of the chip 12. The gate connection electrode 80 is embedded in the insulating film 60 so as to be connected to the gate line wiring 70. In this case, the gate line electrode 90 is electrically connected to the gate line wiring 70 via the gate connection electrode 80. The inner cathode region 120 is disposed along the second main surface 12B at a distance from a position directly below the center of the gate line wiring 70. This configuration can prevent a current detouring path from being formed in the region directly below the gate line wiring 70.

[0232] (2-6) The inner cathode region 120 does not face the gate connection electrode 80 in the thickness direction of the chip 12. The inner cathode region 120 does not face the gate line wiring 70 in the thickness direction of the chip 12. This configuration makes it possible to appropriately prevent the formation of a current detouring path that goes around to the region directly below the gate line wiring 70.

[0233] (2-7) The inner cathode region 120 is disposed only in the region facing the well region 54 in the surface layer portion of the second main surface 12B. With this configuration, the current path of the forward current IF of the diode 112 can be limited to the region between the well region 54 and the inner cathode region 120. Therefore, a decrease in the forward current IF can be appropriately suppressed. In addition, the peak surge current IFSM can be improved.

[0234] (2-8) The inner cathode region 120 is disposed along the second main surface 12B at a distance from the gate reference position PG directly below the center of the gate line electrode 90 toward the well connecting electrode 84 side.

[0235] This configuration can prevent the formation of a current detouring path that goes around to the region directly below the gate line electrode 90 in the region between the well connecting electrode 84 and the inner cathode region 120, and can shorten the current path between the well connecting electrode 84 and the inner cathode region 120. This can increase the forward current IF of the diode 112 during forward operation. This can improve the electrical characteristics of the semiconductor device 10.

[0236] (2-9) When the distance between the center of the gate line electrode 90 and the first well connection electrode 84A is defined as the first reference distance Da, the inner cathode region 120 is not disposed within a range that does not exceed half the distance from the gate reference position PG of the first reference distance Da. In other words, the inner cathode region 120 is disposed in a region outside the prohibited range 122. This structure can prevent the formation of a current detour path that goes around to the region directly below the gate line electrode 90. This can increase the forward current IF.

[0237] (2-10) When the distance between the center of the gate line electrode 90 and the well connecting electrode 84 is defined as a first reference distance Da, the inner cathode region 120 has a portion that is located within a range not exceeding half the distance of the first reference distance Da from the first well reference position PW1 directly below the first well connecting electrode 84A. In other words, when part or all of the inner cathode region 120 is located in a region on the first well reference position PW1 side, it is located within the first allowable range 124. With this configuration, the current path between the first well connecting electrode 84A and the inner cathode region 120 is shortened, thereby making it possible to appropriately increase the forward current IF.

[0238] (2-11) The inner cathode region 120 is disposed at the first well reference position PW1. With this configuration, a current path is formed that linearly connects the first well connection electrode 84A and the inner cathode region 120, thereby making it possible to appropriately increase the forward current IF.

[0239] (2-12) When the distance between the center of the gate line electrode 90 and the second well connection electrode 84B is defined as the second reference distance Db, the inner cathode region 120 is not disposed within a range that does not exceed half the distance from the gate reference position PG of the second reference distance Db. In other words, the inner cathode region 120 is disposed in a region outside the prohibited range 122. This configuration can prevent the formation of a current detour path that goes around to the region directly below the gate line electrode 90. This can increase the forward current IF.

[0240] (2-13) When the distance between the center of the gate line electrode 90 and the second well connecting electrode 84B is defined as a second reference distance Db, the inner cathode region 120 has a portion that is disposed within a range not exceeding half the range of the second reference distance Db from the second well reference position PW2 directly below the second well connecting electrode 84B. In other words, when a part or the entire inner cathode region 120 is disposed in a region on the second well reference position PW2 side, it is disposed within the second allowable range 126. With this configuration, the current path between the second well connecting electrode 84B and the inner cathode region 120 is shortened, thereby making it possible to appropriately increase the forward current IF.

[0241] (2-14) The inner cathode region 120 is disposed at the second well reference position PW2. With this configuration, a current path is formed that linearly connects the second well connection electrode 84B and the inner cathode region 120, thereby making it possible to appropriately increase the forward current IF.

[0242] (2-15) The inner cathode region 120 is disposed along the second main surface 12B at a distance from an intermediate reference position PW3 immediately below the middle between the first well connecting electrode 84A and the second well connecting electrode 84B.

[0243] This configuration can prevent the formation of a detour current path that goes around to the region immediately below the middle between the first well-connecting electrode 84A and the second well-connecting electrode 84B. This can increase the forward current IF of the diode 112 during forward operation. This can improve the electrical characteristics of the semiconductor device 10.

[0244] (2-16) When the distance between the first well connection electrode 84A and the second well connection electrode 84B is defined as the third reference distance Dc, the inner cathode region 120 is not disposed within a range that does not exceed ¼ of the distance from the intermediate reference position PW3. In other words, the inner cathode region 120 is disposed outside the prohibited range 122. This configuration makes it possible to appropriately prevent the formation of a current detour path that goes around to the region immediately below the intermediate position between the first well connection electrode 84A and the second well connection electrode 84B.

[0245] (2-17) The inner cathode region 120 is disposed at a distance from the intermediate reference position PW3 toward the first well connecting electrode 84A. This configuration shortens the current path between the first well connecting electrode 84A and the inner cathode region 120, thereby increasing the forward current IF.

[0246] (2-18) When the distance between the first well connecting electrode 84A and the second well connecting electrode 84B is defined as the third reference distance Dc, the inner cathode region 120 has a portion that is located within a range not exceeding ¼ of the third reference distance Dc from the first well reference position PW1 directly below the first well connecting electrode 84A. In other words, when part or all of the inner cathode region 120 is located in a region on the first well reference position PW1 side, it is located within the first allowable range 124. With this configuration, the current path between the first well connecting electrode 84A and the inner cathode region 120 can be shortened, thereby appropriately increasing the forward current IF.

[0247] (2-19) The inner cathode region 120 has a portion overlapping with the first well reference position PW1. With this configuration, a current path that linearly connects the first well connection electrode 84A and the inner cathode region 120 can be formed, thereby appropriately increasing the forward current IF.

[0248] (2-20) The inner cathode region 120 is disposed at a distance from the intermediate reference position PW3 toward the second well connecting electrode 84B. This configuration shortens the current path between the second well connecting electrode 84B and the inner cathode region 120, thereby increasing the forward current IF.

[0249] (2-21) When the distance between the first well connecting electrode 84A and the second well connecting electrode 84B is defined as the third reference distance Dc, the inner cathode region 120 has a portion that is located within a range not exceeding one-quarter of the third reference distance Dc from the second well reference position PW2 directly below the second well connecting electrode 84B. In other words, when part or all of the inner cathode region 120 is located in a region on the second well reference position PW2 side, it is located within the second allowable range 126. With this configuration, the current path between the second well connecting electrode 84B and the inner cathode region 120 can be shortened, thereby appropriately increasing the forward current IF.

[0250] (2-22) The inner cathode region 120 has a portion overlapping with the second well reference position PW2. With this configuration, a current path that linearly connects the second well connection electrode 84B and the inner cathode region 120 can be formed, thereby appropriately increasing the forward current IF.

[0251] (2-23) The second conductivity type impurity concentration (p-type impurity concentration) of the inner cathode region 120 is equal to the second conductivity type impurity concentration (p-type impurity concentration) of the cathode region 110. According to this configuration, the inner cathode region 120 and the cathode region 110 can be formed in a common process. Therefore, the manufacturing process can be simplified compared to when the inner cathode region 120 and the cathode region 110 are formed in separate processes.

[0252] <Modifications> The above-described embodiments can be modified as follows: The following modifications can be combined with each other to the extent that they are not technically inconsistent.

[0253] In each embodiment, the width W1 of the cathode region 110 may be greater than the width WF of one field region 56. In one example, the width W1 of the cathode region 110 may be greater than the width WF of one field region 56, but less than twice the width WF of one field region 56. In one example, the width W1 of the cathode region 110 may be more than twice the width WF of one field region 56.

[0254] In each embodiment, the relationship between the impurity concentrations of the cathode region 110 and the collector region 24 can be changed as desired. In one example, the n-type impurity concentration of the cathode region 110 may be equal to the p-type impurity concentration of the collector region 24. In another example, the n-type impurity concentration of the cathode region 110 may be lower than the p-type impurity concentration of the collector region 24.

[0255] In each embodiment, the shape of the cathode region 110 in a plan view can be changed as desired. For example, the shape of the cathode region 110 in a plan view may be a ring with a portion open. For example, the shape of the cathode region 110 in a plan view may be a straight line extending along the X direction or a straight line extending along the Y direction.

[0256] In each embodiment, the position of the cathode region 110 can be arbitrarily changed in the peripheral region 18 closer to the periphery of the chip 12 than the well region 54. In one example, the cathode region 110 may be disposed in a position facing the outermost field region 56D of the multiple field regions 56 in the thickness direction of the chip 12. In another example, the cathode region 110 may be disposed in a position facing the channel stop region 58 in the thickness direction of the chip 12.

[0257] In each embodiment, the cathode region 110 is disposed so as to face one field region 56 in the thickness direction of the chip 12, but this is not limited to this. In one example, the cathode region 110 may extend so as to face a plurality of field regions 56 in the thickness direction of the chip 12. FIG. 21 shows a first example of this configuration. FIG. 21 schematically shows the cross-sectional structure at the periphery of the chip 12. The cross-sectional position in FIG. 21 is the same as the cross-sectional position in FIG. 8.

[0258] As shown in FIG. 21 , the cathode region 110 extends in the thickness direction of the chip 12 so as to face the inner field regions 56A and 56B among the multiple field regions 56. In this case, the width W1 of the cathode region 110 is more than twice the width WF of one field region 56. In the example shown in FIG. 21 , the cathode region 110 is located closer to the well region 54 than the inner field region 56C. In the example shown in FIG. 21 , the electric field strength of both the inner field regions 56A and 56B is higher than that of the inner field region 56C and the outermost field region 56D. Furthermore, because the cathode region 110 is located in a position facing the inner field regions 56A and 56B in the thickness direction of the chip 12, electric field concentration in the inner field regions 56A and 56B can be alleviated.

[0259] Furthermore, although not shown, if the electric field strength of both inner field regions 56B and 56C is higher than that of inner field region 56A and outermost field region 56D, cathode region 110 may be positioned opposite inner field regions 56B and 56C in the thickness direction of chip 12. This can mitigate electric field concentration in inner field regions 56B and 56C.

[0260] Although not shown, the cathode region 110 may extend, for example, so as to face all of the inner field regions 56A to 56C in the thickness direction of the chip 12. This makes it possible to alleviate electric field concentration in the inner field regions 56A to 56C.

[0261] Fig. 22 shows a configuration in which an inner cathode region 120 is added to the example shown in Fig. 21. Fig. 22 schematically shows the cross-sectional structure at the peripheral edge of the chip 12. The cross-sectional position in Fig. 22 is the same as the cross-sectional position in Fig. 21.

[0262] 22 , the inner cathode region 120 is disposed at a position facing the second well connecting electrode 84B in the thickness direction of the chip 12. The inner cathode region 120 can also be said to be disposed at the second well reference position PW2. The inner cathode region 120 may also be disposed at a position facing the first well connecting electrode 84A in the thickness direction of the chip 12. In other words, the inner cathode region 120 may be disposed at the first well reference position PW1. The position of the inner cathode region 120 may be the same as in the second embodiment.

[0263] 23 shows a second example in which the width W1 of the cathode region 110 is changed. Fig. 23 schematically shows the cross-sectional structure at the peripheral edge of the chip 12. The cross-sectional position in Fig. 23 is the same as that in Fig. 13.

[0264] 23 , the inner cathode region 120 extends across the entire area of ​​the plurality of field regions 56 in the thickness direction of the chip 12. The inner cathode region 120 is arranged at a distance closer to the plurality of field regions 56 than the channel stop region 58 so as not to face the channel stop region 58 in the thickness direction of the chip 12.

[0265] In the second embodiment, the width W2 of the inner cathode region 120 can be changed as desired. Fig. 24 shows a modified example in which the width W2 of the inner cathode region 120 is changed. Fig. 24 schematically shows the cross-sectional structure of the peripheral portion of the chip 12. The cross-sectional position in Fig. 24 is the same as the cross-sectional position in Fig. 13.

[0266] As shown in FIG. 24 , the inner cathode region 120 includes an opposing portion 132 that faces the well region 54 in the thickness direction of the chip 12 , and a cathode extraction portion 134 that is extracted from the opposing portion 132 to the peripheral edge side of the chip 12 .

[0267] The facing portion 132 is arranged along the second main surface 12B at a distance from the gate reference position PG toward the second well reference position PW2. The facing portion 132 is arranged in the second allowed range 126. On the other hand, the facing portion 132 is not arranged in the prohibited range 122. Here, the prohibited range 122 and the second allowed range 126 according to the first setting example or the second setting example of the second embodiment may be applied.

[0268] The facing portion 132 is disposed at the second well reference position PW2. The facing portion 132 faces the plurality of second well connection electrodes 84B in the thickness direction of the chip 12. The facing portion 132 is disposed at a distance from the gate line electrode 90 toward the second well reference position PW2 so as not to face the gate line electrode 90 in the thickness direction of the chip 12.

[0269] The facing portion 132 is arranged at a distance from a position directly below the center of the gate line wiring 70 toward the second well reference position PW2. The facing portion 132 is arranged at a distance from a position directly below the center of the plurality of gate connection electrodes 80 toward the second well reference position PW2 so as not to face the plurality of gate connection electrodes 80 in the thickness direction of the chip 12. The facing portion 132 is arranged at a distance from the gate line wiring 70 toward the second well reference position PW2 so as not to face the gate line wiring 70 in the thickness direction of the chip 12.

[0270] The cathode lead-out portion 134 extends from the opposing portion 132 across a position directly below the outer edge 54B of the well region 54 toward the peripheral edge of the chip 12. Meanwhile, the cathode lead-out portion 134 is spaced apart from a position directly below the center of the inner field region 56A toward the well region 54 so as not to face multiple field regions 56 in the thickness direction of the chip 12. In one example, the width W2 of the inner cathode region 120 may be equal to or greater than the width of the emitter line electrode 96. In another example, the width W2 of the inner cathode region 120 may be less than the width of the emitter line electrode 96. In the example shown in FIG. 24 , the width W2 of the inner cathode region 120 is greater than the width W1 of the cathode region 110.

[0271] In the modification of Fig. 24, the position of the cathode lead portion 134 can be changed as desired. Fig. 25 shows a modification of the cathode lead portion 134. Fig. 25 schematically shows the cross-sectional structure of the peripheral portion of the chip 12. The cross-sectional position in Fig. 25 is the same as the cross-sectional position in Fig. 13.

[0272] 25 , the cathode lead-out portion 134 may extend in the thickness direction of the chip 12 so as to face multiple field regions 56. In the example shown in FIG. 25 , the cathode lead-out portion 134 extends in the thickness direction of the chip 12 so as to face the inner field region 56A. The cathode region 110 is disposed at a distance from the cathode lead-out portion 134 toward the periphery of the chip 12. In the example shown in FIG. 25 , the cathode region 110 is disposed in a position facing the inner field region 56B in the thickness direction of the chip 12.

[0273] In each embodiment, the widths of the field regions 56 may be different from each other. Fig. 26 shows a modified example in which the widths of a plurality of field regions 56 are changed. Fig. 26 schematically shows the cross-sectional structure at the periphery of the chip 12. The cross-sectional position in Fig. 26 is the same as the cross-sectional position in Fig. 8.

[0274] As shown in FIG. 26 , in one example, the widths WA to WC of the inner field regions 56A to 56C are smaller than the width WD of the outermost field region 56D. With this configuration, the narrower inner field regions 56A to 56C are more likely to have a higher electric field strength than the outermost field region 56D. Therefore, by locating the cathode region 110 directly below one of the inner field regions 56A to 56C, the electric field concentration in the inner field regions 56A to 56C can be alleviated. It is particularly preferable to locate the cathode region 110 directly below the field region with the highest electric field strength among the inner field regions 56A to 56C. This alleviates the electric field concentration in the field region among the inner field regions 56A to 56C that is most susceptible to BV breakdown, thereby improving the breakdown voltage of the semiconductor device 10.

[0275] In one example, the widths WA and WB of the inner field regions 56A, 56B closest to the well region 54 among the inner field regions 56A-56C may be smaller than the width WC of the inner field region 56C. With this configuration, the narrower inner field regions 56A, 56B are more likely to have a higher electric field strength than the inner field region 56C. Therefore, by locating the cathode region 110 directly below one of the inner field regions 56A, 56B, electric field concentration in the inner field regions 56A, 56B can be alleviated. Furthermore, for example, if the peak values ​​of the electric field strengths of the inner field regions 56A, 56B are approximately equal, the widths of the inner field regions 56A, 56B may be made different to make the peak values ​​different. For example, by making the width WB of the inner field region 56B smaller than the width WA of the inner field region 56A, the peak value of the electric field strength of the inner field region 56B will be greater than the peak value of the inner field region 56A. Furthermore, by disposing the cathode region 110 directly below the inner field region 56B, it is possible to alleviate the electric field concentration in the inner field region 56B, where the electric field intensity is likely to be high.

[0276] In this way, by adjusting the spacing between the multiple field regions 56 and then further adjusting the widths WA to WD of the field regions 56, it is possible to create differences in the peak values ​​of the electric field strength among the multiple field regions 56. In other words, it becomes easier to set a specific field region where the electric field strength is at its maximum. Then, by locating the cathode region 110 at a position opposite the specific field region in the thickness direction of the chip 12, it is possible to effectively alleviate the electric field concentration in the specific field region.

[0277] In each embodiment, the widths of the multiple field electrodes 102 can be individually and arbitrarily changed. In one example, the width of the outermost field electrode 102D of the multiple field electrodes 102 may be equal to the widths of the inner field electrodes 102A-102C. In one example, the width of at least one of the inner field electrodes 102A-102C may be different from the widths of the other inner field electrodes. In one example, the widths of the inner field electrodes 102A-102C may be determined according to the widths of the inner field regions 56A-56C. In one example, when the width WC of the inner field region 56C is greater than the widths WA and WB of the inner field regions 56A and 56B, the width of the inner field electrode 102C is greater than the widths of the inner field electrodes 102A and 102B.

[0278] In each embodiment, the multiple emitter connecting electrodes 76 may be integrated with the emitter pad electrode 94 (emitter electrode 92). In other words, the emitter pad electrode 94 may be disposed on the insulating film 60 so as to extend into the multiple emitter openings 74. In this case, multiple portions of the emitter pad electrode 94 located within the multiple emitter openings 74 are formed as the multiple emitter connecting electrodes 76.

[0279] In each embodiment, the multiple gate connection electrodes 80 may be integrated with the gate electrode 86 (gate line electrode 90). That is, the gate electrode 86 may be disposed on the insulating film 60 so as to extend into the multiple gate openings 78. In this case, multiple portions of the gate electrode 86 located within the multiple gate openings 78 are formed as the multiple gate connection electrodes 80.

[0280] In each embodiment, the multiple first well connection electrodes 84A may be integrated with the emitter pad electrode 94 (emitter electrode 92). That is, the emitter pad electrode 94 may be disposed on the insulating film 60 so as to extend into the multiple first well openings 82A. In this case, multiple portions of the emitter pad electrode 94 located within the multiple first well openings 82A are formed as the multiple first well connection electrodes 84A.

[0281] In each embodiment, the multiple second well connection electrodes 84B may be integrated with the emitter pad electrode 94 (emitter electrode 92). That is, the emitter pad electrode 94 may be disposed on the insulating film 60 so as to extend into the multiple second well openings 82B. In this case, multiple portions of the emitter pad electrode 94 located within the multiple second well openings 82B are formed as the multiple second well connection electrodes 84B.

[0282] In each embodiment, the multiple field connection electrodes 100 may be integrated with the field electrode 102. In other words, the field electrode 102 may be disposed on the insulating film 60 so as to extend into the multiple field openings 98. In this case, the multiple portions of the field electrode 102 located within the multiple field openings 98 are formed as the multiple field connection electrodes 100.

[0283] In each embodiment, the emitter line electrode 96 may be disposed only in the region facing the well region 54 in the thickness direction of the chip 12. In each embodiment, the width of the gate line electrode 90 may be equal to or smaller than the width of the gate line wiring 70.

[0284] In the second embodiment, the relationship between the width W1 of the cathode region 110 and the width W2 of the inner cathode region 120 can be changed as desired. In one example, the width W1 of the cathode region 110 may be greater than the width W2 of the inner cathode region 120. In another example, the width W1 of the cathode region 110 may be smaller than the width W2 of the inner cathode region 120.

[0285] In each embodiment, the formation area of ​​the insulating film 60 can be changed as desired. The insulating film 60 only needs to cover at least the well region 54. In each embodiment, the chip 12 is not limited to a silicon single crystal substrate and can be changed as desired. In one example, the chip 12 may be a single crystal substrate of a wide bandgap semiconductor. For example, the chip 12 may be a SiC (silicon carbide) single crystal substrate, a GaN single crystal substrate, or the like.

[0286] In each embodiment, an n-type semiconductor region may be replaced with a p-type semiconductor region, and a p-type semiconductor region may be replaced with an n-type semiconductor region. A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings.

[0287] One or more of the various examples described herein can be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be in contact with the second element and disposed directly on the second element, but in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0288] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z direction described herein being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0289] <Supplementary Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the supplementary notes are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0290] [Supplementary Note 1] A chip (12) having a first main surface (12A) and a second main surface (12B) opposite to the first main surface (12A); an outer peripheral region (18) provided on the periphery of the first main surface (12A); an IGBT region (14) provided inside the outer peripheral region (18) in the first main surface (12A); a well region (54) of a first conductivity type (p) provided in a surface layer portion of the first main surface (12A) in the outer peripheral region (18) so as to partition the IGBT region (14); and a plurality of field regions (56) of a first conductivity type (p) provided at intervals from the well region (54) on the periphery side of the chip (12) in the surface layer portion of the first main surface (12A) of the outer peripheral region (18) and arranged spaced apart from each other. a cathode region (110) of a second conductivity type (n) provided in a surface layer portion of the second main surface (12B) of the peripheral region (18), the cathode region (110) constituting a diode (112) together with the well region (54); an insulating film (60) covering at least the well region (54); an emitter electrode (92) arranged on the insulating film (60) so as to be electrically connected to the well region (54); and a collector electrode (108) provided on the second main surface (12B) so as to be electrically connected to the cathode region (110), the cathode region (110) being located closer to the periphery of the chip (12) than the well region (54) and in a position facing at least one of the plurality of field regions (56) in a thickness direction (Z) of the chip (12).

[0291] [Supplementary Note 2] The semiconductor device described in Supplementary Note 1, wherein the plurality of field regions (56) includes an outermost field region (56D) closest to the periphery of the chip (12), and the cathode region (110) is positioned opposite, in the thickness direction (Z) of the chip (12), inner field regions (56A-56C) of the plurality of field regions (56), which are positioned closer to the well region (54) than the outermost field region (56D).

[0292] [Supplementary Note 3] The semiconductor device according to Supplementary Note 1 or 2, wherein the cathode region (110) is arranged in a position facing one of the plurality of field regions (56) that is closer to the well region (54) in the thickness direction (Z) of the chip (12).

[0293] [Supplementary Note 4] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein a width (W1) of the cathode region (110) is equal to a width (WF) of one of the field regions (56).

[0294] [Supplementary Note 5] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the width (W1) of the cathode region (110) is greater than the width (WF) of one of the field regions (56) and is smaller than twice the width (WF) of the field region (56).

[0295] [Supplementary Note 6] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the cathode region (110) extends to face the plurality of field regions (56) in the thickness direction (Z) of the chip (12).

[0296] [Supplementary Note 7] The semiconductor device according to any one of Supplementary Notes 1 to 6, further comprising: a channel stop region (58) provided in a surface layer portion of the first main surface (12A) of the peripheral region (18) at a distance from the field region (56) toward the periphery of the chip (12); and the cathode region (110) is arranged at a position facing the channel stop region (58) in a thickness direction (Z) of the chip (12) at a position that is closer to the field region (56) than the channel stop region (58).

[0297] [Appendix 8] The semiconductor device according to any one of appendices 1 to 7, wherein the cathode region (110) is provided in a ring shape surrounding the well region (54) when viewed from the thickness direction (Z) of the chip (12).

[0298] [Supplementary Note 9] The semiconductor device according to any one of Supplementary Notes 1 to 8, further comprising a collector region (24) of a first conductivity type (p) provided in a surface layer portion of the second main surface (12B), wherein the cathode region (110) has a second conductivity type impurity concentration higher than the first conductivity type impurity concentration of the collector region (24).

[0299] [Supplementary Note 10] The semiconductor device according to any one of Supplementary Notes 1 to 9, wherein the plurality of field regions (56) includes a specific field region to which an electric field of maximum strength is applied when a collector-emitter voltage (Vce) is applied, and the cathode region (110) is disposed in a position opposite the specific field region in the thickness direction (Z) of the chip (12).

[0300] [Supplementary Note 11] The semiconductor device according to Supplementary Note 2, comprising: inner field electrodes (102A-102C) arranged on the insulating film (60) and electrically connected to the inner field regions (56A-56C); and an outermost field electrode (102D) arranged on the insulating film (60) and electrically connected to the outermost field region (56D), wherein the width of the outermost field electrode (102D) is greater than the width of the inner field electrodes (102A-102C).

[0301] [Supplementary Note 12] The semiconductor device according to Supplementary Note 2, wherein widths (WA to WC) of the inner field regions (56A to 56C) are smaller than width (WD) of the outermost field region (56D).

[0302] [Appendix 13] The semiconductor device according to any one of Appendices 1 to 12, including: a well-connecting electrode (84) embedded in the insulating film (60) so as to be connected to the well region (54); a gate line electrode (90) arranged on the insulating film (60) at a distance from the well-connecting electrode (84 / 84A, 84B) so as to face the well region (54); and an inner cathode region (120) of a second conductivity type (n) that is provided along the second main surface (12B) at a distance from a gate reference position (PG) directly below the center of the gate line electrode (90) toward the well-connecting electrode (84 / 84A, 84B) in a surface layer portion of the second main surface (12B) so as to face the well region (54), and that forms a diode (112) with the well region (54).

[0303] [Appendix 14] The semiconductor device according to appendix 13, wherein when the distance between the center of the gate line electrode (90) and the well connection electrode (84 / 84A, 84B) is defined as a reference distance (Da / Db), the inner cathode region (120) is not disposed in a range (122) that does not exceed 1 / 2 of the reference distance (Da / Db) from the gate reference position (PG) toward the well connection electrode (84 / 84A, 84B).

[0304] [Appendix 15] The semiconductor device according to appendix 13, wherein when the distance between the center of the gate line electrode (90) and the well connection electrode (84 / 84A, 84B) is defined as a reference distance (Da / Db), the inner cathode region (120) has a portion that is arranged within a range not exceeding 1 / 2 of the reference distance (Da / Db) from a well reference position (PW1 / PW2) directly below the well connection electrode (84 / 84A, 84B).

[0305] [Appendix 16] The semiconductor device according to appendix 15, wherein the inner cathode region (120) is not disposed within a range not exceeding 1 / 2 of the reference distance (Da / Db) from the gate reference position (PG) toward the well connection electrode (84 / 84A, 84B).

[0306] [Supplementary Note 17] The semiconductor device according to any one of Supplementary Notes 13 to 16, wherein the inner cathode region (120) has a portion facing the well connection electrode (84 / 84A, 84B) in the thickness direction (Z) of the chip (12).

[0307] [Supplementary Note 18] The semiconductor device according to any one of Supplementary Notes 13 to 17, wherein the inner cathode region (120) does not face the gate line electrode (90) in the thickness direction (Z) of the chip (12).

[0308] [Supplementary Note 19] The semiconductor device according to any one of Supplementary Notes 13 to 18, wherein the gate line electrode (90) is arranged at a distance from the well connection electrode (84 / 84B) on the IGBT region (14) side, and the inner cathode region (120) is arranged at a distance from the gate reference position (PG) on the well connection electrode (84 / 84B) side along the second main surface (12B).

[0309] [Supplementary Note 20] The semiconductor device according to Supplementary Note 19, wherein the inner cathode region (120) is arranged only in a region facing the well region (54) in a surface layer portion of the second main surface (12B).

[0310] [Supplementary Note 21] The semiconductor device according to Supplementary Note 19, wherein the inner cathode region (120) includes: an opposing portion (132) that faces the well region (54) in the thickness direction (Z) of the chip (12); and a cathode lead-out portion (134) that is led out from the opposing portion (132) toward the peripheral edge of the chip (12).

[0311] [Supplementary Note 22] The semiconductor device according to Supplementary Note 21, wherein the cathode lead portion (134) is arranged closer to the well region (54) than the field region (56).

[0312] [Supplementary Note 23] The semiconductor device according to any one of Supplementary Notes 19 to 21, further comprising an emitter line electrode (96) disposed on the insulating film (60) so as to be electrically connected to the well region (54) via the well connection electrode (84 / 84B).

[0313] [Appendix 24] The semiconductor device according to any one of Appendices 13 to 16, wherein the gate line electrode (90) is arranged at a distance from the well connection electrode (84 / 84A) on the peripheral edge side of the chip (12), and the inner cathode region (120) is arranged at a distance from the gate reference position (PG) on the IGBT region (14) side along the second main surface (12B).

[0314] [Supplementary Note 25] The semiconductor device according to Supplementary Note 24, wherein the inner cathode region (120) is arranged only in a region facing the well region (54) in a surface layer portion of the second main surface (12B).

[0315] [Supplementary Note 26] The semiconductor device according to Supplementary Note 24 or 25, further comprising an emitter pad electrode (94) arranged on the insulating film (60) so as to be electrically connected to the well region (54) via the well connection electrode (84 / 84A).

[0316] [Supplementary Note 27] The semiconductor device according to any one of Supplementary Notes 13 to 26, further comprising: a gate line wiring (70) arranged inside the insulating film (60) so as to face the well region (54); and a gate connection electrode (80) embedded in the insulating film (60) so as to be connected to the gate line wiring (70), wherein the gate line electrode (90) is electrically connected to the gate line wiring (70) via the gate connection electrode (80).

[0317] [Supplementary Note 28] The semiconductor device according to Supplementary Note 27, wherein the inner cathode region (120) does not face the gate connection electrode (80) in the thickness direction (Z) of the chip (12).

[0318] [Supplementary Note 29] The semiconductor device according to Supplementary Note 27 or 28, wherein the inner cathode region (120) does not face the gate line wiring (70) in the thickness direction (Z) of the chip (12).

[0319] [Appendix 30] The semiconductor device according to any one of appendices 1 to 12, comprising: a first well-connecting electrode (84A) embedded in the insulating film (60) so as to be connected to the well region (54); a second well-connecting electrode (84B) embedded in the insulating film (60) at a distance from the first well-connecting electrode (84A) toward the periphery of the chip (12) so as to be connected to the well region (54); and an inner cathode region (120) of a second conductivity type (n) that is disposed at a distance from an intermediate reference position (PW3) immediately below the intermediate position between the first well-connecting electrode (84A) and the second well-connecting electrode (84B) along the second main surface (12B) so as to face the well region (54) in a surface portion of the second main surface (12B), and that forms a diode (112) with the well region (54).

[0320] [Appendix 31] The semiconductor device according to Appendix 30, wherein when the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is defined as a reference distance (Dc), the inner cathode region (120) is not positioned within a range that does not exceed ¼ of the reference distance (Dc) from the intermediate reference position (PW3).

[0321] [Supplementary Note 32] The semiconductor device according to Supplementary Note 30, wherein the inner cathode region (120) is disposed at a distance from the intermediate reference position (PW3) toward the first well-connecting electrode (84A).

[0322] [Appendix 33] The semiconductor device according to Appendix 32, wherein when the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is defined as a reference distance (Dc), the inner cathode region (120) is not positioned within a range from the intermediate reference position (PW3) toward the first well connecting electrode (84A) that does not exceed ¼ of the reference distance (Dc).

[0323] [Appendix 34] The semiconductor device according to Appendix 32, wherein when the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is a reference distance (Dc), the inner cathode region (120) has a portion that is arranged within a range not exceeding ¼ of the reference distance (Dc) from a first well reference position (PW1) directly below the first well connecting electrode (84A) toward the intermediate reference position (PW3).

[0324] [Appendix 35] The semiconductor device according to Appendix 34, wherein the inner cathode region (120) is not disposed within a range from the intermediate reference position (PW3) toward the first well connection electrode (84A) that does not exceed a distance of ¼ of the reference distance (Dc).

[0325] [Appendix 36] The semiconductor device according to any one of Appendices 32 to 35, wherein the inner cathode region (120) faces the first well connection electrode (84A) in the thickness direction (Z) of the chip (12).

[0326] [Supplementary Note 37] The semiconductor device according to Supplementary Note 30, wherein the inner cathode region (120) is disposed at a distance from the intermediate reference position (PW3) toward the second well connecting electrode (84B).

[0327] [Appendix 38] The semiconductor device according to Appendix 37, wherein when the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is defined as a reference distance (Dc), the inner cathode region (120) is not positioned within a range from the intermediate reference position (PW3) toward the second well connecting electrode (84B) that does not exceed ¼ of the reference distance (Dc).

[0328] [Appendix 39] The semiconductor device according to Appendix 37, wherein when the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is a reference distance (Dc), the inner cathode region (120) has a portion that is arranged within a range that does not exceed ¼ of the reference distance (Dc) from a second well reference position (PW2) directly below the second well connecting electrode (84B) toward the intermediate reference position (PW3).

[0329] [Appendix 40] The semiconductor device according to Appendix 39, wherein the inner cathode region (120) is not disposed within a range not exceeding ¼ of the reference distance (Dc) from the intermediate reference position (PW3) toward the second well connection electrode (84B).

[0330] [Supplementary Note 41] The semiconductor device according to any one of Supplementary Notes 37 to 40, wherein the inner cathode region (120) faces the second well connection electrode (84B) in the thickness direction (Z) of the chip (12).

[0331] [Supplementary Note 42] The semiconductor device according to Supplementary Note 30, wherein the inner cathode region (120) includes: a first inner cathode region (120A) arranged at a distance from the intermediate reference position (PW3) toward the first well connecting electrode (84A); and a second inner cathode region (120B) arranged at a distance from the intermediate reference position (PW3) toward the second well connecting electrode (84B).

[0332] [Appendix 43] The semiconductor device described in Appendix 42, wherein when the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is defined as a reference distance (Dc), the first inner cathode region (120A) is not positioned within a range from the intermediate reference position (PW3) toward the first well connecting electrode (84A) that does not exceed 1 / 4 of the reference distance (Dc).

[0333] [Appendix 44] The semiconductor device according to Appendix 42, wherein when the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is a reference distance (Dc), the first inner cathode region (120A) has a portion that is arranged within a range that does not exceed 1 / 4 of the reference distance (Dc) from a first well reference position (PW1) directly below the first well connecting electrode (84A) toward the intermediate reference position (PW3).

[0334] [Appendix 45] The semiconductor device according to Appendix 44, wherein the first inner cathode region (120A) is not disposed within a range from the intermediate reference position (PW3) toward the first well connection electrode (84A) that does not exceed a distance of ¼ of the reference distance (Dc).

[0335] [Appendix 46] The semiconductor device according to Appendix 45, wherein the second inner cathode region (120B) is not disposed within a range from the intermediate reference position (PW3) toward the second well connection electrode (84B) that does not exceed a distance of ¼ of the reference distance (Dc).

[0336] [Appendix 47] The semiconductor device according to appendix 45, wherein the second inner cathode region (120B) has a portion disposed within a range not exceeding ¼ of the reference distance (Dc) from the second well reference position (PW2) directly below the second well connection electrode (84B) toward the intermediate reference position (PW3).

[0337] [Appendix 48] The semiconductor device according to Appendix 47, wherein the second inner cathode region (120B) is not disposed within a range from the intermediate reference position (PW3) toward the second well connection electrode (84B) that does not exceed a distance of ¼ of the reference distance (Dc).

[0338] [Appendix 49] The semiconductor device according to any one of Appendices 30 to 48, further comprising a collector region (24) of a first conductivity type (n) provided in a surface layer portion of the second main surface (12B), wherein the inner cathode region (120) has a second conductivity type impurity concentration higher than the first conductivity type impurity concentration of the collector region (24).

[0339] [Supplementary Note 50] The semiconductor device according to any one of Supplementary Notes 13 to 49, wherein the second conductivity type impurity concentration of the inner cathode region (120) is equal to the second conductivity type impurity concentration of the cathode region (110).

[0340] [Supplementary Note 51] The semiconductor device according to any one of Supplementary Notes 13 to 49, wherein the second conductivity type impurity concentration of the inner cathode region (120) is higher than the second conductivity type impurity concentration of the cathode region (110).

[0341] [Supplementary Note 52] The semiconductor device according to any one of Supplementary Notes 13 to 49, wherein the second conductivity type impurity concentration of the inner cathode region (120) is lower than the second conductivity type impurity concentration of the cathode region (110).

[0342] [Supplementary Note 53] The semiconductor device according to any one of Supplementary Notes 13 to 52, wherein a width (W2) of the inner cathode region (120) is equal to a width (W1) of the cathode region (110).

[0343] [Supplementary Note 54] The semiconductor device according to any one of Supplementary Notes 13 to 52, wherein a width (W2) of the inner cathode region (120) is greater than a width (W1) of the cathode region (110).

[0344] [Supplementary Note 55] The semiconductor device according to any one of Supplementary Notes 13 to 52, wherein a width (W2) of the inner cathode region (120) is smaller than a width (W1) of the cathode region (110).

[0345] [Appendix 56] The semiconductor device according to any one of Appendices 13 to 55, further comprising a base region (36) of a first conductivity type (n) provided in a surface layer portion of the first main surface (12A) in the IGBT region (14).

[0346] [Supplementary Note 57] The semiconductor device according to Supplementary Note 56, wherein the inner cathode region (120) does not face the base region (36) in the thickness direction (Z) of the chip (12).

[0347] [Supplementary Note 58] The semiconductor device according to Supplementary Note 56 or 57, wherein the well region (54) is deeper than the base region (36).

[0348] [Appendix 59] The semiconductor device according to any one of appendices 56 to 58, wherein the well region (54) has a portion that is drawn from the outer peripheral region (18) to the IGBT region (14) and connected to the base region (36).

[0349] [Supplementary Note 60] The semiconductor device according to any one of Supplementary Notes 13 to 59, further comprising a trench gate structure (38) provided on the first main surface (12A) in the IGBT region (14).

[0350] [Supplementary Note 61] The semiconductor device according to Supplementary Note 60, wherein the inner cathode region (120) does not face the trench gate structure (38) in the thickness direction (Z) of the chip (12).

[0351] [Supplementary Note 62] The semiconductor device according to Supplementary Note 60 or 61, wherein the well region (54) is drawn from the outer peripheral region (18) to the IGBT region (14) and has a portion covering a bottom wall of the trench gate structure (38).

[0352] [Supplementary Note 63] The semiconductor device according to any one of Supplementary Notes 13 to 62, wherein the inner cathode region (120) is provided in an annular shape surrounding the IGBT region (14).

[0353] [Supplementary Note 64] The semiconductor device according to Supplementary Note 21, wherein the lead-out portion (134) extends closer to the periphery of the chip (12) than the well region (54).

[0354] [Supplementary Note 65] The semiconductor device according to Supplementary Note 64, wherein the lead-out portion (134) extends to a position opposite the field region (56) in the thickness direction (Z) of the chip (12).

[0355] [Supplementary Note 66] The semiconductor device according to Supplementary Note 8, wherein the cathode region (110) faces the opposing field region (56) in the thickness direction (Z) of the chip (12) over the entire periphery of the field region (56).

[0356] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0357] 10...Semiconductor device 12...Chip 12A...First main surface 12B...Second main surface 12C-12F...First to fourth side surfaces 14...IGBT region 16...Pad region 18...Peripheral region 20...Drift region 22...Buffer region 24...Collector region 26...Trench isolation structure 28...Isolation trench 30...Isolation insulating film 32...Isolation buried electrode 34...IGBT structure 36...Base region 38...Trench gate structure 40...Gate trench 42...Gate insulating film 44...Gate buried electrode 46...Emitter region 48...Contact hole 50...Contact region 52...Pad well region 54...Well region 54A...Inner edge 54B...Outer edge 56...Field region 56A-56C...Inner field region 56D...Outermost field region 58...Channel stop region 60...Insulating film 62...Main surface insulating film 64...Interlayer insulating film 66...Gate wiring 68...Gate pad wiring 70...Gate line wiring 72...Gate connecting wiring 74...Emitter opening 76...Emitter connecting electrode 78...Gate opening 80...Gate connecting electrode 82...Well opening 82A...First well opening 82AA...Segment opening 82B...Second well opening 84...Well connecting electrode 84A...First well connecting electrode 84B...Second well connecting electrode 86...Gate electrode 88...Gate pad electrode 90...Gate line electrode 90A...Open end 92...Emitter electrode 94...Emitter pad electrode 94A...Emitter lead-out portion 96...Emitter line electrode 98...Field opening 100...Field connecting electrode 102...Field electrodes 102A to 102C...Inner field electrodes 102D...Outermost field electrode 102E...Field lead-out portion 104...Channel stop opening 106...Channel stop electrode 108...Collector electrode 110...Cathode region 112...Diode 120...Inner cathode region 120A...First inner cathode region 120B...Second inner cathode region 122...Forbidden range 124...First allowed range 126...Second allowed range 132...Facing portion 134...Cathode lead-out portion Dwc...Distance between well region and channel stop region W1...Width of cathode regionW2...Width of inner cathode region WA to WC...Width of inner field region WD...Width of outermost field region WF...Width of field region WP...Width of well region WT...Total width of multiple field regions PW1...First well reference position PW2...Second well reference position PW3...Intermediate reference position PG...Gate reference position PK...Position of maximum electric field strength RA to RC...Range of inner field region RD...Range of outermost field region RW...Range of outer edge of well region v1...First maximum value v2...Minimum value v3...Second maximum value v4...First inflection point v5...Second inflection point Da...First reference distance Db...Second reference distance Dc...Third reference distance

Claims

1. A semiconductor device including: a chip having a first main surface and a second main surface opposite to the first main surface; an outer peripheral region provided at a peripheral portion of the first main surface; an IGBT region provided inside the outer peripheral region on the first main surface; a well region of a first conductivity type provided in a surface layer portion of the first main surface in the outer peripheral region so as to partition the IGBT region; a plurality of field regions of the first conductivity type provided at intervals from the well region toward a peripheral side of the chip in the surface layer portion of the first main surface of the outer peripheral region and arranged apart from each other; a cathode region of a second conductivity type provided in a surface layer portion of the second main surface of the outer peripheral region and constituting a diode with the well region; an insulating film covering at least the well region; an emitter electrode disposed on the insulating film so as to be electrically connected to the well region; and a collector electrode provided on the second main surface so as to be electrically connected to the cathode region, wherein the cathode region is located closer to the peripheral side of the chip than the well region and is arranged at a position facing at least one of the plurality of field regions in a thickness direction of the chip.

2. The semiconductor device according to claim 1, wherein the plurality of field regions include an outermost field region closest to the peripheral side of the chip, and the cathode region is arranged at a position facing an inner field region arranged closer to the well region than the outermost field region among the plurality of field regions in a thickness direction of the chip.

3. The semiconductor device according to claim 1 or 2, wherein the cathode region is arranged at a position facing one of the plurality of field regions closer to the well region in a thickness direction of the chip.

4. The semiconductor device according to any one of claims 1 to 3, wherein a width of the cathode region is equal to a width of one of the field regions.

5. The semiconductor device according to any one of claims 1 to 3, wherein the width of the cathode region is larger than a width of one of the field regions and smaller than twice the width of the field region.

6. The semiconductor device according to any one of claims 1 to 3, wherein the cathode region extends so as to face the plurality of field regions in a thickness direction of the chip.

7. The semiconductor device according to any one of claims 1 to 6, including a channel stop region provided in a surface layer portion of the first main surface of the outer peripheral region at an interval from the field region toward the peripheral edge side of the chip, and the cathode region is disposed at a position facing in the thickness direction of the chip with respect to a position spaced from the field region side of the channel stop region.

8. The semiconductor device according to any one of claims 1 to 7, wherein the cathode region is provided in an annular shape surrounding the well region when viewed from the thickness direction of the chip.

9. The semiconductor device according to any one of claims 1 to 8, including a collector region of a first conductivity type provided in a surface layer portion of the second main surface, and the cathode region has a second conductivity type impurity concentration higher than the first conductivity type impurity concentration of the collector region.

10. The semiconductor device according to any one of claims 1 to 9, wherein the plurality of field regions include a specific field region to which an electric field of maximum intensity is applied when a collector-emitter voltage is applied, and the cathode region is disposed at a position facing in the thickness direction of the chip with respect to the specific field region.

11. The semiconductor device according to claim 2, including an inner field electrode disposed on the insulating film and electrically connected to the inner field region, and an outermost field electrode disposed on the insulating film and electrically connected to the outermost field region, and the width of the outermost field electrode is larger than the width of the inner field electrode.

12. The semiconductor device according to claim 2, wherein the width of the inner field region is smaller than the width of the outermost field region.

13. The semiconductor device according to any one of claims 1 to 12, including a well connection electrode embedded in the insulating film so as to be connected to the well region, a gate line electrode disposed on the insulating film at an interval from the well connection electrode so as to face the well region, and an inner cathode region of a second conductivity type provided in a surface layer portion of the second main surface at an interval from a gate reference position directly below the center of the gate line electrode along the second main surface so as to face the well region and constituting a diode with the well region.

14. The semiconductor device according to claim 13, wherein when the distance between the center of the gate line electrode and the well connection electrode is defined as a reference distance, the inner cathode region is not arranged in a range that does not exceed a distance of 1 / 2 of the reference distance from the gate reference position toward the well connection electrode side.

15. The semiconductor device according to claim 13, wherein when the distance between the center of the gate line electrode and the well connection electrode is defined as a reference distance, the inner cathode region has a portion arranged in a range that does not exceed a distance of 1 / 2 of the reference distance from the well reference position directly below the well connection electrode.

16. The semiconductor device according to claim 15, wherein the inner cathode region is not arranged in a range that does not exceed a distance of 1 / 2 of the reference distance from the gate reference position toward the well connection electrode side.

17. The semiconductor device according to any one of claims 13 to 16, wherein the inner cathode region has a portion facing the well connection electrode in the thickness direction of the chip.

18. The semiconductor device according to any one of claims 13 to 17, wherein the inner cathode region does not face the gate line electrode in the thickness direction of the chip.

19. The semiconductor device according to any one of claims 13 to 18, wherein the gate line electrode is arranged at an interval from the well connection electrode toward the IGBT region side, and the inner cathode region is arranged at an interval from the gate reference position toward the well connection electrode side along the second main surface.

20. The semiconductor device according to claim 19, wherein the inner cathode region is arranged only in a region facing the well region in the surface layer portion of the second main surface.

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