Semiconductor light-emitting element and method for manufacturing semiconductor light-emitting element

Abstract

A semiconductor light-emitting element (100) comprises: a growth substrate (10); a mask (30) formed on the growth substrate (10); and columnar semiconductor layers (40) each grown from an opening part provided in the mask (30). Each of the columnar semiconductor layers (40) has an n-type nanowire layer (41) formed at the center thereof, an active layer (42) formed on the outer circumference of the n-type nanowire layer (41), and a p-type semiconductor layer (43) formed on the outer circumference of the active layer (42). The n-type impurity concentration in the n-type nanowire layer (41) is higher on the growth substrate (10) side than on the leading end side.

Description

Semiconductor light emitting device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor light emitting device and a method for manufacturing the same.

[0002] In recent years, rapid advances have been made in crystal growth methods for nitride-based semiconductors, and high-brightness light-emitting devices using these materials have been put to practical use. It is desirable for such semiconductor light-emitting devices using nitride semiconductors to achieve high energy conversion efficiency and high optical output in high current density regions, and it is also desirable for the emitted light to have stable light distribution characteristics. To address these issues, Patent Document 1 proposes a semiconductor light-emitting device in which an n-type nanowire core, an active layer, and a p-type layer are grown on a semiconductor substrate.

[0003] In the semiconductor light-emitting device disclosed in Patent Document 1, in which an active layer is formed on the outer periphery of a nanowire core, there are fewer crystal defects and threading dislocations than in a device in which an active layer is formed on the entire surface of a sapphire substrate, and high-quality crystals can be obtained, and m-plane growth can be achieved, thereby improving external quantum efficiency at high current densities. Furthermore, in the semiconductor light-emitting device using the nanowire core of Patent Document 1, because the active layer can be formed from high-quality crystals, it is expected that the In composition of the active layer can be increased to achieve longer wavelengths.

[0004] Japanese Patent Application Publication No. 2022-040676

[0005] In conventional semiconductor light-emitting devices, nanowires with a high aspect ratio in the height direction are used, and current is injected from the p-type layer into the active layer formed on the side of the nanowire, which tends to result in a high current density at the top of the nanowire and a low current density at the bottom. This makes it difficult to inject current uniformly into the active layer, and therefore makes it difficult to improve the light-emitting efficiency of the entire nanowire.

[0006] Therefore, the present disclosure has been made in consideration of the above-mentioned conventional problems, and aims to provide a semiconductor light-emitting element and a method for manufacturing a semiconductor light-emitting element that can uniformize the current density injected into an active layer formed on the side of a nanowire.

[0007] In order to solve the above problems, (1) the semiconductor light-emitting element of the present disclosure is a semiconductor light-emitting element comprising a growth substrate, a mask formed on the growth substrate, and a columnar semiconductor layer grown from an opening provided in the mask, wherein the columnar semiconductor layer has an n-type nanowire layer formed in the center, an active layer formed on the outer periphery of the n-type nanowire layer, and a p-type semiconductor layer formed on the outer periphery of the active layer, and the n-type impurity concentration of the n-type nanowire layer is higher on the growth substrate side than on the tip side.

[0008] In such a semiconductor light-emitting element disclosed herein, the n-type impurity concentration of the n-type nanowire layer is higher on the growth substrate side than on the tip side, thereby increasing the electrical conductivity of the n-type nanowire layer on the growth substrate side and making it possible to uniformize the current density injected into the active layer formed on the side of the nanowire.

[0009] (2) In the semiconductor light emitting device of (1) above, the n-type impurity concentration of the n-type nanowire layer may be gradually decreased from the growth substrate side toward the tip side.

[0010] (3) In the semiconductor light-emitting device of (2) above, the n-type nanowire layer may have a first region on the growth substrate side and a second region on the tip side, and the gradient of the n-type impurity concentration may be greater in the first region than in the second region.

[0011] (4) In the semiconductor light emitting device of (3) above, the maximum n-type impurity concentration in the second region may be 1.2 times or more the minimum n-type impurity concentration.

[0012] (5) In the semiconductor light-emitting device of (3) or (4), the n-type impurity concentration in the second region has a maximum value of 3×10 ２０ / cm ３ It may be the following:

[0013] (6) In the semiconductor light emitting device according to any one of (1) to (5) above, the p-type impurity concentration of the p-type semiconductor layer may be higher around the tip side than around the growth substrate side.

[0014] In order to solve the above problems, (6) the manufacturing method of the semiconductor light-emitting element of the present disclosure includes a mask formation process for forming a mask having an opening on a growth substrate, and a growth process for forming a columnar semiconductor layer in the opening using selective growth, the growth process including a nanowire growth process for forming an n-type nanowire layer, an active layer growth process for forming an active layer outside the n-type nanowire layer, and a p-type layer growth process for forming a p-type semiconductor layer outside the active layer, and the nanowire growth process is characterized in that the n-type impurity concentration is higher on the growth substrate side than on the tip side.

[0015] (7) In the method for manufacturing a semiconductor light-emitting element according to (6) above, the nanowire growing step may include decreasing the amount of n-type impurity supplied to the tip side relative to the growth substrate side.

[0016] (8) In the method for manufacturing a semiconductor light-emitting element according to (6) or (7) above, the nanowire growing step may involve decreasing the growth temperature on the tip side relative to the growth substrate side.

[0017] The present disclosure can provide a semiconductor light emitting device and a method for manufacturing the semiconductor light emitting device that can uniformize the current density injected into an active layer formed on the side surface of a nanowire.

[0018] 1 is a schematic diagram showing a semiconductor light emitting device 100 according to a first embodiment; FIG. 2 is a diagram showing a structure and impurity concentration of a columnar semiconductor layer 40 according to the first embodiment; FIG. 3 is a diagram showing a mask formation step in a method for manufacturing the semiconductor light emitting device 100 according to the first embodiment; FIG. 4 is a diagram showing a nanowire growth step and an active layer growth step in a method for manufacturing the semiconductor light emitting device 100 according to the first embodiment; FIG. 5 is a diagram showing a p-type layer growth step and a tunnel junction layer growth step in a method for manufacturing the semiconductor light emitting device 100 according to the first embodiment; FIG. 6 is a diagram showing an electrode formation step in a method for manufacturing the semiconductor light emitting device 100 according to the first embodiment; FIG. 7 is a graph showing changes in temperature and n-type impurity supply amount in a nanowire growth step, illustrating an example in which the n-type impurity supply amount is changed; FIG. 8 is a graph showing changes in temperature and n-type impurity supply amount in a nanowire growth step, illustrating an example in which the temperature is changed; FIG. 9 is a schematic diagram explaining a method for measuring the impurity concentration of an n-type nanowire layer 41, illustrating the formation of a columnar semiconductor layer 40; FIG. 10 is a schematic diagram explaining a method for measuring the impurity concentration of an n-type nanowire layer 41, illustrating the formation of a p-type GaN layer 90. 1A is a schematic cross-sectional view of SIMS analysis in a method for measuring the impurity concentration of an n-type nanowire layer 41. FIG. 1B is a schematic plan view of SIMS analysis in a method for measuring the impurity concentration of an n-type nanowire layer 41. FIG. 1C is a cross-sectional SEM image of a sample for explaining the shape and density of the n-type nanowire layer 41. FIG. 1D is a schematic plan view showing the arrangement of the n-type nanowire layer 41 in the plane of the growth substrate 10 for explaining the shape and density of the n-type nanowire layer 41. FIG. 1E is a diagram showing the results of SIMS analysis, where (a) is a schematic diagram showing a position in the n-type nanowire layer 41, and (b) is a graph showing a SIMS depth profile of Si concentration and a correction value. FIG. 1F is a schematic diagram showing a semiconductor light-emitting device 100 according to a second embodiment. FIG. 1G is a diagram showing a structure and impurity concentration of a columnar semiconductor layer 40 according to the second embodiment. FIG. 1H is a diagram showing a mask formation step in a method for manufacturing a semiconductor light-emitting device 100 according to the second embodiment. FIG. 1I is a diagram showing a nanowire growth step and an active layer growth step in a method for manufacturing a semiconductor light-emitting device 100 according to the second embodiment. FIG. 1J is a diagram showing a p-type layer growth step in a method for manufacturing a semiconductor light-emitting device 100 according to the second embodiment.10A to 10C are diagrams illustrating an electrode formation step in the manufacturing method of the semiconductor light emitting device 100 according to the second embodiment.

[0019] First Embodiment Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be denoted by the same reference numerals, and redundant description will be omitted as appropriate. Figure 1 is a schematic diagram showing a semiconductor light emitting device 100 according to this embodiment.

[0020] 1 , the semiconductor light emitting device 100 includes a growth substrate 10, an underlayer 20, a mask 30, an n-type nanowire layer 41, an active layer 42, a p-type semiconductor layer 43, a tunnel junction layer 44, an embedded semiconductor layer 50, a protective film 60, an anode electrode 70, and a cathode electrode 80. Here, the n-type nanowire layer 41, the active layer 42, the p-type semiconductor layer 43, and the tunnel junction layer 44 are selectively grown in a direction perpendicular to the growth substrate 10 to form a columnar shape, and constitute the columnar semiconductor layer 40 of the present disclosure.

[0021] The growth substrate 10 is a substantially flat plate-shaped member made of a material that allows for crystal growth of a semiconductor material, and a mask 30 is formed on the main surface side. The growth substrate 10 may be made of a single material, or may be a single-crystal substrate on which multiple semiconductor layers, such as a buffer layer, are grown. The growth substrate 10 may be any single-crystal substrate made of a material that allows for the growth of a semiconductor single-crystal layer via a buffer layer. When the semiconductor light-emitting device 100 is made of a nitride-based semiconductor, a c-plane sapphire substrate is preferred, but other heterogeneous substrates such as Si may also be used. Furthermore, for laser oscillation, a c-plane GaN substrate, which allows for the formation of a cavity facet by cleavage, may also be used. The buffer layer is formed between the single-crystal substrate and the underlayer 20 to reduce lattice mismatch between the two. When a c-plane sapphire substrate is used as the single-crystal substrate, GaN is preferably used as the buffer layer material, but AlN, AlGaN, etc. may also be used.

[0022] The underlayer 20 is a single-crystal semiconductor layer formed on the growth substrate 10 or the buffer layer, and is preferably composed of a plurality of layers, with non-doped GaN formed to a thickness of several μm and an n-type semiconductor layer such as an n-type contact layer formed thereon. The n-type contact layer is a semiconductor layer doped with n-type impurities, for example, Si-doped n-type Al ０．０５ Ga ０．９５ As shown in FIG. 1, a cathode electrode 80 is formed on a part of the underlayer 20 .

[0023] The mask 30 is a layer made of a dielectric material formed on the surface of the underlayer 20. The material constituting the mask 30 is selected from those that are difficult for semiconductor crystal growth to occur on, for example, SiO ２ and SiN ｘ and Al ２ O ３ The mask 30 has a plurality of openings, which will be described later, formed therein, allowing a semiconductor layer to grow on the base layer 20 within the openings.

[0024] The pillar-shaped semiconductor layer 40 is a semiconductor layer crystal-grown in the openings provided in the mask 30, and is formed as a substantially pillar-shaped semiconductor layer standing vertically relative to the main surface of the growth substrate 10. Such a pillar-shaped semiconductor layer 40 is obtained by setting appropriate growth conditions according to the semiconductor material constituting the layer and performing selective growth that grows a specific crystal plane orientation. In the example shown in FIG. 1 , a plurality of openings are formed two-dimensionally and periodically in the mask 30, and therefore the pillar-shaped semiconductor layer 40 is also formed two-dimensionally and periodically on the growth substrate 10.

[0025] The n-type nanowire layer 41 is a columnar semiconductor layer selectively grown on the underlayer 20 exposed through the opening in the mask 30, and is composed of, for example, GaN doped with n-type impurities. When GaN is used as the n-type nanowire layer 41, the n-type nanowire layer 41 selectively grown on the c-plane of the underlayer 20 has a roughly hexagonal prism shape with six m-planes formed as facets. In FIG. 1 , the n-type nanowire layer 41 appears to grow only in the region where the opening is formed, but in reality, crystal growth also progresses on the mask 30 due to lateral growth, resulting in the formation of an enlarged hexagonal prism around the opening. For example, when the opening is formed as a circle with a diameter of approximately 150 nm, the n-type nanowire layer 41 can be formed as a hexagonal prism with a height of approximately 1 to 2 μm, with a base that is a hexagon inscribed in a circle with a diameter of approximately 240 nm.

[0026] The active layer 42 is a semiconductor layer grown on the outer periphery of the n-type nanowire layer 41. For example, it may be a multi-quantum well active layer formed by stacking five periods of 5-nm-thick GaInN quantum well layers and 10-nm-thick GaN barrier layers. While a multi-quantum well active layer is used here, a single quantum well structure or a bulk active layer may also be used. Because the active layer 42 is formed on the side and top surfaces of the n-type nanowire layer 41, a sufficient area for the active layer 42 can be ensured. The higher the proportion of In incorporated into the active layer, the longer the emission wavelength of the semiconductor light-emitting device 100 becomes. By setting the In composition ratio to 0.1 or greater, the emission wavelength can be increased to 480 nm or greater. Furthermore, by setting the In composition ratio to 0.12 or greater, the emission wavelength can be increased to 500 nm or greater.

[0027] The p-type semiconductor layer 43 is a semiconductor layer grown on the outer periphery of the active layer 42, and is made of, for example, GaN doped with p-type impurities. Because the p-type semiconductor layer 43 is formed on the side and top surfaces of the active layer 42, a double heterostructure is formed by the n-type nanowire layer 41, the active layer 42, and the p-type semiconductor layer 43, which can effectively confine carriers in the active layer 42 and improve the probability of radiative recombination.

[0028] The tunnel junction layer 44 is a semiconductor layer grown on the outer periphery of the p-type semiconductor layer 43, and has a two-layer structure in which, for example, a p+ layer doped with a high concentration of p-type impurities on the inside and an n+ layer doped with a high concentration of n-type impurities on the outside are grown in this order. The p+ layer is a semiconductor layer doped with a high concentration of p-type impurities, and has, for example, a thickness of 5 nm and an Mg concentration of 2×10 ２０ cm －３ The n+ layer may be made of GaN with a thickness of 10 nm and a Si concentration of 2×10 ２０ cm －３ Since a tunnel junction is formed by the p+ layer and the n+ layer, the two layers of the p+ layer and the n+ layer constitute the tunnel junction layer 44 in the present invention.

[0029] The buried semiconductor layer 50 is a semiconductor layer formed to cover the top and side surfaces of the pillar-shaped semiconductor layer 40 and to cover the entire surface down to the mask 30. As shown in FIG. 1 , above the pillar-shaped semiconductor layer, the buried semiconductor layer 50 also covers the tunnel junction layer 44. The buried semiconductor layer 50 is in ohmic contact with the anode electrode 70 and is an n-type semiconductor layer in order to inject carriers via the tunnel junction layer 44. Although the buried semiconductor layer 50 is shown as a single layer here, it may be composed of multiple semiconductor layers with different materials, compositions, and impurity concentrations.

[0030] The anode electrode 70 is an electrode formed on a portion of the buried semiconductor layer 50, and is composed of a laminated structure of a metal material that makes ohmic contact with the outermost surface of the buried semiconductor layer 50 and a pad electrode. The cathode electrode 80 is an electrode formed in an area where the base layer 20 is exposed, and is composed of a laminated structure of a metal material that makes ohmic contact with the outermost surface of the base layer 20 and a pad electrode. If necessary, a known structure may be applied, such as covering the surface of the semiconductor light emitting element 100 with a protective film 60. A transparent electrode extending from the anode electrode 70 may be formed over the entire upper surface of the buried semiconductor layer 50.

[0031] In order to lengthen the emission wavelength of the semiconductor light emitting device 100, it is necessary to increase the InN mole fraction of the active layer 42. For example, when the circumscribed circle diameter of the n-type nanowire layer 41 is 300 nm, the red active layer composition Ga ０．６ In０．４ However, as the InN mole fraction increases, compressive stress increases, which may cause misfit dislocations. ０．６ In ０．４ It is also possible to reduce the thickness of the N well layer or to use GaInN as the material for the n-type nanowire layer 41. Similarly, to shorten the wavelength of the semiconductor light emitting device 100, it is also possible to use AlGaN for the n-type nanowire layer 41 or to change the well layer and barrier layer of the active layer 42 to AlGaN with different compositions.

[0032] 2 is a diagram schematically illustrating the structure and impurity concentration of the pillar-shaped semiconductor layer 40 according to this embodiment. The gradations in the n-type nanowire layer 41, p-type semiconductor layer 43, and tunnel junction layer 44 in the figure visually represent the gradient of the impurity concentration in each layer. In this embodiment, as shown in FIG. 2, in the n-type nanowire layer 41, the n-type impurity concentration is higher on the growth substrate 10 side than on the tip side, and gradually decreases from the growth substrate 10 side toward the tip side. Methods for forming and measuring the n-type impurity concentration gradient in the n-type nanowire layer 41 will be described later.

[0033] In the p-type semiconductor layer 43 and the p+ layer of the tunnel junction layer 44, the concentration of the p-type impurity is higher on the tip side than on the growth substrate 10 side, and gradually decreases from the tip side toward the growth substrate side. The concentration gradient of the p-type impurity in the p-type semiconductor layer 43 may be formed naturally when the aspect ratio of the n-type nanowire layer 41 is large and the raw material of the p-type impurity is not sufficiently supplied to the growth substrate 10 side.

[0034] 3A to 3E are schematic diagrams showing a method for manufacturing the semiconductor light-emitting element 100 according to this embodiment, in which FIG. 3A shows a mask formation process, FIG. 3B shows a nanowire growth process and an active layer growth process, FIG. 3C shows a p-type layer growth process and a tunnel junction layer growth process, FIG. 3D shows a burying process, and FIG. 3E shows an electrode formation process.

[0035] 3A, a buffer layer made of GaN and an underlayer 20 made of GaN and AlGaN are grown on a growth substrate 10 made of single crystal sapphire using metal organic chemical vapor deposition (MOCVD). The growth conditions for the buffer layer are, for example, TMG (trimethylgallium) and ammonia as source gases, a growth temperature of 1100°C, a V / III ratio of 1000, hydrogen as carrier gas, and a pressure of 10 hPa. The growth conditions for the underlayer 20 and the n-type semiconductor layer are, for example, TMA (Trimethylaluminum), TMG (Trimethylgallium), and ammonia as source gases, a growth temperature of 1050° C., a V / III ratio of 1000, hydrogen as carrier gas, and a pressure of 500 hPa. After the buffer layer and underlayer 20 are grown, SiO is sputtered on the underlayer 20. ２ A mask 30 made of SiO 2 is deposited to a thickness of about 30 nm, and a plurality of openings 31 with a diameter of about 150 nm are formed using a fine pattern forming method such as nanoimprinting lithography.

[0036] 3B, an n-type nanowire layer 41 made of GaN is grown by selective growth using the MOCVD method on the base layer 20 exposed from the opening 31. The growth conditions for the n-type nanowire layer 41 are, for example, TMG, silane, and ammonia as source gases, a growth temperature of 1050°C, a V / III ratio of 10, hydrogen as a carrier gas, and a pressure of 100 hPa. As described above, the concentration of n-type impurities gradually decreases in the height direction of the n-type nanowire layer 41 from the growth substrate 10 side toward the tip side. The method for forming and measuring this concentration gradient will be described later.

[0037] In the active layer growth step, an MOCVD method is used to grow an active layer 42, which is composed of five periods of 5-nm-thick GaInN quantum well layers and 10-nm-thick GaN barrier layers, on the side and top surfaces of the n-type nanowire layer 41. The growth conditions for the active layer 42 are, for example, a growth temperature of 800° C., a V / III ratio of 3000, a pressure of 1000 hPa using nitrogen as a carrier gas, and TMG, TMI (Trimethylindium), and ammonia as source gases.

[0038] 3C, a p-type semiconductor layer 43 made of GaN doped with p-type impurities is grown. The growth conditions for the p-type semiconductor layer 43 are, for example, a growth temperature of 950° C., a V / III ratio of 1000, a pressure of 300 hPa using hydrogen as a carrier gas, and TMG, Cp ２ Mg (bisCyclopentadienylMagnesium) and ammonia are used.

[0039] In the tunnel junction layer growth process, the Mg concentration is 2×10 ２０ cm －３ and a p+ layer made of GaN with a thickness of 10 nm and a Si concentration of 2×10 ２０ cm －３ A tunnel junction layer 44 including an n+ layer made of GaN is grown. The growth conditions for the tunnel junction layer 44 are, for example, a growth temperature of 800°C, a V / III ratio of 3000, and a pressure of 500 hPa using nitrogen as a carrier gas. As a result, a pillar-shaped semiconductor layer 40 made of an n-type nanowire layer 41, an active layer 42, a p-type semiconductor layer 43, and the tunnel junction layer 44 is formed.

[0040] Next, in the burying step shown in FIG. 3D , a buried semiconductor layer 50 made of n-type GaN is grown, burying the outer periphery and upper surface of the tunnel junction layer 44 with the buried semiconductor layer 50. The buried semiconductor layer 50 must be grown on the mask 30 provided between the pillar-shaped semiconductor layers 40. During growth of the buried semiconductor layer 50, voids may form beneath the pillar-shaped semiconductor layer 40. Therefore, the buried semiconductor layer 50 is preferably grown using TMG, silane, and ammonia as source gases at a low temperature and a low V / III ratio, which promotes lateral growth of the m-plane in the initial stage. Examples of low temperatures and low V / III ratios include a V / III ratio of 100 or less at 800°C or less, a pressure of 200 hPa using hydrogen as the carrier gas, and a temperature of 200°C or less. After the lateral growth of the buried semiconductor layer 50 completely fills the mask 30 beneath the pillar-shaped semiconductor layer 40, it is preferable to grow the buried semiconductor layer 50 at a high temperature and a high V / III ratio, which promotes vertical growth of the c-plane. An example of a high temperature and a high V / III ratio is a temperature of 1000° C. or higher, a V / III ratio of 2000 or higher, and a pressure of 500 hPa using hydrogen as a carrier gas.

[0041] 3E , the region where the element isolation region and the cathode electrode 80 are to be formed is selectively dry-etched, and the buried semiconductor layer 50 and the columnar semiconductor layer 40 are removed down to the mask 30 to expose the upper surface of the base layer 20. Annealing is then performed at 600° C. in an air atmosphere to remove hydrogen trapped in the p-type semiconductor layer 43 and the tunnel junction layer 44, thereby activating the p-type semiconductor layer 43 and the tunnel junction layer 44. While annealing in an air atmosphere is shown here, any atmosphere may be used as long as it is free of atomic hydrogen and can activate the p-type semiconductor layer 43 and the tunnel junction layer 44.

[0042] Finally, an anode electrode 70 is formed on the buried semiconductor layer 50, and a cathode electrode 80 is formed on the surface of the base layer 20. Furthermore, if necessary, annealing after electrode formation, formation of a protective film 60, and element division are performed to obtain a semiconductor light emitting element 100.

[0043] 4A and 4B are graphs showing the change in temperature and n-type impurity supply rate during the nanowire growth process. Fig. 4A shows an example in which the n-type impurity supply rate is changed, and Fig. 4B shows an example in which the temperature is changed. In Fig. 4A and Fig. 4B, the horizontal axis represents the passage of time, and the vertical axis represents the relative change in temperature and n-type impurity supply rate. In the example shown in Fig. 4A, the growth temperature of the n-type nanowire layer 41 is kept constant, while the flow rate of the Si source, which is the supply rate of the n-type impurity, is gradually reduced. This results in a high n-type impurity concentration at the bottom (growth substrate 10 side) of the n-type nanowire layer 41 and a decrease in n-type impurity concentration toward the top (tip side), thereby achieving the impurity concentration gradient of the n-type nanowire layer 41 shown in Fig. 2.

[0044] 4B, the growth temperature of the n-type nanowire layer 41 is gradually decreased while the flow rate of the Si source, which is the supply rate of the n-type impurity, is kept constant. As a result, the amount of n-type impurity incorporated into the n-type nanowire layer 41 increases in the lower part (the growth substrate 10 side) and decreases toward the upper part (the tip side), thereby realizing the impurity concentration gradient in the n-type nanowire layer 41 shown in FIG.

[0045] Although FIGS. 4A and 4B show examples in which either the temperature or the n-type impurity supply rate is kept constant while the other is varied, both may be varied. Furthermore, the temperature and the n-type impurity supply rate do not necessarily change stepwise as shown in FIGS. 4A and 4B , but may be gradually decreased. Furthermore, the amount of change in the temperature and the n-type impurity supply rate is not necessarily constant, but may be varied at each stage. Furthermore, because nitride semiconductors tend to have n-type conductivity without intentional doping with n-type impurities, the n-type impurity supply rate may be set to zero when growing the tip vicinity of the n-type nanowire layer 41. Furthermore, the n-type impurity supply rate may be set to zero during the growth of the n-type nanowire layer 41, so that n-type impurities remaining in the MOCVD apparatus are incorporated into the semiconductor layer.

[0046] In the semiconductor light emitting device 100 of this embodiment, when a voltage is applied between the anode electrode 70 and the cathode electrode 80, a current flows through the buried semiconductor layer 50, the tunnel junction layer 44, the p-type semiconductor layer 43, the active layer 42, the n-type nanowire layer 41, and the underlayer 20 in this order, and light is generated by radiative recombination in the active layer 42. The light emitted from the active layer 42 is extracted to the outside of the semiconductor light emitting device 100.

[0047] Furthermore, in the semiconductor light emitting device 100 of this embodiment, the active layer 42 is formed on the outer periphery of the n-type nanowire layer 41, and a tunnel junction layer 44 is further formed on the outer periphery thereof and is buried with the buried semiconductor layer 50. Therefore, current injected from the anode electrode 70 passes from the buried semiconductor layer 50 through the tunnel junction layer 44 and is injected as a tunnel current from the sidewall of the p-type semiconductor layer 43 into the active layer 42. The current injection by the tunnel current via the tunnel junction layer 44 has low resistance, allowing for satisfactory current injection. Furthermore, because the buried semiconductor layer 50, which is an n-type semiconductor layer, allows current to diffuse more easily than a p-type semiconductor layer, current can be diffused on the side surfaces of the columnar semiconductor layer 40 to the vicinity of the bottom surface, allowing for satisfactory current injection from the entire tunnel junction layer 44.

[0048] As a result, the current injected from the anode electrode 70 is effectively injected into the p-type semiconductor layer 43 from the entire side surface of the columnar semiconductor layer 40 rather than from the top surface thereof, thereby enabling effective current injection into the active layer 42, realizing a high current density and improving the external quantum efficiency.

[0049] Furthermore, because the side surfaces of the n-type nanowire layer 41 are m-planes formed by selective growth, the active layer 42 and p-type semiconductor layer 43 formed on the outer periphery are also in contact with each other at the m-plane. The m-plane is a nonpolar plane and does not generate polarization, so the light emission efficiency of the active layer 42 is high. Moreover, because all of the side surfaces of the hexagonal prism are m-planes, the light emission efficiency of the semiconductor light-emitting element 100 can be improved. Furthermore, because the film thickness of the active layer 42 can be increased, the volume of the active layer 42 can be increased by approximately 3 to 10 times compared to conventional semiconductor light-emitting elements, reducing the injected carrier density and significantly reducing efficiency droop.

[0050] In this embodiment, the concentration of n-type impurities in the n-type nanowire layer 41 is higher on the growth substrate 10 side than on the tip side, and gradually decreases from the growth substrate 10 side toward the tip side. This prevents the current density from increasing at the tip of the columnar semiconductor layer 40, and allows the current to be diffused to the lower part of the n-type nanowire layer 41 (the side closer to the growth substrate 10) far from the anode electrode 70, thereby making it possible to uniformize the current density injected into the active layer 42.

[0051] In this embodiment, the p-type impurity concentration in the p-type semiconductor layer 43 and the p+ layer of the tunnel junction layer 44 is higher on the tip side than on the growth substrate 10 side, and gradually decreases from the tip side toward the growth substrate side. This allows the current density injected into the active layer 42 to be made uniform by combining the concentration gradient of the n-type impurity in the n-type nanowire layer 41 and the concentration gradient of the p-type impurity in the p-type semiconductor layer 43.

[0052] In this embodiment, the pillar-shaped semiconductor layer 40 including the n-type nanowire layer 41 is grown vertically on the growth substrate 10, and then the buried semiconductor layer 50 is grown between the n-type nanowire layers 41. Therefore, in a normal SIMS (Secondary Ion Mass Spectrometry) analysis, n-type impurities contained in both the n-type nanowire layer 41 and the buried semiconductor layer 50 are detected, and it is not possible to obtain a depth profile of only the n-type nanowire layer 41. Therefore, in order to obtain a depth profile of only the n-type nanowire layer 41, SIMS analysis is performed using the pillar-shaped semiconductor layer 40 for measurement.

[0053] 5A to 5D are schematic diagrams illustrating a method for measuring the impurity concentration of the n-type nanowire layer 41, in which Fig. 5A shows the formation of the columnar semiconductor layer 40, Fig. 5B shows the formation of the p-type GaN layer 90, Fig. 5C is a schematic cross-sectional view of the SIMS analysis, and Fig. 5D is a schematic plan view of the SIMS analysis. The growth substrate 10 and the mask 30 are not shown in Figs. 5A to 5D.

[0054] First, as shown in Fig. 5A, a pillar-shaped semiconductor layer 40 is selectively grown on the underlayer 20. At this time, the growth conditions for the pillar-shaped semiconductor layer 40 are the same as those for the nanowire growth process shown in Fig. 3B. The pillar-shaped semiconductor layer 40 includes an n-type nanowire layer 41, but the active layer 42 and p-type semiconductor layer 43 may not be included in this measurement. Because the tunnel junction layer 44 includes an n+ layer, it is preferable that the pillar-shaped semiconductor layer 40 used for measurement does not include the tunnel junction layer 44 so as not to detect n-type impurities in the n+ layer.

[0055] 5B , a p-type GaN layer 90 is grown between and on top of the columnar semiconductor layers 40 to flatten the surface. The growth conditions for the p-type GaN layer 90 may be the same as or different from those for the p-type semiconductor layer 43. Here, an example is shown in which the spaces between the measurement columnar semiconductor layers 40 are filled with the p-type GaN layer 90, but as long as the semiconductor layer does not contain n-type impurities, it may be undoped, or may be filled with AlGaN or the like. The p-type impurity contained in the p-type GaN layer 90 is not limited, but Mg can be used.

[0056] Next, as shown in Figures 5C and 5D, ion beam B is irradiated from the surface side of the p-type GaN layer 90 to perform SIMS analysis. The simplified graph shown on the right side of Figure 5C is a schematic representation of the concentration distribution of n-type impurities obtained by SIMS analysis. As shown in Figures 5C and 5D, the ion beam B used in the SIMS analysis is irradiated over an area wider than the diameter of the pillar-shaped semiconductor layer 40, so the detected depth profile includes both the pillar-shaped semiconductor layer 40 and the p-type GaN layer 90.

[0057] 6A and 6B are diagrams illustrating the shape and density of the n-type nanowire layer 41. FIG. 6A is a cross-sectional SEM image of the sample, and FIG. 6B is a schematic plan view showing the arrangement of the n-type nanowire layer 41 within the plane of the growth substrate 10. As shown in FIG. 6A, the n-type nanowire layer 41 (n-GaN core shown in the figure) included in the pillar-shaped semiconductor layer 40 had a height of 1070 nm, and the p-type GaN layer 90 formed on the pillar-shaped semiconductor layer 40 had a thickness of 230 nm, resulting in a total thickness of 1300 nm. Furthermore, as shown in FIG. 6B, the pillar-shaped semiconductor layers 40 were arranged in a triangular lattice pattern, and each unit region enclosed by a rectangle in the figure contains two pillar-shaped semiconductor layers 40. Therefore, the concentration of the depth profile obtained by SIMS analysis can be corrected based on the ratio of the cross-sectional area of ​​the pillar-shaped semiconductor layer 40 to the area of ​​the unit region. As an example, if the width of the opposing m-planes of the pillar-shaped semiconductor layers 40 is 340 nm and the pitch of the pillar-shaped semiconductor layers 40 is 1200 nm, the proportion of the cross-sectional area of ​​the pillar-shaped semiconductor layers 40 to the area of ​​the unit region is 8%.

[0058] FIG. 7 shows the results of SIMS analysis, where (a) is a schematic diagram showing positions in the n-type nanowire layer 41, and (b) is a graph showing the SIMS depth profile of Si concentration and the corrected value. Position a shown in (a) of FIG. 7 is the surface of the p-type GaN layer 90 and corresponds to a depth of 0 nm in (b) of FIG. 7. Position b is the tip of the pillar-shaped semiconductor layer 40 and corresponds to a depth of 230 nm in (b) of FIG. 7. Position c corresponds to the position where the concentration gradient changes in (b) of FIG. 7. Position d is the base of the pillar-shaped semiconductor layer 40 (the opening in the mask 30) and corresponds to a depth of 1260 to 1300 nm in (b) of FIG. 7. The horizontal axis of (b) of FIG. 7 indicates the depth from the surface of the p-type GaN layer 90, and the vertical axis indicates the Si concentration in logarithm. The dashed line graph in FIG. 7B indicates the detected value of Si obtained by SIMS analysis, and the solid line graph indicates the Si concentration corrected by the area ratio of the pillar-shaped semiconductor layer 40.

[0059] 7 , in the measurement columnar semiconductor layer 40 formed by the same process as the semiconductor light emitting device 100, the concentration of Si, which is an n-type impurity, gradually decreases from position d to position b. Furthermore, the gradient of the Si concentration is large from position d to position c, whereas the gradient of the Si concentration is small from position c to position b. Here, the region from position d to position c where the gradient of the Si concentration is large corresponds to the first region in the present disclosure, and the region from position c to position b where the gradient is small corresponds to the second region in the present disclosure.

[0060] The reason why the gradient of the Si concentration is large from position d to position c in the first region is unclear. However, it is thought that the Si concentration is large in the SiO 2 film that constitutes the mask 30 in the initial stage of growth of the n-type nanowire layer 41. ２ However, in this embodiment, the second region, which is grown later than the first region, also has a gradient in the Si concentration, with the Si concentration gradually decreasing toward the tip.

[0061] In the example shown in FIG. 7 , the n-type impurity concentration in the second region reaches its maximum value at position c, which is the boundary between the first region and the second region, and its minimum value at position b, which is the tip of the second region. Here, the maximum value of the n-type impurity concentration in the second region is preferably 1.2 times or more, more preferably 2 times or more, of the minimum value. If the maximum value is smaller than this range, the gradient of the Si concentration may be insufficient, and current diffusion in the height direction of the pillar-shaped semiconductor layer 40 may be insufficient. There is no particular limit to the upper limit of the ratio of the maximum value to the minimum value, but for example, the maximum value may be 10 times or less of the minimum value. Furthermore, the n-type impurity concentration in the second region may be such that the maximum value is 3×10 ２０ / cm ３ It is preferable that the maximum value is 5×10 or less. １９ / cm ３ The maximum value in this range is preferable because the crystal quality of the n-type nanowire layer 41 is less likely to deteriorate. The lower limit of the maximum value is not particularly limited, but may be, for example, 1×10 １８ / cm ３ It may be more than that.

[0062] As described above, in the semiconductor light-emitting element 100 and its manufacturing method of this embodiment, the n-type impurity concentration of the n-type nanowire layer 41 is higher on the growth substrate 10 side than on the tip side, which increases the electrical conductivity of the n-type nanowire layer 41 on the growth substrate 10 side and makes it possible to uniformize the current density injected into the active layer 42 formed on the side of the n-type nanowire layer 41.

[0063] Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS. 8 to 10D. Description of content that overlaps with the first embodiment will be omitted. FIG. 8 is a schematic diagram showing a semiconductor light emitting device 100 according to this embodiment. This embodiment differs from the first embodiment in that the pillar-shaped semiconductor layer 40 does not include a p-type semiconductor layer 43 and a tunnel junction layer 44, and the pillar-shaped semiconductor layer 40 is buried with a p-type semiconductor layer 43 instead of a buried semiconductor layer 50.

[0064] 8, the semiconductor light emitting element 100 includes a growth substrate 10, an underlayer 20, a mask 30, an n-type nanowire layer 41, an active layer 42, a p-type semiconductor layer 43, a protective film 60, an anode electrode 70, and a cathode electrode 80. The n-type nanowire layer 41 and the active layer 42 are selectively grown in a direction perpendicular to the growth substrate 10 to form a columnar shape, which constitutes the columnar semiconductor layer 40 of the present invention.

[0065] In this embodiment, the p-type semiconductor layer 43 functions as a buried layer, and the anode electrode 70 is formed on the surface of the p-type semiconductor layer 43. Although Fig. 8 shows an example in which the p-type semiconductor layer 43 is configured as a single layer, it may be configured as a plurality of semiconductor layers with different materials, compositions, and impurity concentrations. As an example, the p-type impurity concentration may be increased on the surface on which the anode electrode 70 is formed, and a p-type contact layer may be added.

[0066] 9 is a diagram schematically illustrating the structure and impurity concentration of the pillar-shaped semiconductor layer 40 according to this embodiment. The gradation applied to the n-type nanowire layer 41 and the p-type semiconductor layer 43 in the figure visually represents the gradient of the impurity concentration in each layer. As shown in FIG. 9 , in the n-type nanowire layer 41 according to this embodiment, the n-type impurity concentration is higher on the growth substrate 10 side than on the tip side, and gradually decreases from the growth substrate 10 side toward the tip side.

[0067] 10A to 10D are schematic diagrams showing a method for manufacturing the semiconductor light-emitting element 100 according to this embodiment, in which FIG. 10A shows a mask formation process, FIG. 10B shows a nanowire growth process and an active layer growth process, FIG. 10C shows a p-type layer growth process, and FIG. 10D shows an electrode formation process.

[0068] 10A, a buffer layer made of GaN and an underlayer 20 made of GaN and AlGaN are grown by MOCVD on a growth substrate 10. Next, a mask 30 is deposited on the underlayer 20, and a plurality of openings 31 are formed therein by nanoimprinting lithography or the like.

[0069] 10B, an n-type nanowire layer 41 made of GaN is grown by selective growth using the MOCVD method on the base layer 20 exposed from the opening 31. In an active layer growth step, an active layer 42 is grown by the MOCVD method on the side and top surfaces of the n-type nanowire layer 41. This forms a columnar semiconductor layer 40 composed of the n-type nanowire layer 41 and the active layer 42.

[0070] 10C, the outer periphery and upper surface of the pillar-shaped semiconductor layer 40 are filled with a p-type semiconductor layer 43. Next, in the electrode formation step shown in FIG. 10D, the p-type semiconductor layer 43 and the pillar-shaped semiconductor layer 40 are removed down to the mask 30 to expose the upper surface of the base layer 20. Annealing is then performed to activate the p-type semiconductor layer 43 and the tunnel junction layer 44. Finally, an anode electrode 70 is formed on the p-type semiconductor layer 43, and a cathode electrode 80 is formed on the surface of the base layer 20.

[0071] In the semiconductor light-emitting element 100 and its manufacturing method of this embodiment, the n-type impurity concentration of the n-type nanowire layer 41 is higher on the growth substrate 10 side than on the tip side, which increases the electrical conductivity of the n-type nanowire layer 41 on the growth substrate 10 side and makes it possible to uniformize the current density injected into the active layer 42 formed on the side of the n-type nanowire layer 41.

[0072] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention.

[0073] This application is based on Japanese Patent Application No. 2024-3647, filed on January 14, 2024, the contents of which are incorporated herein by reference.

Claims

1. A semiconductor light-emitting device comprising a growth substrate, a mask formed on the growth substrate, and a columnar semiconductor layer grown from an opening provided in the mask, wherein the columnar semiconductor layer has an n-type nanowire layer formed at the center, an active layer formed on the outer periphery of the n-type nanowire layer, and a p-type semiconductor layer formed on the outer periphery of the active layer, and the n-type impurity concentration of the n-type nanowire layer is higher on the growth substrate side than on the tip side.

2. The semiconductor light-emitting device according to claim 1, wherein the n-type impurity concentration of the n-type nanowire layer gradually decreases from the growth substrate side toward the tip side.

3. The semiconductor light-emitting device according to claim 2, wherein the n-type nanowire layer includes a first region on the growth substrate side and a second region on the tip side, and the gradient of the n-type impurity concentration is such that the first region is larger than the second region.

4. The semiconductor light-emitting device according to claim 3, wherein the maximum value of the n-type impurity concentration in the second region is 1.2 times or more the minimum value.

5. The semiconductor light-emitting device according to claim 3, wherein the n-type impurity concentration in the second region has a maximum value of 3×10 ２０ / cm ３ or less.

6. The semiconductor light-emitting device according to claim 1, wherein the p-type impurity concentration of the p-type semiconductor layer is higher around the tip side than around the growth substrate side.

7. A method for manufacturing a semiconductor light-emitting device, comprising a mask forming step of forming a mask having an opening on a growth substrate, and a growth step of forming a columnar semiconductor layer in the opening using selective growth, wherein the growth step includes a nanowire growth step of forming an n-type nanowire layer, an active layer growth step of forming an active layer outside the n-type nanowire layer, and a p-type layer growth step of forming a p-type semiconductor layer outside the active layer, and in the nanowire growth step, the n-type impurity concentration is increased on the growth substrate side than on the tip side.

8. The method for manufacturing a semiconductor light-emitting device according to claim 7, wherein in the nanowire growth step, the supply amount of the n-type impurity is decreased on the tip side than on the growth substrate side.

9. A method for manufacturing a semiconductor light-emitting device according to claim 7, wherein in the nanowire growth step, the growth temperature is decreased on the tip side rather than on the growth substrate side.

Images