Low noise amplifier with improved linearity

Abstract

An amplifier (28, 40, 40a, 40b) includes a first transistor (Q 3a ), a first non-linear semiconductor (Q 4a,1 , D 4a,1 ) and a second non-linear semiconductor (Q 4a,2 , D 4a,2 ), where the first non-linear semiconductor (Q 4a, 1 , D 4a,1 ) and the second non-linear semiconductor (Q 4a,2 , D 4a,2 ) are connected to the first transistor (Q 3a ), and the first non-linear semiconductor (Q 4a,1 , D 4a,1 ) is connected in parallel to the second non-linear semiconductor (Q 4a,2 , D 4a,2 ). The amplifier also includes a first resistance (RIA) in series with the first non-linear semiconductor (Q 4a,1 , D 4a,1 ) and a second resistance (R2A) in series with the second non linear semiconductor (Q 4a,2 , D 4a,2 ) where a ratio of the first resistance (RIA) and the second resistance (R2A) determines a range of linearity of the amplifier.

Description

65REL-509920-WO-2 (INT1015PCT) LOW NOISE AMPLIFIER WITH IMPROVED LINEARITY CROSS REFERENCE TO RELATED APPLICATIONS This application claims the benefit of an earlier filing date from U.S. Provisional Application Serial No.63 / 619,448 filed January 10, 2024. BACKGROUND

[0001] In the resource recovery and fluid sequestration industries, understanding the characteristics of geologic formations and fluids located therein is important. Evaluation of formations and / or subterranean regions relies on accurate petrophysical interpretation derived from a diverse set of logging technologies. Such technologies include electromagnetic measurement systems, such as resistivity and nuclear magnetic resonance (NMR) systems, and data communication systems, which can be used in applications such as wireline logging and logging-while-drilling (LWD). Tools such as NMR and resistivity tools include separate receiving and transmitting antennas, or transceiver antennas capable of both transmission of measurement signal and detection of signals from a sensitive volume. SUMMARY

[0002] An embodiment of an amplifier includes a first transistor, a first non-linear semiconductor and a second non-linear semiconductor. The first non-linear semiconductor and the second non-linear semiconductor are connected to the first transistor, and the first non-linear semiconductor is connected in parallel to the second non-linear semiconductor. The amplifier also includes a first resistance in series with the first non-linear semiconductor, and a second resistance in series with the second non-linear semiconductor. A ratio of the first resistance and the second resistance determines a range of linearity of the amplifier.

[0003] An embodiment of a method of amplifying a signal includes inputting an input voltage to an amplifier that includes a first transistor, a first non-linear semiconductor and a second non-linear semiconductor, where the first non-linear semiconductor and the second non-linear semiconductor are connected to the first transistor, and the first non-linear semiconductor is connected in parallel to the second non-linear semiconductor. A first resistance is connected in series with the first non-linear semiconductor, and a second resistance is connected in series with the second non-linear semiconductor, where a ratio of the first resistance and the second resistance determines a range of linearity of the amplifier. The method also includes amplifying the input voltage at an input stage to generate an65REL-509920-WO-2 (INT1015PCT) amplified input voltage, providing the amplified input voltage to the first transistor, and outputting an output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The following descriptions should not be considered limiting in any way. With reference to the accompanying drawings, like elements are numbered alike:

[0005] Figure 1 depicts an embodiment of a downhole system that includes an electromagnetic apparatus, device or tool configured to perform measurements of a subterranean region and / or borehole, and / or configured to communicate data;

[0006] Figure 2 depicts an embodiment of an open-loop amplifier having semi- conductor devices configured to increase a linearity of the amplifier;

[0007] Figure 3A depicts an embodiment of a portion of a stage of an open-loop amplifier, the portion including a split transistor configuration having a controllable operating point;

[0008] Figure 3B depicts an embodiment of a portion of a stage of an open-loop amplifier, the portion including a split diode configuration having a controllable operating point;

[0009] Figure 4 depicts examples of a characteristic curve of an open-loop amplifier of Figure 2; and

[0010] Figure 5 is a flow diagram depicting an embodiment of a method of amplifying an input signal. DETAILED DESCRIPTION

[0011] A detailed description of one or more embodiments of the disclosed apparatus and method are presented herein by way of exemplification and not limitation with reference to the Figures.

[0012] Apparatuses, devices and methods related to amplification are described herein. An embodiment of a low-noise amplifier (LNA) is configured to amplify signals provided from a signal source, such as an antenna. Embodiments may be applicable to systems and devices used to measure properties of a subterranean region using electromagnetic measurements. For example, an amplifier as described herein may be incorporated into a measurement apparatus, such as a resistivity tool, drilling sub and / or logging-while-drilling (LWD) component, which includes one or more antennas for65REL-509920-WO-2 (INT1015PCT) transmitting and / or receiving measurement signals. Embodiments are not so limited, and are applicable to other low noise applications.

[0013] An embodiment of an amplifier is a multi-stage circuit formed as an integrated circuit (IC), which includes stages for impedance matching and amplification. The amplifier is an open-loop amplifier circuit. At least one stage of the amplifier includes a set (i.e., one or more) of parallel non-linear semiconductor devices , such as p / n or n / p junctions (e.g., transistors or diodes), that are shifted relative to each other in their characteristic curve, which results in increased linearity of the gain or amplification of the amplifier as compared to existing systems.

[0014] In an embodiment, at least one stage of the amplifier includes a split non- linear semiconductor device configuration that includes a pair of devices, such as a pair of transistors. Each transistor (or other non-linear semiconductor device) is connected to a resistor. Resistance values of the resistors are selected to achieve a resistance ratio that acts to control or adjust an operating point of each of the pair of non-linear semiconductor devices, in order to increase linearity of the amplifier or optimize the linearity of the amplifier. In an embodiment, the resistance is included in the non-linear semiconductor, such as the resistance of a p-n junction in a transistor or in a diode.

[0015] Embodiments described herein present a number of advantages. For example, the embodiments improve linearity of amplifiers, which improves the input voltage range that is linearly amplified and other properties of amplifiers. In this way, signals are amplified and reproduced more accurately, improving the quality of measurement results and communications, and reducing the need for further processing, such as trimming or correcting output signals.

[0016] Figure 1 illustrates an embodiment of a downhole system 10 including a borehole string 12 disposed in a borehole 13 that penetrates a subterranean region. The subterranean region may include a formation 14. The downhole system 10 is configured to perform one or more downhole operations, such as drilling, measurement, data acquisition, and / or analysis system.

[0017] In an embodiment, the downhole system 10 includes downhole devices or systems for in-situ measurement of characteristics of the formation 14. For example, the system 10 includes a measurement apparatus such as a measurement tool 16 configured to perform electromagnetic measurements (e.g., resistivity or nuclear magnetic resonance (NMR)). The measurement tool 16, additionally or alternatively, includes components for65REL-509920-WO-2 (INT1015PCT) acoustic measurements. In this embodiment, the measurement tool 16 is part of a logging- while-drilling (LWD) sub or assembly, but is not so limited.

[0018] The measurement tool 16 includes a tool body 18, such as a mandrel, pipe segment or other elongated structure. The tool body 18 may be part of a rotating component, such as a LWD or bottom hole assembly connected to a drill bit 20. The bottom hole assembly can include a mud motor 25 and / or a steering unit 27. The tool body 18 has a fluid conduit or inner bore (not shown) for allowing flow of drilling mud, formation fluids and other fluids 29.

[0019] In an example, the measurement tool 16 includes at least one transmitting antenna 22 for emitting electromagnetic signals into the formation 14, and at least one receiving antenna 24 for detecting signals resulting from a response of the formation 14 to the electromagnetic signals.

[0020] Detected signals are transmitted to an electronics module 26, where detected signals from the receiving antenna 24 are amplified and processed. For example, the electronics module 26 houses circuity that includes an amplifier 28 for amplification of detected signals. Amplified signals may be provided to additional electronics and a processing device for analysis.

[0021] The processing device may be a downhole processor 30 and / or a surface processing unit 32. The surface processing unit 32 is part of, or attached to surface equipment 34 (e.g., a drilling rig). The processing device may also be a remote processor (e.g., in a data center or workstation).

[0022] The borehole string 12 may be equipped with transmission equipment to communicate with surface components, such as the surface processing unit 32. Such transmission equipment may take any desired form, and different transmission media and methods may be used, such as wired, fiber optic, and / or wireless transmission methods (e.g., mud pulse telemetry, electromagnetic telemetry, etc.).

[0023] In an embodiment, the amplifier 28 is a low noise amplifier (LNA) for detecting a frequency range selected based on parameters of the resistivity measurements and / or other measurements (e.g., acoustic measurements). The LNA is configured for amplifying detected signals having a frequency range below a certain threshold (e.g., about 2 MHz).

[0024] The noise behavior of the amplifier 28 is important for accurately reproducing a received signal. The noise behavior of an amplifier is specified by the noise figure (NF) of the amplifier, which is related to the impedance of the source. For example, for resistivity65REL-509920-WO-2 (INT1015PCT) and other measurements having low signal-to-noise levels, the amplifier 28 is required to have a low noise figure, such as a noise figure of 2 decibels (dB). The amplifier equivalent input voltage noise should be smaller than that of the real part of the source impedance, such as the impedance of the receiving antenna 24.

[0025] The amplifier 28 in this example is designed to have an input voltage noise of less than 200 fV / sqrt(Hz) and a noise figure of 2 dB or less for a source impedance of 10 Ohms.

[0026] In addition to the noise performance, the impedance matching of the amplifier 28 is important to pick up the maximum power at the antenna. Open-loop gain amplifier topologies are generally used for matching at an antenna while maintaining the noise figure less than 3 dB. As the detected signal range can be large, open-loop amplifiers typically do not behave linearly.

[0027] Embodiments of the amplifier described herein are able to maintain noise at desired levels, while still providing sufficient gain linearity. Thus, the embodiments provide for effective balancing of noise behavior and linearity of the amplifier.

[0028] Figure 2 depicts an embodiment of an amplification circuit (i.e., amplifier) 40. The amplification circuit may be part of a measurement device such as the measurement tool 16 of Figure 1, or any other suitable device or system that utilizes antenna for transmission and reception of electromagnetic signals.

[0029] The amplifier 40 is formed as an integrated circuit that includes various non- linear semiconductor devices, such as transistors and / or diodes. Examples of transistors include bipolar junction transistors (BJTs), field effect transistors (FET) and various types of diodes.

[0030] The amplifier 40 is described as having BJTs as the non-linear semiconductor devices for illustration purposes, but are not so limited, as the embodiments may include any suitable type of semiconductor device. Examples of such semiconductor device include p / n junction diodes, and field-effect transistors such as metal-oxide field-effect transistors (MOSFET) and junction field-effect transistors (JFET).

[0031] In an embodiment, the amplifier 40 is a fully differential open-loop amplification circuit (differential amplifier). The amplifier 40 has symmetrical sides, including a first side 40a (negative side) that receives negative components of an input radiofrequency (RF) signal (voltage Vin) via an input Inn, and a second side 40b (positive side) that receives positive components of the input radiofrequency (RF) signal (voltage Vip)65REL-509920-WO-2 (INT1015PCT) via input Inp. The input radiofrequency signal provided by the voltages Vinand Vipinclude a pay load signal and an input noise signal (such as the noise of an antenna).

[0032] The amplifier 40 has active noise cancellation, which isolates and inverts noise components. The noise components are typically dominated by noise originating from a signal source (e.g., an antenna), but may include noise introduced by internal components of the amplifier 40 (amplifier noise signal). The amplifier 40 isolates the noise components and feeds the noise components introduced by the internal components of the amplifier to an output stage with an inverted phase. This allows for cancellation of the amplifier noise at the output.

[0033] Each side defines a number of stages, where each stage includes one or more transistors Q. The transistors in the stages of the amplifier 40 are grounded and connected to positive power supply voltages (VDD). VBIAS transistors are used to bias the transistors to control operation regions (active region operation).

[0034] In an embodiment, each side includes four sequentially coupled stages. The stages may include a first stage (42a, 42b) (“input stage”) for receiving an input signal and matching the input signal to a source impedance. Each side also includes a linearity adjustment stage (44a, 44b) (gain linearity), a noise phase inversion stage (45a, 45b) and a noise-cancelling or noise reduction stage, which also serves as output stage (46a, 46b).

[0035] The amplifier 40 receives an input signal Vipand Vin(e.g., from a receiver antenna in a downhole measurement device, such as a resistivity, NMR or acoustic device). The first side 40a of the amplifier 40 includes an input stage 42a that receives the input signal Vipvia input Inp. The input signal Vipis pre-amplified in the input stage 42a, which includes a pair of transistors Q1aand Q2aand a resistor RFain feedback configuration. The transistors Q1aand Q2aform a common emitter amplifier that serves to match the impedance of the first side of the amplifier 40a (and amplifier 40, respectively) to the impedance of the input source. The operating points of the transistors Q1aand Q2aare defined by resistor RBIASand a voltage VBIAS2on a base pin PBIAS2of a transistor QBIAS2. In an embodiment, the transistors Q1aand Q2aform a common collector amplifier that serves to match the impedance of the first side of the amplifier 40a (and amplifier 40, respectively) to the impedance of the input source.

[0036] The input signal Vip is also provided to a noise phase inversion stage 45a. The noise phase inversion stage 45a includes a transistor Q5awith a resistive load RBa. In this stage, the input signal Vip including the amplifier noise signal is fed to the transistor Q5a, which is in a common emitter configuration (alternatively in a common collector65REL-509920-WO-2 (INT1015PCT) configuration). This configuration rotates the amplifier noise signal phase by 180 degrees while keeping the phase of the pay load signal, resulting in a phase inverted amplifier noise signal on voltage V45aat the output of the stage 45a. The phase inverted amplifier noise signal is also referred to herein as phase inverted noise on voltage V45a. The operating point of the transistor Q5ais defined by a voltage VBIAS3on a base pin PBIAS3of a transistor QBIAS3. The voltage V45a is measured against ground.

[0037] The pre-amplified signal V42a(also referred to as an amplified input voltage) from the input stage 42a (including amplifier noise signal components) is fed through a linearity adjustment stage 44a to an output stage 46a. The signal V42ais measured against ground. The phase inverted amplifier noise on the signal V45a the stage 45a is also fedto the output stage 46a. The output stage 46a includes a of transistors Q6aand Q7a. In the output stage 46a, the amplifier noise is canceled out by adding the phase inverted amplifier noise signal on the voltage V45aprovided by the stage 45a to the signal (voltage V44a) that was pre-amplified in 42a and that passed through the linearityadjustment stage 44a. The voltage V44acarries no phase inverted amplifier noise. The voltage V44a is measured against ground. By combining the voltages V44a and V45a, amplifier noise is canceled out in the output stage (noise cancelation stage) providing an output signal Vonvia an output Outn with reduced or canceled amplifier noise when measured against voltage Vop on output Outpon the second side 40b of differential amplifier 40. Through the stage 44a, the amplifier noise reduced signal at the output Outnis further provided with linear amplification in an enlarged linearity range (adjusted linearity). The factor of the cancellation can be adjusted by adjusting the amplification of the transistor Q6aand the transistor Q7a. The operating point of the transistor Q6ais defined by the resistor RBaand the voltage VBIAS3on the base pin PBIAS3of the transistor QBIAS3. The operating point of the transistor Q7ais defined by the voltage VBIAS1on the base pin PBIAS1of the transistor QBIAS1. The voltage range in which the amplifier 40 amplifies the input signal linearly may be adjusted in the linearity adjustment stage 44a using two weighted p / n junctions (the transistors Q4a,1and Q4a,2). For example, around 50% of the amplification of the amplifier 44a takes place in the stage 42a, and another around 50% of the amplification takes place in the stage 45a. The stages 44a and 46a do not significantly contribute to the gain of the amplifier 40a. An output voltage (Vop, Von) measured between Outp and Outn (differential signal of differential amplifier) provides an amplified voltage based in input voltage (Vin, Vip) with canceled amplifier noise signal and increased linearity voltage range. The amplifier 40 can be used in any frequency range. It65REL-509920-WO-2 (INT1015PCT) may be used in combination with an RF antenna in a frequency range between 1 kHz and 2 MHz.

[0038] As the amplifier 40 does not employ closed loop feedback, the linearity of the amplifier is an important consideration. Noise components, such as noise introduced at a signal source (e.g., antenna) or by internal components of the amplifier as well as distortions introduced during amplification, should be removed or reduced as much as possible.

[0039] To facilitate and improve linearity, the linearity adjustment stage 44a has a set of transistors that include a transistor Q3a and a pair of transistors Q4a,1 and Q4a,2. The transistor Q3ais configured to receive the pre-amplified signal V42avia a base pin P3aof the transistor Q3a. The pair of transistors Q4a,1 and Q4a,2 are connected in series to the transistorQ3a, and in parallel to each other. The pair of transistors Q4a,2are referred to as “split transistors.” The split transistors act as a parallel diode combination. The operating point of the transistor Q3ais defined by a voltage VBIAS1on a base pin PBIAS1of a transistor QBIAS1. The parallel configuration of the split transistors is achieved by connecting the base pins P4a,1and P4a,2of the split transistors Q4a,1and Q4a,2, the collectors C4a,1and C4a,2of the split transistors Q4a,1 and Q4a,2 and the collector C3a of Q3a all together. That is, the base pin P4a,1of the transistor Q4a,1, the base pin P4a,2of the transistor Q4a,2, the collector C4a,1of the transistor Q4a,1, the collector C4a,2 of the transistor Q4a,2, and the collector C3a (alternatively the emitter E3a) of theQ3aare electrically the same point or are at the same electrical potential. In an embodiment, instead of the collectors, the emitters E4a,1and E4a,2of Q4a,1and Q4a,2are connected with the base pins P4a,1and P4a,2of Q4a,1and Q4a,2. Transistors Q4a,1and Q4a,2may be matched transistors.

[0040] Inclusion of the split transistors Q4a,1and Q4a,2allows for applying a shift to the operating point of the diode combination (weighting the p / n junctions). The operating point of the diode combination is based on the operating points of the split transistors Q4a,1and Q4a,2 which are defined by split resistors R1a and R2a.

[0041] In an embodiment, the diode combination is shifted by controlling or selecting a resistance connected to each of the split transistors. For example, an emitter E4a,1 of the transistor Q4a,1is connected to a resistor R1awith a resistance R1A, and an emitter E4a,2of the transistor Q4a,2 is connected to a resistor R2a with a resistance R2A.

[0042] In an alternativethe resistors R1aand R2aare connected to a collector C4a,1 and a collector C4a,2 of Q4a,1 and Q4a,2, respectively. The resistor R1a is connected at a first end to one of the emitter E4a,1and the collector C4a,1of the transistor Q4a,1, and connected at a second end to ground of the amplifier 40. The resistor R2a is connected at65REL-509920-WO-2 (INT1015PCT) a first end to one of the emitter E4a,2and the collector C4a,2of the transistor Q4a,2, and is connected at a second end to ground of the amplifier 40. The second ends of the resistors R1a and R2amay be connected directly to ground, or may be connected to ground indirectly through another electronic component.

[0043] The split resistors R1aand R2amay have any suitable resistance properties or values. In an embodiment, the split resistors are low impedance conduction path resistors. For example, the resistors have resistances in the range of less than 10 ohms.

[0044] In an alternative embodiment, the split transistors Q4a,1 and Q4a,2 or the non- linear semiconductor device are configured or built differently (Application-Specific Integrated Circuit (ASIC)) to contribute to the determination of the different operating points by geometric differences, such as channel length, width and depth of the p / n junctions of the split transistors. For example, the properties of the p / n junctions of the non-linear semiconductors, such as the diode combination of split transistors Q4a,1and Q4a,2, can be geometrically dimensioned to define a different characteristic curve.

[0045] FIG.3 schematically depicts the connections of the split transistors in the linearity adjustment stage 44a. As shown, the split transistors Q4a,1 and Q4a,2 are connected in series to the transistor Q3a, either to its collector C3aor its emitter E3a. The split transistors function similarly to a single transistor, but with the added feature of having a variable or controllable operating point that can be adjusted to increase the linearity of the amplifier 40. The variable or controllable operating point is achieved by the split resistor configuration in combination with the split transistor configuration. The split transistors lead to a split of current I44a(FIG.2) flowing from collector C3athrough the split transistors Q4a,1and Q4a,2and through the resistors R1a and R2a. The current I44ais split into currents I44a,1and I44a,2(I44a =I44a,1+ I44a,2). A resistance ratio R2A / R1A of the resistors R1aand R2adetermines how the currents I44a1and I44a2are split. At the same time, the resistors R1aand R2adetermine the operating points of the split transistors Q4a,1and Q4a,2. The operating points determine at which point on the characteristic curve the split transistors operate and what distortions are associated with the operation. Proper selection of the resistance ratio R2A / R1A leads to a selection of the operating points that cause the distortion to be canceled out. Consequently, the gain linearity range of the amplification is increased.

[0046] In an embodiment, the operating point of the split transistors Q4a,1 and Q4a,2 is controlled or adjusted by selecting a corresponding ratio of the resistance connected to one of the split transistors to the resistance connected of the other split transistor. For example, the transistor Q4a,1is connected to a resistor R1a, which has a resistance R1A, and the transistor65REL-509920-WO-2 (INT1015PCT) Q4a,2is connected to a resistor R2a, which has a resistance R2A. The resistance ratio is a ratio of R2A to R1A, or R2A / R1A.

[0047] The resistance ratio is selected to shift the operating point of the split transistors Q4a,1 and Q4a,2, configuring the split transistor or the diode combination, such that linearity of the amplifier 40 is improved. For example, a resistance ratio R2A / R1A in a range of about 5-15 has been found to significantly improve the linearity of the amplifier 40. The resistance ratio R2A / R1A can be between 1 to 50, or between 2 to 30, or between 3 to 20, or between 5 to 15. The resistors R1a and R2a have fixed resistances that are dimensioned during the design phase of the amplifier. They are dimensioned to fit the voltage range of the expected input voltage Vip, such as the voltage range of an antenna signal. In an embodiment the split resistors R1aand R2aare variable and are controllable by a processor or controller during the operation of the amplifier 40 to react to a changes of the input voltage range. The size of the resistors R1aand R2amay be of minor interest. The ratio of the resistances is relevant for achieving the gain linearity increase of the amplifier and not the absolute value of the single resistances R1A and R2A. However, the size of the single resistors are R1aand R2acombined with the electronic needs and constraints defined by the other electronics components of the amplifier 40 (40a, 40b).

[0048] FIG.3B depicts and alternative configuration of the linearity adjustment stage 44a. Instead of split transistors split diodes are used. In the same manner as the split transistors, an operating point of diode D4a,1and diode D4a,2is shifted by the resistances R2 and R1A of resistors R1aand R2a, such that the gain linearity of the amplifier is improved. The electrical current through the split diodes is weighted according to the ratio of the resistances R1A and R2A, leading to an increase of the range in which the amplifier 40 linearly amplifies the input signal Vin. The linearity adjustment stage 44b is configured accordingly and includes diodes D4b,1and diode D4b,2, and resistors R1band R2bwith resistances R1B and R2B. In an alternative embodiment, instead of using transistors or diodes in the linearity adjustment stage for the split non-linear semiconductor, a MOS-FET or a JFET transistor can be used.

[0049] As noted above, the amplifier 40 may be a symmetrical differential amplifier, in which the side 40b with an input voltage Vinhas a similar configuration to that of side 40a with an input voltage Vip . Vin and Vip are the negative and positive terminals of the input voltage.

[0050] The second side 40b of the amplifier 40 includes an input stage 42b that receives the input signal Vinvia the input Inn. The input signal Vinis pre-amplified in the65REL-509920-WO-2 (INT1015PCT) input stage 42b, which includes a pair of transistors Q1band Q2band a resistor RFbin feedback configuration. The transistors Q1b and Q2b form a common emitter amplifier that serves to match the impedance of the second side of the amplifier 40b (and amplifier 40, respectively) to the impedance of the input source. In an embodiment, the transistors Q1b and Q2b form a common collector amplifier and serve to match the impedance of the second side of the amplifier 40b (and amplifier 40, respectively) to the impedance of the input source. The operating points of the transistors Q1band Q2bin the input stage 42b are defined by the resistor RBIAS and the voltage VBIAS2 on the base pin PBIAS2 of the transistor QBIAS2.

[0051] A linearity adjustment stage 44b includes a matched set of transistors Q4b,1and Q4b,2 (split transistors), and a transistor Q3b. The transistor Q3b is configured to receive a pre- amplified signal V42b(also referred to as an amplified input voltage) via a base pin P3bof the transistor Q3b. The split transistors Q4b,1 and Q4b,2 form a diode combination. The split transistors Q4b,1and Q4b,2are connected in series to the transistor Q3b, and parallel to each other. The split transistors act as a parallel diode combination. The operating points of the split transistors Q4b,1and Q4b,2(operating point of the diode combination) is shifted by controlling or selecting resistances of connected resistors R1b and R2b to define a desired resistance ratio R2B / R1B, which may be the same as the resistance ratio R2A / R1A of the resistors R1a and R2a in the first side 40a. By adjusting the operating points of the split transistors Q4b,1and Q4b,2by choosing a specific ratio of the resistors R1band R2b, the range of linear amplification of the amplifier’s second side 40b is maximized. The resistors R1band R2bare connected at a first end to one of the emitter E4b,1and the collector C4b,1of the transistor Q4b,1, and one of the emitter E4b,2and collector C4b,2of the transistor Q4b,2, respectively, and at a second end to ground of the second side 40b (and amplifier 40). The second ends of the resistors R1band R2bmay be connected directly to ground, or may be connected to ground indirectly through another electronic component. The operating point of Q3bis defined by the voltage VBIAS1on the base pin PBIAS1of the transistor QBIAS1.

[0052] The second side 40b includes a noise phase inversion stage 45b having a transistor Q5b, with a resistive load RBb, in a common emitter configuration (alternatively in a common collector configuration), and an output stage 46b. the noise phase inversion stage 45b inverts the phase of the amplifier noise signal taken from the input Innand feeds the resulting phase inverted noise signal V45b (also referred to herein as phase inverted noise or voltage V45b) into the output stage 46b. The output stage 46b includes a matched pair of transistors Q6b and Q7b. In the output stage 46b, the amplifier noise signal is canceled out by adding the phase inverted noise signal V45bprovided by the transistor Q5bto the signal65REL-509920-WO-2 (INT1015PCT) (voltage V44b) that was pre-amplified in input stage 42b and that passed through the linearity adjustment stage 44b, thereby cancelling out the amplifier noise signal and providing an output signal Vopvia an output Outpwith reduced noise. The factor of the cancellation can be adjusted via the amplification of transistors Q6b and transistor Q7b. The operating point of the transistor Q5bis defined by the voltage VBIAS3on the base pin PBIAS3of the transistor QBIAS3. The operating point of the transistor Q6b is defined by the resistor RBb and the voltage VBIAS3 on the base pin PBIAS3of the transistor QBIAS3. The operating of the transistor Q7bisdefined by the voltage VBIAS1 on the pin PBIAS1 of the QBIAS1. Through the stage 44b, the noise reduced signal is provided with linear amplification in an increased linearity range (adjusted linearity). The voltage range in which the amplifier amplifies the input signal linearly can be adjusted in the linearity adjustment stage 44b by using two weighted p / n junctions (the transistors Q4b,1 and Q4b,2). The increase of the linearity range achieved by the implementation of split transistors is significant, such as an increase of one decade. In an example, around 50% of the amplification of amplifier 44b takes place in stage 42b and another around 50% of the amplification takes place in stage 45b. Stages 44b and 46b do not significantly contribute to the gain of the amplifier 40b.

[0053] Figure 4 is a graph 50 that demonstrates the effect of changes in the resistance ratio R2 / R1 (FG.3A, 3B). In this example, characteristic curves of the amplifier 40 are shown for different resistance ratios. Also in this example, both linearity adjustment stages 44a and 44b include the same resistance ratios (R1a= R1b= R1 and R2a= R2b= R2). A base curve 52, which corresponds to a conventional transistor arrangement without the linearity range adjustment (i.e., both R1 and R2 are zero), is shown for comparison purposes.

[0054] Curves 54, 56, 60 and 58 show the linearity range for different R1 / R2 ratios. In this example, the resistance R2 is one Ohm (Ω). The curve 54 corresponds to a resistance ratio of one (R1 / R2 = 1). A curve 56 corresponds to a resistance ratio of 10 (R1 = 10 Ω, R2 = 1 Ω), the curve 58 corresponds to a resistance ratio of 18 (R1 = 18 Ω, R2 = 1 Ω), and the curve 60 corresponds to a resistance ratio of 30 (R1 = 30 Ω, R2 = 1 Ω). It is noted that the improvements resulting from selection of the resistance ratio are irrespective of specific resistance values of individual resistors.

[0055] As shown by the arrow in the graph, increasing the resistance ratio (R1 / R2) does not affect the compression point 62, but increases the linearity of the characteristic curve of the amplifier 40. This results in a significant improvement in linear behavior of the whole amplifier 40. Curve 56 corresponding to a resistance ratio of 10 provides the largest range of linearity. The whole displayed voltage range from 1 mV to 100 mV shows almost the same65REL-509920-WO-2 (INT1015PCT) gain or amplification (Av). In comparison, the base curve 52 (corresponding to the conventional amplifier configuration without the adjusted operating points of the split transistors) shows significant non-linearity from 10 m V and above. Accordingly, the configuration of the linearity adjustment stages 44a and 44b results in a significant improvement of the linearity of the amplification of amplifier 40 (increase of one decade in voltage range). Linearity of the amplifier is determined by the design of stages 44a and 44b (split non-linear semiconductors). Stages 44a 44b do not contribute to the amplification or gain of the amplifier 40. Consequently, the amplification Av is around 1.0. The negative sign originates from a phase shift, which is not of relevance for the functionality of the linearity adjustment stages 44a and 44b, and is not explained here. At least the non-linear semiconductor configuration (split transistor configuration, Q4a,1and Q4a,2and Q4b,1, Q4b,2with connected resistors R1a, R2a and R1b, R2b) in the linearity adjustment stages 44a and 44b is new and first disclosed in this application.

[0056] Embodiments are applicable to any of various low noise applications (e.g., low noise applications in a frequency range up to about 20 MHz). Low noise applications may include applications where a source impedance is less than about 10 Ohms.

[0057] Figure 5 shows aspects of an embodiment of a method 70 of amplifying an input signal. Aspects of the method 70 are discussed in conjunction with an example of a downhole operation using the downhole system 10 of Figure 1. In this example, the amplifier is located in a downhole device and operates while the downhole device in in a borehole and the input signal is generated by an electrical antenna. However, embodiments are not so limited, as the method 70 can be used in various systems and contexts where amplification is desired.

[0058] The method includes a plurality of steps represented by blocks 71-74. All of the steps may be performed in the order described, but the method is not so limited. For example, one or more of the steps may be performed in a different order, or the method may include fewer than all of the steps.

[0059] At block 71, an input signal is received at the amplifier 40. For example, the measurement tool 16 is deployed and electromagnetic measurements are performed by applying electromagnetic signals to a subterranean region via the transmitting antenna 22. For example, resistivity measurements are performed during drilling for estimating formation properties and / or for informing steering direction. Based on the measurements, operational parameters such as steering direction, weight-on-bit may be adjusted, an earth model may be65REL-509920-WO-2 (INT1015PCT) created or updated. Measurement signals are detected at the receiver antenna 24 and provided to the amplifier 28 (which may be configured as the amplifier 40).

[0060] At block 72, the input signal is amplified by operating the amplifier 28 as discussed herein. At least one of the amplifier stages includes a split non-linear semiconductor device as described herein, such as a split transistor configuration (FIG.3A) or a split diode configuration (FIG.3B).

[0061] At block 73, an operating point of the split transistor configuration or split diode configuration is selected or shifted by selection of a resistance ratio R2 / R1. Selection of the resistance ratio may be selected based on, for example, physical specifications of the amplifier (such as noise figure, split transistor characteristic curves), noise characteristics of the antenna, impedance of the antenna (source impedance), signal power, and others. The resistance ratio is selected based on these factors to achieve a desired characteristic curve of the amplifier (linearity).

[0062] It is noted that the steps of block 73 may be performed at different points or time during the method 70. For example, the resistance ratio can be selected by installing or replacing resistors in the amplifier 28 (e.g., prior to deployment of the tool 16). In another example, the resistors are variable resistors whose resistance can be actively controlled by a controller (e.g., the surface processing unit 32 and / or the downhole processor 30). Actively controlling the resistors R1 and R2 can be beneficial to adapt the amplifier and its linearity range to a changed input signal or a changed source impedance. Thus, adjustment of the resistance ratio can be performed at any suitable time (e.g., between measurements).

[0063] At block 74, the amplified signal is further processed as desired, and analyzed. For example, outputs from the amplifier 28 are provided to a processing device for analysis of signals to measure formation properties, such as resistivity. Based on the outputs of the amplifier, operational parameters may be changed, such as a control parameter of the steering unit 27 (FIG.1) (e.g. geosteering). In another example, the output of the amplifier may be used to produce a log of formation properties, such as a resistivity log or an NMR log, displaying resistivity values or NMR values of the formation over the depth of the borehole.

[0064] Set forth below are some embodiments of the foregoing disclosure:

[0065] Embodiment 1: An amplifier (28, 40, 40a, 40b) comprising: a first transistor (Q3a); a first non-linear semiconductor (Q4a,1, D4a,1); a second non-linear semiconductor (Q4a,2, D4a,2), wherein the first non-linear semiconductor (Q4a,1, D4a,1) and the second non- linear semiconductor (Q4a,2, D4a,2) are connected to the first transistor (Q3a), and the first non- linear semiconductor (Q4a,1, D4a,1) is connected in parallel to the second non-linear65REL-509920-WO-2 (INT1015PCT) semiconductor (Q4a,2, D4a,2); a first resistance (R1A) in series with the first non-linear semiconductor (Q4a,1, D4a,1); and a second resistance (R2A) in series with the second non- linear semiconductor (Q4a,2, D4a,2), wherein a ratio of the first resistance (R1A) and the second resistance (R2A) determines a range of linearity of amplifier.

[0066] Embodiment 2: The amplifier as in any prior embodiment, wherein the first non-linear semiconductor (Q4a,1, Q4b,1), and the second non-linear semiconductor (Q4a,2, Q4b,2) are transistors.

[0067] Embodiment 3: The amplifier as in any prior embodiment, wherein the first non-linear semiconductor (D4a,1, D4b,1) and the second non-linear semiconductor (D4a,2, D4b,2) are diodes.

[0068] Embodiment 4: The amplifier as in any prior embodiment, wherein the amplifier is a differential amplifier, the differential amplifier includes a second transistor (Q3b), a third non-linear semiconductor (Q4b,1), a fourth non-linear semiconductor (Q4b,2), a third resistance (R1B) and a fourth resistance (R2B), wherein: the third non-linear semiconductor (Q4b,1) and the fourth non-linear semiconductor are connected to the second transistor (Q3b), the third non-linear semiconductor (Q4b,1) is parallel to the fourth non-linear semiconductor (Q4b,2), the third resistance (R1B) is in series with the third non-linear semiconductor (Q4b,1), and the fourth resistance (R2B) is in series with the fourth non-linear semiconductor (Q4b,2).

[0069] Embodiment 5: The amplifier as in any prior embodiment, further including an input stage (42a) that receives an input voltage (Vip), the input stage configured to amplify the input voltage (Vip) and provides an amplified input voltage (V42a) to the first transistor (Q3a).

[0070] Embodiment 6: The amplifier as in any prior embodiment, wherein the first transistor (Q3a) receives at a base pin (P3a) the amplified input voltage (V42a).

[0071] Embodiment 7: The amplifier as in any prior embodiment, wherein the first non-linear semiconductor (Q4a,1, D4a,1) and the second non-linear semiconductor (Q4a,2, D4a,2) are connected to one of an emitter (E3a) or a collector (C3a) of the first transistor (Q3a).

[0072] Embodiment 8: The amplifier as in any prior embodiment, wherein the first resistance (R1A) and the second resistance (R2A) are connected to ground of the amplifier.

[0073] Embodiment 9: The amplifier as in any prior embodiment, wherein the amplifier (28, 40, 40a, 40b) further includes a noise cancelation stage 46a, the noise cancelation stage configured to receive a voltage (V44a) from the first transistor (Q3a).65REL-509920-WO-2 (INT1015PCT)

[0074] Embodiment 10: The amplifier as in any prior embodiment, wherein the amplifier (28, 40, 40a, 40b) is included in a measurement tool (16) in a borehole (13) and is configured to amplify an antenna signal measured inside the borehole (13).

[0075] Embodiment 11: The amplifier as in any prior embodiment, wherein the ratio of first resistance (R1A) and the second resistance (R2A) is at least 5.

[0076] Embodiment 12: The amplifier as in any prior embodiment, wherein an input impedance of the amplifier is 10 Ohms or less.

[0077] Embodiment 13: The amplifier as in any prior embodiment, wherein the amplifier is an open-loop amplifier.

[0078] Embodiment 14: A method of amplifying a signal, comprising: inputting an input voltage (Vip) to an amplifier (28, 40, 40a, 40b), the amplifier (28, 40, 40a, 40b) including: a first transistor (Q3a); a first non-linear semiconductor (Q4a,1, D4a,1); a second non- linear semiconductor (Q4a,2, D4a,2), wherein the first non-linear semiconductor (Q4a,1, D4a,1) and the second non-linear semiconductor (Q4a,2, D4a,2) are connected to the first transistor (Q3a), and the first non-linear semiconductor (Q4a,1, D4a,1) is connected in parallel to the second non-linear semiconductor (Q4a,2, D4a,2); a first resistance (R1A) in series with the first non-linear semiconductor (Q4a,1, D4a,1); and a second resistance (R2A) in series with the second non-linear semiconductor (Q4a,2, D4a,2), wherein a ratio of the first resistance (R1A) and the second resistance (R2A) determines a range of linearity of the amplifier; amplifying the input voltage (Vip) at an input stage (42a) to generate an amplified input voltage (V42a); providing the amplified input voltage (V42a) to the first transistor (Q3a); and outputting an output signal (Vop).

[0079] Embodiment 15: The method as in any prior embodiment, wherein the first non-linear semiconductor (Q4a,1, Q4b,1), and the second non-linear semiconductor (Q4a,2, Q4b,2) are transistors.

[0080] Embodiment 16: The method as in any prior embodiment, wherein the first non-linear semiconductor (D4a,1, D4b,1) and the second non-linear semiconductor (D4a,2, D4b,2) are diodes.

[0081] Embodiment 17: The method as in any prior embodiment, wherein the first transistor (Q3a) receives at a base pin (P3a) the amplified input voltage (V42a).

[0082] Embodiment 18: The method as in any prior embodiment, wherein the first non-linear semiconductor (Q4a,1, D4a,1) and the second non-linear semiconductor (Q4a,2, D4a,2) are connected to one of an emitter (E3a) or a collector (C3a) of the first transistor (Q3a), and65REL-509920-WO-2 (INT1015PCT) the first resistance (R1A) and the second resistance (R2A) are connected to ground of the amplifier.

[0083] Embodiment 19: The method as in any prior embodiment, further comprising receiving a voltage (V44a) from the first transistor (Q3a) at a noise cancellation stage (46a).

[0084] Embodiment 20: The method as in any prior embodiment, wherein the amplifier is included in a measurement tool (16) in a borehole (13) and is configured to amplify an antenna signal measured inside the borehole (13).

[0085] The use of the terms “a” and “an” and “the” and similar referents in the context of describing the invention (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Further, it should be noted that the terms “first,” “second,” and the like herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The terms “about”, “substantially” and “generally” are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” and / or “substantially” and / or “generally” can include a range of ± 8% of a given value.

[0086] The teachings of the present disclosure may be used in a variety of well operations. These operations may involve using one or more treatment agents to treat a formation, the fluids resident in a formation, a borehole, and / or equipment in the borehole, such as production tubing. The treatment agents may be in the form of liquids, gases, solids, semi-solids, and mixtures thereof. Illustrative treatment agents include, but are not limited to, fracturing fluids, acids, steam, water, brine, anti-corrosion agents, cement, permeability modifiers, drilling muds, emulsifiers, demulsifiers, tracers, flow improvers etc. Illustrative well operations include, but are not limited to, hydraulic fracturing, stimulation, tracer injection, cleaning, acidizing, steam injection, water flooding, cementing, etc.

[0087] While the invention has been described with reference to an exemplary embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the65REL-509920-WO-2 (INT1015PCT) claims. Also, in the drawings and the description, there have been disclosed exemplary embodiments of the invention and, although specific terms may have been employed, they are unless otherwise stated used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention therefore not being so limited.

Claims

65REL-509920-WO-2 (INT1015PCT) CLAIMS What is claimed is:

1. An amplifier (28, 40, 40a, 40b) comprising: a first transistor (Q3a); a first non-linear semiconductor (Q4a,1, D4a,1); a second non-linear semiconductor (Q4a,2, D4a,2), wherein the first non-linear semiconductor (Q4a,1, D4a,1) and the second non-linear semiconductor (Q4a,2, D4a,2) are connected to the first transistor (Q3a), and the first non-linear semiconductor (Q4a,1, D4a,1) is connected in parallel to the second non-linear semiconductor (Q4a,2, D4a,2); a first resistance (R1A) in series with the first non-linear semiconductor (Q4a,1, D4a,1); and a second resistance (R2A) in series with the second non-linear semiconductor (Q4a,2, D4a,2), wherein a ratio of the first resistance (R1A) and the second resistance (R2A) determines a range of linearity of the amplifier.

2. The amplifier of claim 1, wherein the first non-linear semiconductor (Q4a,1, Q4b,1), and the second non-linear semiconductor (Q4a,2, Q4b,2) are transistors.

3. The amplifier of claim 1, wherein the first non-linear semiconductor (D4a,1, D4b,1) and the second non-linear semiconductor (D4a,2, D4b,2) are diodes.

4. The amplifier of claim 1, wherein the amplifier is a differential amplifier, the differential amplifier includes a second transistor (Q3b), a third non-linear semiconductor (Q4b,1), a fourth non-linear semiconductor (Q4b,2), a third resistance (R1B) and a fourth resistance (R2B), wherein: the third non-linear semiconductor (Q4b,1) and the fourth non-linear semiconductor are connected to the second transistor (Q3b), the third non-linear semiconductor (Q4b,1) is parallel to the fourth non-linear semiconductor (Q4b,2), the third resistance (R1B) is in series with the third non-linear semiconductor (Q4b,1), and the fourth resistance (R2B) is in series with the fourth non-linear semiconductor (Q4b,2).

5. The amplifier of claim 1, further including an input stage (42a) that receives an input voltage (Vip), the input stage configured to amplify the input voltage (Vip) and provides an amplified input voltage (V42a) to the first transistor (Q3a).

6. The amplifier of claim 5, wherein the first transistor (Q3a) receives at a base pin (P3a) the amplified input voltage (V42a).65REL-509920-WO-2 (INT1015PCT) 7. The amplifier of claim 5, wherein the first non-linear semiconductor (Q4a,1, D4a,1) and the second non-linear semiconductor (Q4a,2, D4a,2) are connected to one of an emitter (E3a) or a collector (C3a) of the first transistor (Q3a).

8. The amplifier of claim 5, wherein the first resistance (R1A) and the second resistance (R2A) are connected to ground of the amplifier.

9. The amplifier of claim 8, wherein the amplifier (28, 40, 40a, 40b) further includes a noise cancelation stage 46a, the noise cancelation stage configured to receive a voltage (V44a) from the first transistor (Q3a).

10. The amplifier of claim 1, wherein the amplifier (28, 40, 40a, 40b) is included in a measurement tool (16) in a borehole (13) and is configured to amplify an antenna signal measured inside the borehole (13).

11. The amplifier of claim 1, wherein the ratio of first resistance (R1A) and the second resistance (R2A) is at least 5.

12. The amplifier of claim 1, wherein an input impedance of the amplifier is 10 Ohms or less.

13. The amplifier of claim 1, wherein the amplifier is an open-loop amplifier.

14. A method of amplifying a signal, comprising: inputting an input voltage (Vip) to an amplifier (28, 40, 40a, 40b), the amplifier (28, 40, 40a, 40b) including: a first transistor (Q3a); a first non-linear semiconductor (Q4a,1, D4a,1); a second non-linear semiconductor (Q4a,2, D4a,2), wherein the first non-linear semiconductor (Q4a,1, D4a,1) and the second non-linear semiconductor (Q4a,2, D4a,2) are connected to the first transistor (Q3a), and the first non-linear semiconductor (Q4a,1, D4a,1) is connected in parallel to the second non-linear semiconductor (Q4a,2, D4a,2); a first resistance (R1A) in series with the first non-linear semiconductor (Q4a,1, D4a,1); and a second resistance (R2A) in series with the second non-linear semiconductor (Q4a,2, D4a,2), wherein a ratio of the first resistance (R1A) and the second resistance (R2A) determines a range of linearity of the amplifier; amplifying the input voltage (Vip) at an input stage (42a) to generate an amplified input voltage (V42a);65REL-509920-WO-2 (INT1015PCT) providing the amplified input voltage (V42a) to the first transistor (Q3a); and outputting an output signal (Vop).

15. The method of claim 14, wherein the first non-linear semiconductor (Q4a,1, Q4b,1), and the second non-linear semiconductor (Q4a,2, Q4b,2) are transistors.

16. The method of claim 14, wherein the first non-linear semiconductor (D4a,1, D4b,1) and the second non-linear semiconductor (D4a,2, D4b,2) are diodes.

17. The method of claim 14, wherein the first transistor (Q3a) receives at a base pin (P3a) the amplified input voltage (V42a).

18. The method of claim 14, wherein the first non-linear semiconductor (Q4a,1, D4a,1) and the second non-linear semiconductor (Q4a,2, D4a,2) are connected to one of an emitter (E3a) or a collector (C3a) of the first transistor (Q3a), and the first resistance (R1A) and the second resistance (R2A) are connected to ground of the amplifier.

19. The method of claim 18, further comprising receiving a voltage (V44a) from the first transistor (Q3a) at a noise cancellation stage (46a).

20. The method of claim 14, wherein the amplifier is included in a measurement tool (16) in a borehole (13) and is configured to amplify an antenna signal measured inside the borehole (13).

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