Parallel operation of multi-level power converters

Abstract

Circuits and methods are provided that more effectively and efficiently implement multi-level converter circuits. An integrated circuit (IC) configurable for dual IC operation in a master-slave mode, includes a compensation pin, power switch circuitry coupled between a first terminal and a second terminal, and multi-level control circuitry configurable to: control operation of the power switch circuitry to selectively charge and / or discharge one or more capacitors in accordance with a mode of operation to generate an output voltage; adjust the operation of the power switch circuitry in accordance with a control signal based on an error signal; and operate as a slave in a master-slave mode of operation, wherein the multi-level controller is further configurable to receive, at the compensation pin, a compensation voltage generated from a master multi-level power converter.

Description

PARALLEL OPERATION OF MULTI-LEVEL POWER CONVERTERSGreg SzczeszynskiCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims the benefit of and priority to in their entirety the following United States Provisional Patent Applications, which are all incorporated by reference in their entirety:

[0002] Application No. 63 / 620,507 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0003] Application No. 63 / 620,623 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0004] Application No. 63 / 620,613 entitled “INTEGRATED CURRENT RESISTOR SENSING FOR MULTI-LEVEL CONVERTER;”

[0005] Application No. 63 / 620,465 entitled “STARTUP INTERLOCK FOR POWER CONVERTER CIRCUITS;”

[0006] Application No. 63 / 620,331 entitled “FULLY DIFFERENTIAL LEVEL SHIFT IN A NOISY ENVIRONMENT;”

[0007] Application No. 63 / 620,450 entitled “CAPACITOR SENSING AND CAPACITOR BALANCING SYSTEMS AND METHODS;”

[0008] Application No. 63 / 620,469 entitled “CAPACITOR SENSING AND CAPACITOR BALANCING SYSTEMS AND METHODS;”

[0009] Application No. 63 / 620,678 entitled “RECONFIGURABLE MULTI-LEVEL POWER CONVERTER TO CHARGE PUMP MODE AND FRACTIONAL CHARGE PUMP MODE;”

[0010] Application No. 63 / 620,417 entitled “INPUT CURRENT SLEW FOR A MULTILEVEL CONVERTER;”

[0011] Application No. 63 / 620,726 entitled “ADJUSTING OVERVOLTAGE PROTECTION BASED ON MODE OF OPERATION SYSTEMS AND METHODS;”

[0012] Application No. 63 / 620,737 entitled “HYBRID PEAK AVERAGE CURRENT MODE CONTROL;”

[0013] Application No. 63 / 620,741 entitled “CURRENT LIMITED VOLTAGE MODE CONTROL OF MULTIPLE INPUTS;”

[0014] Application No. 63 / 620,527 entitled “MULTI-FUNCTION COMP PIN SYSTEMS AND METHODS;”

[0015] Application No. 63 / 620,488 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0016] Application No. 63 / 620,553 entitled “MULTI-LEVEL REVERSE CURRENT BLOCKING SYSTEMS AND METHODS;”

[0017] Application No. 63 / 620,638 entitled “GENERAL STARTUP FOR MULTILEVEL POWER CONVERTER CIRCUITS;”

[0018] Application No. 63 / 620,733 entitled “PRECISION ANALOG TO DIGITAL CIRCUIT TUNED VOLTAGE AND CURRENT MODE DC-DC CONVERTER;”

[0019] Application No. 63 / 620,738 entitled “PREDICTIVE CONTROL LOOP PRECHARGING DURING A MULTI-LEVEL ZONE CHANGE;”

[0020] Application No. 63 / 620,764 entitled “DETECTOR CIRCUIT FOR DETECTING ONE OF MULTI-INPUT CONTROLLING SIGNALS THAT CONTROLS A CONTROLLOOP CIRCUIT;”

[0021] Application No. 63 / 620,607 entitled “STARTUP VOLTAGE SELECTION FOR MULTI-LEVEL POWER CONVERTER CIRCUITS;”

[0022] Application No. 63 / 620,575 entitled “MULTI-LEVEL CAPACITOR FAULTDETECTION SYSTEMS AND METHODS;”

[0023] Application No. 63 / 620,582 entitled “PARELLEL OPERATION OF MULTILEVEL POWER CONVERTERS;” and

[0024] Application No. 63 / 620,763 entitled “AVERAGE AND PEAK CURRENT SENSE SYSTEMS AND METHODS.”BACKGROUND

[0025] This disclosure relates to electronic circuits, and more particularly for example to multi-level power converters.

[0026] Many electronic products, including mobile computing and / or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, LCD, LED displays, and the like) use multiple voltage levels for operation. For example, radio frequency (RF) transmitter power amplifiers may operate at relatively high voltages (e.g., 12V or more), whereas logic circuitry may operate at a relatively low voltage level (e.g., 1-3V) and other circuitry may operate at an intermediate voltage level (e.g., 5-10V).

[0027] Direct current power converters are often used to generate a lower or higher voltage from a common power source, such as a battery, solar cells, and rectified AC sources. Power converters which generate a lower output voltage level from a higher input voltage power source are commonly known as buck converters, so-called because the output voltage VOUT is less than the input voltage VIN, and hence the converter is “bucking” the input voltage. Power converters which generate a higher output voltage level from a lower input voltage power source are commonly known as boost converters, because VOUT is greater than VIN. Some power converters may be either a buck converter or a boost converter depending on which terminals are used for input and output. Some power converters may provide an inverted output.

[0028] One type of direct current power converter known as a multi-level power converter includes charge transfer capacitors as energy storage elements coupled by controlled switches to transfer charge from VIN to VOUT. Such charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors”. When a fly capacitor is used (z.e., not bypassed), the electrical energy flowing through that fly capacitor generally will either charge it or discharge it.

[0029] There is a continued need for improved circuits and methods for more effectively and efficiently operating and implementing various type of electrical circuits and devices, including for example multi-level converter circuits.SUMMARY

[0030] Embodiments of the present disclosure include systems, circuits, and methods for operating and implementing various electronics circuits, including multi-level converter circuits.

[0031] In various embodiments, an integrated circuit includes a compensation pin, power switch circuitry coupled between a first terminal and a second terminal, and multi-level control circuitry configurable to: control operation of the power switch circuitry to selectively charge and / or discharge one or more capacitors in accordance with a mode of operation to generate an output voltage; adjust the operation of the power switch circuitry in accordance with a control signal based on an error signal; and operate as a slave in a master-slave mode of operation, wherein the multi-level controller is further configurable to receive, at the compensation pin, a compensation voltage generated from a master multi-level power converter. The multi-level control circuitry may further include a feedback circuit configurable to monitor a voltage level associated with the power switch circuitry and generate the error signal. When operating as a slave in the master-slave mode of operation, the multi-level controller may use the compensation voltage received at the compensation pin from the master multi-level power converter as the error signal.

[0032] In various embodiments, a method includes configuring a multi-level controller of a first integrated circuit to control operation of power switch circuitry to selectively charge and / or discharge one or more capacitors in accordance with a mode of operation to generate an output voltage, wherein operation of the power switch circuitry is adjusted by the multi-level controller based on a control signal. The method may further include electrically coupling a first compensation pin of the first integrated circuit with a second compensation pin of a second integrated circuit, if the multi-level controller is configured as a slave in a master-slave mode of operation, the method further comprises sensing, at the first compensation pin, a compensation voltage generated by the second compensation pin, and generating the control signal to adjust operation of the power switch circuitry based on the sensed compensation voltage.

[0033] In various embodiments, a system includes a plurality of integrated circuits comprising a first integrated circuit configured to operate as a master integrated circuit and at least one integrated circuit configured to operate as a slave integrated circuit. Each integratedcircuit may include a compensation pin, power switch circuitry coupled between a first terminal and a second terminal, and a multi-level controller.

[0034] The multi-level controller may be configurable to control operation of the power switch circuitry to selectively charge and / or discharge one or more capacitors to generate an output voltage in accordance with a mode of operation comprising operating as a master in a master-slave mode of operation or operating as a slave in the master-slave mode of operation. The multi-level controller may further be configurable to adjust the operation of the power switch circuitry in accordance with a control signal, generate a compensation voltage for the compensation pin if configured as the master in the master-slave mode of operation, and if the multi-level controller is configured as the slave in the master-slave mode of operation, receive at the compensation pin the compensation voltage generated from one of the plurality of integrated circuits configured as the master in the master-slave mode of operation.

[0035] The system may further include a secondary controller configurable to generate the control signal based on an error signal. The secondary controller may include a feedback circuit configurable to monitor a voltage level of the power switch circuitry to generate the error signal when the multi-level controller is configured as a master in the master-slave mode of operation. If the multi-level controller is configured as a slave in a master-slave mode of operation, the compensation voltage received from the master integrated circuit is used as the error signal.

[0036] The scope of the present disclosure is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present disclosure will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.DESCRIPTION OF THE DRAWINGS

[0037] FIG. 1 A is an example power converter circuit with internal input current sense, in accordance with one or more embodiments of the present disclosure.

[0038] FIG. IB is an example power converter circuit with external input current sense, in accordance with one or more embodiments of the present disclosure.

[0039] FIG. 2A is an example dual integrated circuit (IC) power converter circuit with internal input current sense, in accordance with one or more embodiments of the present disclosure.

[0040] FIG. 2B is an example dual IC power converter circuit with external input current sense, in accordance with one or more embodiments of the present disclosure.

[0041] FIG. 3A is an example functional block diagram of a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0042] FIG. 3B is an example functional block diagram of a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0043] FIG. 4 is a diagram illustrating an example charging function in step down regulation mode of an example power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0044] FIG. 5 is a diagram illustrating an example charging function in step down divide by 3 charge pump mode, in accordance with one or more embodiments of the present disclosure.

[0045] FIG. 6 is a functional block diagram illustrating aspects of an example power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0046] FIG. 7 is a block diagram illustrating an example system implementing a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0047] FIG. 8A is a circuit diagram illustrating an example 3-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0048] FIG. 8B is a circuit diagram illustrating an example 4-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0049] FIG. 8C is a circuit diagram illustrating an example M-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0050] FIG. 9 is an example M-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0051] FIG. 10 is a block diagram of an example embodiment of control circuitry for an A / -level converter cell, in accordance with one or more embodiments of the present disclosure.

[0052] FIG. 11 illustrates an example multi-level power converter including two multilevel controller integrated circuits, in accordance with one or more embodiments of the present disclosure.

[0053] FIG. 12 is a block diagram illustrating a master-slave configuration including two multi-level controller integrated circuits, in accordance with one or more embodiments of the present disclosure.

[0054] FIG. 13 illustrates three operational control loops of a secondary controller, in accordance with one or more embodiments of the present disclosure.

[0055] FIG. 14 illustrates an example process for operating a plurality of multi-level power converter ICs in a master-slave mode, in accordance with one or more embodiments of the present disclosure.

[0056] Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It is noted that sizes of various components and distances between these components are not drawn to scale in the figures. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.DETAILED DESCRIPTION

[0057] The present disclosure encompasses novel circuits, architectures, systems, and methods that more effectively and efficiently address the configuration and operation of multilevel converter circuits. It will be appreciated that various improvements disclosed herein encompass innovative circuits, hardware components, architectures, and related logic that are applicable to applications beyond multi-level converter circuits.

[0058] FIGs. 1-6 illustrate various embodiments of a high efficiency 4-level step-down and step-up power converter for battery charging applications, such as single cell Li-ion and Li- polymer battery applications. In the illustrated embodiments, the power converter is configured to deliver up to 5 amperes (A) of charging current in regulation mode and in a divide-by-3 charge pump mode, though other configurations are within the scope of the present disclosure.The power converter can be configured, for example, into dual ICs operation for 9A charging current in regulation mode and in divide-by-3 charge pump mode. Although a 4-level power converter is illustrated, it will be appreciated that the embodiments described herein may be applicable to various M-level implementations, where M >= 3.

[0059] In some implementations, for example, the power converter may supply an input range of approximately 4.5 V to 18 V input to support both universal serial bus (USB) and wireless inputs, and in a reverse step-up mode, the output may be programmable from 4.8 V to 16 V in 100 mV step with a programmable output current limit up to 1.7 A. This input voltage range may be used, for example, to support fast charging of single Li-Ion cells from USB and wireless input. It will be appreciated that other voltage and current ranges and limits may be implemented depending on the application. It will also be appreciated that while compatibility with USB is described herein, other wired interfaces and protocols may be implemented with the power converter of the present disclosure.

[0060] In various embodiments, the power converter may be implemented as a single integrated circuit (IC) (see, e.g., Figs. 1 A-B), dual-integrated circuits (see, e.g., Figs. 2A-B), or in other configurations depending on the implementation. In various embodiments, the power converter may operate as a parallel charger along with a main charger, as shown in Fig. 3B, to provide the desired functionality noted herein and, for example, as illustrated in Figs. 4 and 5 for the desired charging functionality for various applications, as would be understood by one skilled in the art. Fig. 3B may represent a system level point of view of a mobile architecture having a parallel charger and a main charger that accepts power from a wired port (e.g., a wired USB) or from a wireless interface. The parallel charger for one or more embodiments may represent an IC as illustrated in Figs. 1-3 A, for example, and may function to charge a battery for some portion of the charging profile (e.g., as shown in Figs. 4 and 5), while the main charger charges the battery for other portions of the charging profile. In various embodiments, the parallel charger may also be configured to function as the main charger as well, depending upon the desired application. The novel architecture disclosed herein may be implemented to enable (i) improved efficiency (e.g., at 9A charging current) in a low-profile solution; (ii) low electromagnetic interference (EMI) fixed-frequency operation under heavy load conditions; (iii) input and output current and voltage, IC temperature monitoring and telemetry via interintegrated circuit (EC) technology; and / or (iv) full protection including input and output under voltage lockout (UVLO), input and output over voltage protection (OVP), input and outputover current protection (OCP), and IC over-temperature with fault and warning status. In some implementations, the power converter supports divide-by-3, step-down and step-up regulating modes, dual external disconnect switch control, and / or paralleled operation.

[0061] In the illustrated embodiments, the power converter is implemented as a multi-level charge pump incorporating power switches and control circuitry. The power converter’s internal bias may be provided by the system battery through a VOUT connection (e.g., pin). The charging input can be USB (or other wired input) or wireless input by an external FET register control. In some implementations, the power converter may be programmed to different operating modes, which may include a step-down regulation mode, a step-down divide-by-3 charge pump mode, and a reverse step-up mode.

[0062] In a step-down regulation mode, the power converter operates as a multi-level stepdown regulator to support USB power delivery (USB-PD) (or other wired protocol) or fixed input charging. During a constant-current (CC) phase, the maximum charging current may be limited for example, by configuring registers. When the input current does not reach a predetermined maximum input setting, the charge current is set to a predetermined maximum output setting. If the input current reaches the input maximum setting, then the charge current throttles and maintains input current at the input maximum setting. This allows maximum charging current while ensuring that the charge current does not go above a battery maximum current rating and the input current does not trip adapter over-current protection.

[0063] During a constant-voltage (CV) phase, the CV regulation may be limited, for example, by configuring registers. In operation, a single-wire sense pin or other sensor is configured to sense the output voltage VOUT, which is compared to a predetermined value stored in a register, VOUT REG. The voltage differential between the battery’s positive terminal and negative terminal is sensed and compared to a predetermined value stored in a register, VBATT REG. In some implementations, a single-wire sense pin or other sensor senses VBATTP (battery voltage at positive terminal) and a single-wire sense pin or other sensor senses VBATTN (battery volage at negative terminal). The CV regulates to the lower of the two settings. If the VOUT sensed voltage reaches VOUT REG first, then CV is regulated to VOUT REG. If the VBATTP sensed voltage reaches VBATT REG first, then CV is regulated to VB ATT REG. This provides a fast battery top off while preventing voltage above safety limit.

[0064] In a step-down divide-by-3 charge pump mode (which may be selected, for example, by setting a corresponding register), the power converter is configured as a divide- by-3 step-down charge divider to support USB-Programmable Power Supply (USB-PPS) or other charging protocol or programmable input charging. In some embodiments, the power converter allows the USB-PPS adapter to control voltage and current and ignores conflicting settings (e.g., settings stored in registers for I0UT MAX, VOUT REG and VBATT REG). In this mode, the power converter monitors an IIN MAX setting, shuts down the power train (which includes switches to configure, enable and disable various modes of operation) and disconnects external FET when UN current exceeds IIN MAX setting. In the illustrated embodiment, the output current is up to 10A in dual IC operation and 5 A in single IC operation.

[0065] In a reverse step-up mode (which may be selected, for example, by setting a corresponding register) the power converter is configured as a multi-level step-up regulator to power peripheral device(s) connected to USB (or other wired protocol or standard) or wireless input. The power converter draws power from the system battery and regulates VIN to the VOUT REG programmable setting of 4.8V to 16V. The VIN output current limit may be set, for example, by an IIN_MAX register.

[0066] In some embodiments, to enable the IC, both an EN pin and an IC EN bit are set to logic high (1). When either the EN pin or IC EN bit is set to logic low (0), the IC is disabled. After the IC is enabled, the POR status bit sets to 1 to indicate the IC has a fresh power up.

[0067] In some embodiments, the power converter provides a gate driver to control two external N-channel MOSFETs and sense inputs to monitor source input voltage at each FET. The external FETs may be controlled by registers (e.g., 1 -bit registers V EXTG, EXTG EN and EXTGX). The V EXTG bit sets the gate drive voltage and can be set to 9V or 5 V, in the illustrated embodiment. The EXTGX bits select which FET(s) to turn on. The EXTG EN bit enables the gate driver to turn on the selected FET(s). In various embodiments, the external FET can be turned on or off independently from other IC operations except when the IC is disabled. The EXT EN IND status bit set to 1 when external FET is enabled. When a fault is detected and triggers a shutdown, the external FET may be turned off automatically. If EXT1 or EXT2 detects an OVP, then the respected FET would not turn on from the off mode.

[0068] In various embodiments, the power train is enabled after all the registers have been initialized and the target input external FET is turned on. Sufficient time based on capacitance on the power path may be configured between the external FET on time and the power train on time to minimize in-rush current. Next, both PT EN pin and PT EN bit are set to logic high (1) to turn on the power train. When either PT EN pin or PT EN pin is logic low, the power train is off. In dual IC operation, the slave IC power train may be configured to turn on first before the master IC. The COMP, SYNC and SYNCH pins from two ICs gate the power train and synchronize the operation. The SYNC SEL pin sets the IC to master mode or slave mode. IC internal fault and programmable fault detection shuts down the power train operation when fault is detected.

[0069] In a reverse step-up mode (which may be selected, for example, by setting a corresponding register), the power converter is configured as a multi-level step-up regulator to power peripheral device(s) connected to USB (or other wired port) or wireless input. The power converter draws power from the system battery and regulates VIN pin to a VOUT REG programmable setting of 4.8V to 16V. The VIN output current limit is set by IIN_MAX register.

[0070] To enable the IC, both the EN pin and IC EN bit are set to logic high (1). When either EN pin or IC EN bit is set to logic low (0), the IC is disabled. After the IC enables, the POR status bit sets to 1 to indicate the IC has a fresh power up. The power converter provides a gate driver to control two external N-channel MOSFETs and sense inputs to monitor source input voltage at each FET. The external FETs are controlled by register bits, such as V EXTG, EXTG EN and EXTGX. The V EXTG bit sets the gate drive voltage and can be set to 9V or 5V, for example. The EXTGX bits select which FET(s) to turn on. The EXTG EN bit enables the gate driver to turn on the selected FET(s). The external FET can be turned on or off independently from other IC operation except when the IC is disabled. The EXT EN IND status bit set to 1 when external FET is enabled.

[0071] When a fault is detected and triggers a shutdown, the external FET may be turned off automatically. If EXT1 or EXT2 detects an OVP, then the respective FET would not turn on from off mode. The power train is enabled after all the registers have been initialized and the target input external FET is turned on. Sufficient time based on capacitance on the power path should be given between external FET on time to power train on time to minimize in-rush current. Next, both PT EN pin and PT EN bit are set to logic high (1) to turn on the powertrain. When either PT EN pin or PT EN pin is logic low, the power train is off. In dual IC operation, the slave IC power train is turned on before the master IC. The COMP, SYNC and SYNCH pins from the two ICs gate the power train and synchronize the operation. SYNC SEL pin sets the IC to master mode or slave mode. IC internal fault and programmable fault detection shuts down power train operation when a fault is detected.

[0072] In accordance with various embodiments, an example power converter initialization, an example power up sequence, and an example fault handling will now be described for the three different operating modes. In an example step-down regulation mode, the initialization and power up sequence uses EXT1 as an example. The same sequence may apply to EXT2 with the only change in EXTGX bit and related EXT2 register settings. First, pull EN to logic high and then set IC EN bit= 1 at lOOus(TBD) after EN is logic high to enable IC. IC startup from POR stage, POR bit reports 1 indicating fresh IC startup. Next, the POR bit is read to confirm the IC is enabled. The FREQUENCY register is then set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The VOUT REG register is set to the target regulation voltage on the VOUT sense pin in CV operation. The VBATT REG register is set to the target regulation voltage on the VBATTP sense pin in CV operation. The IOUT MAX register is set to the target maximum charger current in CC operation, and the IIN MAX register is set to a value below the adapter current limit. Next, the FAULT and WARNING registers was set to a desired setting. Each Fault and Warning enables at a different time based on IC status and operating mode. The WATCHDOG register is then set to a desired setting.

[0073] The MODE register and other related registers are set for step -down regulation mode, including power train setup and enablement of an external FET, while checking for faults. In a dual IC operation, the external FETs are controlled by the master IC. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the external FET after the shutdown fault is initiated. Next, the power train is enabled. In a dual IC operation, the slave IC power train is turned on before the master IC. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation.

[0074] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), an externalFET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault.

[0075] An example step-down divide-by-3 power converter mode initialization and power up sequence will now be described. The initialization and power up sequence uses EXT1 as an example, but it will be appreciated that the same sequence applies to EXT2 with a change in EXTGX bit and related EXT2 register settings. The EN is pulled to logic high and then IC EN bit=l at lOOus(TBD) after EN is logic high to enable IC. The IC starts up from POR stage, POR bit reports 1 indicating fresh IC startup. The POR bit is read to confirm the IC is enabled. The FREQUENCY register is set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The IIN MAX register is set to a value below the adapter current limit. VOUT REG, VBATT REG and I0UT MAX registers are not used in step-down divide-by-3 charge pump mode. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter. The FAULT, WARNING, and WATCHDOG registers are set to desired settings. Each Fault and Warning enables at different time based on IC status and operating mode.

[0076] The MODE register and other registers are set for step-down divide-by-three mode, including power train setup and external FET setup, while checking for faults. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the power train or external FET, as appropriate, after the shutdown fault is initiated. Next, the power train is enabled. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter.

[0077] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), or an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault.

[0078] An example reverse step-up mode initialization and power up sequence will now be described. This initialization and power up sequence uses EXT2 as an example, but the same sequence applies to EXT1 with the change in EXTGX bit and related EXT1 register setting. The value EN is pulled to logic high and then IC EN bit is set to 1 at lOOus(TBD) after EN is logic high to enable IC. The IC starts up from the POR stage, and the POR bit reports 1 indicating a fresh IC startup. The POR bit is read to confirm the IC is enabled. Next, the FREQUENCY register is set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The VOUT REG register is set to the target regulation voltage at VIN. Next, the IIN MAX register is set to the target current limit. VBATT REG and I0UT MAX registers are not used in reverse step-up mode. FAULT, WARNING, and WATCHDOG registers are set to desired settings. Each Fault and Warning enables at a different time based on IC status and operating mode.

[0079] The MODE register and other registers are set for reverse step-up mode, including power train setup and external FET setup, while checking for faults. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the power train or external FET, as appropriate, after the shutdown fault is initiated. Next, the power train is enabled. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter. In dual IC operation, the slave IC power train is turned on before the master IC and is controlled by the master IC.

[0080] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), or an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault. The EXT2 or VIN pins are not configured to detect OVP as it is set as the output in reverse step-up mode. But if EXT2 or VIN pin detects an OVP event, then IC STATUS1 and IC STATUS2 would report the fault event.

[0081] In an example system 700 illustrated in FIG. 7, a power converter 720 is implemented in a host 710 (e.g., a device or system) that includes a battery 730 and various system components 740. The host 710 may be any system or device that implements a powerconverter as described herein, including but not limited to a smart phone, tablet, portable electronics, a mobile device, low power electronics, and other electronic systems. The battery 730 may include one or more batteries that store electricity for use by the host 710, such as single cell Li-ion and Li-polymer batteries.

[0082] The power converter 720 may be configured to convert electricity stored in the battery 730 to a desired system voltage, VSYS, for powering various system components 740, which may include one or more logic devices 742, memories 744, communications components 746, input / output (I / O) components 748, circuitry 750, and other components 752. The power converter 720 may also supply power to one or more external devices 760, such as a component connected to the host 710 through a wired or wireless connection, such as a USB compatible device. The power converter 720 may also be configured to receive power from an external power source 712 and convert the received power to the battery 730 for storage, or to the system components 740 and / or external device 760, as applicable.

[0083] In various embodiments, the one or more logic devices 742 and memories 744 may be configured to perform operations of the host 710. A logic device 742 may be implemented as a general -purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a microcontroller, a programmable logic device (PLD), a field-programmable gate array (FPGA), or other programmable logic device(s). The logic device 742 and other components may be configured through hardwiring, software execution, or a combination of both. In various embodiments, the host 710 includes one or more memory devices designed to retain data, such as software instructions for execution by the logic device. The memory may include volatile and non-volatile memories, such as randomaccess memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), non-volatile randomaccess memory (NVRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically-erasable programmable read-only memory (EEPROM), flash memory, hard disk drives, or other memory types. The logic device may be configured to execute software instructions residing in the memory, thereby accomplishing method steps and operations.

[0084] Referring to FIGs. 8A-8C, the converter circuit may be configured to switch between two or more switch states. One or more PWM duty cycle controllers may be provided to set the time in each switch state based on the voltage at VOUT. For example, FIG. 8A is a schematic diagram of a 3 -level DC-to-DC buck converter circuit 800 that may be used as theconverter circuit 920 of FIG. 9. A set of four switches, S1-S4, is series-coupled between VIN and circuit ground. A fly capacitor Cl is coupled in series with switches S3 and S4, and in parallel with switches SI and S2. An inductor LI is coupled to an output capacitor COUT and to a node Lx between switches SI and S2, and the voltage across the output capacitor COUT is VOUT.

[0085] In the illustrated example, the presence of the single fly capacitor Cl in the converter circuit 800 enables four switch states that each generate one of three voltage levels at node Lx. In a first switch state, S2 and S4 are closed and SI and S3 are open, effectively bypassing Cl and connecting Lx to circuit ground (voltage level at Lx = GND). In a second switch state, S2 and S4 are open and SI and S3 are closed, effectively bypassing Cl and connecting Lx to VIN (voltage level at Lx = VIN). In a third switch state SI and S4 are open and S2 and S3 are closed, connecting Cl from VIN to LX, and thus charging Cl with inductor LI current flowing into a load. The voltage across Cl will be about VIN / 2 and the voltage level at Lx will also equal about VIN / 2. In a fourth switch state, SI and S4 are closed and S2 and S3 are open, connecting Cl from Lx to GND and thus discharging Cl with inductor LI current flowing to a load. The voltage across Cl will be about VIN / 2 and the voltage level at Lx will also equal about VIN / 2 (e.g., this may assume that Cl was previously charged in state three). Accordingly, the illustrated converter circuit 800 has two switch states that generate a voltage level of VIN / 2 at the Lx node.

[0086] If the converter circuit 800 is toggled between switch states three and four (avoiding switch state two that bypasses the fly capacitor Cl), the inductor LI sees small jumps in the voltage level at Lx, going from GND to only VIN / 2 and back to GND, which results in reduced voltage ripple across the inductor LI and less filtering to smooth VOUT than a converter circuit with only SI and S2 switches.

[0087] Adding additional series switches Sx and fly capacitors Cx to the 2-level converter circuit 800 increases the number of switch states and resulting voltage levels between VIN and circuit ground that can be applied to the Lx node, thus generating an even smaller voltage ripple across the inductor L. This reduces the filtering requirements to get a smooth output voltage. For example, a 4-level DC-to-DC buck converter circuit (see, e.g., FIG. 8B) includes 6 series- coupled switches S1-S6 and two fly capacitors Cx (X = 2). Consequently, a 4-level converter circuit can define 4 voltage levels (VIN, GND, ’AVIN, and %VIN) at node LX from 8 switch states (3 switch states result in the ’AVIN level at Lx, and 3 other switch states result in the%VIN level at Lx). For some applications, VOUT is set low enough that the voltage level at node Lx alternates between GND and the next higher voltage level available. For higher output voltages, the switching pattern may never use GND. For example, in a 4-level converter circuit, an output VOUT set to 0.5*VIN can be achieved by alternating the Lx node between % VIN and % V.

[0088] A different interpretation of a multi-level converter circuit is that the fly capacitors Cx create a charge-pump for the buck converter circuit. Unlike a standard charge-pump where the output is restricted to one output, a multi-level converter circuit allows the fly capacitors Cx to be coupled to create multiple intermediate voltages. For the 4-level example, the two fly capacitors each act as a % charge-pump with the additional benefit that any input voltage that is a sum of % ratios can be created, including VIN and GND.

[0089] A multi-level converter circuit couples the fly capacitors Cx in different combinations in order to bring the voltage level at the Lx node down or up. As noted above, when a fly capacitor is used (i.e., not bypassed), the electrical energy flowing through that fly capacitor generally will either charge it or discharge it, which creates a control problem in maintaining an average voltage.

[0090] Resolving the charge-balance problem so as to maintain an average voltage across the single capacitor in a 3 -level converter circuit will now be described. For example, in a 3- level converter circuit, one way to generate the Level-1 (GND) and Level-3 (VIN) voltage levels at the Lx node is to not use the fly capacitors Cl for these Lx voltage levels. However, for the Level 2 (VIN / 2) voltage level at Lx, two separate switch states can be used: one switch state charges the capacitor (S3 and S2 closed, SI and S4 open) and the other switch state discharges the capacitor (S3 and S2 open, SI and S4 closed). The control of a 3-level converter circuit may operate such that each time the converter circuit switches states to Level-2, a controller can alternate between charging and discharging the single capacitor to maintain its voltage. A voltage comparator can be used to monitor the capacitor to help decide on a charging state or a discharging state. For instance, if the capacitor voltage is below VIN / 2, then a controller would select charge (the third switch state), and if the capacitor voltage is above VIN / 2, then the controller would select discharge (the fourth switch state).

[0091] Referring to FIGs. 8B, a 4-level converter circuit 830 (X = 2) illustrates the chargebalance difficulty when more capacitors are present. A Level-1 voltage level (GND) and aLevel-4 voltage level (VIN) at the Lx node are each determined by a single switch state. However, the Level-2 voltage level (’A VIN) and Level-3 voltage level (% VIN) at Lx each can be achieved by any of three different switch states. At higher orders of a multi-level converter circuit (X > 2), more switch states are possible for generating the intermediate levels between VIN and GND. The problem gets more complicated with a 5-level converter circuit (X= 3). A Level-1 voltage level (GND) and a Level-5 voltage level (VIN) at the Lx node are each determined by a single switch state. However, the Level-2 voltage level (’AVIN) and Level-4 voltage level (3A VIN) at Lx each can be achieved by any of four different switch states, the Level-3 voltage level (2 / 4 VIN) at Lx can be achieved by any of six different switch states.

[0092] As should be clear from these examples, determining a suitable charge-balance method can become exceedingly difficult as the complexity of a multi-level converter circuit increases. As previously noted, most conventional control methods rely on establishing a sequence of linked state-changes to try to achieve charge balance. Control systems based on long sequences of switch states generally assume that all system variables - such as input voltage and output current - are constant during the sequence. This is unrealistic for a real- world environment, where all system variables tend to be dynamic.

[0093] In a 2-Level example, the converter circuit switches between two switch states: SI closed and S2 open (voltage level at Lx = VIN), or SI open and S2 closed (voltage level at Lx = GND). A PWM duty cycle controller sets the time in each switch state based on the voltage at VOUT, which determines the amplitude of the average voltage at Lx (noting that, the average Lx voltage in theory is equal to the VOUT average voltage, but that, due to parasitics, the Lx average voltage is higher and / or lower (for negative currents) than the VOUT average). As can be appreciated, the inductor L sees large jumps in the voltage level at Lx, from GND to VIN and back to GND. The resulting voltage ripple across the inductor L necessitates a significant amount of filtering to smooth VOUT.

[0094] An alternative way of reducing the voltage ripple across the inductor L is to add more series switches as well as charge transfer capacitors as energy storage elements to transfer charge from VIN to VOUT. AS noted above, such charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors” and may be external components coupled to an integrated circuit embodiment of a converter circuit. The presence of X fly capacitors Cx defines a multi-level capacitive converter circuit capable of generating M=X+ 2 voltage levels at node Lx from 2CV I’ switch states.

[0095] FIG. 8C is schematic diagram of a generalized A7-level multi-level converter cell 870 that may be used as the converter circuit 920 of FIG. 9. A set of switches, Sl-S[2*( f- 1)], is series-coupled between VIN and circuit ground. The set of switches are organized in switch pairs: SI & S2, S3 & S4, ... S[2*(AT- 2)+l] & S[2*( f- 1)]. A set of AT- 2 fly capacitor Cx is coupled in series with certain respective switches, and in parallel with switches in between those switches. In terms of switch pairs, there are M~ 1 pairs of switches, or one more than the number of fly capacitors. An optional inductor L is coupled to an output capacitor COUT and to a node Lx between switches SI and S2, and again the voltage across the output capacitor COUT is VOUT. The inductor L doubles as a virtual current source that facilitates movement of charge between the fly capacitors Cx. This creates a very efficient form of charge transfer, but introduces the problem of charge-balancing the fly capacitors Cx.

[0096] In various embodiments, each fly capacitor Cx has a first terminal coupled between an outer high-side switch S[2*x + 1] and an inner high-side switch S[2*x-1], where “high- side” refers to the VIN side of the converter circuit. Each fly capacitor Cx has a second terminal coupled between an outer low-side switch S[2*x + 2] and an inner low-side switch S[2*x], where “low-side” refers to the circuit ground (GND) side of the converter circuit. Thus, for an M= 3 multi-level converter cell, a first terminal of the single (X= 1) fly capacitor Cl would be coupled between outer high-side switch S3 and inner high-side switch SI, and a second terminal of the capacitor Cl would be coupled between inner low-side switch S2 and outer low-side switch S4. Accordingly, each fly capacitor Cx within the multi-level converter cell 870 has four switches that can affect current flow through that fly capacitor Cx.

[0097] In some embodiments, a voltage detector, which may be a simple comparator-type circuit, is provided to sense the voltage across a corresponding fly capacitor Cx with respect to a reference voltage, VREF, which represents a desired target voltage for the fly capacitor Cx. Every fly capacitor Cx may have a target average voltage in order to maintain proper output level. For an A7-level converter and capacitor Cx, where x = 1, 2, ... \M~ 2], its target voltage is:Vtarget

[0098] The voltage detector may be configured to output a HIGH / LOW status signal, CT.v _H / L, indicating with the voltage across the corresponding fly capacitor Cx is greater thanVREF or less than VREF. The CT.v _H / L status signal is coupled to control circuitry for the switches associated with the fly capacitor Cx.

[0099] The control circuitry for the four switches that can affect current flow through a fly capacitor Cx set states for those switches in part as a function of the voltage across the fly capacitor Cx as measured by the associated voltage detector and conveyed by the CT.VH / LX status signal. Accordingly, for ease of understanding, it can be said that each fly capacitor Cx “controls” its own pairs of high-side and low-side switches. If it is assumed that current flow in the inductor is charging the output VOUT, there are four possible states that can be defined for the pairs of high-side and low-side switches for each fly capacitor Cx.

[0100] In a switch state in which the outer high-side and inner low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be in a charging configuration (whether or not charging actually occurs may depend on the switch states for other fly capacitors Cx). In a switch state in which the inner high-side and outer low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be in a discharging configuration (whether or not discharging actually occurs may depend on the switch states for other fly capacitors Cx). In a switching state in which the inner low-side and outer low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be bypassed. In a switching state in which the outer high-side and inner high-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would again be bypassed.

[0101] While each fly capacitor Cx can control both of its own pairs of high-side and low- side switches, in general, methods of control disclosed herein may utilize either the outer switches or the inner switches controllable by each corresponding capacitor. For example, referring to FIG. 8B, in “outer-switch” methods, fly capacitor Cl will control its outer switches S3 and S4, fly capacitor C2 will control its outer switches S5 and S6, etc. Conversely, for example, in “inner-switch” methods, fly capacitor Cl will control its inner switches SI and S2, fly capacitor C2 will control its inner switches S3 and S4, etc. The switch states of either pair (inner or outer) of switches controlled by a fly capacitor Cx may be complementary - that is, no fly capacitor Cx closes or opens both of its high-side and low-side controlled switches at the same time. If each fly capacitor Cx controls its outer-switches, then no fly capacitor controls the left-over innermost switches SI and S2. If instead each fly capacitor Cx controls its inner-switches, then no fly capacitor controls the left-over outermost switches S[2*(A1-1)] and S[2*(Al-2)+l], Switch states for the left-over switches are also complementary.

[0102] FIG. 9 is a high-level block diagram of an example circuit that includes a power converter 900, in accordance with one or more embodiments of the present disclosure. In the illustrated example, the power converter 900 includes a converter circuit 920 and a controller 910. The converter circuit 920 and controller 910 may be configured to implement, for example, any of the multi-level power converter circuits as previously described with reference to FIGs. 1 A-8C, and as described further herein. In the illustrated embodiment, the converter circuit 920 is configured to receive an input voltage VIN from a voltage source and transform the input voltage VIN into an output voltage VOUT. In some embodiments of the power converter 900, auxiliary circuitry (not shown), such as a bias voltage generator(s), a clock generator, a voltage control circuit, etc., may also be present and coupled to the converter circuit 920 and the controller 910.

[0103] The controller 910 receives a set of input signals and produces a set of output signals. Some of these input signals arrive along a signal path connected to the converter circuit 920. These input signals carry information that is indicative of the operational state of the converter circuit 920. The controller 910 may also receive a clock signal CLK (for synchronous converter circuits 920) and one or more external input / output signals VO that may be analog, digital (encoded or direct signal lines), or a combination of both. Based upon the received input signals, the controller 910 produces a set of control signals back to the converter circuit 920 that control the internal components of the converter circuit 920 (e.g., internal switches, such as low voltage FETs / MOSFETs) to cause the converter circuit 920 to boost or buck VIN to VOUT. In some embodiments, an auxiliary circuit (not shown) may provide various signals to the controller 910 (and optionally directly to the converter circuit 920), such as the clock signal CLK, the input / output signals I / O, as well as various voltages, such as a general supply voltage VDD and a transistor bias voltage VBIAS.

[0104] FIG. 10 is a block diagram of one embodiment of advanced control circuitry 1000 for an Al-level converter cell 1000 such as the generalized version depicted in FIG. 8B. The Al- level converter cell 1020 is shown coupled to an output block 1001 comprising an inductor L and an output capacitor COUT (conceptually, the inductor L also may be considered as being included within the Al-level converter cell 1020). The advanced control circuitry 1000 functions as a control loop coupled to the output of the Al-level converter cell 1020 and toswitch control inputs of the AT-level converter cell 1020. In general, the advanced control circuitry 1000 is configured to monitor the output (e.g., voltage and / or current) of the / W-level converter cell 1020 and dynamically generate a set of switch control inputs to the AT-level converter cell 1020 that attempt to stabilize the output voltage and / or current at specified values, taking into account variations of VIN and output load. In alternative embodiments, the advanced control circuitry 1000 may be configured to monitor the input of the A-Z-level converter cell 1020 (e.g., voltage and / or current) and / or an internal node of the -level converter cell 1020 (e.g., the voltage across one or more fly capacitors or the current through one or more power switches). Accordingly, most generally, the advanced control circuitry 1000 may be configured to monitor the voltage and / or current of a node (e.g., input terminal, internal node, or output terminal) of the AT-level converter cell 1020. The advanced control circuitry 1000 may be incorporated into, or separate from, the overall controller for a power converter 100 embodying the AT-level converter cell 1020.

[0105] A first block comprises a feedback controller 1002, which may be a traditional controller such as a fixed frequency voltage mode or current mode controller, a constant-ON- time controller, a hysteretic controller, or any other variant. The feedback controller 1002 is shown as being coupled to VOUT from the AT-level converter cell 1020. In alternative embodiments, the feedback controller 1002 may be configured to monitor the input of the M- level converter cell 1020 and / or an internal node of the A- / - level converter cell 1020. The feedback controller 1002 produces a signal directly or indirectly indicative of the voltage at VOUT that determines in general terms what needs to be done in the multi-level converter cell 1020 to maintain desired values for VOUT: charge, discharge, or tri-state (z.e., open, with no current flow).

[0106] In the illustrated example, the feedback controller 1002 includes a feedback circuit 1004, a compensation circuit 1006, and a PWM generator 1008. The feedback circuit 1004 may include, for example, a feedback-loop voltage detector which compares VOUT (or an attenuated version of VOUT) to a reference voltage which represents a desired VOUT target voltage (which may be dynamic) and outputs a control signal to indicate whether VOUT is above or below the target voltage. The feedback-loop voltage detector may be implemented with a comparison device, such as an operational amplifier (op-amp) or transconductance amplifier (gm amplifier).

[0107] The compensation circuit 1006 is configured to stabilize the closed-loop response of the feedback controller 1002 by avoiding the unintentional creation of positive feedback, which may cause oscillation, and by controlling overshoot and ringing in the step response of the feedback controller 1002. The compensation circuit 1006 may be implemented in known manner, and may include LC and / or RC circuits.

[0108] The PWM generator 1008 generates the actual PWM control signal which ultimately sets the duty cycle of the switches of the multi-level converter cell 1020. In addition, in some embodiments, the PWM generator 1008 may pass on additional optional control signals CTRL indicating, for example, the magnitude of the difference between VOUT and the reference voltage (thus indicating that some levels of the A- / - level converter cell 1020 should be bypassed to get to higher or lower levels), and the direction of that difference (e.g., whether VOUT is greater than or less than the reference voltage). In other embodiments, the optional control signals CTRL can be derived from the output of the compensation circuit 1006, or from the output of the feedback circuit 1004, or from a separate comparator (not shown) coupled to, for example, VOUT. One purpose of the optional control signals CTRL is for advanced control algorithms, when it may be beneficial to know how far away VOUT is from a target output voltage, thus allowing faster charging of the inductor L if the VOUT is severely under regulated.

[0109] A second block comprises a multi-level controller 1010, the primary function of which is to select the switch states that generate a desired VOUT while maintaining a chargebalance state on the fly capacitors within the Af-level converter cell 1020 every time an output voltage level is selected, regardless of what switch state or states were used in the past.

[0110] The multi-level controller 1010 includes a Voltage Level Selector 1012 which receives the PWM control signal and the additional control signals CTRL if available. In addition, the Voltage Level Selector 1012 may be coupled to VOUT and / or VIN, and, in some embodiments, to the HIGH / LOW status signals, CT.v _H / L, from the voltage detectors coupled to corresponding fly capacitors Cx within the Af-level converter cell 1020. A function of the Voltage Level Selector 1012 is to translate the received signals to an output voltage Target Level (e.g., on a cycle-by-cycle basis). The Voltage Level Selector 1012 typically will consider at least VOUT and VIN to determine which Target Level should charge or discharge the output of the A- / - level converter cell 1020 with a desired rate. For example, in a 6-level converter circuit, the available Target Levels are Level-1 (GND), Level-2 (1 / 5VIN), Level-3 (2 / 5VIN),Level-4 (3 / 5VIN), Level-5 (4 / 5VIN), and Level-6 (VIN), which may be represented as a count value from 1-6 (or 0-5).

[0111] As an example, in a 4-Level converter circuit, if VIN = 12V and VOUT nominally should be 3 V, then the Voltage Level Selector 1012 may indicate that a Target Level of “2” can be selected, which results in a 1 / 3 VIN voltage level at Lx (i.e. , 4V). The PWM control signal sets a duty cycle between that Target Level and another Target Level (e.g., GND) so that the average voltage level at Lx will be about 3 V.

[0112] In general, for steady-state operations, the Target Level voltage closest to VOUT that either charges or discharges the inductor L may be selected for simplicity of the selection algorithm. In general, for transient response, a Target Level that is higher (for charging) or lower (for discharging) than the closest Target Level may be selected to quickly charge or discharge the inductor L. The Voltage Level Selector 1012 may be implemented, for example, as a look-up table (LUT) or as comparison circuitry and combinatorial logic or more generalized processor circuitry. In some embodiments, the Voltage Level Selector 1012 can implement advanced methods (described below) that try to speed up charging or discharging based on additional factors, such as inductor voltage drop, load transients, the magnitude of output deviations, and / or external input signals from external sources. The output of the Voltage Level Selector 1012 may include duty cycle information (e.g., derived from the input PWM control signal) as well as switch state.

[0113] The output of the Voltage Level Selector 1012 is coupled to a Multi-Level Switch State Selector 1014, which generally would be coupled to the status signals, CT.v _H / L, from the voltage detectors for the fly capacitors Cx. Taking into account the Target Level generated by the Voltage Level Selector 1012, the Multi-Level Switch State Selector 1014 determines a pattern of switch states for the desired output level that generally achieves charge-balancing the fly capacitors Cx. The Multi-Level Switch State Selector 1014 may be implemented, for example, as comparison circuitry and combinatorial logic, as a look-up table (LUT), or as more generalized processor circuitry. The output of the Multi-Level Switch State Selector 1014 is coupled to the switches of the multi-level converter cell 1020 (through appropriate level-shifter circuits and drivers circuits, as may be needed for a particular converter cell) and includes a pattern of switch state settings determined by the Multi-Level Switch State Selector 1014. The pattern of switch state settings selects the configuration of the switches within the multi-level converter cell 1020.

[0114] In general (but not always), for PWM-based control systems, the Voltage Level Selector 1012 and the -level Switch State Selector 1014 only change their states when the PWM signal changes. For example, when the PWM signal goes high, the Voltage Level Selector 1012 selects which level results in charging of the inductor L and the A-f-level Switch State Selector 1014 sets which version to use of that level. Then when the PWM signal goes low, the Voltage Level Selector 1012 selects which level can discharge the inductor L and the A-f-level Switch State Selector 1014 sets which version of that level to use. Thus, the Voltage Level Selector 1012 and the AT-level Switch State Selector 1014 generally only change states when the PWM signal changes (the PWM signal is in effect their clock signal). However, there may be situations or events where it is desirable for the CTRL signal to change the state of the Voltage Level Selector 1012. Further, there may be situations or events where it is desirable for the CFX H / L status signal(s) to cause the A-f-level Switch State Selector 1014 to select a particular configuration of power switch settings, such as when a severe mid-cycle imbalance occurs. In some embodiments, it may be useful to include a timing function that forces the Al- level Switch State Selector 1014 to re-evaluate the optimal version of the state periodically, for example, in order to avoid being “stuck” at one level for a very long time, potentially causing charge imbalances.

[0115] One notable benefit of the control circuitry shown in FIG. 10 is that it enables generation of voltages in boundary zones between voltage levels, which represent unattainable output voltages for conventional multi-level DC-to-DC converter circuits.

[0116] In alternative unregulated charge-pumps embodiments, the feedback controller 1002 and the Voltage Level Selector 1012 may be omitted, and instead a clock signal CLK may be applied to the A-f-level Switch State Selector 1014. The A-f-level Switch State Selector 1014 would generate a pattern of switch state settings that periodically charge balances the fly capacitors Cx regardless of what switch state or states were used in the past (as opposed to cycling through a pre-defined sequency of states). This ensures that if VIN changes or anomalous evens occur, the system generally always seeks charge balance for the fly capacitors Cx.

[0117] In some embodiments, the A-f-level Switch State Selector 1014 may take into account the current II flowing through the inductor L by way of an optional currentmeasurement input 1016, which may be implemented in conventional fashion.

[0118] In an A- / - level multi-level converter circuit, the configuration of switches that achieves Level-1 (e.g., GND) or Level -AY (e.g., VIN) effectively bypasses the fly capacitors Cx. Conversely, for all intermediate voltage levels, at least one fly capacitor Cx is coupled to VOUT and there are always at least two configurations of switches that can achieve any intermediate voltage level. For any particular intermediate voltage level, at least one configuration of switches results in charging the associated fly capacitor and at least one other configuration of switches results in discharging the associated fly capacitor. One aspect of the present disclosure is the realization that any achievable output voltage VOUT requiring intermediate voltage levels can be attained by dynamically selecting patterns of switch configurations - that is, by selecting switch configurations without regard to or memory of the switch configurations of any previous switching cycle - to select appropriate Levels, and doing so in a way that purposefully selects either charging or discharging switch configurations that also balance charge across the fly capacitors Cx.

[0119] Embodiments of the disclosure use the following approach for positive inductor L current (charging VOUT):(1) a fly capacitor Cx that needs charging will be set to close its charging switch (the outer high-side switch in outer-switch control methods, or the inner low-side switch for inner-switch control methods); and(2) a fly capacitor Cx that needs discharging will be set to close its discharging switch (the outer low-side switch for outer-switch control methods, or the inner high-side switch for inner-switch control methods).

[0120] For negative inductor L current (discharging VOUT), the selection of switches inverts. Accordingly:(1) a fly capacitor Cx that needs charging will be set to close its charging switch (the outer low-side switch in outer-switch control methods, or the inner high-side switch for inner-switch control methods); and(2) a fly capacitor Cx that needs discharging will be set to close its discharging switch (the outer high-side switch for outer-switch control methods, or the inner low-side switch for inner-switch control methods).

[0121] Note again that whether or not charging actually occurs for a particular fly capacitor Cx generally depends on the switch states for all other fly capacitors. For a fly capacitor C(x) to actually charge or discharge, the next inward (if one exists) fly capacitor C(x 7) (for outer-switch control methods) or the previous outward (if one exists) fly capacitor C(x+7) (for inner- switch control methods) must be set to the opposite state (z.e., discharge or charge) so that a bypass situation does not occur.

[0122] For any multi-level converter circuit of order M that can create M voltage levels - z.e., Level-1 (e.g., GND) through Level -M (e.g., VIN) - then the following switch count rules apply for any Level -m:(1) - zzz low-side switches must be set to be closed (ON);(2) m - 1 high-side switches must be set to be closed (ON); and(3) switches that are not required to be ON must be set to be OFF (open).

[0123] With these switch count rules in mind, the following generalized capacitor control method applies for each state change of the Multi-Level Switch State Selector 1014:Step 1) Select a fly capacitor that has not previously been selected;Step 2) If the voltage of the selected fly capacitor is above its Vtarget and there are remaining (z.e., not been set by this method in this cycle) low-side or high-side switches that can be set to be closed to enable a discharge path for the selected fly capacitor, then set those switches that enable a discharge path for the selected fly capacitor to be closed, decrement one or more appropriate counters (e.g., for the number of low-side switches set to be closed and the number of high-side switches set to be closed), and flag the current fly capacitor as “done” (z.e., as having been selected); otherwise (since the voltage of the selected fly capacitor is below its Vtarget) set the switches that enable a charging path for the selected fly capacitor to be closed and flag the current fly capacitor as “done”;Step 3) Loop to Step 1 until all fly capacitors have been selected;Step 4) For the remaining pair of left-over switches, set the high-side switch or the low-side switch to be closed based on the switch count rules and the counter values.

[0124] With the above generalized capacitor control method, more specific multi-level charge-balancing control methods can be created. Examples can be found, for example, in U.S. Patent Publication No. 20230148059, which is incorporated by reference herein in its entirety.

[0125] In various embodiments, a multi-level controller including multi-level control circuitry (e.g., as described in one or more of FIGs. 1 A-10), may be implemented in an integrated circuit (IC). For example, a multi-level controller IC may be electrically coupled to one or more voltage supplies, batteries, fly capacitors, inductors, and other circuitry andcomponents of a host system forming a multi-level power converter as described herein. In some embodiments, a multi-level power converter may be implemented in a system including two or more multi-level controller ICs (e.g., as illustrated in FIGs. 2A-B) operating in parallel providing performance and efficiency advantages over single multi-level controller IC implementations.

[0126] Referring to FIG. 11, an example system 1100 configurable to operate as a power converter including two multi-level controller ICs will now be described, in accordance with embodiments of the present disclosure. In the illustrated embodiment, the system 1100 includes a plurality of multi-level controller ICs, including a first multi-level controller IC 1110 (also referred to herein as the “master controller”) configured to operate as a master controller, and a second multi-level controller IC 1150 (also referred to herein as the “slave controller”) configured as a slave controller. The multi-level controller ICs 1110 and 1150 represent two instances of the same multi-level controller IC. In some embodiments, multilevel controller ICs having a different architectures and / or configurations may be implemented.

[0127] Each multi-level controller IC 1110 and 1152 includes a voltage input terminal, VIN, electrically coupled to a voltage supply 1170 providing an input voltage VIN to each multi-level controller IC. Each multi-level controller IC 1110 and 1152 also includes a COMP terminal (also referred to herein as a compensation pin), with the COMP terminal of the slave controller 1150 electrically coupled to the COMP terminal of the master controller 1110.

[0128] The master controller 1110 includes multi-level control circuitry 1112, and the slave controller 1150 includes multi-level control circuitry 1152. The multi-level control circuitry 1112 and 1152 may include multi-level control circuitry as described herein with respect to FIG. 10, and / or as otherwise described with respect to FIGs. 1 A-9. The multi-level control circuitry 1112 and 1152 include a power switch circuitry for a 4-level converter circuit, including a plurality of switches coupled to: VIN, a plurality of capacitors CA and CB, and one or more inductors LI and L2 through one or more output terminals LX1 and LX2. Example 4-level switching circuitry is described herein with reference to FIG. 8B.

[0129] Although a 4-level power converter is illustrated, it will be appreciated that the embodiments described herein may be applicable to various M-level implementations, whereM >= 3. In operation, the multi-level control circuitry 1112 is configured to control operation of the plurality of power switches to selectively charge and / or discharge one or more capacitors CA / CB in accordance with a mode of operation to generate an output voltage. Similarly, the multi-level control circuitry 1152 is configured to control operation of the plurality of power switches to selectively charge and / or discharge one or more capacitors CA / CB in accordance with the mode of operation to generate an output voltage.

[0130] Each multi-level controller IC 1110 and 1150 is electrically coupled to one or more loads, such as battery 1172. In some embodiments, the battery 1172 is a single cell Li- ion or Li-polymer battery or other battery capable of being charged by the power converter of system 1100. In one mode of operation, each multi-level controller IC 1110 and 1150 is configured to receive a supply voltage Vsupply at a terminal VIN and generate an output voltage VOUT to charge the battery 1172. In an example implementation, each multi-level controller IC 1110 and 1150 may be configured to individually deliver up to 5 amperes (A) of charging current in a regulation mode and in a divide-by-3 charge pump mode, though other configurations delivering more or less ampere are within the scope of the present disclosure. In the dual IC configuration of FIG. 11, the system 1100 may be configured to deliver, for example, 10 amperes of charging current in regulation mode and in divide-by-3 charge pump mode, enabling faster battery charging than a single multi-level controller IC solution.

[0131] In various embodiments, each of the multi-level controller ICs 1110 and 1150 may be configurable to support divide-by-3, step-down and step-up regulating modes, dual external disconnect switch control, and / or paralleled operation. In a dual IC operation, both multi-level controller ICs 1110 and 1150 may be set to the same frequency setting. In some embodiments, the external FETs (e.g., as illustrated in FIGs. 2 A and 2B) may be controlled by the master controller 1110. In a dual IC operation, the slave controller 1150 may be turned on before the master controller 1110 as described with reference to FIGs. 2A-B.

[0132] Referring to FIG. 12, further details of a parallel, dual IC operation of the master controller 1110 and the slave controller 1150 will now be described, in accordance with embodiments of the present disclosure. A system 1200 includes a master multi-level controller IC 1210 and a slave multi-level controller IC 1250, each electrically coupled to a voltage supply 1270. The master multi-level controller IC 1210 is an integrated circuit comprising multi-level control circuitry 1211 such as the advanced control circuitry 1000 as described with reference to FIG. 10, a compensation pin 1226, and other circuitry andcomponents. The multi-level control circuitry 1211 includes a secondary controller 1212, a multi-level controller 1220, and a multi-level converter circuit 1222.

[0133] The multi-level converter circuit 1222 is shown coupled to an output block 1224, which may include an inductor and an output capacitor COUT (e.g., as illustrated in FIG. 11), which may be provided as components of a host system or device. The multi-level control circuitry 1211 functions as a control loop coupled to the output of the multi-level converter circuit 1222 to control power switch circuitry of multi-level converter circuit 1222. In operation, the multi-level control circuitry 1211 is configured to monitor the output (e.g., voltage and / or current) of the multi-level converter circuit 1222 and dynamically generate a set of switch control inputs to the multi-level converter circuit 1222 to stabilize the output voltage and / or current at target values, taking into account variations of VIN and output load. In various embodiments, the multi-level control circuitry 1211 may be configured to monitor the input of the multi-level converter circuit 1222 (e.g., voltage and / or current) and / or an internal node of the multi-level converter circuit 1222 (e.g., the voltage across one or more fly capacitors or the current through one or more power switches).

[0134] The secondary controller 1212, which may be implemented as feedback controller 1002 of FIG. 10, is shown coupled to VOUT, but may be configured to monitor the input of the multi-level converter circuit 1222 and / or an internal node of the multi-level converter circuit 1222. The secondary controller 1212 produces a control signal based on the voltage at VOUT that may be used to adjust the operation of the multi-level converter circuit 1222 to maintain a target voltage.

[0135] In the illustrated embodiment, the secondary controller 1212 includes a feedback circuit 1214, a compensation circuit 1216, and a PWM generator 1218. The feedback circuit 1214 may include, for example, a feedback-loop voltage detector which compares VOUT to a reference voltage representing a desired VOUT target voltage and outputs an error signal indicative of whether VOUT is above or below the target voltage. The feedback-loop voltage detector may be implemented, for example, with a comparison device, such as an operational amplifier (op-amp) or transconductance amplifier (gm amplifier) or other circuitry.

[0136] The compensation circuit 1216 is configured to stabilize the closed-loop response of the secondary controller 1212 by avoiding the unintentional creation of positive feedback, which may cause oscillation, and by controlling overshoot and ringing in the step response ofthe secondary controller 1212. The compensation circuit 1216 may include LC and / or RC circuits. The PWM generator 1218 generates the PWM control signal (and optionally other control information) to set the duty cycle of the switches of the multi-level converter circuit 1222.

[0137] The multi-level controller 1220 selects the switch states of the power switch circuitry of the multi-level converted circuit 1222 that generate a desired VOUT while maintaining a charge-balance state on the fly capacitors. The multi-level controller 1220 may include a voltage level selector (e.g., voltage level selector 1012 as described with reference to FIG. 10), which selects a target level voltage, and a multi-level switch state selector (e.g., multilevel switch state selector 1012 as described with reference to FIG. 10) that determines a pattern of switch states to achieve the desired output level.

[0138] The slave multi-level controller IC 1250 is an integrated circuit comprising multilevel control circuitry 1251, which may include similar components as the multi-level control circuitry 1211 of the master multi-level controller IC 1210, and a compensation pin 1266. The multi-level control circuitry 1251 includes a secondary controller 1252, a multi-level controller 1260, and a multi-level converter circuit 1262. The multi-level converter circuit 1262 is shown coupled to an output block 1264, which may include an inductor and an output capacitor COUT (e.g., as illustrated in FIG. 11), which may be provided as components of a host system or device. In the illustrated embodiment, the multi-level control circuitry 1251 functions as a control loop coupled to the output of the multi-level converter circuit 1262 and to switch control inputs of the multi-level converter circuit 1262. The secondary controller 1252 includes a feedback circuit 1254, a compensation circuit 1256, and a PWM generator 1258.

[0139] During operation, the multi-level controller 1220 generally controls a plurality of switches of the multi-level converter circuit 1222 to selectively charge and / or discharge one or more capacitors in accordance with a mode of operation to generate an output voltage. The secondary controller 1212 provides a control signal, based on an error signal generated by the feedback circuit 1214, to adjust the operation of the multi-level circuit 1222. The feedback circuit 1214 is configured to monitor a voltage level associated with the multi-level converter circuit 1222 and generate the error signal based on a difference between the monitored voltage level and a target voltage level. The error signal (or a signal in another form indicating an operating state) is provided to the compensation pin 1226.

[0140] The multi-level control circuitry 1251 of the slave multi-level controller IC 1250 is configured to operate as a slave in a master-slave mode of operation. During operation, the multi-level controller 1260 generally controls a plurality of switches of the multi-level converter circuit 1262 to selectively charge and / or discharge one or more capacitors in accordance with a mode of operation to generate an output voltage. The secondary controller 1252 bypasses the feedback circuit 1254 and provides a control signal based on a sensed value at the compensation pin 1266, which represents the error signal generated by the feedback circuit 1214 of the master multi-level controller IC 1210.

[0141] The compensation pin 1266 of the slave multi-level controller IC 1250 is electrically coupled to the compensation pin 1226 of the master multi-level controller IC 1210. When operating as a slave, the secondary controller 1252 reads the compensation voltage from compensation pin 1266 and provides the compensation voltage as an input to the compensation circuit 1256 in place of an error signal generated by the feedback circuit 1254. The secondary controller 1252 generates the control signal for adjusting operation of the multi-level controller 1260 based on the received compensation voltage.

[0142] In various embodiments, the master multi-level controller IC 1210 and the slave multi-level controller IC 1250 may be identical ICs, arranged and configured for a masterslave mode of operation. In some embodiments, the ICs may be pre-configured for operation as dedicated master and / or slave ICs. Although embodiments including two instances of a multi-level controller IC that operate in parallel in a master-slave operation are described, it will be appreciated that 2 or more slave multi-level controller ICs may be implemented in the same system. For example, the master multi-level controller IC may provide an error signal via the compensation pins to each of the slave controllers for use in the respective control loops to determine the appropriate voltage level and switch state to provide regulation. In some embodiments, the compensation voltage corresponds to a current level. For example, each volt of the compensation voltage may correspond to 1 amp of current.

[0143] In some embodiments, the master controller IC and slave controller IC may be assigned by a programming pin, set by a digital communication bus such as I2C or SMBUS, or via other known methods. In some embodiments, each of the master controller IC and slave controller IC regulate its own current, while the master controller IC controls the voltage mode.

[0144] As previously discussed, the master secondary controller 1212 and the slave secondary controller 1252 each includes 3 control loops to provide regulation. Referring to FIG. 13, the control loops will now be described in further detail, in accordance with embodiments of the present disclosure. As illustrated, each secondary controller 1300 (e.g., secondary controllers 1212 and 1252 of FIG. 12) includes an outer loop 1310, a middle loop 1330, and an inner loop 1350.

[0145] The outer loop 1310 includes a feedback circuit that generates a current error signal, IERROR, from an output voltage, VOUT, and a voltage error reference. In some embodiments, the feedback circuit may be implemented as a transconductance amplifier 1312 configurable to receive the output voltage, VOUT, and a voltage error reference, VREF, and output the current error signal, IERROR, based on a difference between the output voltage and a reference voltage. The output may be coupled to a resistor-capacitor circuit 14 connected in series between the transconductance amplifier and the middle loop 1330.

[0146] The middle loop 1330 includes a compensation circuit that compares the error signal generated in the outer loop 1310 to an average inductor current value. In some embodiments, the compensation circuit is implemented using a comparator 1332 configured to compare the error signal to an average inductor current value.

[0147] The inner loop 1350 includes a pulse-width modulation (PWM) generator 1352 configurable to compare an output of the compensation circuit 1332 to a peak current value associated with an inductor (e.g., the inductor(s) in the output block coupled to the secondary controller) electrically couplable to a low-side of the multi-level converter circuit. The PWM generator 1352 is configured to generate a PWM signal based on the comparison.

[0148] In an example operation, the master controller IC regulates the output voltage and / or the output current, and the slave controller disables its respective outer loop and receives an error signal generated from the transconductance amplifier of the master controller through the compensation pins. The slave controller uses the compensation voltage from the master controller to regulate a voltage level and a current level of the output voltage.

[0149] In some embodiments, the master controller IC may be connected to a first inductor, and the slave controller IC may be connected to a second inductor that is different in size. In this arrangement, the master controller IC and the slave controller IC may be tuned to different current levels, facilitating further optimization. For example, at low currents thecontroller IC coupled to the larger inductor may be used to charge a battery. In some embodiments, the master controller IC and the slave controller IC may be connected to inductors having the same properties.

[0150] In some embodiments, the multi-level control circuitry may be configurable to operate in a standalone mode of operation, as a master in the master-slave mode of operation, or a slave in a master-slave mode of operation. When operating in the standalone mode of operation or as a master, the multi-level control circuitry is configured to generate the compensation voltage for the compensation pin.

[0151] In some embodiments, the master multi-level control circuitry is configured as buck converter tuned to a first current level associated with an inductor coupled to the multilevel converter circuit of the master multi-level control circuitry, and the slave multi-level control circuitry is configured as a buck converter tuned to a second current level, different than the first current level and associated with an inductor coupled to the multi-level converter circuit of the slave multi-level control circuitry. In some embodiments, the master multi-level controller IC and the slave multi-level controller IC are each configured as a buck converter tuned to the same current level.

[0152] Referring to FIG. 14, an example process 1400 for operating a plurality of multilevel power converter ICs in a master-slave mode will now be described, in accordance with embodiments of the present disclosure. In various embodiments, the process 1400 may be executed by any control circuitry or controller configurable to operate and / or configure a multi-level power converter, such as the advanced control circuitry 1000 as described with reference to FIG. 10, the multi-level control circuitry 1211 and 1251 of FIG. 12 and / or as otherwise described herein with reference to FIGs. 1A-13. The multi-level power converter ICs may be implemented as any multi-level power converter, such as described herein with reference to FIGs. 1A-13.

[0153] At block 1402, a first multi-level controller IC is configured for operation as a master multi-level controller. In some embodiments, configuring the multi-level controller IC as a master multi-level controller may be performed, for example, by setting one or more registers or other configuration settings as described with reference to FIGs. 1 A-6.

[0154] Next, at block 1404, one or more additional multi-level controller ICs are configured for operation as slave multi-level controllers. In some embodiments, configuringthe multi-level controller IC as a slave multi-level controller may be performed, for example, by setting one or more registers or other configuration settings and / or by implementing configuring settings directed by the master multi-level controller, as described with reference to FIGs. 1 A-6.

[0155] At block 1406, the master multi-level controller IC compensation pin is electrically coupled to each slave multi-level controller IC compensation pin. In this configuration, the voltage at each slave compensation pin is controlled by the compensation pin of the master multi-level controller.

[0156] At blocks 1408 and 1410, the master controller IC and the slave controller ICs are operated in parallel. Generally, the master multi-level controller IC and the slave multi-level controller ICs are configured to control operation of power switch circuitry in a multi-level converter circuit to selectively charge and / or discharge one or more capacitors in accordance with a mode of operation (e.g., a buck mode) to generate an output voltage, and the operation of the power switch circuitry is adjusted by the multi-level controller based on a control signal.

[0157] At block 1408, the master multi-level controller IC is operated using a master feedback control loop which senses an operational voltage and generates a control signal to adjust operation towards a target voltage. In some embodiments, the master multi-level controller IC is configured to generate the compensation voltage at the master multi-level controller compensation pin, compute an error signal based on a sensed voltage level associated with the power switch circuitry of the master multi-level controller IC, and generate the control signal to adjust operation of the master multi-level controller power switch circuitry towards a target voltage level.

[0158] In some embodiments, the master controller is further configured to compute, using a feedback circuit, a current error signal based on a difference between the output voltage and a reference voltage. The method may further include comparing, using a comparator circuit of the master multi-level controller IC, the current error signal to an average current value of an inductor electrically coupled to the master multi-level controller power switch circuitry. The method may further include comparing an output of the comparator circuit to a peak current value associated with the inductor to generate the control signal using a pulse-width modulation generator.

[0159] At block 1410, each slave multi-level controller IC is operated using the master multi-level controller IC compensation signal (as set by the master multi-level controller IC compensation pin) as input to a modified feedback control loop. Unlike the master feedback control loop which senses an operational voltage of the IC, the modified feedback control loop uses the compensation signal in place of a feedback error signal to generate a control signal to adjust operation of the slave multi-level controller IC towards the target voltage. In some embodiments, each slave multi-level controller IC is configured to sense, at the slave multi-level controller compensation pin, a compensation voltage generated by the master multi-level controller compensation pin, and generate the control signal to adjust operation of the slave multi-level multi-level controller IC power switch circuitry based on the sensed compensation voltage.

[0160] The method may further include using the compensation voltage sensed at the slave multi-level controller compensation pin as the current error signal in the modified feedback control loop. The method may further include comparing, using the slave multilevel controller comparator circuit, the current error signal to an average inductor current value, and comparing an output of the comparator circuit to a peak current value associated with an inductor to generate the control signal for adjusting operation of slave multi-level controller using a pulse-width modulation generator. In some embodiments, the method further comprises disabling and / or bypassing the feedback circuit of the slave multi-level controller.

[0161] Aspect 1 includes an integrated circuit comprising: a compensation pin; power switch circuitry coupled between a first terminal and a second terminal; a multi-level control circuitry configurable to: control operation of the power switch circuitry to selectively charge and / or discharge one or more capacitors in accordance with a mode of operation to generate an output voltage; adjust the operation of the power switch circuitry in accordance with a control signal based on an error signal; and operate as a slave in a master-slave mode of operation, wherein the multi-level controller is further configurable to receive, at the compensation pin, a compensation voltage generated from a master multi-level power converter; and a feedback circuit configurable to monitor a voltage level associated with the power switch circuitry and generate the error signal; and wherein, when operating as a slave in the masterslave mode of operation, the multi-level controller uses the compensation voltage received at the compensation pin from the master multi-level power converter as the error signal.

[0162] Aspect 2 includes the integrated circuit of aspect 1, wherein the multi-level controller is further configurable to operate in a standalone mode of operation, and as a master in the master-slave mode of operation; and wherein, if operating in the standalone mode of operation or as a master in the master-slave mode of operation, the multi-level controller is configured to generate the compensation voltage for the compensation pin.

[0163] Aspect 3 includes the integrated circuit of any of aspects 1-2, wherein the feedback circuit comprises: a transconductance amplifier configurable to output a current error signal based on a difference between the output voltage and a reference voltage.

[0164] Aspect 4 includes the integrated circuit of any of aspects 1-3, further comprising a compensation circuit comprising: a comparator configurable to compare the error signal to an average inductor current value.

[0165] Aspect 5 includes the integrated circuit of any of aspects 1-4, further comprising a resistor-capacitor circuit connected in series between the transconductance amplifier and the comparator.

[0166] Aspect 6 includes the integrated circuit of any of aspects 1-5, further comprising a compensation circuit configurable to receive the error signal from the feedback circuit and stabilize a response of the feedback circuit.

[0167] Aspect 7 includes the integrated circuit of any of aspects 1-6, further comprising a pulse-width modulation (PWM) generator configurable to compare an output of the compensation circuit to a peak current value associated with an inductor electrically couplable to a low-side of the power switch circuitry and generate the control signal.

[0168] Aspect 8 includes the integrated circuit of any of aspects 1-7, wherein in the master-slave mode of operation, the master multi-level power converter is configured as buck converter tuned to a first current level and the slave is configured as a buck converter tuned to a second current level, different than the first current level.

[0169] Aspect 9 includes the integrated circuit of any of aspects 1-8, wherein in the master-slave mode of operation, the master multi-level power converter and the slave are each configured as a buck converter tuned to a first current level.

[0170] Aspect 10 includes the integrated circuit of any of aspects 1-9, wherein if the multi-level controller is configured to operate as a slave in a master-slave mode of operation, the compensation voltage is used to regulate a voltage level and a current level of the output voltage.

[0171] Aspect 11 includes the integrated circuit of any of aspects 1-10, wherein if the multi-level controller is configured to operate as a slave in a master-slave mode of operation, the multi-level controller is further configured to disable the feedback circuit.

[0172] Aspect 12 includes a method comprising: configuring a multi-level controller of a first integrated circuit to control operation of power switch circuitry to selectively charge and / or discharge one or more capacitors in accordance with a mode of operation to generate an output voltage, wherein operation of the power switch circuitry is adjusted by the multilevel controller based on a control signal; electrically coupling a first compensation pin of the first integrated circuit with a second compensation pin of a second integrated circuit; and if the multi-level controller is configured as a slave in a master-slave mode of operation, the method further comprises: sensing, at the first compensation pin, a compensation voltage generated by the second compensation pin; and generating the control signal to adjust operation of the power switch circuitry based on the sensed compensation voltage.

[0173] Aspect 13 includes the method of aspect 12, wherein if the multi-level controller is configured as a master in a master-slave mode of operation, the method further comprises: generating the compensation voltage for the first compensation pin; and computing an error signal based on a sensed voltage level associated with the power switch circuitry; and generating the control signal to adjust operation of the power switch circuitry to generate the output voltage at a target voltage level.

[0174] Aspect 14 includes the method of any of aspects 12-13, wherein if the multi-level controller is configured as a master in the master-slave mode of operation, the method further comprises: computing, using a feedback circuit, a current error signal based on a difference between the output voltage and a reference voltage; comparing, using a comparator circuit, the current error signal to an average current value of an inductor electrically coupled to the power switch circuitry; and comparing an output of the comparator circuit to a peak current value associated with the inductor to generate the control signal using a pulse-width modulation generator.

[0175] Aspect 15 includes the method of any of aspects 12-14, wherein if the multi-level controller is configured as a slave in the master-slave mode of operation, the method further comprises: using the compensation voltage sensed at the first compensation pin as the current error signal; comparing, using the comparator circuit, the current error signal to an average inductor current value; and comparing an output of the comparator circuit to a peak current value associated with an inductor to generate the control signal using a pulse-width modulation generator.

[0176] Aspect 16 includes the method of any of aspects 12-15, wherein if the multi-level controller is configured as a slave in the master-slave mode of operation, the method further comprises disabling and / or bypassing the feedback circuit.

[0177] Aspect 17 includes a system comprising: a plurality of integrated circuits comprising a first integrated circuit configured to operate as a master integrated circuit and at least one integrated circuit configured to operate as a slave integrated circuit, each integrated circuit comprising: a compensation pin; power switch circuitry coupled between a first terminal and a second terminal; a multi-level controller configurable to: control operation of the power switch circuitry to selectively charge and / or discharge one or more capacitors to generate an output voltage in accordance with a mode of operation comprising operating as a master in a master-slave mode of operation or operating as a slave in the master-slave mode of operation; adjust the operation of the power switch circuitry in accordance with a control signal; generate a compensation voltage for the compensation pin if configured as the master in the master-slave mode of operation; and if the multi-level controller is configured as the slave in the master-slave mode of operation, receive at the compensation pin the compensation voltage generated from one of the plurality of integrated circuits configured as the master in the master-slave mode of operation; and a secondary controller configurable to: generate the control signal based on an error signal; wherein the secondary controller comprises a feedback circuit configurable to monitor a voltage level of the power switch circuitry to generate the error signal when the multi-level controller is configured as a master in the master-slave mode of operation; and wherein, if the multi-level controller is configured as a slave in a master-slave mode of operation, the compensation voltage received from the master integrated circuit is used as the error signal.

[0178] Aspect 18 includes the system aspect 17, wherein the feedback circuit comprises a transconductance amplifier configurable to output a current error signal based on a differencebetween the output voltage and a reference voltage; and wherein the secondary controller further comprises: a compensation circuit comprising a comparator circuit configurable to compare the error signal to an average current value of an inductor electrically coupled to the power switch circuitry; and a pulse-width modulation (PWM) generator configurable to compare an output of the compensation circuit to a peak current value associated with the inductor to generate the control signal.

[0179] Aspect 19 includes the system of any of aspects 17-18, wherein the secondary controller uses the compensation voltage to regulate a voltage and a current output.

[0180] Aspect 20 includes the system of any of aspects 17-19, wherein each slave multilevel controller is configurable to disable the feedback circuit and use the error signal received from the master integrated circuit.

[0181] General Benefits and Advantages of Multi-Level Power Converters

[0182] Embodiments of the current invention improve the power density and / or power efficiency of incorporating circuits and circuit modules or blocks. As a person of ordinary skill in the art should understand, a system architecture is beneficially impacted utilizing embodiments of the current invention in critical ways, including lower power and / or longer battery life. The current invention therefore specifically encompasses system-level embodiments that are creatively enabled by inclusion in a large system design and application.

[0183] More particularly, multi-level power converters provide or enable numerous benefits and advantages, including:

[0184] - adaptability to applications in which input and / or output voltages may have a wide dynamic-range (e.g., varying battery input voltage levels, varying output voltages);

[0185] - efficiency improvements on the run-time of devices operating on portable electrical energy sources (batteries, generators or fuel cells using liquid or gaseous fuels, solar cells, etc.);

[0186] - efficiency improvements where efficiency is important for thermal management, particularly to protect other components (e.g, displays, nearby ICs) from excessive heat;

[0187] - enabling design optimizations for power efficiency, power density, and formfactor of the power converter - for example, smaller-size multi-level power converters may allow placing power converters in close proximity to loads, thus increasing efficiency, and / or to lower an overall bill of materials;

[0188] - the ability to take advantage of the performance of smaller, low voltage transistors;

[0189] - adaptability to applications in which power sources can vary widely, such as batteries, other power converters, generators or fuel cells using liquid or gaseous fuels, solar cells, line voltage (AC), and DC voltage sources (e.g., USB, USB-C, power-over Ethernet, etc.);

[0190] - adaptability to applications in which loads may vary widely, such as ICs in general (including microprocessors and memory ICs), electrical motors and actuators, transducers, sensors, and displays (e.g., LCDs and LEDs of all types);

[0191] - the ability to be implemented in a number of IC technologies (e.g., MOSFETs,GaN, GaAs, and bulk silicon) and packaging technologies (e.g., flip chips, ball-grid arrays, wafer level scale chip packages, wide-fan out packaging, and embedded packaging).

[0192] The advantages and benefits of multi-level power converters enable usage in a wide array of applications. For example, applications of multi-level power converters include portable and mobile computing and / or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, and cell phones), displays (e.g., LCDs, LEDs), radio-based devices and systems (e.g., cellular systems, WiFi, Bluetooth, Zigbee, Z- Wave, and GPS-based devices), wired network devices and systems, data centers (e.g., for battery -backup systems and / or power conversion for processing systems and / or electronic / op- tical networking systems), internet-of-things (IOT) devices (e.g., smart switches and lights, safety sensors, and security cameras), household appliances and electronics (e.g., set-top boxes, battery-operated vacuum cleaners, appliances with built-in radio transceivers such as washers, dryers, and refrigerators), AC / DC power converters, electric vehicles of all types (e.g., for drive trains, control systems, and / or infotainment systems), and other devices and systems that utilize portable electricity generating sources and / or require power conversion.

[0193] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, and WiFi (e.g., 802.1 la, b, g, ac, ax), as well as other radio communication standards and protocols.

[0194] Programmable Embodiments

[0195] Some or all aspects of the invention, particularly the Multi-Level Switch State Selector 1014 of FIG. 10, may be implemented in hardware or software, or a combination of both (e.g., programmable logic arrays). Unless otherwise specified, the algorithms included as part of the invention are not inherently related to any particular computer or other apparatus. In particular, various general purpose computing machines may be used with programs written in accordance with the teachings herein, or it may be more convenient to use a special purpose computer or special-purpose hardware (such as integrated circuits) to perform particular functions. Thus, embodiments of the invention may be implemented in one or more computer programs (z.e., a set of instructions or codes) executing on one or more programmed or programmable computer systems (which may be of various architectures, such as distributed, client / server, or grid) each comprising at least one processor, at least one data storage system (which may include volatile and non-volatile memory and / or storage elements), at least one input device or port, and at least one output device or port. Program instructions or code may be applied to input data to perform the functions described in this disclosure and generate output information. The output information may be applied to one or more output devices in known fashion.

[0196] Each such computer program may be implemented in any desired computer language (including machine, assembly, or high-level procedural, logical, or object-oriented programming languages) to communicate with a computer system, and may be implemented in a distributed manner in which different parts of the computation specified by the software are performed by different computers or processors. In any case, the computer language may be a compiled or interpreted language. Computer programs implementing some or all of the invention may form one or more modules of a larger program or system of programs. Some or all of the elements of the computer program can be implemented as data structures stored in acomputer readable medium or other organized data conforming to a data model stored in a data repository.

[0197] Each such computer program may be stored on or downloaded to (for example, by being encoded in a propagated signal and delivered over a communication medium such as a network) a tangible, non-transitory storage media or device (e.g., solid state memory media or devices, or magnetic or optical media) for a period of time (e.g., the time between refresh periods of a dynamic memory device, such as a dynamic RAM, or semi-permanently or permanently), the storage media or device being readable by a general or special purpose programmable computer or processor for configuring and operating the computer or processor when the storage media or device is read by the computer or processor to perform the procedures described above. The inventive system may also be considered to be implemented as a non-transitory computer-readable storage medium, configured with a computer program, where the storage medium so configured causes a computer or processor to operate in a specific or predefined manner to perform the functions described in this disclosure.

[0198] Fabrication Technologies & Options

[0199] In various embodiments of multi-level power converters, it may be beneficial to use specific types of capacitors, particularly for the fly capacitors. For example, it is generally useful for such capacitors to have low equivalent series resistance (ESR), low DC bias degradation, high capacitance, and small volume. Low ESR is especially important for multi-level power converters that incorporate additional switches and fly capacitors to increase the number of voltage levels. Selection of a particular capacitor should be made after consideration of specifications for power level, efficiency, size, etc. Various types of capacitor technologies may be used, including ceramic (including multi-layer ceramic capacitors), electrolytic capacitors, film capacitors (including power film capacitors), and IC -based capacitors. Capacitor dielectrics may vary as needed for particular applications, and may include dielectrics that are paraelectric, such as silicon dioxide (SiCE), hafnium dioxide (HFO2), or aluminum oxide AI2O3. In addition, multi-level power converter designs may beneficially utilize intrinsic parasitic capacitances (e.g., intrinsic to the power FETs) in conjunction with or in lieu of designed capacitors to reduce circuit size and / or increase circuit performance. Selection of capacitors for multi-level power converters may also take into account such factors as capacitor component variations, reduced effective capacitance with DC bias, and ceramic capacitortemperature coefficients (minimum and maximum temperature operating limits, and capacitance variation with temperature).

[0200] Similarly, in various embodiments of multi-level power converters, it may be beneficial to use specific types of inductors. For example, it is generally useful for the inductors to have low DC equivalent resistance, high inductance, and small volume.

[0201] The controlled s) used to control startup and operation of a multi-level power converter may be implemented as a microprocessor, a microcontroller, a digital signal processor (DSP), register-transfer level (RTL) circuitry, and / or combinatorial logic.

[0202] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and / or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0203] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0204] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions have been greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0205] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated usingany suitable substrates and processes, including but not limited to standard bulk silicon, high- resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (z.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0206] Voltage levels may be adjusted, and / or voltage and / or logic signal polarities reversed, depending on a particular specification and / or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0207] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, testequipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0208] A number of embodiments of the disclosure have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0209] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the disclosure, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the disclosure includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

CLAIMSWHAT IS CLAIMED IS:

1. An integrated circuit comprising: a compensation pin; power switch circuitry coupled between a first terminal and a second terminal; a multi-level control circuitry configurable to: control operation of the power switch circuitry to selectively charge and / or discharge one or more capacitors in accordance with a mode of operation to generate an output voltage; adjust the operation of the power switch circuitry in accordance with a control signal based on an error signal; and operate as a slave in a master-slave mode of operation, wherein the multi-level controller is further configurable to receive, at the compensation pin, a compensation voltage generated from a master multi-level power converter; and a feedback circuit configurable to monitor a voltage level associated with the power switch circuitry and generate the error signal; and wherein, when operating as a slave in the master-slave mode of operation, the multilevel controller uses the compensation voltage received at the compensation pin from the master multi-level power converter as the error signal.

2. The integrated circuit of claim 1, wherein the multi-level controller is further configurable to operate in a standalone mode of operation, and as a master in the master-slave mode of operation; and wherein, if operating in the standalone mode of operation or as a master in the masterslave mode of operation, the multi-level controller is configured to generate the compensation voltage for the compensation pin.

3. The integrated circuit of claim 1, wherein the feedback circuit comprises: a transconductance amplifier configurable to output a current error signal based on a difference between the output voltage and a reference voltage.

4. The integrated circuit of claim 3, further comprising a compensation circuit comprising:a comparator configurable to compare the error signal to an average inductor current value.

5. The integrated circuit of claim 4, further comprising a resistor-capacitor circuit connected in series between the transconductance amplifier and the comparator.

6. The integrated circuit of claim 1, further comprising a compensation circuit configurable to receive the error signal from the feedback circuit and stabilize a response of the feedback circuit.

7. The integrated circuit of claim 6, further comprising a pulse-width modulation (PWM) generator configurable to compare an output of the compensation circuit to a peak current value associated with an inductor electrically couplable to a low-side of the power switch circuitry and generate the control signal.

8. The integrated circuit of claim 1, wherein in the master-slave mode of operation, the master multi-level power converter is configured as buck converter tuned to a first current level and the slave is configured as a buck converter tuned to a second current level, different than the first current level.

9. The integrated circuit of claim 1, wherein in the master-slave mode of operation, the master multi-level power converter and the slave are each configured as a buck converter tuned to a first current level.

10. The integrated circuit of claim 1, wherein if the multi-level controller is configured to operate as a slave in a master-slave mode of operation, the compensation voltage is used to regulate a voltage level and a current level of the output voltage.

11. The integrated circuit of claim 1, wherein if the multi-level controller is configured to operate as a slave in a master-slave mode of operation, the multi-level controller is further configured to disable the feedback circuit.

12. A method comprising:configuring a multi-level controller of a first integrated circuit to control operation of power switch circuitry to selectively charge and / or discharge one or more capacitors in accordance with a mode of operation to generate an output voltage, wherein operation of the power switch circuitry is adjusted by the multi-level controller based on a control signal; electrically coupling a first compensation pin of the first integrated circuit with a second compensation pin of a second integrated circuit; and if the multi-level controller is configured as a slave in a master-slave mode of operation, the method further comprises: sensing, at the first compensation pin, a compensation voltage generated by the second compensation pin; and generating the control signal to adjust operation of the power switch circuitry based on the sensed compensation voltage.

13. The method of claim 12, wherein if the multi-level controller is configured as a master in a master-slave mode of operation, the method further comprises: generating the compensation voltage for the first compensation pin; and computing an error signal based on a sensed voltage level associated with the power switch circuitry; and generating the control signal to adjust operation of the power switch circuitry to generate the output voltage at a target voltage level.

14. The method of claim 12, wherein if the multi-level controller is configured as a master in the master-slave mode of operation, the method further comprises: computing, using a feedback circuit, a current error signal based on a difference between the output voltage and a reference voltage; comparing, using a comparator circuit, the current error signal to an average current value of an inductor electrically coupled to the power switch circuitry; and comparing an output of the comparator circuit to a peak current value associated with the inductor to generate the control signal using a pulse-width modulation generator.

15. The method of claim 14, wherein if the multi-level controller is configured as a slave in the master-slave mode of operation, the method further comprises: using the compensation voltage sensed at the first compensation pin as the current error signal;comparing, using the comparator circuit, the current error signal to an average inductor current value; and comparing an output of the comparator circuit to a peak current value associated with an inductor to generate the control signal using a pulse-width modulation generator.

16. The method of claim 14, wherein if the multi-level controller is configured as a slave in the master-slave mode of operation, the method further comprises disabling and / or bypassing the feedback circuit.

17. A system comprising: a plurality of integrated circuits comprising a first integrated circuit configured to operate as a master integrated circuit and at least one integrated circuit configured to operate as a slave integrated circuit, each integrated circuit comprising: a compensation pin; power switch circuitry coupled between a first terminal and a second terminal; a multi-level controller configurable to: control operation of the power switch circuitry to selectively charge and / or discharge one or more capacitors to generate an output voltage in accordance with a mode of operation comprising operating as a master in a master-slave mode of operation or operating as a slave in the master-slave mode of operation; adjust the operation of the power switch circuitry in accordance with a control signal; generate a compensation voltage for the compensation pin if configured as the master in the master-slave mode of operation; and if the multi-level controller is configured as the slave in the masterslave mode of operation, receive at the compensation pin the compensation voltage generated from one of the plurality of integrated circuits configured as the master in the master-slave mode of operation; and a secondary controller configurable to: generate the control signal based on an error signal; wherein the secondary controller comprises a feedback circuit configurable to monitor a voltage level of the power switch circuitry togenerate the error signal when the multi-level controller is configured as a master in the master-slave mode of operation; and wherein, if the multi-level controller is configured as a slave in a master-slave mode of operation, the compensation voltage received from the master integrated circuit is used as the error signal.

18. The system of claim 17, wherein the feedback circuit comprises a transconductance amplifier configurable to output a current error signal based on a difference between the output voltage and a reference voltage; and wherein the secondary controller further comprises: a compensation circuit comprising a comparator circuit configurable to compare the error signal to an average current value of an inductor electrically coupled to the power switch circuitry; and a pulse-width modulation (PWM) generator configurable to compare an output of the compensation circuit to a peak current value associated with the inductor to generate the control signal.

19. The system of claim 17, wherein the secondary controller uses the compensation voltage to regulate a voltage and a current output.

20. The system of claim 17, wherein each slave multi-level controller is configurable to disable the feedback circuit and use the error signal received from the master integrated circuit.

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