Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure. The method comprises: providing a substrate; forming a gate structure on the substrate; forming a threshold-voltage-adjustment region in the substrate, wherein the threshold-voltage-adjustment region has threshold-voltage-adjusting ions; and forming a lightly doped drain region in the substrate, wherein the lightly doped drain region has light-doping ions. Threshold-voltage-adjusting ions are implanted after a gate structure is formed, such that the threshold-voltage-adjusting ions have a deeper implantation depth outside a channel region. The implantation of light-doping ions is performed after the implantation of the threshold-voltage-adjusting ions, and since the threshold-voltage-adjusting ions have a deeper implantation depth outside the channel region, the formation of deeper and more hierarchical junction depths in source-drain regions by the implanted light-doping ions is thus facilitated, thereby alleviating the hot carrier injection effect. During such procedure, it is not necessary to increase the implantation energy and annealing heat for the light-doping ions, thereby effectively reducing damage to the structure and performance of a device. Moreover, it is also not necessary to perform non-self-aligned masked ion implantation, thereby effectively simplifying the process.

Description

Method for forming semiconductor structure

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 18, 2024, with application number 202410077877.4 and invention name “Method for Forming a Semiconductor Structure”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art

[0003] Input / output (I / O) devices are crucial components in integrated circuits. Compared to core devices, I / O devices feature high operating voltages and high drive capabilities. However, under high operating voltages, the I / O device channel generates strong lateral electric fields, which can easily lead to hot carrier injection (HCI).

[0004] In advanced CMOS processes, the hot carrier injection (HCI) effect in input / output (I / O) devices is an increasingly significant challenge. The reasons are as follows: The operating voltage of I / O devices is typically 2.5V, which inherently creates a significant HCI effect. Furthermore, the operating voltage often reaches 3.3V, placing even higher demands on HCI reliability. If the core device and I / O device share a well region, the I / O device will have a heavier well doping, hindering the formation of a layered lightly doped drain (LDD) region and, in turn, hindering HCI improvement. In advanced CMOS analog applications and embedded processes, I / O devices typically operate at 5V, where HCI is even more pronounced than in 2.5V devices. With the advancement of process nodes, the thickness of the polysilicon gates in CMOS devices has been significantly reduced, placing greater restrictions on the injection depth of ions into the source and drain of the device, further hindering HCI improvement.

[0005] However, the existing technology still has many problems in improving the hot carrier injection effect.

[0006] Summary of the Invention

[0007] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which improves the hot carrier injection effect while simplifying the process steps and reducing damage to the device structure performance.

[0008] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a gate structure on the substrate; after forming the gate structure, injecting threshold voltage adjustment ions into the substrate, the threshold voltage adjustment ions penetrating the gate structure to form a threshold voltage adjustment region in the substrate; after forming the threshold voltage adjustment region, injecting lightly doped ions into the substrate using the gate structure as a mask to form a lightly doped drain region in the substrate, the lightly doped ions having an electrical type opposite to that of the threshold voltage adjustment ions; forming sidewalls on the sidewalls of the gate structure; injecting source and drain ions into the substrate using the gate structure and the sidewalls as masks to form a source and drain doped region in the substrate, the source and drain ions having the same electrical type as the lightly doped ions.

[0009] Optionally, before forming the gate structure, the method further includes: forming a well region in the substrate, wherein the well region contains well ions, and the well ions are of the same electrical type as the threshold voltage adjustment ions.

[0010] Optionally, the method for forming the well region includes: injecting the well region ions into the substrate to form the well region in the substrate.

[0011] Optionally, after forming the gate structure and before forming the lightly doped drain region, the method further includes: forming a well region in the substrate, wherein the well region has well ions, and the well ions are of the same electrical type as the threshold voltage adjustment ions.

[0012] Optionally, the method for forming the well region includes: injecting the well region ions into the substrate, wherein the well region ions penetrate the gate structure to form the well region in the substrate.

[0013] Optionally, the threshold voltage adjustment region, the lightly doped drain region and the source-drain doped region are located in the well region.

[0014] Optionally, the threshold voltage adjustment ions include: P-type ions or N-type ions; P-type ions include: boron ions, BF2 - ions or indium ions; N-type ions include: phosphorus ions or arsenic ions.

[0015] Optionally, the gate structure includes: a gate dielectric layer, and a gate layer located on the gate dielectric layer.

[0016] Optionally, the method for forming the sidewall includes: forming an initial sidewall on the sidewall and top surface of the gate structure and the surface of the substrate; and etching back the initial sidewall until the top surface of the gate structure and the surface of the substrate are exposed to form the sidewall.

[0017] Optionally, the method for forming the lightly doped drain region includes: injecting lightly doped ions into the substrate using the gate structure as a mask to form an initial lightly doped drain region in the substrate; and performing a first annealing treatment on the initial lightly doped drain region to form the lightly doped drain region.

[0018] Optionally, the method for forming the source-drain doped region includes: injecting source-drain ions into the substrate using the gate structure and the side wall as a mask to form an initial source-drain doped region in the substrate; and performing a second annealing treatment on the initial source-drain doped region to form the source-drain doped region.

[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0020] In the method for forming a semiconductor structure of the technical solution of the present invention, the threshold voltage adjustment ion implantation is performed after the gate structure is formed. The threshold voltage adjustment ion requires a relatively large implantation energy to ensure that it penetrates the gate structure and enters the channel region, thereby completing the adjustment of the threshold voltage. Outside the channel region, the threshold voltage adjustment ion is implanted at a relatively deep depth due to the absence of the gate structure. The lightly doped ion implantation is performed after the threshold voltage adjustment ion implantation. Since the threshold voltage adjustment ion has a deeper implantation depth outside the channel region, the implanted lightly doped ion is facilitated to form a deeper and more layered junction depth in the source and drain region, thereby improving the hot carrier injection effect. In this process, there is no need to increase the implantation energy and annealing heat of the lightly doped ion, effectively reducing damage to the device structure and performance. At the same time, there is no need to use non-self-aligned mask ion implantation, effectively simplifying the process and improving process efficiency.

[0021] Furthermore, after forming the gate structure and before forming the lightly doped drain region, it also includes: forming a well region in the substrate, wherein the well region contains well ions, and the well ions are of the same electrical type as the threshold voltage adjustment ions. Since the well ions need to penetrate the gate structure, the energy of the well ions injected after the gate structure is formed is higher than the energy of the well ions injected before the gate structure is formed. Since the well ions are injected in a maskless manner, the well ions finally injected into the channel region are shielded by the gate structure, so the injection depth of the well ions in the channel region is shallow. Outside the channel region, since there is no shielding from the gate structure, the injection depth of the well ions is deeper, which is conducive to the lightly doped ions injected outside the channel region to form a deeper and more layered junction depth, further improving the hot carrier injection effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] 1 to 3 are schematic structural diagrams of various steps of a method for forming a semiconductor structure;

[0023] 4 to 10 are schematic structural diagrams of various steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0024] 11 to 17 are schematic structural diagrams of various steps of a method for forming a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0025] As described in the background art, the prior art still has many problems in improving the hot carrier injection effect, which will be described in detail below with reference to the accompanying drawings.

[0026] 1 to 3 are schematic structural diagrams of various steps of a method for forming a semiconductor structure.

[0027] Please refer to Figure 1, provide a substrate 100; inject well region ions into the substrate 100 to form a well region 101 in the substrate 100; inject threshold voltage adjustment ions into the substrate 100 to form a threshold voltage adjustment region 102 in the well region 101, and the well region ions and the threshold voltage adjustment ions are of the same electrical type.

[0028] 2 , a gate structure 103 is formed on the substrate 100 ; lightly doped ions are implanted into the substrate 100 using the gate structure 103 as a mask to form a lightly doped drain region 104 in the well region 101 , wherein the lightly doped ions have an electrical type opposite to that of the well region ions.

[0029] Please refer to Figure 3. Sidewall spacers 105 are formed on the sidewalls of the gate structure 103. Source and drain ions are injected into the substrate 100 using the gate structure 103 and the sidewall spacers 105 as masks to form source and drain doped regions 106 in the well region 101. The source and drain ions are of the same electrical type as the lightly doped ions.

[0030] Currently, conventional process methods for improving the hot carrier injection effect have certain problems, including: increasing the injection energy of the lightly doped ions, but this will penetrate the thinner gate structure; increasing the annealing after the lightly doped ion injection, but this will change the channel doping distribution of the core device; using non-self-aligned injection of the lightly doped ions before forming the gate structure, but this will cause large fluctuations in device performance, which is particularly unsuitable for analog circuit applications.

[0031] On this basis, the present invention provides a method for forming a semiconductor structure, wherein the implantation of the threshold voltage adjustment ions is performed after the gate structure is formed. The implantation energy required for the threshold voltage adjustment ions is relatively large to ensure that they penetrate the gate structure and enter the channel region, thereby completing the adjustment of the threshold voltage. The implantation of the lightly doped ions is performed after the implantation of the threshold voltage adjustment ions. Since the implantation energy of the threshold voltage adjustment ions is relatively large, the lightly doped ions have a deeper implantation depth in the source and drain regions, which is conducive to forming a more hierarchical junction depth of the lightly doped drain region, thereby improving the hot carrier injection effect. In this process, there is no need to increase the implantation energy and annealing heat of the lightly doped ions, effectively reducing damage to the device structure and performance. At the same time, there is no need to use non-self-aligned mask ion implantation, which effectively simplifies the process and improves process efficiency.

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] 4 to 10 are schematic structural diagrams of various steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0034] Referring to FIG. 4 , a substrate 200 is provided.

[0035] The material of the substrate 200 includes: single crystal silicon, polycrystalline silicon or amorphous silicon; the material of the substrate 200 may also include: semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc.

[0036] In this embodiment, the substrate 200 is made of single crystal silicon.

[0037] Referring to FIG. 5 , well region ions are implanted into the substrate 200 to form a well region 201 in the substrate 200 .

[0038] In this embodiment, the device structure formed is an NMOS device, so the corresponding well region ions are P-type ions; in other embodiments, if the device structure formed is a PMOS device, the corresponding well region ions are N-type ions.

[0039] P-type ions include: boron ions, BF2 - ions or indium ions; N-type ions include: phosphorus ions or arsenic ions.

[0040] Referring to FIG. 6 , a gate structure 202 is formed on the substrate 200 .

[0041] The gate structure 202 includes a gate dielectric layer and a gate layer (not shown) located on the gate dielectric layer.

[0042] The method for forming the gate structure 202 includes: forming a gate dielectric material layer (not shown) on the substrate 200; forming a gate material layer (not shown) on the gate dielectric material layer; patterning the gate dielectric material layer and the gate material layer to form the gate dielectric layer and a gate layer located on the gate dielectric layer, and forming the gate structure 202 by the gate dielectric layer and the gate layer.

[0043] The material of the gate dielectric layer includes one of silicon oxide, hafnium oxide and silicon hafnium oxide. In this embodiment, the material of the gate dielectric layer is silicon oxide.

[0044] The gate layer is made of polysilicon.

[0045] Referring to FIG. 7 , after forming the gate structure 202 , threshold voltage adjustment ions are implanted into the substrate 200 . The threshold voltage adjustment ions penetrate the gate structure 202 to form a threshold voltage adjustment region 203 in the substrate 200 .

[0046] The electrical type of the threshold voltage adjustment ions is the same as the electrical type of the trap region ions.

[0047] In this embodiment, the device structure formed is an NMOS device, so the electrical type of the corresponding threshold voltage adjustment ion is P-type; in other embodiments, if the device structure formed is a PMOS device, the electrical type of the corresponding threshold voltage adjustment ion is N-type.

[0048] P-type ions include: boron ions, BF2 - ions or indium ions; N-type ions include: phosphorus ions or arsenic ions. In this embodiment, the threshold voltage adjustment ions are boron ions.

[0049] The threshold voltage adjustment region 203 is located in the well region 201 .

[0050] It should be noted that, since the threshold voltage adjusting ions need to penetrate the gate structure 202, the energy of the threshold voltage adjusting ions injected after the gate structure 202 is formed is higher than the energy of the threshold voltage adjusting ions injected before the gate structure 202 is formed. The injection energy of the threshold voltage adjusting ions penetrating the gate structure 202 is specifically determined by the thickness of the gate dielectric layer and the gate layer.

[0051] Since the threshold voltage adjustment ions are implanted without a mask, the threshold voltage adjustment ions ultimately implanted into the channel region (i.e., the region of the substrate 200 covered by the gate structure 202) are shielded by the gate structure 202. Therefore, the implantation depth of the threshold voltage adjustment ions in the channel region is relatively shallow. Outside the channel region, however, without the shielding of the gate structure 202, the implantation depth of the threshold voltage adjustment ions is relatively deep, thereby facilitating the formation of a deeper and more layered junction depth for the lightly doped ions subsequently implanted outside the channel region.

[0052] Please refer to Figure 8. After the threshold voltage adjustment region 203 is formed, lightly doped ions are injected into the substrate 200 using the gate structure 202 as a mask to form a lightly doped drain region 204 in the substrate 200. The electrical type of the lightly doped ions is opposite to that of the threshold voltage adjustment ions.

[0053] By implanting the threshold voltage adjustment ions after forming the gate structure 202, the threshold voltage adjustment ions require a larger implantation energy to ensure that they penetrate the gate structure 202 and enter the channel region (i.e., the region of the substrate 200 covered by the gate structure 202), thereby completing the adjustment of the threshold voltage. Outside the channel region, due to the absence of the shielding of the gate structure 202, the implantation depth of the threshold voltage adjustment ions is deeper. The lightly doped ions are implanted after the threshold voltage adjustment ions are implanted. Since the threshold voltage adjustment ions have a deeper implantation depth outside the channel region, the implanted lightly doped ions are facilitated to form a deeper and more layered junction depth in the source and drain region (region outside the channel region), thereby improving the hot carrier injection effect. In this process, there is no need to increase the implantation energy and annealing heat of the lightly doped ions, effectively reducing damage to the device structure and performance. At the same time, there is no need to use non-self-aligned masked ion implantation, effectively simplifying the process and improving process efficiency.

[0054] The method for forming the lightly doped drain region 204 includes: injecting lightly doped ions into the substrate 200 using the gate structure 202 as a mask to form an initial lightly doped drain region in the substrate 200; and performing a first annealing treatment on the initial lightly doped drain region to form the lightly doped drain region 204.

[0055] It should be noted that the lightly doped ions are implanted into the substrate 200 using the gate structure 202 as a mask, that is, the lightly doped ions do not penetrate the gate structure 202 .

[0056] The lightly doped ions are of opposite electrical type to the well region ions.

[0057] In this embodiment, the device structure formed is an NMOS device, so the corresponding lightly doped ions are N-type ions; in other embodiments, if the device structure formed is a PMOS device, the corresponding lightly doped ions are P-type ions.

[0058] P-type ions include: boron ions, BF2 - ions or indium ions; N-type ions include: phosphorus ions or arsenic ions.

[0059] The lightly doped drain region 204 is located in the well region 201 .

[0060] Referring to FIG. 9 , a spacer 205 is formed on the sidewall of the gate structure 202 .

[0061] The method for forming the sidewall 205 includes: forming an initial sidewall (not shown) on the sidewall and top surface of the gate structure 202 and the surface of the substrate 200; etching back the initial sidewall until the top surface of the gate structure 202 and the surface of the substrate 200 are exposed to form the sidewall 205.

[0062] The material of the sidewall spacer 205 includes one or more of silicon oxide and silicon nitride.

[0063] 10 , source and drain ions are implanted into the substrate 200 using the gate structure 202 and the sidewall spacer 205 as masks to form source and drain doped regions 206 in the substrate 200 . The source and drain ions are of the same electrical type as the lightly doped ions.

[0064] The method for forming the source-drain doped region 206 includes: injecting source-drain ions into the substrate 200 using the gate structure 202 and the sidewall 205 as a mask to form an initial source-drain doped region in the substrate 200; and performing a second annealing treatment on the initial source-drain doped region to form the source-drain doped region 206.

[0065] It should be noted that source and drain ions are implanted into the substrate 200 using the gate structure 202 and the sidewall spacer 205 as masks, that is, the source and drain ions do not penetrate the gate structure 202 and the sidewall spacer 205 .

[0066] The source and drain ions are of opposite electrical types to the lightly doped ions.

[0067] In this embodiment, the device structure formed is an NMOS device, so the corresponding source and drain ions are N-type ions; in other embodiments, if the device structure formed is a PMOS device, the corresponding source and drain ions are P-type ions.

[0068] P-type ions include: boron ions, BF2 -ions or indium ions; N-type ions include: phosphorus ions or arsenic ions.

[0069] The source-drain doped region 206 is located in the well region 201 .

[0070] 11 to 17 are schematic structural diagrams of various steps of a method for forming a semiconductor structure according to another embodiment of the present invention.

[0071] The present invention also provides a method for forming a semiconductor structure, which differs from the above embodiment in that the well region is formed after the gate structure is formed and before the lightly doped drain region is formed. The specific process is shown in Figures 11 to 17.

[0072] Referring to FIG. 11 , a substrate 300 is provided.

[0073] The material of the substrate 300 includes: single crystal silicon, polycrystalline silicon or amorphous silicon; the material of the substrate 300 may also include: semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc.

[0074] In this embodiment, the substrate 300 is made of single crystal silicon.

[0075] Referring to FIG. 12 , a gate structure 302 is formed on the substrate 300 .

[0076] The gate structure 302 includes a gate dielectric layer and a gate layer (not shown) located on the gate dielectric layer.

[0077] The method for forming the gate structure 302 includes: forming a gate dielectric material layer (not shown) on the substrate 300; forming a gate material layer (not shown) on the gate dielectric material layer; patterning the gate dielectric material layer and the gate material layer to form the gate dielectric layer and a gate layer located on the gate dielectric layer, and forming the gate structure 302 by the gate dielectric layer and the gate layer.

[0078] The material of the gate dielectric layer includes one of silicon oxide, hafnium oxide and silicon hafnium oxide. In this embodiment, the material of the gate dielectric layer is silicon oxide.

[0079] The gate layer is made of polysilicon.

[0080] Referring to FIG. 13 , after the gate structure 302 is formed, well region ions are implanted into the substrate 300 to form a well region 301 in the substrate 300 .

[0081] In this embodiment, the device structure formed is an NMOS device, so the corresponding well region ions are P-type ions; in other embodiments, if the device structure formed is a PMOS device, the corresponding well region ions are N-type ions.

[0082] P-type ions include: boron ions, BF2 - ions or indium ions; N-type ions include: phosphorus ions or arsenic ions.

[0083] It should be noted that, since the well ions need to penetrate the gate structure 302, the energy of the well ions injected after the gate structure 302 is formed is higher than the energy of the well ions injected before the gate structure 302 is formed. The injection energy of the well ions penetrating the gate structure 302 is specifically determined by the thickness of the gate dielectric layer and the gate layer.

[0084] Since the well ions are implanted without a mask, the well ions ultimately injected into the channel region (i.e., the region of the substrate 300 covered by the gate structure 302) are shielded by the gate structure 302. Therefore, the implantation depth of the well ions in the channel region is relatively shallow. Outside the channel region, however, there is no shielding from the gate structure 302, so the implantation depth of the well ions is relatively deep, which in turn facilitates the formation of a deeper and more layered junction depth for the lightly doped ions subsequently implanted outside the channel region.

[0085] Referring to FIG. 14 , after the gate structure 302 is formed, threshold voltage adjustment ions are implanted into the substrate 300 . The threshold voltage adjustment ions penetrate the gate structure 302 to form a threshold voltage adjustment region 303 in the substrate 300 .

[0086] The electrical type of the threshold voltage adjustment ions is the same as the electrical type of the trap region ions.

[0087] In this embodiment, the device structure formed is an NMOS device, so the electrical type of the corresponding threshold voltage adjustment ion is P-type; in other embodiments, if the device structure formed is a PMOS device, the electrical type of the corresponding threshold voltage adjustment ion is N-type.

[0088] P-type ions include: boron ions, BF2 - ions or indium ions; N-type ions include: phosphorus ions or arsenic ions. In this embodiment, the threshold voltage adjustment ions are boron ions.

[0089] The threshold voltage adjustment region 303 is located in the well region 301 .

[0090] It should be noted that, since the threshold voltage adjusting ions need to penetrate the gate structure 302, the energy of the threshold voltage adjusting ions injected after the gate structure 302 is formed is higher than the energy of the threshold voltage adjusting ions injected before the gate structure 302 is formed. The injection energy of the threshold voltage adjusting ions penetrating the gate structure 302 is specifically determined by the thickness of the gate dielectric layer and the gate layer.

[0091] Since the threshold voltage adjustment ions are implanted without a mask, the threshold voltage adjustment ions ultimately implanted into the channel region (i.e., the region of the substrate 300 covered by the gate structure 302) are shielded by the gate structure 302. Therefore, the implantation depth of the threshold voltage adjustment ions in the channel region is relatively shallow. Outside the channel region, however, there is no shielding by the gate structure 302, so the implantation depth of the threshold voltage adjustment ions is relatively deep, which in turn facilitates the formation of a deeper and more layered junction depth for the lightly doped ions subsequently implanted outside the channel region.

[0092] Please refer to Figure 15. After the threshold voltage adjustment region 303 is formed, lightly doped ions are injected into the substrate 300 using the gate structure 302 as a mask to form a lightly doped drain region 304 in the substrate 300. The electrical type of the lightly doped ions is opposite to that of the threshold voltage adjustment ions.

[0093] By implanting the threshold voltage adjustment ions after forming the gate structure 302, the threshold voltage adjustment ions require a larger implantation energy to ensure that they penetrate the gate structure 302 and enter the channel region (i.e., the region of the substrate 300 covered by the gate structure 302), thereby completing the adjustment of the threshold voltage. Outside the channel region, due to the absence of the shielding of the gate structure 302, the implantation depth of the threshold voltage adjustment ions is deeper. The lightly doped ions are implanted after the threshold voltage adjustment ions are implanted. Since the threshold voltage adjustment ions have a deeper implantation depth outside the channel region, the implanted lightly doped ions are facilitated to form a deeper and more layered junction depth in the source and drain region (region outside the channel region), thereby improving the hot carrier injection effect. In this process, there is no need to increase the implantation energy and annealing heat of the lightly doped ions, effectively reducing damage to the device structure and performance. At the same time, there is no need to use non-self-aligned mask ion implantation, effectively simplifying the process and improving process efficiency.

[0094] The method for forming the lightly doped drain region 304 includes: injecting lightly doped ions into the substrate 300 using the gate structure 302 as a mask to form an initial lightly doped drain region in the substrate 300; and performing a first annealing treatment on the initial lightly doped drain region to form the lightly doped drain region 304.

[0095] It should be noted that the lightly doped ions are implanted into the substrate 300 using the gate structure 302 as a mask, that is, the lightly doped ions do not penetrate the gate structure 302 .

[0096] The lightly doped ions are of opposite electrical type to the well region ions.

[0097] In this embodiment, the device structure formed is an NMOS device, so the corresponding lightly doped ions are N-type ions; in other embodiments, if the device structure formed is a PMOS device, the corresponding lightly doped ions are P-type ions.

[0098] P-type ions include: boron ions, BF2 - ions or indium ions; N-type ions include: phosphorus ions or arsenic ions.

[0099] The lightly doped drain region 304 is located in the well region 301 .

[0100] Referring to FIG. 16 , a spacer 305 is formed on the sidewall of the gate structure 302 .

[0101] The method for forming the sidewall 305 includes: forming an initial sidewall (not shown) on the sidewall and top surface of the gate structure 302 and the surface of the substrate 300; etching back the initial sidewall until the top surface of the gate structure 302 and the surface of the substrate 300 are exposed to form the sidewall 305.

[0102] The material of the sidewall spacer 305 includes one or more of silicon oxide and silicon nitride.

[0103] 17 , source and drain ions are implanted into the substrate 300 using the gate structure 302 and the sidewall spacer 305 as masks to form source and drain doped regions 306 in the substrate 300 . The source and drain ions are of the same electrical type as the lightly doped ions.

[0104] The method for forming the source-drain doped region 306 includes: injecting source-drain ions into the substrate 300 using the gate structure 302 and the sidewall 305 as a mask to form an initial source-drain doped region in the substrate 300; and performing a second annealing treatment on the initial source-drain doped region to form the source-drain doped region 306.

[0105] It should be noted that source and drain ions are implanted into the substrate 300 using the gate structure 302 and the sidewall spacer 305 as masks, that is, the source and drain ions do not penetrate the gate structure 302 and the sidewall spacer 305 .

[0106] The source and drain ions are of opposite electrical types to the lightly doped ions.

[0107] In this embodiment, the device structure formed is an NMOS device, so the corresponding source and drain ions are N-type ions; in other embodiments, if the device structure formed is a PMOS device, the corresponding source and drain ions are P-type ions.

[0108] P-type ions include: boron ions, BF2 - ions or indium ions; N-type ions include: phosphorus ions or arsenic ions.

[0109] The source-drain doped region 306 is located in the well region 301 .

[0110] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate; Forming a gate structure on the substrate; After forming the gate structure, injecting threshold voltage adjusting ions into the substrate, the threshold voltage adjusting ions penetrate the gate structure, and a threshold voltage adjusting region is formed in the substrate; After forming the threshold voltage adjusting region, injecting lightly doped ions into the substrate using the gate structure as a mask, and a lightly doped drain region is formed in the substrate, the electrical type of the lightly doped ions is opposite to that of the threshold voltage adjusting ions; Forming sidewalls on the sidewalls of the gate structure; Injecting source / drain ions into the substrate using the gate structure and the sidewalls as a mask, and a source / drain doped region is formed in the substrate, the electrical type of the source / drain ions is the same as that of the lightly doped ions.

2. The method for forming a semiconductor structure according to claim 1, wherein, Before forming the gate structure, it further includes: forming a well region in the substrate, the well region has well region ions, and the electrical type of the well region ions is the same as that of the threshold voltage adjusting ions.

3. The method for forming a semiconductor structure according to claim 2, wherein, The method for forming the well region includes: injecting the well region ions into the substrate to form the well region in the substrate.

4. The method for forming a semiconductor structure according to claim 1, wherein, After forming the gate structure and before forming the lightly doped drain region, it further includes: forming a well region in the substrate, the well region has well region ions, and the electrical type of the well region ions is the same as that of the threshold voltage adjusting ions.

5. The method for forming a semiconductor structure according to claim 4, wherein, The method for forming the well region includes: injecting the well region ions into the substrate, the well region ions penetrate the gate structure, and the well region is formed in the substrate.

6. The method for forming a semiconductor structure according to claim 2 or 4, characterized in that, The threshold voltage adjusting region, the lightly doped drain region, and the source / drain doped region are located in the well region.

7. The method for forming a semiconductor structure according to claim 1, wherein, The threshold voltage regulating ions include: P-type ions or N-type ions; the P-type ions include: boron ions, BF2 - ions or indium ions; the N-type ions include: phosphorus ions or arsenic ions.

8. The method for forming a semiconductor structure according to claim 1, wherein The gate structure includes: a gate dielectric layer and a gate layer located on the gate dielectric layer.

9. The method for forming a semiconductor structure according to claim 1, wherein, The method for forming the sidewalls includes: forming an initial sidewall on the sidewalls and the top surface of the gate structure and the surface of the substrate; etching back the initial sidewall until the top surface of the gate structure and the surface of the substrate are exposed to form the sidewalls.

10. The method for forming the semiconductor structure according to claim 1, wherein The method for forming the lightly doped drain region includes: injecting lightly doped ions into the substrate using the gate structure as a mask to form an initial lightly doped drain region; performing a first annealing treatment on the initial lightly doped drain region to form the lightly doped drain region.

11. The method for forming a semiconductor structure according to claim 1, wherein, The method for forming the source / drain doped region includes: injecting source / drain ions into the substrate using the gate structure and the sidewalls as a mask to form an initial source / drain doped region; performing a second annealing treatment on the initial source / drain doped region to form the source / drain doped region.

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