Semiconductor structure manufacturing method, semiconductor structure, electronic device, and electronic apparatus

Abstract

A semiconductor structure manufacturing method, a semiconductor structure, an electronic device, and an electronic apparatus, aiming at solving the technical problem of large resistance between a channel layer and a source structure and between the channel layer and a drain structure. According to the semiconductor structure manufacturing method, part of channel layers in contact with sacrificial layers would be removed while gaps are formed, so that the thickness of the channel layers corresponding to the gaps is reduced; and when second grooves are formed, part of the channel layers corresponding to the gaps would be removed, that is, part of the channel layers having a relatively small thickness is removed, so that the contact area between the channel layers and an electrode structure is increased, and the resistance between the channel layers and the electrode structure is reduced.

Description

Semiconductor structure manufacturing method, semiconductor structure, electronic device and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 16, 2024, with application number 202410068254.0 and application name “Semiconductor structure manufacturing method, semiconductor structure, electronic device and electronic equipment”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of semiconductor manufacturing technology, and specifically to a semiconductor structure manufacturing method, a semiconductor structure, an electronic device, and an electronic device. Background Art

[0003] Gate-all-around (GAA) transistors have become widely used due to their high controllability. They consist of multiple gate layers and multiple channel layers stacked alternately. One end of the channel layer is connected to the source structure, and the other end is connected to the drain structure. The portion of the channel layer that contacts the source and drain structures is relatively thin, resulting in high resistance between the channel layer and the source and drain structures. Summary of the Invention

[0004] The embodiments of the present application provide a semiconductor structure manufacturing method, a semiconductor structure, an electronic device, and an electronic device, which can reduce the resistance between the channel layer and the source structure and the drain structure.

[0005] In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising: forming a stacking structure on a substrate, the stacking structure comprising a plurality of sacrificial layers and a plurality of channel layers alternately stacked; forming a plurality of dummy gate structures on the stacking structure, the plurality of dummy gate structures being spaced apart; forming a first mask layer on each dummy gate structure, the first mask layer covering the sidewalls adjacent to the dummy gate structure and the stacking structure; forming a second mask layer on the first mask layer; using the second mask layer as a mask to remove part of the stacking structure to form a plurality of first grooves, the first grooves extending to the substrate; removing part of the sacrificial layer at the walls of the first grooves to form gaps; removing the second mask layer; using the first mask layer as a mask to form second grooves extending to the substrate; forming an electrode structure in contact with each channel layer at the second groove.

[0006] The semiconductor structure manufacturing method provided in the embodiment of the present application removes part of the channel layer in contact with the sacrificial layer while forming the gap, resulting in a reduction in the thickness of the channel layer corresponding to the gap. When forming the second groove, part of the channel layer corresponding to the gap is removed, that is, the part of the channel layer with a smaller thickness is removed, thereby increasing the contact area between the channel layer and the electrode structure and reducing the resistance between the channel layer and the electrode structure.

[0007] In some embodiments that may include the above embodiments, before forming the second mask layer on the first mask layer, the method further includes: forming a stop layer on the first mask layer, wherein the etching selectivity of the stop layer is different from the etching selectivity of the first mask layer and the second mask layer; and before forming the second groove extending to the substrate using the first mask layer as a mask, the method further includes: removing the stop layer. With this arrangement, when removing the second mask layer, the stop layer can protect the first mask layer from being damaged.

[0008] In some embodiments that may include the above embodiments, removing a portion of the sacrificial layer at the wall of the first groove to form the gap includes: removing the portion of the sacrificial layer at the wall of the first groove and simultaneously removing a portion of the channel layer in contact with the sacrificial layer to form a thinned region on the channel layer. In this manner, the sacrificial layer in the gap can be completely removed to avoid any remaining sacrificial layer in the gap.

[0009] In some embodiments that may include the above embodiments, forming a second groove extending to the substrate using the first mask layer as a mask includes removing at least a portion of the thinned region on each channel layer simultaneously with forming the second groove. This arrangement increases the thickness of the channel layer at the exposed portion, thereby increasing the contact area between the channel layer and the electrode structure, thereby reducing the resistance between the channel layer and the electrode structure.

[0010] In some embodiments that may include the above embodiments, before removing the second mask layer, a filler is formed in the gap. In this manner, the filler can support the channel layer in the gap to prevent the channel layer from falling off during subsequent fabrication processes. Furthermore, the filler can isolate the sacrificial layer, thereby isolating the gate layer from the electrode structure.

[0011] In some embodiments that may include the above embodiments, forming the filler in the gap includes: forming a first dielectric layer on the wall of the first groove, partially filling the gap to form the filler; and removing the first dielectric layer from the wall of the first groove. This arrangement simplifies manufacturing and ensures that the filler fills the gap.

[0012] In some embodiments that may include the above embodiments, forming an electrode structure in contact with each channel layer in the second groove includes: forming the electrode structure by epitaxial growth based on the channel layer at the wall of each second groove. In this configuration, the electrode structure formed by epitaxial growth forms an integrated structure with the channel layer, which can reduce the resistance between the channel layer and the electrode structure.

[0013] In some embodiments that may include the above embodiments, after forming the electrode structure in contact with each channel layer at the second groove, the method further includes: replacing the sacrificial layer with a gate layer, and connecting the gate layers, so that each gate layer corresponding to each sub-stack structure serves as a gate of a gate-all-around transistor, each channel layer corresponding to the sub-stack structure serves as a channel of the gate-all-around transistor, the electrode structure at one end of the sub-stack structure serves as a source of the gate-all-around transistor, and the electrode structure at the other end of the sub-stack structure serves as a drain of the gate-all-around transistor.

[0014] Secondly, embodiments of the present application further provide a semiconductor structure, which is manufactured using the semiconductor structure manufacturing method described above. The semiconductor structure provided in the embodiments of the present application is manufactured using the semiconductor structure manufacturing method described in the above embodiments, and therefore both can solve the same technical problems and achieve the same technical effects.

[0015] In a third aspect, an embodiment of the present application further provides an electronic device, a packaging substrate, and the semiconductor structure as described above, wherein the semiconductor structure is disposed on the packaging substrate.

[0016] The electronic device provided in the embodiments of the present application includes the semiconductor structure in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects.

[0017] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising: a circuit board and the electronic device as described above, wherein the electronic device is arranged on the circuit board.

[0018] The electronic device provided in the embodiments of the present application includes the semiconductor device in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG1 is a schematic diagram of the structure of a planar transistor in the related art;

[0020] FIG2 is a schematic structural diagram of a fin field effect transistor in the related art;

[0021] FIG3 is a schematic diagram of the structure of a gate-all-around transistor in the related art;

[0022] FIG4 is a cross-sectional view of a gate-all-around transistor in the related art;

[0023] FIG5 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application;

[0024] FIG6 is a perspective view of a conductor structure fabrication method according to an embodiment of the present application after a second mask layer is formed;

[0025] FIG7 is a cross-sectional view of a conductor structure fabrication method according to an embodiment of the present application after a second mask layer is formed;

[0026] FIG8 is a perspective view of a conductor structure manufacturing method according to an embodiment of the present application after a first groove is formed;

[0027] FIG9 is a first cross-sectional view of a conductor structure fabrication method according to an embodiment of the present application after a first groove is formed;

[0028] FIG10 is a three-dimensional diagram of a conductor structure after a gap is formed in the method for manufacturing the conductor structure according to an embodiment of the present application;

[0029] FIG11 is a cross-sectional view of a conductor structure after a gap is formed in the method for manufacturing the conductor structure according to an embodiment of the present application;

[0030] FIG12 is a cross-sectional view of a conductor structure fabrication method according to an embodiment of the present application after forming a first dielectric layer;

[0031] FIG13 is a cross-sectional view of the conductor structure manufacturing method provided in an embodiment of the present application after the first dielectric layer at the wall of the first groove is removed;

[0032] FIG14 is a cross-sectional view of the conductor structure manufacturing method provided in an embodiment of the present application after the second mask layer is removed;

[0033] FIG15 is a cross-sectional view of a conductor structure fabrication method according to an embodiment of the present application after a second groove is formed;

[0034] FIG16 is a cross-sectional view of a conductor structure fabrication method according to an embodiment of the present application after an electrode structure is formed;

[0035] FIG17 is a second cross-sectional view after the first groove is formed in the conductor structure manufacturing method provided in an embodiment of the present application.

[0036] Explanation of the reference numerals: 10: substrate; 101: shallow trench isolation structure; 20: stacked structure; 201: channel layer; 202: sacrificial layer; 203: gate layer; 204: channel structure; 205: filling body; 206: first dielectric layer; 207: gap; 208: thinning area; 210: sub-stacked structure; 30: virtual gate structure; 301: hard mask; 302: first hard mask; 303: second hard mask; 304: second dielectric layer; 305: isolation layer; 306: first mask layer; 307: second mask layer; 308: stop layer; 310: source structure; 320: drain structure; 401: first groove; 402: second groove. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0038] In the following, the terms "first," "second," etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the quantity of the technical features indicated. Therefore, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features.

[0039] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", "right", "horizontal" and "vertical" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to changes in the orientation of the components in the drawings.

[0040] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, an electrical connection, a detachable connection, or an integrated connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0041] With the gradual development of semiconductor technology, transistors have gradually evolved from planar transistors to fin field-effect transistors (FinFETs) and gate-all-around transistors (GAA). As shown in FIG1 , a planar transistor includes a channel layer 201 and a gate layer 203 stacked on the channel layer 201. The planar transistor can be controlled by the gate layer 203. As shown in FIG2 , a fin field-effect transistor includes a fin-shaped channel structure 204. The gate layer 203 covers the top surface and two side surfaces of the channel structure 204 to increase the contact area between the gate layer 203 and the channel structure 204, thereby improving the control capability of the fin field-effect transistor.

[0042] As shown in Figures 3 and 4, the gate-all-around transistor includes a plurality of stacked channel layers 201, with a gate layer 203 disposed between adjacent channel layers 201. The plurality of gate layers 203 are connected, with one end of the channel layer 201 connected to a source structure 310, and the other end of the channel layer 201 connected to a drain structure 320. Each channel layer 201 is located between the source structure 310 and the drain structure 320. During fabrication, in order to prevent the source structure 310 and the drain structure 320 from contacting the gate layer 203, it is generally necessary to first alternately stack a plurality of channel layers 201 and a plurality of sacrificial layers to form a stacked structure. Subsequently, a portion of the sacrificial layers at both ends of the stacked structure is removed by etching to form a gap, which is then filled with a body 205. Subsequently, a source structure 310 is formed at one end of the stacked structure, and a drain structure 320 is formed at the other end of the stacked structure.

[0043] However, while removing part of the sacrificial layer at both ends of the stacked structure, part of the channel layer 201 adjacent to the sacrificial layer will also be removed, so that the thickness of the portion of the channel layer 201 in contact with the source structure 310 and the drain structure 320 is smaller (point A in Figure 4), resulting in a larger resistance between the channel layer 201 and the source structure 310 and the drain structure 320.

[0044] 5 , an embodiment of the present application provides a method for manufacturing a semiconductor structure, which may include a gate-all-around transistor. The method includes:

[0045] S101: forming a stack structure on a substrate, wherein the stack structure includes a plurality of sacrificial layers and a plurality of channel layers alternately stacked.

[0046] 6 and 7 , multiple sacrificial layers 202 and multiple channel layers 201 are alternately stacked. For example, a sacrificial layer 202 may be formed on the substrate 10 first, followed by a channel layer 201 formed on the sacrificial layer 202, followed by another sacrificial layer 202 formed on the channel layer 201, and so on. Alternatively, a channel layer 201 may be formed on the substrate 10 first, followed by a sacrificial layer 202 formed on the channel layer 201, followed by another channel layer 201 formed on the sacrificial layer 202, and so on.

[0047] In the embodiment of the present application, the material of the substrate 10 may include silicon (Si), germanium (Ge), etc. The material of the channel layer 201 may include silicon, germanium, etc., and the channel layer 201 may serve as the channel of the all-around gate transistor. The material of the sacrificial layer 202 may include silicon germanium (SiGe), silicon oxide (SiOx), silicon nitride (SiN), etc. The embodiment of the present application does not limit the material of the sacrificial layer 202, as long as the etching selectivity of the sacrificial layer 202 is different from the etching selectivity of the channel layer 201.

[0048] In some embodiments, the stacked structure 20 may extend along a first direction (the X direction in FIG. 6 ) on the substrate 10, and there may be multiple stacked structures 20. The multiple stacked structures 20 may be spaced apart along a second direction (the Y direction in FIG. 6 ) perpendicular to the first direction on the substrate 10. Adjacent stacked structures 20 may be isolated by shallow trench isolation structures 101. For example, shallow trench isolation structures 101 may be formed in the substrate 10 between adjacent stacked structures 20. The material of the shallow trench isolation structures 101 may include silicon oxide, silicon oxynitride (SiON), etc.

[0049] After forming the stacked structure 20, referring to FIG. 5 , the semiconductor structure manufacturing method provided in the embodiment of the present application further includes:

[0050] S102: forming a plurality of dummy gate structures on the stacked structure, wherein the plurality of dummy gate structures are arranged at intervals.

[0051] 6 and 7 , illustratively, a plurality of dummy gate structures 30 may be arranged at intervals along the first direction; the material of the dummy gate structures 30 may include single crystal silicon or polycrystalline silicon.

[0052] It is understood that during fabrication, an isolation layer 305 can be first formed on the surface of the stacked structure 20 facing away from the substrate 10, as well as on the side surface adjacent to the surface; a dummy gate layer can then be formed on the isolation layer 305, and a hard mask 301 can be formed on the dummy gate layer. Using the hard mask 301 as a mask, portions of the dummy gate layer and the isolation layer 305 can be removed to form a plurality of spaced dummy gate structures 30, each of which is isolated from the stacked structure 20 by the isolation layer 305. The isolation layer 305 can be made of silicon oxide, silicon oxynitride, or the like.

[0053] In the above implementation, the hard mask 301 may include a first hard mask 302 and a second hard mask 303 that are stacked, and the second hard mask 303 is located between the virtual gate layer and the first hard mask 302. The material of the first hard mask 302 may include silicon oxide, silicon oxynitride, etc., and the material of the second hard mask 303 may include silicon nitride, etc.

[0054] After forming the dummy gate structure 30 , referring to FIG. 5 , the semiconductor structure manufacturing method provided in the embodiment of the present application further includes:

[0055] S103: forming a first mask layer on each dummy gate structure, wherein the first mask layer covers sidewalls adjacent to the dummy gate structure and the stacked structure.

[0056] 6 and 7 , illustratively, the material of the first mask layer 306 may include silicon nitride, silicon oxynitride, etc.

[0057] It is understandable that the first mask layer 306 covers the sidewalls of the dummy gate structure 30 adjacent to the stacked structure 20 , and also covers the surface of the dummy gate structure 30 facing away from the substrate 10 .

[0058] After forming the first mask layer 306 , and still referring to FIG. 5 , the semiconductor structure manufacturing method provided in the embodiment of the present application further includes:

[0059] S104: forming a second mask layer on the first mask layer.

[0060] 6 and 7 , illustratively, the second mask layer 307 may completely cover the first mask layer 306 , and the material of the second mask layer 307 may include silicon oxide, silicon oxynitride, and the like.

[0061] After forming the second mask layer 307 , and still referring to FIG. 5 , the semiconductor structure manufacturing method provided in the embodiment of the present application further includes:

[0062] S105 : using the second mask layer as a mask to remove a portion of the stacked structure to form a plurality of first grooves, wherein the first grooves extend to the substrate.

[0063] 8 and 9 , illustratively, a portion of the stack structure 20 may be removed by dry etching or wet etching to form a first groove 401 extending to the substrate 10 . The first groove 401 divides the stack structure 20 into a plurality of sub-stack structures 210 .

[0064] After forming the first groove 401 , referring to FIG. 5 , the semiconductor structure manufacturing method provided in the embodiment of the present application further includes:

[0065] S106: removing a portion of the sacrificial layer at the wall of the first groove to form a gap.

[0066] 10 and 11 , it can be understood that, since the etching selectivity of the sacrificial layer 202 is different from that of the channel layer 201 , a portion of the sacrificial layer 202 at the wall of the first groove 401 can be removed by selective etching; that is, a portion of the sacrificial layer 202 near the first groove 401 in the sub-stack structure 210 is removed to form a gap 207 .

[0067] As shown in FIG12 , after forming the gap 207, a filler 205 may be filled in the gap 207. The filler 205 may support the channel layer 201 in the gap 207 to prevent the channel layer 201 from falling off during subsequent fabrication processes. In addition, the filler 205 may also isolate the sacrificial layer 202. For example, the filler 205 may be made of insulating materials such as silicon oxycarbon (SiCO) and silicon carbon oxynitride (SiOCN).

[0068] Exemplarily, forming the filling body 205 within the gap 207 includes forming a first dielectric layer 206 on the walls of the first groove 401, partially filling the gap 207 with the first dielectric layer 206 to form the filling body 205. As shown in FIG13 , the first dielectric layer 206 on the walls of the first groove 401 is then removed to retain the filling body 205 within the gap 207. This arrangement simplifies manufacturing and ensures that the filling body 205 fills the gap 207.

[0069] After forming the gap 207 , referring to FIG. 5 , the semiconductor structure manufacturing method provided in the embodiment of the present application further includes:

[0070] S107: removing the second mask layer.

[0071] As shown in FIG. 14 , illustratively, the second mask layer 307 may be removed by dry etching or wet etching, which is not limited in the embodiment of the present application.

[0072] In some embodiments, the etching selectivity ratios of the first mask layer 306 and the second mask layer 307 may be different. Accordingly, when the second mask layer 307 is removed, the first mask layer 306 is retained.

[0073] After removing the second mask layer 307 , referring to FIG. 5 , the semiconductor structure manufacturing method provided in the embodiment of the present application further includes:

[0074] S108: forming a second groove extending to the substrate using the first mask layer as a mask.

[0075] As shown in Figure 15, illustratively, the portion of the sub-stack structure 210 covered by the second mask layer 307 shown in Figure 12 can be removed by wet etching or dry etching to form a second groove 402 extending to the substrate 10, and the second groove 402 is connected to the first groove 401.

[0076] After forming the second groove 402 , referring to FIG. 5 , the semiconductor structure manufacturing method provided in the embodiment of the present application further includes:

[0077] S109: forming an electrode structure in contact with each channel layer at the second groove.

[0078] As shown in FIG16 , the electrode structure 30 can be filled in the second groove 402 and the first groove 401. The electrode structure 30 can serve as the source or drain of the all-around gate transistor. Taking the orientation shown in FIG16 as an example, the electrode structure 30 on the left side of the sub-stack structure 210 can serve as the source of the all-around gate transistor, and the electrode structure 30 on the right side of the sub-stack structure 210 can serve as the drain of the all-around gate transistor.

[0079] Illustratively, based on the channel layer 201 at the wall of each second groove 402, the electrode structure 30 is formed by epitaxial growth. The electrode structure 30 formed by epitaxial growth forms an integrated structure with the channel layer 201, which can reduce the resistance between the channel layer 201 and the electrode structure.

[0080] In an embodiment of the present application, after the electrode structure is formed, each sacrificial layer 202 can be replaced with a gate layer, and the gate layers are connected so that each gate layer corresponding to each sub-stack structure 210 serves as the gate of a ring-gate transistor, and each channel layer 201 corresponding to the sub-stack structure 210 serves as the channel of the ring-gate transistor. The electrode structure 30 at one end of the sub-stack structure 210 serves as the source of the ring-gate transistor, and the electrode structure 30 at the other end of the sub-stack structure 210 serves as the drain of the ring-gate transistor.

[0081] In the above implementation, the gate layer may include a gate metal layer and a gate dielectric layer wrapped around the gate metal layer. For example, the gate metal layer may be made of tungsten, copper, or the like, and the gate dielectric layer may be made of a high-k dielectric material such as hafnium oxide.

[0082] The semiconductor structure manufacturing method provided by the embodiment of the present application is shown in Figures 6 and 7. The stacked structure 20 includes a plurality of sacrificial layers 202 and a plurality of channel layers 201 alternately stacked. A plurality of dummy gate structures 30 are formed on the stacked structure 20 at intervals. A first mask layer 306 is then formed on the dummy gate structure 30. The first mask layer 306 covers the sidewalls of the dummy gate structure 30 adjacent to the stacked structure 20. A second mask layer 307 is formed on the first mask layer 306. The second mask layer 307 is then used as a mask. Part of the stacked structure 20 is removed to form a plurality of first grooves 401 extending to the substrate 10 (as shown in Figures 8 and 9); thereafter, part of the sacrificial layer 202 at the walls of the first grooves 401 is removed to form gaps 207 (as shown in Figures 10 and 11); the second mask layer 307 is removed, and then the first mask layer 306 is used as a mask to form second grooves 402 extending to the substrate 10 (as shown in Figure 15), and an electrode structure in contact with each channel layer 201 is formed at the second grooves 402. Through the above-mentioned setting, part of the channel layer 201 contacting the sacrificial layer 202 will be removed while forming the gap 207 (as shown in FIG11 ), resulting in a reduction in the thickness of the channel layer 201 corresponding to the gap 207. When the second groove 402 is formed, part of the channel layer 201 corresponding to the gap 207 will be removed (as shown in FIG15 ), that is, part of the channel layer 201 with a smaller thickness will be removed, thereby increasing the contact area between the channel layer 201 and the electrode structure 30 and reducing the resistance between the channel layer 201 and the electrode structure 30.

[0083] 11 , it can be understood that, although the etching selectivity of the sacrificial layer 202 is different from that of the channel layer 201, when the portion of the sacrificial layer 202 at the wall of the first groove 401 is removed, the portion of the channel layer 201 in contact with the sacrificial layer 202 is also removed, thereby forming a thinned region 208 on the channel layer 201, thereby reducing the thickness of the channel layer 201. In this manner, the sacrificial layer 202 within the gap 207 can be completely removed to prevent any remaining sacrificial layer 202 within the gap 207.

[0084] In order to ensure a sufficiently large filler 205 between the gate layer 203 and the electrode structure, a relatively large gap 207 is generally required. Accordingly, the formed thinned region 208 has a relatively large thickness in a direction perpendicular to the substrate 10, further reducing the thickness of the channel layer 201. In the embodiment of the present application, as shown in FIG15 , when forming the second groove 402, at least a portion of the thinned region 208 (as shown in FIG11 ) is removed to increase the thickness of the channel layer 201 at the exposed portion. This increases the contact area between the channel layer 201 and the electrode structure, thereby reducing the resistance between the channel layer 201 and the electrode structure.

[0085] 6 and 7, in the embodiment in which the etching selectivity ratios of the first mask layer 306 and the second mask layer 307 are different, the thickness of the first mask layer 306 can be (like etc.), the thickness of the second mask layer 307 can be (like Such a configuration makes the second mask layer 307 thicker. When forming the second groove 402 (as shown in FIG15 ), the width of the second groove 402 along the first direction is larger, further increasing the contact area between the channel layer 201 and the electrode structure.

[0086] As shown in FIG17 , in other embodiments, the etching selectivities of the first mask layer 306 and the second mask layer 307 are equal or similar. Accordingly, before forming the second mask layer 307, a stop layer 308 is formed on the first mask layer 306. The etching selectivity of the stop layer 308 is different from the etching selectivities of the first mask layer 306 and the second mask layer 307. When removing the second mask layer 307, the stop layer 308 can protect the first mask layer 306 from being damaged. The stop layer 308 is removed before forming the second recess 402 shown in FIG15 to ensure that the width of the second recess 402 along the first direction is large.

[0087] Exemplarily, the material of the stop layer 308 may include silicon oxide, silicon oxynitride, etc. The embodiment of the present application does not limit the material of the stop layer 308, as long as the etching selectivity of the stop layer 308 is different from the etching selectivity of the first mask layer 306 and the second mask layer 307.

[0088] As shown in FIG17 , in an implementation in which the etching selectivity ratios of the first mask layer 306 and the second mask layer 307 are equal or similar, the sum of the thickness of the first mask layer 306 and the thickness of the stop layer 308 can be (like etc.), the thickness of the second mask layer 307 can be (like With this configuration, under the premise that the sum of the thicknesses of the first mask layer 306, the stop layer 308, and the second mask layer 307 is not too large, the thickness of the second mask layer 307 is kept large, thereby ensuring that the width of the formed second groove 402 along the first direction is large.

[0089] Continuing with FIG. 6 and FIG. 7 , in an embodiment of the present application, a second dielectric layer 304 can be formed on the dummy gate structure 30 before forming the first mask layer 306. The second dielectric layer 304 can cover the sidewalls of the dummy gate structure 30 adjacent to the stacked structure 20 and the hard mask 301. The second dielectric layer 304 can be made of a low-k dielectric constant (Low-k) material such as silicon carbon oxide nitrogen (SiOCN). The second dielectric layer 304 can reduce the capacitance effect between the gate-all-around transistors.

[0090] The present application also provides an electronic device, which may include a mobile phone, a computer, a tablet computer, a smart bracelet, a smart watch, AR, VR, etc. The present application does not limit the electronic device. The electronic device includes a circuit board and an electronic device disposed on the circuit board. The electronic device may include a central processing unit (CPU), a memory, etc., and the electronic device is electrically connected to the circuit on the circuit board.

[0091] In the above implementation, the electronic device may include a packaging substrate and a semiconductor structure, wherein the semiconductor structure is packaged on the packaging substrate. For example, a packaging circuit may be provided on the packaging substrate, the semiconductor structure is electrically connected to the packaging circuit, and the packaging circuit is connected to a circuit on a circuit board to achieve electrical connection between the semiconductor structure and the circuit board. It is understood that the above semiconductor structure can be manufactured using the semiconductor structure manufacturing method described in the above embodiment.

[0092] In an implementation where the electronic device is a central processing unit, the ring-gate transistor in the semiconductor structure can be a logic device of the central processing unit. In an implementation where the electronic device is a memory, the ring-gate transistor in the semiconductor structure can be a switching device. The embodiments of the present application do not limit the function of the ring-gate transistor.

[0093] The above description is merely a specific embodiment of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Comprising: Forming a stacked structure on a substrate, the stacked structure including a plurality of sacrificial layers and a plurality of channel layers alternately stacked; Forming a plurality of dummy gate structures on the stacked structure, the plurality of dummy gate structures being disposed at intervals; Forming a first mask layer on each of the dummy gate structures, the first mask layer covering sidewalls of the dummy gate structures adjacent to the stacked structure; Forming a second mask layer on the first mask layer; Using the second mask layer as a mask to remove a part of the stacked structure to form a plurality of first grooves, the first grooves extending to the substrate; Removing a part of the sacrificial layer at the sidewalls of the first grooves to form voids; Removing the second mask layer; Using the first mask layer as a mask to form second grooves extending to the substrate; Forming electrode structures in contact with each of the channel layers at the second grooves.

2. The method for fabricating a semiconductor structure according to claim 1, wherein Before forming the second mask layer on the first mask layer, further comprising: Forming a stop layer on the first mask layer, the etching selectivity of the stop layer being unequal to the etching selectivities of both the first mask layer and the second mask layer; Before forming the second grooves extending to the substrate using the first mask layer as a mask, further comprising: removing the stop layer.

3. The method for fabricating a semiconductor structure according to claim 1 or 2, characterized in that, Removing a part of the sacrificial layer at the sidewalls of the first grooves to form voids includes: When removing a part of the sacrificial layer at the sidewalls of the first grooves, a part of the channel layer in contact with the sacrificial layer is removed to form a thinning region on the channel layer.

4. The method for fabricating a semiconductor structure according to claim 3, wherein Using the first mask layer as a mask to form second grooves extending to the substrate includes: When forming the second grooves, at least a part of the thinning regions on each of the channel layers are also removed.

5. The method for fabricating a semiconductor structure according to any one of claims 1-4, wherein Before removing the second mask layer, further comprising: Forming a filler in the voids.

6. The method for fabricating a semiconductor structure according to claim 5, wherein, Forming a filler in the voids includes: Forming a first dielectric layer at the sidewalls of the first grooves, and a part of the first dielectric layer fills the voids to form the filler; Removing the first dielectric layer at the sidewalls of the first grooves.

7. The method for fabricating a semiconductor structure according to any one of claims 1-6, wherein Forming electrode structures in contact with each of the channel layers at the second grooves includes: Based on the channel layers at the sidewalls of each of the second grooves, forming electrode structures by epitaxial growth.

8. The method for fabricating a semiconductor structure according to any one of claims 1-7, characterized in that, After forming electrode structures in contact with each of the channel layers at the second grooves, further comprising: Replacing the sacrificial layers with gate layers, and connecting the gate layers.

9. A semiconductor structure, characterized in that, The semiconductor structure is obtained by the semiconductor structure manufacturing method according to any one of claims 1-8.

10. An electronic device, characterized in that, A packaging substrate and the semiconductor structure according to claim 9, the semiconductor structure being disposed on the packaging substrate.

11. An electronic device, characterized in that, Comprising: A circuit board and the electronic device according to claim 10, the electronic device being disposed on the circuit board.

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