Image decoding method and apparatus, electronic device, and readable storage medium

Abstract

The present application relates to the technical field of image processing, and discloses an image decoding method and apparatus, an electronic device, and a readable storage medium. Embodiments of the present application provide an image decoding method, and the method comprises: an electronic device determines the value of N on the basis of the number and / or load condition of CPU cores, wherein N is an integer greater than 1; the electronic device obtains N encoded bit sequences on the basis of the N and an encoded bit stream corresponding to a target image; and the electronic device decodes the N encoded bit sequences by means of N decoding threads, wherein one decoding thread corresponds to one encoded bit sequence.

Description

Image decoding method, device, electronic device and readable storage medium

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 17, 2024, with application number 202410068877.8 and application name “Image decoding method, device, electronic device and readable storage medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application belongs to the field of image processing technology, and specifically relates to an image decoding method, device, electronic device and readable storage medium. Background Art

[0003] Typically, in a scenario where an encoded file corresponding to an image (e.g., a Joint Photographic Experts Group (JPEG) image) is decoded, an electronic device may perform image decoding on the encoded file through a central processing unit (CPU) of the electronic device, such as performing Huffman entropy decoding and inverse discrete cosine transform (DCT) on the encoded file to obtain YUV image data of the JPEG image, and converting the obtained YUV data into red, green, and blue (RGB) data, so that the electronic device may display the JPEG image based on the RGB data.

[0004] However, since the electronic device may need a long time to perform Huffman entropy decoding and DCT inverse transformation on the above-mentioned encoded file through the CPU core to obtain RGB data of the JPEG image, the image decoding efficiency of the electronic device is low. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide an image decoding method, device, electronic device and readable storage medium, which can solve the problem of low image decoding efficiency of electronic devices.

[0006] In a first aspect, an embodiment of the present application provides an image decoding method, the method comprising: an electronic device determines a value of N based on the number of CPU cores and / or load conditions, where N is an integer greater than 1; the electronic device obtains N coded bit sequences based on N and the coded bit stream corresponding to the target image; the electronic device decodes the N coded bit sequences through N decoding threads; wherein one decoding thread corresponds to one coded bit sequence.

[0007] In a second aspect, embodiments of the present application provide an image decoding apparatus, comprising: a processing module configured to determine a value of N based on the number and / or load of CPU cores, where N is an integer greater than 1; obtain N coded bit sequences based on N and a coded bit stream corresponding to a target image; and decode the N coded bit sequences using N decoding threads, where one decoding thread corresponds to one coded bit sequence.

[0008] In a third aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method described in the first aspect are implemented.

[0009] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0010] In a fifth aspect, an embodiment of the present application provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the steps of the method described in the first aspect.

[0011] In a sixth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the steps of the method described in the first aspect.

[0012] In an embodiment of the present application, the electronic device can determine the value of N based on at least one of the number of CPU cores and the load condition of the CPU cores, where N is an integer greater than 1, and obtain N coded bit sequences based on N and the coded bit stream corresponding to the target image, so that the electronic device can decode the N coded bit sequences through N decoding threads. Since the electronic device determines the value of N based on at least one of the number of CPU cores and the load condition of the CPU cores, that is, the value of N is related to the number of CPU cores and / or the load condition of the CPU cores, it can avoid the electronic device taking a long time to decode the image due to CPU overload. And since the N coded bit sequences are decoded through N decoding threads, the time for decoding the image can be shortened. In summary, the image decoding efficiency of the electronic device is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG1 is a flow chart of an image decoding method according to an embodiment of the present invention;

[0014] FIG2 is a second flow chart of the image decoding method provided in an embodiment of the present application;

[0015] FIG3 is a third flow chart of the image decoding method provided in an embodiment of the present application;

[0016] FIG4 is a fourth flow chart of the image decoding method provided in an embodiment of the present application;

[0017] FIG5 a is a schematic diagram showing one of the electronic device storing decoded data in a storage space of a memory of the electronic device;

[0018] FIG5 b is a second schematic diagram of an electronic device storing decoded data in a storage space of a memory of the electronic device;

[0019] FIG6 is a third schematic diagram of an electronic device storing decoded data in a storage space of a memory of the electronic device;

[0020] FIG7 is a fifth flow chart of the image decoding method provided in an embodiment of the present application;

[0021] FIG8 is a schematic structural diagram of an image decoding device provided in an embodiment of the present application;

[0022] FIG9 is a schematic diagram of a hardware structure of an electronic device provided in an embodiment of the present application;

[0023] FIG10 is a second schematic diagram of the hardware structure of the electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0025] The following describes the terms involved in the embodiments of the present application.

[0026] 1. Heterogeneous computing units

[0027] Generally, computing units different from CPUs, such as digital signal processors (DSPs), neural network processors (NPUs), graphics processing units (GPUs), and video processing units (VPUs), are all heterogeneous computing units.

[0028] The main frequency of the heterogeneous computing unit is lower than the main frequency of the CPU of the electronic device, that is, the computing power of the heterogeneous computing unit is lower than the computing power of the electronic device, and the power consumption of the heterogeneous computing unit for computing is lower than the power consumption of the electronic device for computing through the CPU.

[0029] 2. Other terms

[0030] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0031] The image decoding method, device, electronic device, and readable storage medium provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0032] The image decoding method provided in the embodiment of the present application is applied in the scenario of image decoding.

[0033] The image decoding method provided in the embodiment of the present application can be executed by an image decoding device, an electronic device, or a functional module or entity in an electronic device. In the embodiment of the present application, the image decoding method provided in the embodiment of the present application is described by taking an electronic device executing the image decoding method as an example.

[0034] FIG1 is a flow chart of an image decoding method provided by an embodiment of the present application. As shown in FIG1 , an image decoding method provided by an embodiment of the present application may include the following steps 101 to 103 .

[0035] Step 101: The electronic device determines a value of N according to the number of CPU cores and / or load conditions.

[0036] In the embodiment of the present application, N is an integer greater than 1.

[0037] In some embodiments of the present application, when the electronic device obtains the target image, the electronic device can determine the value of N based on the number of CPU cores and / or load conditions according to the user's click input on the thumbnail of the target image.

[0038] In some embodiments of the present application, the target image may be any one of the following: a JPEG image, a Portable Network Graphic (PNG) image, a Graphics Interchange Format (GIF) image, a WEBP image, an AVIF image, and the like.

[0039] In some embodiments of the present application, the target image may be a frame of an image in a target video, and the target video may be any of the following: Moving Pictures Experts Group (Mpeg) 4 video, H.264 / 265 video, VP8 / 9 video, etc.

[0040] In some embodiments of the present application, the electronic device may obtain the target image by downloading it from a server, or the electronic device may obtain the target image by photographing it with a camera of the electronic device.

[0041] In the embodiment of the present application, the above-mentioned N may indicate the number of decoding threads required to decode the target image.

[0042] In some embodiments of the present application, the electronic device may determine the value of N based on the number of first CPU cores in the CPU; and / or the electronic device may determine the value of N based on the load of each first CPU core in the CPU. Specifically, the first CPU core may be: the CPU core with the highest operating frequency among the CPU cores included in the CPU, or the CPU core with the second highest operating frequency among the CPU cores included in the CPU, or the CPU core with a lower operating frequency among the CPU cores included in the CPU. The first CPU core may also be various combinations of the CPU cores included in the CPU.

[0043] Exemplarily, it is assumed that the CPU of an electronic device includes multiple CPU cores, the multiple CPU cores include an extra-large CPU core, a large CPU core, and a small CPU core, the operating frequency of the extra-large CPU core is the CPU core with the highest operating frequency among the multiple CPU cores, the large CPU core is the CPU core with the second highest operating frequency among the multiple CPU cores, and the small CPU core is the CPU core with the lowest operating frequency among the multiple CPU cores, so that the electronic device can determine the value of N based on the number and / or load conditions of the first CPU cores (for example, the extra-large CPU core), or the electronic device can determine the value of N based on the number and / or load conditions of the first CPU cores (for example, the large CPU core), or the electronic device can determine the value of N based on the number and / or load conditions of the first CPU cores (for example, the extra-large CPU core and the large CPU core), and so on.

[0044] Optionally, in a case where the electronic device determines the value of N according to the number of CPU cores, the electronic device may directly determine the number of first CPU cores as the value of N.

[0045] For example, assuming that the CPU of an electronic device includes multiple CPU cores, including 1 extra-large CPU core, 3 large CPU cores, and 4 small CPU cores, and the first CPU core is a large CPU core, the electronic device can directly determine the number of large CPU cores, 3, as the value of N, that is, N=3.

[0046] Optionally, when the electronic device determines the value of N based on the load conditions of the CPU core, the electronic device can first obtain the occupancy rate of each first CPU core, and then determine the number of first CPU cores whose occupancy rate is less than the preset occupancy rate, and determine this number as the value of N.

[0047] For example, assuming that the CPU of an electronic device includes multiple CPU cores, the multiple CPU cores include 1 extra-large CPU core, 3 large CPU cores, and 4 small CPU cores, and the first CPU core is a large CPU core with a preset occupancy of 70%. The electronic device can first obtain the occupancy of each first CPU core, for example, the occupancy of large CPU core 1 is 40%, the occupancy of large CPU core 2 is 50%, and the occupancy of large CPU core 3 is 80%, and then determine the number of first CPU cores whose occupancy is less than the preset occupancy (i.e., 70%), i.e., the number of large CPU core 1 and large CPU core 2, i.e., 2, and determine the number 2 as the value of N, i.e., N=2.

[0048] Step 102: The electronic device obtains N coded bit sequences according to N and the coded bit stream corresponding to the target image.

[0049] In some embodiments of the present application, the electronic device may perform block processing on the coded bit stream corresponding to the target image according to N pairs, to obtain N coded bit sequences corresponding to the N image blocks.

[0050] It can be understood that each coding bit sequence is a coding bit sequence corresponding to an image block.

[0051] The following example illustrates a specific solution for an electronic device to process the coded bit stream corresponding to the target image in blocks according to N:

[0052] In some embodiments of the present application, in combination with FIG. 1 , as shown in FIG. 2 , the above step 102 may be specifically implemented through the following step 102 a.

[0053] Step 102a: The electronic device scans the coded bit stream corresponding to the target image to obtain N-1 coded bit sequences, ends the scanning, and obtains the Nth coded bit sequence based on the bits in the coded bit stream that have not been scanned.

[0054] In some embodiments of the present application, the electronic device may first scan the coded bit stream to determine the first coded bit sequence corresponding to the first image block, then scan the coded bit stream to determine the second coded bit sequence corresponding to the second image block, and so on, until the N-1th coded bit sequence corresponding to the N-1th image block is determined to obtain N-1 coded bit sequences.

[0055] In some embodiments of the present application, after obtaining N-1 coded bit sequences, the electronic device may determine the coded bit sequence in the coded bit stream except the N-1 coded bit sequences as the Nth coded bit sequence, thereby obtaining N coded bit sequences.

[0056] It can be seen that since the electronic device only needs to scan to obtain N-1 coding bit sequences (i.e., partial coding bit sequences) to end the scan and obtain the Nth coding bit sequence (i.e., the remaining coding bit sequence), it does not need to scan to obtain N coding bit sequences (i.e., all coding bit sequences) before ending the scan. Therefore, the time consumed by the electronic device in scanning the coding bit stream can be reduced, so that the electronic device does not need to wait for a long time and can decode the N coding bit sequences through N decoding threads. In this way, the image decoding efficiency of the electronic device can be improved.

[0057] The following example illustrates a specific scheme in which an electronic device scans a coded bit stream to obtain N-1 coded bit sequences:

[0058] In some embodiments of the present application, in combination with FIG. 2 , as shown in FIG. 3 , the above step 102 a may be specifically implemented through the following step 102 a 1 .

[0059] Step 102a1: The electronic device determines the data length information corresponding to the DC coefficient of the macroblock and the data length information corresponding to the AC coefficient of the macroblock in the coded bit stream corresponding to the target image based on the Huffman coding characteristics, obtains N-1 coded bit sequences, ends the scan, and obtains the Nth coded bit sequence based on the bits in the coded bit stream that have not been scanned.

[0060] A macroblock may be a pixel block of a target image, wherein the macroblock may be a 4×4 macroblock (i.e., a pixel block consisting of 4 adjacent rows of pixels and 4 adjacent columns of pixels) or an 8×8 macroblock (i.e., a pixel block consisting of 8 adjacent rows of pixels and 8 adjacent columns of pixels). It will be understood that the target image may correspond to multiple macroblocks.

[0061] Each of the N image blocks may include multiple macroblocks. It should be noted that the “multiple macroblocks” may be understood as at least two macroblocks.

[0062] Optionally, the above macroblock may specifically be an 8×8 macroblock.

[0063] The following example illustrates a specific solution for an electronic device to determine data length information corresponding to a DC coefficient of a macroblock and data length information corresponding to an AC coefficient of a macroblock in a coded bit stream corresponding to a target image based on Huffman coding characteristics:

[0064] In some embodiments of the present application, the above step 102a1 can be specifically implemented through the following steps 102a1a to 102a1c.

[0065] Step 102a1a: The electronic device scans the encoded bit stream to obtain at least one first data length information.

[0066] In an embodiment of the present application, each piece of first data length information in the at least one piece of first data length information is used to indicate a coding length corresponding to a macroblock of a target image.

[0067] It can be understood that the number of at least one first data length information is equal to the number of macroblocks in the target image.

[0068] In some embodiments of the present application, each piece of first data length information may include: data length information corresponding to a DC coefficient of a macroblock and data length information corresponding to an AC coefficient of a macroblock.

[0069] In some embodiments of the present application, for each first data length information in at least one first data length information, the electronic device can read the encoded bit value in the encoded bit stream one by one, and determine a first data length information based on all the encoded bit values ​​read by the electronic device, thereby determining at least one first data length information.

[0070] It can be understood that, in the process of determining the at least one first data length information, the electronic device may read the coded bit values ​​in the coded bit stream in sequence without completely decoding each coded bit value.

[0071] The following describes a specific solution for determining at least one first data length information by taking an electronic device determining any data length information as an example:

[0072] In some embodiments of the present application, the above step 102a1a can be specifically implemented through the following steps 102a1a1 to 102a1a4.

[0073] Step 102a1a1: The electronic device obtains R coded bit values ​​from the coded bit stream each time.

[0074] In the embodiments of the present application, R is a positive integer.

[0075] In some embodiments of the present application, R may specifically be 1.

[0076] It can be understood that the electronic device can obtain one coded bit value each time from the coded bit stream.

[0077] Step 102a1a2: The electronic device determines whether there is a bit value in the first Huffman table that matches all the encoded bit values ​​acquired by the electronic device.

[0078] In the embodiment of the present application, the first Huffman table is a Huffman table corresponding to the target image.

[0079] In some embodiments of the present application, the first Huffman table may be a Huffman table included in a file header of the target image.

[0080] In the embodiment of the present application, all the coded bit values ​​obtained by the above-mentioned electronic device can be understood as: the coded bit values ​​obtained by the electronic device from the coded bit stream this time, and the coded bit values ​​obtained by the electronic device from the coded bit stream before.

[0081] Exemplarily, assuming that the coded bit value obtained by the electronic device from the coded bit stream this time is 0, and the coded bit values ​​previously obtained by the electronic device from the coded bit stream are 1, 0, 1, then all coded bit values ​​obtained by the electronic device are 1010.

[0082] In some embodiments of the present application, at least one bit value is included in the first Huffman table, so that the electronic device can determine whether there is a bit value in the at least one bit value that is exactly the same as all the encoded bit values ​​already obtained by the electronic device, so as to determine whether there is a bit value in the first Huffman table that matches all the encoded bit values ​​already obtained by the electronic device.

[0083] Step 102a1a3: When there is a bit value in the first Huffman table that matches all the encoded bit values ​​acquired by the electronic device, the electronic device determines a third data length information corresponding to the bit value in the first Huffman table.

[0084] In some embodiments of the present application, each bit value of the above-mentioned at least one bit value in the first Huffman table corresponds to a length information, so that when there is a bit value in the first Huffman table that matches all the encoded bit values ​​obtained by the electronic device, the electronic device can determine the length information corresponding to the bit value that matches all the encoded bit values ​​obtained by the electronic device as a third data length information.

[0085] In some embodiments of the present application, when there is no bit value in the first Huffman table that matches all the encoded bit values ​​obtained by the electronic device, the electronic device may perform the above steps 102a1a1 and 102a1a2 again until there is a bit value in the first Huffman table that matches all the encoded bit values ​​obtained by the electronic device.

[0086] Step 102a1a4: The electronic device determines first data length information based on R and third data length information.

[0087] In some embodiments of the present application, the electronic device can determine the sum of the numerical value of R and the coding length indicated by a third data length information as the coding length corresponding to a macroblock of the target image, thereby determining the data length information indicating the coding length as a first data length information.

[0088] In some embodiments of the present application, after determining a first data length information, the electronic device can also perform a decoding action based on the data length information corresponding to the DC coefficient in the first data length information to obtain the DC coefficient corresponding to the first data length information, so that in subsequent steps, the electronic device can determine the DC coefficient corresponding to the next data length information of the first data length information based on the DC coefficient corresponding to the first data length information.

[0089] Furthermore, after determining a first data length information, the electronic device does not need to perform a decoding operation according to the data length information corresponding to the AC coefficient in the first data length information, so that N coded bit sequences can be obtained quickly.

[0090] It can be seen that since the electronic device can obtain R coded bit values ​​from the coded bit stream each time and determine whether there is a bit value in the first Huffman table that matches all the coded bit values ​​already obtained by the electronic device, when there is a bit value in the first Huffman table that matches all the coded bit values ​​already obtained by the electronic device, the electronic device can accurately determine the coding length corresponding to a macroblock of the target image based on a third data length information corresponding to the bit value in the first Huffman table, without having to completely decode each coded data corresponding to a macroblock of the target image. Therefore, the time spent in determining the coding length corresponding to a macroblock of the target image can be reduced, so that the electronic device can decode the N coded bit sequences through N decoding threads without having to wait for a long time. In this way, the image decoding efficiency of the electronic device can be improved.

[0091] Step 102a1b: The electronic device determines N-1 second data length information according to N, the size information of the target image, and at least one first data length information.

[0092] In the embodiment of the present application, each second data length information in the above-mentioned N-1 second data length information is used to indicate the coding length of a coding bit sequence.

[0093] It can be understood that each second data length information is used to indicate the coding length of a coding bit sequence corresponding to an image block of the target image.

[0094] In some embodiments of the present application, the electronic device may first determine the size information of each of the N image blocks mentioned above based on the size information of the target image, and then determine the number of first data length information included in each image block based on the size information of each image block and at least one first data length information, so that the electronic device can determine each second data length information based on the number of first data length information included in each image block and each first data length information.

[0095] Step 102a1c: The electronic device determines N-1 coded bit sequences according to the coded bit stream and the N-1 second data length information.

[0096] In some embodiments of the present application, the electronic device may first determine the coding bits corresponding to the coding length indicated by the first second data length information from the coding bit stream to determine the position information of the first coding bit sequence to determine the first coding bit sequence, and then determine the coding bits corresponding to the coding length from the coding bit stream to determine the position information of the second coding bit sequence to determine the second coding bit sequence, and so on, until the N-1th coding bit sequence is determined.

[0097] Thus, it can be seen that since the electronic device can first scan the coded bit stream to obtain at least one first data length information indicating the coding length corresponding to at least one macroblock of the target image, so as to determine the coding length corresponding to at least one macroblock, and then determine the N-1 second data length information indicating the coding length corresponding to the N-1 image blocks of the target image based on N, the size information of the target image and at least one first data length information, so as to determine the coding length corresponding to the N-1 image blocks, the electronic device can determine each coding bit sequence corresponding to each image block from the coded bit stream based on the coding length corresponding to the N-1 image blocks, without the need for the electronic device to completely decode each coding bit value in the coded bit stream. Therefore, the time consumption of determining the N coding bit sequences corresponding to the N image blocks of the target image can be reduced, so that the electronic device can decode the N coding bit sequences through N decoding threads without waiting for a long time, thereby improving the image decoding efficiency of the electronic device.

[0098] Specifically, when decoding an image with N=2 and a target image of 640x1440, complete Huffman decoding in the related art takes 2000 usec. However, using the image decoding method provided in the embodiment of the present application, the electronic device can first determine a second data length information, which is used to indicate the length of a coded bit sequence corresponding to an image block, taking 500 usec. Then, two decoding threads are started through two CPU cores to perform Huffman entropy decoding of the two coded bit sequences, taking 1000 usec, for a total of 1500 usec. That is, using the image decoding method provided in the embodiment of the present application, when performing Huffman decoding on the target image, the decoding speed of the electronic device is increased by 25% compared to the decoding speed in the related art.

[0099] Step 103: The electronic device decodes the N encoded bit sequences through N decoding threads.

[0100] In the embodiment of the present application, for each decoding thread in the N decoding threads, one decoding thread corresponds to one coded bit sequence.

[0101] In some embodiments of the present application, the electronic device may first create N-1 decoding threads through N-1 first CPU cores respectively, and use the first thread as 1 decoding thread through the second CPU core, thereby obtaining N decoding threads, and then decode the N encoded bit sequences through the N decoding threads.

[0102] The first thread is a thread that executes step 101 and step 102, and the second CPU core is a CPU core in a CPU of an electronic device that runs the first thread.

[0103] In some embodiments of the present application, the electronic device may perform parallel decoding or serial decoding on N coded bit sequences through N decoding threads.

[0104] In some embodiments of the present application, the electronic device may perform Huffman entropy decoding on a coded bit sequence through each decoding thread.

[0105] It should be noted that, for the description of Huffman entropy decoding, reference may be made to the specific description in the related art, which will not be described in detail in the embodiment of the present application.

[0106] An embodiment of the present application provides an image decoding method, in which the electronic device can determine the value of N based on at least one of the number of CPU cores and the load condition of the CPU cores, where N is an integer greater than 1, and obtain N coded bit sequences based on N and the coded bit stream corresponding to the target image, so that the electronic device can decode the N coded bit sequences through N decoding threads. Since the electronic device determines the value of N based on at least one of the number of CPU cores and the load condition of the CPU cores, that is, the value of N is related to the number of CPU cores and / or the load condition of the CPU cores, it can avoid the electronic device taking a long time to decode the image due to CPU overload. And since the N coded bit sequences are decoded through N decoding threads, the time for decoding the image can be shortened. In summary, the image decoding efficiency of the electronic device is improved.

[0107] In some embodiments of the present application, after the electronic device decodes N encoded bit sequences through N decoding threads, the electronic device can also adjust the position of the decoded data obtained by decoding in the memory, and transmit the adjusted decoded data to the register of the heterogeneous computing unit (such as a digital signal processing (DSP) module), wherein the number of the registers can be multiple (for example, 30), and the number of the registers can be related to the number of rows or columns of the decoded data included in the macroblock (for example, the second macroblock in the following embodiment) included in the adjusted decoded data, so that the register can perform inverse DCT on the decoded data to obtain YUV data of the target image, which will be illustrated below with an example.

[0108] In some embodiments of the present application, in combination with Figure 1, as shown in Figure 4, the above-mentioned step 103 can be specifically implemented through the following step 103a, and after the above-mentioned step 103a, the image decoding method provided in the embodiment of the present application can also include the following steps 201 and 202.

[0109] Step 103a: The electronic device decodes the N encoded bit sequences through N decoding threads to obtain first decoded data.

[0110] In an embodiment of the present application, the first decoded data includes decoded data of M first macroblocks, the target image corresponds to M first macroblocks, and M is an integer greater than 1.

[0111] In some embodiments of the present application, the N image blocks include M first macroblocks, and each image block includes at least two first macroblocks.

[0112] In some embodiments of the present application, after obtaining the first decoded data, the electronic device may store the first decoded data in a memory. After the first decoded data is stored in the memory, the decoded data of each first macroblock is continuous in the memory, that is, the decoded data of different rows of the first macroblock are continuous in the memory.

[0113] For example, assuming that M=8, and each of the M first macroblocks is an 8×8 macroblock, after the electronic device decodes the N coded bit sequences through N decoding threads, it can obtain first decoded data (i.e., 8 groups of decoded data), and each group of decoded data includes 64 decoded data, as shown in Figure 5a. At this time, the electronic device can store the 64 decoded data (e.g., A0 to A63) in the first first macroblock (e.g., macroblock A) of the M first macroblocks in the same row storage space in the memory of the electronic device. For example, the electronic device can store A0 to A63 in the first row storage space 10 in the memory of the electronic device, as shown in Figure 5b. As shown, the electronic device can then store the 64 decoded data (e.g., B0 to B63) in the second first macroblock (e.g., macroblock B) among the M first macroblocks in the same row of storage space in the memory of the electronic device. For example, the electronic device can store B0 to B63 in the second row of storage space 11 in the memory of the electronic device, and so on, until the 64 decoded data (e.g., H0 to H63) in the last first macroblock (e.g., macroblock H) among the M first macroblocks are stored in the same row of storage space in the memory of the electronic device. For example, the electronic device can store H0 to H63 in the Hth row of storage space 12 in the memory of the electronic device.

[0114] It should be noted that in Figures 5a and 5b, the decoded data of each first macroblock is located in the same row of storage space in the memory, which is used to indicate that the decoded data of each first macroblock is continuous in the memory, and does not limit the storage space to be divided into rows.

[0115] Step 201: The electronic device adjusts the position of the decoded data of M first macroblocks in the memory to obtain second decoded data.

[0116] In an embodiment of the present application, the above-mentioned second decoded data includes decoded data of M second macroblocks; wherein, after adjusting the position, different rows of decoded data of the first macroblock are discontinuous in the memory, and the same row of decoded data of adjacent first macroblocks are continuous in the memory.

[0117] In some embodiments of the present application, each of the M second macroblocks includes one line of decoded data of the M first macroblocks.

[0118] In some embodiments of the present application, the electronic device may adjust the positions of the decoded data of the M first macroblocks in the memory through the CPU core to obtain the second decoded data.

[0119] It can be understood that since the main frequency of the CPU core is higher than the main frequency of each register of the DSP, the time consumed by adjusting the position of the decoded data of the M first macroblocks in the memory through the CPU core is shorter than the time consumed by adjusting the position of the decoded data of the M first macroblocks in the memory through each register. Therefore, the electronic device can quickly adjust the position of the decoded data of the M first macroblocks in the memory through the CPU core.

[0120] For example, in combination with the above example, in combination with FIG5b, as shown in FIG6, the electronic device can first store the first row of decoded data included in the 8 groups of decoded data in the first row storage space 13 of the memory of the electronic device, that is, the 64 decoded data of A0 to A7, B0 to B7, C0 to C7, ..., H0 to H7, etc. are stored in the first row storage space 13 of the memory of the electronic device, and store the second row of decoded data included in the 8 groups of decoded data in the second row storage space 14 of the memory of the electronic device, that is, A8 to A15, B8 The 64 decoded data of A56~A63, B56~B63, C56~C63, …, H56~H63, etc. are stored in the second row storage space 14 in the memory of the electronic device, and so on, until the eighth row of decoded data included in the 8 groups of decoded data is stored in the eighth row storage space 15 in the memory of the electronic device, that is, the 64 decoded data of A56~A63, B56~B63, C56~C63, …, H56~H63, etc. are stored in the eighth row storage space 15 in the memory of the electronic device, so that eight groups of decoded data, that is, the second decoded data, can be obtained.

[0121] It should be noted that in Figure 6, different rows of decoded data of the first macroblock are located in different rows of storage space in the memory, and the same row of decoded data of adjacent first macroblocks are located in the same row of storage space in the memory, to illustrate that different rows of decoded data of the first macroblock are not connected in the memory, and the same row of decoded data of adjacent first macroblocks are continuous in the memory. In actual applications, the memory may not include any row of storage space, that is, there is no need to divide the memory into multiple rows of storage space.

[0122] In an embodiment of the present application, since the registers for inverse DCT require the use of macroblock data for calculation, after the decoded data is input into multiple registers of the DSP, the data of a macroblock is in the same register. The DCT calculation requires obtaining row data and performing mathematical operations with other rows. If the macroblock data is in the same register, relatively complex shift and XOR operations are required to obtain the data and perform the calculation, which is highly complex and inefficient. Therefore, in an embodiment of the present application, when the electronic device obtains the decoded data of M first macroblocks (i.e., first decoded data), it can first adjust the position of the decoded data of the M first macroblocks in the memory through the CPU to obtain the decoded data of M second macroblocks (i.e., second decoded data). After the position adjustment, the decoded data of different rows of the first macroblock are discontinuous in the memory, while the decoded data of the same row of adjacent first macroblocks are continuous in the memory. The electronic device can then transmit the second decoded data to multiple registers of the DSP, so that each register can directly use the second decoded data to perform inverse DCT to generate YUV data of the target image.

[0123] In some embodiments of the present application, in combination with FIG. 4 , as shown in FIG. 7 , the above step 201 may be specifically implemented through the following step 201 a.

[0124] Step 201a: The electronic device adjusts the position of the decoded data of L first macroblocks in the memory each time, and obtains second decoded data through P adjustments.

[0125] In the embodiment of the present application, M is equal to L multiplied by P; L is determined according to the bit width of the register, the length of a decoded data and the number of data in a row of the macroblock.

[0126] In some embodiments of the present application, L is determined based on a quotient of a first value and the number of data in a row of a macroblock, where the first value is the quotient of a register bit width and a decoding length.

[0127] For example, assuming that the number M of the M first macroblocks is 8, the first macroblock is an 8×8 macroblock, the bit width of the register is 1024 bits, the length of one decoded data is 16 bits, and the number of data in each row of the macroblock is 8, then L=1024 / 16 / 8=8, P=8 / 8=1, that is, the electronic device adjusts the position of the decoded data of 8 first macroblocks in the memory each time, and the second decoded data can be obtained through one adjustment.

[0128] It can be seen that since the electronic device can determine the number of first macroblocks to be adjusted each time based on the bit width of the register, the length of a decoded data and the number of data in a row of macroblocks, the second decoded data obtained by adjustment matches the bit width of the register. Therefore, in subsequent steps, multiple registers can directly use the second decoded data for inverse DCT to obtain the decoded data of the target image without the need for further adjustment. Therefore, the time spent in obtaining the decoded data of the target image can be reduced, that is, the image decoding efficiency of the electronic device can be improved.

[0129] Step 202: The electronic device transmits the second decoded data to the DSP register.

[0130] In some embodiments of the present application, the number of the registers may match the number of rows of decoded data included in the second macroblock. For example, when the second macroblock is an 8×8 macroblock, the electronic device may transfer the second decoded data to 8 registers of the DSP.

[0131] In some embodiments of the present application, after the second decoded data is transmitted to the DSP register, the register may perform an inverse DCT operation on the second decoded data to obtain image data of the target image, so that the electronic device may display the target image based on the image data.

[0132] Optionally, after the register performs an inverse DCT operation on the second decoded data, the electronic device can obtain the YUV data of the target image, so that the electronic device can continue to perform a color space conversion operation on the YUV data through the heterogeneous computing unit DSP, so that the electronic device can obtain the red, green, and blue (RGB) data of the target image and display the target image according to the RGB data of the target image.

[0133] In an embodiment of the present application, since the register needs to use the same row of decoded data of different macroblocks when performing an inverse DCT operation on the decoded data, in an embodiment of the present application, the electronic device can adjust the position of the decoded data of the M first macroblocks in the memory to obtain the second decoded data, wherein after the position is adjusted, the same row of decoded data of adjacent first macroblocks is continuous in the memory, so that after the second decoded data is transferred to the DSP register, the register can directly use the second decoded data to perform an inverse DCT operation without the register performing multiple operations to adjust the position of the decoded data of the M first macroblocks in the memory of the register. In this way, the time spent in obtaining the decoded data of the target image can be reduced, that is, the image decoding efficiency of the electronic device can be improved.

[0134] As can be seen, after obtaining the first decoded data, the electronic device can adjust the position of the decoded data of the M first macroblocks in the memory to obtain the decoded data of the M second macroblocks (i.e., the second decoded data). In this way, the electronic device can transfer the decoded data of the M second macroblocks to the DSP register, so that the DSP with lower power consumption can perform subsequent decoding actions on the decoded data of the M second macroblocks, without having to use the CPU core with higher power consumption to perform subsequent decoding actions on the decoded data of the M second macroblocks. Therefore, the power consumption of the electronic device for image decoding can be reduced. In addition, due to the large bit width of the DPS register, the DSP performs the inverse DCT transform and color space conversion, which can further improve the image decoding efficiency of the electronic device.

[0135] The image decoding method provided in the embodiment of the present application can be executed by an image decoding device. In the embodiment of the present application, the image decoding device performing the image decoding method is taken as an example to illustrate the image decoding device provided in the embodiment of the present application.

[0136] FIG8 illustrates a possible structural diagram of an image decoding apparatus according to an embodiment of the present application. As shown in FIG8 , the image decoding apparatus 50 may include: a processing module 51 configured to determine a value of N based on the number of CPU cores and / or CPU load, where N is an integer greater than 1; obtain N coded bit sequences based on N and a coded bit stream corresponding to a target image; and decode the N coded bit sequences using N decoding threads, where one decoding thread corresponds to each coded bit sequence.

[0137] An embodiment of the present application provides an image decoding device. Because the image decoding device determines the value of N based on at least one of the number of CPU cores and the CPU core load, that is, the value of N is related to the number of CPU cores and / or the CPU core load, this can prevent the image decoding device from taking a long time to decode an image due to CPU overload. Furthermore, because N coded bit sequences are decoded using N decoding threads, the image decoding time can be shortened. In summary, the image decoding efficiency of the image decoding device is improved.

[0138] In a possible implementation, the processing module 51 is specifically configured to scan the coded bit stream corresponding to the target image to obtain N-1 coded bit sequences, terminate the scan, and obtain the Nth coded bit sequence based on the bits in the coded bit stream that have not been scanned.

[0139] In a possible implementation, the processing module 51 is specifically configured to determine data length information corresponding to DC coefficients and data length information corresponding to AC coefficients of macroblocks in the coded bit stream corresponding to the target image based on Huffman coding characteristics.

[0140] In one possible implementation, the processing module 51 is specifically configured to decode N coded bit sequences through N decoding threads to obtain first decoded data, where the first decoded data includes decoded data of M first macroblocks, and the target image corresponds to the M first macroblocks; and after decoding the N coded bit sequences through N decoding threads to obtain the first decoded data, adjust the positions of the decoded data of the M first macroblocks in the memory to obtain second decoded data, where the second decoded data includes decoded data of M second macroblocks; wherein, after the positions are adjusted, different rows of decoded data of the first macroblock are discontinuous in the memory, and the same row of decoded data of adjacent first macroblocks are continuous in the memory, and M is an integer greater than 1; and transmit the second decoded data to the DSP register.

[0141] In one possible implementation, the processing module 51 is specifically configured to adjust the position of the decoded data of L first macroblocks in the memory each time, and obtain the second decoded data through P adjustments; wherein M is equal to L multiplied by P; L is determined based on the bit width of the register, the length of one decoded data, and the number of data rows in a macroblock, and both L and P are positive integers.

[0142] The image decoding device in the embodiment of the present application can be an electronic device or a component in the electronic device, such as an integrated circuit or chip. The electronic device can be a terminal or other device other than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a mobile internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc. It can also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine or a self-service machine, etc., and the embodiment of the present application does not specifically limit it.

[0143] The image decoding device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0144] The image decoding device provided in the embodiment of the present application can implement each process implemented in the method embodiments of Figures 1 to 7. To avoid repetition, they will not be described here.

[0145] In some embodiments of the present application, as shown in Figure 9, the embodiment of the present application further provides an electronic device 60, including a processor 61 and a memory 62, and the memory 62 stores a program or instruction that can be run on the processor 61. When the program or instruction is executed by the processor 61, the various process steps of the above-mentioned image decoding method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0146] It should be noted that the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.

[0147] FIG10 is a schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application.

[0148] The electronic device 100 includes but is not limited to components such as a radio frequency unit 101 , a network module 102 , an audio output unit 103 , an input unit 104 , a sensor 105 , a display unit 106 , a user input unit 107 , an interface unit 108 , a memory 109 , and a processor 110 .

[0149] Those skilled in the art will appreciate that the electronic device 100 may further include a power source (such as a battery) for powering various components. The power source may be logically connected to the processor 110 via a power management system, thereby enabling the power management system to manage charging, discharging, and power consumption. The electronic device structure shown in FIG10 does not limit the electronic device. The electronic device may include more or fewer components than shown, or may combine certain components or arrange the components differently, which will not be described in detail here.

[0150] The processor 110 is configured to determine a value of N based on the number of CPU cores and / or load conditions, where N is an integer greater than 1; obtain N coded bit sequences based on N and a coded bit stream corresponding to a target image; and decode the N coded bit sequences using N decoding threads.

[0151] Among them, one decoding thread corresponds to one encoded bit sequence.

[0152] An embodiment of the present application provides an electronic device. Because the electronic device determines the value of N based on at least one of the number of CPU cores and the load of the CPU cores, that is, the value of N is related to the number of CPU cores and / or the load of the CPU cores, this can avoid the electronic device requiring a long time to decode an image due to CPU overload. Furthermore, because N coded bit sequences are decoded using N decoding threads, the time required to decode the image can be shortened. In summary, the image decoding efficiency of the electronic device is improved.

[0153] In some embodiments of the present application, the processor 110 is specifically configured to scan the coded bit stream corresponding to the target image to obtain N-1 coded bit sequences, terminate the scan, and obtain the Nth coded bit sequence based on the bits in the coded bit stream that have not been scanned.

[0154] In some embodiments of the present application, the processor 110 is specifically configured to determine data length information corresponding to DC coefficients and data length information corresponding to AC coefficients of macroblocks in a coded bit stream corresponding to a target image based on Huffman coding characteristics.

[0155] In some embodiments of the present application, the processor 110 is specifically configured to decode N encoded bit sequences through N decoding threads to obtain first decoded data, where the first decoded data includes decoded data of M first macroblocks, and the target image corresponds to the M first macroblocks.

[0156] The processor 110 is further configured to adjust the position of the decoded data of the M first macroblocks in the memory to obtain second decoded data, where the second decoded data includes the decoded data of the M second macroblocks; wherein, after the position adjustment, the decoded data of different rows of the first macroblocks are discontinuous in the memory, and the decoded data of the same row of adjacent first macroblocks are continuous in the memory, where M is an integer greater than 1; and transmit the second decoded data to the DSP register.

[0157] In some embodiments of the present application, the processor 110 is specifically configured to adjust the position of the decoded data of L first macroblocks in the memory each time, and obtain the second decoded data through P adjustments.

[0158] Wherein, M is equal to L multiplied by P; L is determined according to the bit width of the register, the length of a decoded data and the number of data in one row of the macroblock, and both L and P are positive integers.

[0159] It should be understood that in an embodiment of the present application, the input unit 104 may include a graphics processing unit (GPU) 1041 and a microphone 1042, and the graphics processor 1041 processes image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 107 includes a touch panel 1071 and at least one of other input devices 1072. The touch panel 1071 is also called a touch screen. The touch panel 1071 may include two parts: a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0160] The memory 109 can be used to store software programs and various data. The memory 109 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, applications or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 109 may include a volatile memory or a non-volatile memory, or the memory 109 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM), and a direct rambus RAM (DRRAM). The memory 109 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0161] Processor 110 may include one or more processing units. Optionally, processor 110 integrates an application processor and a modem processor. The application processor primarily handles operations related to the operating system, user interface, and application programs, while the modem processor primarily processes wireless communication signals, such as a baseband processor. It is understood that the modem processor may not be integrated into processor 110.

[0162] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned image decoding method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0163] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0164] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned image decoding method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0165] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0166] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned image decoding method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0167] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0168] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0169] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. An image decoding method, wherein, The method includes: The electronic device determines the value of N according to the number and / or load condition of CPU cores, where N is an integer greater than 1; The electronic device obtains N encoded bit sequences according to N and the encoded bitstream corresponding to the target image; The electronic device decodes the N encoded bit sequences through N decoding threads; Wherein, one of the decoding threads corresponds to one of the encoded bit sequences.

2. The method according to claim 1, wherein The electronic device obtains N encoded bit sequences according to N and the encoded bitstream corresponding to the target image, including: The electronic device scans the encoded bitstream corresponding to the target image to obtain N - 1 encoded bit sequences, ends the scan, and obtains the Nth encoded bit sequence according to the bits in the encoded bitstream that have not been scanned.

3. The method according to claim 2, wherein The electronic device scans the encoded bitstream corresponding to the target image, including: The electronic device determines the data length information corresponding to the DC coefficient of the macroblock and the data length information corresponding to the AC coefficient of the macroblock in the encoded bitstream corresponding to the target image according to the Huffman coding characteristics.

4. The method according to claim 1, wherein, The electronic device decodes the N encoded bit sequences through N decoding threads, including: The electronic device decodes the N encoded bit sequences through N decoding threads to obtain first decoded data, where the first decoded data includes the decoded data of M first macroblocks, and the target image corresponds to M first macroblocks; After decoding the N encoded bit sequences through N decoding threads to obtain the first decoded data, the method further includes: The electronic device adjusts the positions of the decoded data of the M first macroblocks in the memory to obtain second decoded data, where the second decoded data includes the decoded data of M second macroblocks; wherein, after adjusting the positions, the decoded data of different rows of the first macroblock are not continuous in the memory, and the decoded data of the same row of adjacent first macroblocks are continuous in the memory, and M is an integer greater than 1; The electronic device transfers the second decoded data to the digital signal processing (DSP) register.

5. The method according to claim 4, wherein, The electronic device adjusts the positions of the decoded data of the M first macroblocks in the memory to obtain second decoded data, including: The electronic device adjusts the positions of the decoded data of L first macroblocks in the memory each time, and obtains the second decoded data through P adjustments; Wherein, M is equal to L multiplied by P; L is determined according to the bit width of the register, the length of one decoded data, and the number of data in one row of the macroblock, and both L and P are positive integers.

6. An image decoding device, wherein, The image decoding device includes: A processing module, configured to determine the value of N according to the number and / or load condition of CPU cores, where N is an integer greater than 1; and obtain N encoded bit sequences according to N and the encoded bitstream corresponding to the target image; and decode the N encoded bit sequences through N decoding threads; Wherein, one of the decoding threads corresponds to one of the encoded bit sequences.

7. The image decoding apparatus according to claim 6, wherein, The processing module is specifically configured to scan the encoded bitstream corresponding to the target image to obtain N - 1 encoded bit sequences, end the scan, and obtain the Nth encoded bit sequence according to the bits in the encoded bitstream that have not been scanned.

8. The image decoding device according to claim 7, wherein, The processing module is specifically configured to determine the data length information corresponding to the DC coefficient of the macroblock and the data length information corresponding to the AC coefficient of the macroblock in the encoded bitstream corresponding to the target image according to the Huffman coding characteristics.

9. The image decoding apparatus according to claim 6, wherein The processing module is specifically configured to decode the N encoded bit sequences through the N decoding threads to obtain first decoded data, where the first decoded data includes the decoded data of M first macroblocks, and the target image corresponds to M first macroblocks; and after decoding the N encoded bit sequences through the N decoding threads to obtain the first decoded data, adjust the positions of the decoded data of the M first macroblocks in the memory to obtain second decoded data, where the second decoded data includes the decoded data of M second macroblocks; wherein, after the position adjustment, the decoded data of different rows of the first macroblock are not continuous in the memory, and the decoded data of the same row of adjacent first macroblocks are continuous in the memory, and M is an integer greater than 1; and, transmit the second decoded data to the DSP register.

10. The image decoding device according to claim 9, wherein, The processing module is specifically configured to adjust the positions of the decoded data of L first macroblocks in the memory each time, and obtain the second decoded data through P adjustments; wherein, M is equal to L multiplied by P; L is determined according to the bit width of the register, the length of a decoded data, and the number of data in one row of the macroblock, and both L and P are positive integers.

11. An electronic device, wherein, It includes a processor and a memory, and the memory stores a program or instruction that can run on the processor. When the program or instruction is executed by the processor, the steps of the image decoding method according to any one of claims 1 to 5 are implemented.

12. A readable storage medium, wherein, A program or instruction is stored on the readable storage medium. When the program or instruction is executed by a processor, the steps of the image decoding method according to any one of claims 1 to 5 are implemented.

13. A chip, the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run a program or instruction to implement the steps of the image decoding method according to any one of claims 1 to 5.

14. A computer program product, the computer program product is stored in a non - volatile storage medium, and the computer program product is executed by at least one processor to implement the steps of the image decoding method according to any one of claims 1 to 5.

15. An electronic device, the electronic device is configured to execute the steps of the image decoding method according to any one of claims 1 to 5.

Images