Interposer

Abstract

This interposer comprises: a silicon substrate; a through-wiring part; a plurality of conductor parts; a dielectric film; and a substrate electrode. The silicon substrate has a first main surface, and a second main surface on the side opposite the first main surface. The through-wiring part penetrates the silicon substrate in the thickness direction of the silicon substrate. The plurality of conductor parts protrude from a side surface of the through-wiring part. The dielectric film is interposed between the silicon substrate and the side surface of the through-wiring part as well as the plurality of conductor parts. The substrate electrode is connected to the silicon substrate.

Description

Interposer

[0001] The present disclosure relates to interposers, and more particularly to interposers comprising silicon substrates.

[0002] Non-Patent Document 1 describes a silicon substrate, a through silicon via (TSV), an insulating layer surrounding the through silicon via, and a SiO ２ layer (TSV liner) and SiO ２ A structure is disclosed that includes a first electrode layer surrounding a silicon substrate, a high-k dielectric layer surrounding the first electrode layer, a second electrode layer surrounding the high-k dielectric layer, and an insulating layer interposed between the second electrode layer and the silicon substrate.

[0003] “Modeling, Fabrication, and Characterization of 3-D Capacitor Embedded in Through-Silicon Via”, Ye Lin , Student Member, IEEE, and Chuan Seng Tan , Member, IEEE, IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 8, NO.9, SEPTEMBER 2018

[0004] In an interposer equipped with a capacitor, there is a demand for increasing the capacitance of the capacitor while also achieving miniaturization.

[0005] An interposer according to one aspect of the present disclosure includes a silicon substrate, a through wiring portion, a plurality of conductor portions, a dielectric film, and a substrate electrode. The silicon substrate has a first main surface and a second main surface opposite to the first main surface. The through wiring portion penetrates the silicon substrate in the thickness direction of the silicon substrate. The plurality of conductor portions protrude from the through wiring portion in a direction intersecting the thickness direction of the silicon substrate. The dielectric film is interposed between a side surface of the through wiring portion and the silicon substrate, and between the plurality of conductor portions and the silicon substrate. The substrate electrode is connected to the silicon substrate.

[0006] An interposer according to one aspect of the present disclosure makes it possible to increase the capacitance of a capacitor while achieving miniaturization.

[0007] FIG. 1 is a cross-sectional view of an interposer according to a first embodiment. FIG. 2A is a schematic plan view of a main portion of the interposer. FIG. 2B is a cross-sectional view of the interposer taken along line X-X in FIG. 2A, showing the interposer. FIG. 3 is a conceptual diagram of a capacitor included in the interposer. FIG. 4A is a cross-sectional view of a module including the interposer. FIG. 4B is another cross-sectional view of the module shown in FIG. 4A. FIG. 5 is an equivalent circuit diagram of a module including the interposer. FIG. 6A is a cross-sectional view illustrating steps in a method for manufacturing the interposer. FIG. 6B is a cross-sectional view illustrating steps in a method for manufacturing the interposer. FIG. 6C is a cross-sectional view illustrating steps in a method for manufacturing the interposer. FIG. 7A is a cross-sectional view illustrating steps in a method for manufacturing the interposer. FIG. 7B is a cross-sectional view illustrating steps in a method for manufacturing the interposer. FIG. 7C is a cross-sectional view illustrating steps in a method for manufacturing the interposer. FIG. 8A is a cross-sectional view illustrating steps in a method for manufacturing the interposer. 8B is a process cross-sectional view illustrating a method for manufacturing the interposer of the same embodiment. FIG. 8C is a process cross-sectional view illustrating a process for manufacturing the interposer of the same embodiment. FIG. 9A is a process cross-sectional view illustrating a process for manufacturing the interposer of the same embodiment. FIG. 9B is a process cross-sectional view illustrating a process for manufacturing the interposer of the same embodiment. FIG. 9C is a process cross-sectional view illustrating a process for manufacturing the interposer of the same embodiment. FIG. 10A is a process cross-sectional view illustrating a process for manufacturing the interposer of the same embodiment. FIG. 10B is a process cross-sectional view illustrating a process for manufacturing the interposer of the same embodiment. FIG. 10C is a process cross-sectional view illustrating a process for manufacturing the interposer of the same embodiment. FIG. 11A is a process cross-sectional view illustrating a process for manufacturing the interposer of the same embodiment. FIG. 11B is a process cross-sectional view illustrating a process for manufacturing the interposer of the same embodiment. FIG. 12A is a schematic plan view of a main part of an interposer according to a second embodiment. FIG. 12B is a cross-sectional view of the interposer of the same embodiment, taken along line X-X of FIG. 12A. FIG. 13 is a cross-sectional view of an interposer according to a third embodiment. FIG. 14 is a cross-sectional view of an interposer according to the fourth embodiment.

[0008] Hereinafter, embodiments 1 to 4 will be described with reference to the drawings. The drawings referred to in the following embodiments 1 to 4 are schematic diagrams, and the sizes and thicknesses of the components in the drawings do not necessarily reflect the actual dimensions, and the size ratios and thickness ratios between the components do not necessarily reflect the actual dimensional ratios.

[0009] (First Embodiment) (1) Interposer Hereinafter, the configuration of an interposer 1 according to a first embodiment will be described with reference to the drawings.

[0010] As shown in FIG. 1 , the interposer 1 according to the first embodiment includes a silicon substrate 2, a through wiring portion 3, a plurality of conductor portions 5, a dielectric film 4, and a substrate electrode 6. The silicon substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. The first main surface 21 and the second main surface 22 of the silicon substrate 2 are aligned in a thickness direction D1 of the silicon substrate 2 and are perpendicular to the thickness direction D1. The through wiring portion 3 penetrates the silicon substrate 2 in the thickness direction D1 of the silicon substrate 2. The plurality of conductor portions 5 protrude from the through wiring portion 3 in a direction intersecting the thickness direction D1 of the silicon substrate 2. The dielectric film 4 is interposed between a side surface 30 of the through wiring portion 3 and the silicon substrate 2, and between the plurality of conductor portions 5 and the silicon substrate 2. The substrate electrode 6 is connected to the silicon substrate 2.

[0011] The interposer 1 according to the first embodiment realizes a capacitor C1 (see FIG. 3 ) including a through wiring portion 3, a plurality of conductor portions 5, a dielectric film 4, and a silicon substrate 2, thereby enabling an increase in the capacitance of the capacitor C1 while achieving miniaturization. The capacitor C1 in the interposer 1 according to the first embodiment includes a first electrode 101, a second electrode 102, and a dielectric film 4, where the first electrode 101 includes the through wiring portion 3 and the plurality of conductor portions 5, the second electrode 102 includes the silicon substrate 2, and the dielectric film 4 is interposed between the first electrode 101 and the second electrode 102.

[0012] In the interposer 1 according to the first embodiment, the silicon substrate 2 has a through hole 23 extending along the thickness direction D1 of the silicon substrate 2. The through wiring portion 3 is disposed in the through hole 23 of the silicon substrate 2. The through wiring portion 3 has a first end 31 and a second end 32. The silicon substrate 2 further includes a porous region 25. The porous region 25 has a plurality of pores 26 formed from an inner circumferential surface 24 of the through hole 23 into the silicon substrate 2. The porous region 25 surrounds the through wiring portion 3 (see FIGS. 2A and 2B ). The dielectric film 4 covers the inner circumferential surface 24 of the through hole 23 in the silicon substrate 2 and the inner circumferential surfaces 27 of each of the plurality of pores 26 in the porous region 25. The plurality of conductor portions 5 protrude from the side surface 30 of the through wiring portion 3 and cover portions 42 of the dielectric film 4 located inside each of the plurality of pores 26.

[0013] The interposer 1 according to the first embodiment further includes a first insulating layer 7, a second insulating layer 8, a first external electrode 11, and a second external electrode 12. The first insulating layer 7 is disposed on the first main surface 21 of the silicon substrate 2. The second insulating layer 8 is disposed on the second main surface 22 of the silicon substrate 2. The first external electrode 11 is connected to the through wiring portion 3 and exposed through an opening 71 in the first insulating layer 7. The second external electrode 12 is connected to the through wiring portion 3 and exposed through a first opening 81 in the second insulating layer 8. The substrate electrode 6 is disposed on the second main surface 22 of the silicon substrate 2 and exposed through a second opening 82 in the second insulating layer 8.

[0014] The interposer 1 according to the first embodiment is disposed between a semiconductor chip 300 and a mounting substrate 400, as shown in, for example, FIG. 4A. The semiconductor chip 300 includes, for example, a processor, a logic integrated circuit (IC), a memory (for example, a high bandwidth memory (HBM)), etc. FIG. 5 is an equivalent circuit diagram of a module 500 including the interposer 1 shown in FIG. 4A.

[0015] (2) Components of the Interposer Hereinafter, each component of the interposer 1 according to the first embodiment will be described with reference to FIGS.

[0016] (2.1) Silicon Substrate In this embodiment, the silicon substrate 2 is, for example, a p-type silicon substrate. The resistivity of the p-type silicon substrate is preferably 0.1 Ωcm or more and 1 Ωcm or less. In this case, the carrier concentration of the p-type silicon substrate is 1×10 １８ cm －３ 1x10 or more １９ cm －３ The following is preferable: The p-type silicon substrate contains, for example, boron as an impurity. The p-type silicon substrate contains boron as an impurity, but may contain indium as an impurity instead of boron.

[0017] 1, the silicon substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. When viewed from a thickness direction D1 of the silicon substrate 2, the outer edge of the silicon substrate 2 has a rectangular shape (see FIG. 2A). The thickness of the silicon substrate 2 is, for example, not less than 300 μm and not more than 1 mm.

[0018] The silicon substrate 2 has a through hole 23 extending along a thickness direction D1 of the silicon substrate 2. In the first main surface 21 of the silicon substrate 2, the opening shape of the through hole 23 is, for example, circular (see FIG. 2A ). In addition, in the second main surface 22 of the silicon substrate 2, the opening shape of the through hole 23 is, for example, circular.

[0019] The silicon substrate 2 further includes a porous region 25. The porous region 25 has a plurality of pores 26 formed from the inner peripheral surface 24 of the through hole 23 into the silicon substrate 2. FIG. 1 schematically shows a portion of a group of pores 26 among the plurality of pores 26 that are visible in the X-X cross section of FIG. 2A. The plurality of pores 26 extend in a direction intersecting the thickness direction D1 of the silicon substrate 2. The plurality of pores 26 communicate with the through hole 23. The porous region 25 surrounds the through wiring portion 3. In this embodiment, the porous region 25 is a cylindrical region that is long in the thickness direction D1 of the silicon substrate 2.

[0020] The depth of each of the plurality of pores 26 from the inner circumferential surface 24 of the through hole 23 is preferably equal to or greater than the inner diameter of the through hole 23. The depth of the plurality of pores 26 is also smaller than the thickness of the silicon substrate 2. The plurality of pores 26 do not reach the side surface of the silicon substrate 2. The opening width of each of the plurality of pores 26 on the inner circumferential surface 24 of the through hole 23 is, for example, equal to or greater than 0.1 μm and equal to or less than 10 μm.

[0021] In the interposer 1 of this embodiment, the deeper the pores 26 in the porous region 25, the larger the surface area of ​​the surface 251 of the porous region 25, and the larger the capacitance of the capacitor. Also, in the interposer 1 of this embodiment, the greater the number of pores 26 in the porous region 25, the larger the surface area of ​​the surface 251 of the porous region 25, and the larger the capacitance of the capacitor C1.

[0022] (2.2) Through Wiring Portion The through wiring portion 3 penetrates the silicon substrate 2 in the thickness direction D1 of the silicon substrate 2. The through wiring portion 3 is a long straight line in the thickness direction D1 of the silicon substrate 2. The outer diameter of the through wiring portion 3 is determined by the inner diameter of the through hole 23. The through wiring portion 3 is located in the through hole 23 of the silicon substrate 2. In the interposer 1, the through hole 23 is filled with the through wiring portion 3. Therefore, the through wiring portion 3 is a through hole wiring. The material of the through wiring portion 3 includes, for example, copper. The material of the through wiring portion 3 is not limited to copper and may be, for example, nickel.

[0023] The through wiring portion 3 has a first end 31 and a second end 32 in the thickness direction D1 of the silicon substrate 2. The first end 31 of the through wiring portion 3 is an end portion close to the first main surface 21 of the silicon substrate 2 in the thickness direction D1 of the silicon substrate 2, and the second end 32 of the through wiring portion 3 is an end portion close to the second main surface 22 of the silicon substrate 2 in the thickness direction D1 of the silicon substrate 2.

[0024] (2.3) Dielectric Film The dielectric film 4 covers the inner circumferential surface 24 of the through hole 23 in the silicon substrate 2 and the inner circumferential surface 27 of each of the multiple pores 26 in the porous region 25. The dielectric film 4 has a shape that conforms to the inner circumferential surface 24 of the through hole 23 in the silicon substrate 2 and the inner circumferential surface 27 of each of the multiple pores 26 in the porous region 25. From another perspective, the dielectric film 4 covers the side surface 30 of the through wiring portion 3 and the multiple conductor portions 5. In other words, the dielectric film 4 is interposed between the first electrode including the through wiring portion 3 and the multiple conductor portions 5, and the second electrode including the silicon substrate 2.

[0025] The thickness of the dielectric film 4 is, for example, 10 nm to 500 nm, and the upper limit of the thickness of the dielectric film 4 is limited by the opening width of the plurality of pores 26 and the like.

[0026] From the viewpoint of increasing the capacitance of the capacitor C1, the material of the dielectric film 4 is preferably a material having a higher dielectric constant than both silicon oxide and silicon nitride. The material of the dielectric film 4 is, for example, hafnium oxide. The material of the dielectric film 4 is not limited to hafnium oxide, but may be, for example, tantalum oxide or zirconium oxide.

[0027] (2.4) Multiple Conductors The multiple conductors 5 protrude from the through wiring portion 3 in a direction intersecting the thickness direction D1 of the silicon substrate 2. In this embodiment, the multiple conductors 5 protrude from the side surface 30 of the through wiring portion 3 in a direction intersecting the thickness direction D1 of the silicon substrate 2. The multiple conductors 5 are connected to the through wiring portion 3. "The multiple conductors 5 are connected to the through wiring portion 3" means that the multiple conductors 5 are electrically connected to the through wiring portion 3. The multiple conductors 5 are formed integrally with the through wiring portion 3. In other words, the multiple conductors 5 are seamlessly connected to the through wiring portion 3. The material of each of the multiple conductors 5 is the same as the material of the through wiring portion 3. The material of the multiple conductors 5 is, for example, copper. The material of the multiple conductors 5 is not limited to copper and may be, for example, nickel.

[0028] Each of the plurality of conductors 5 entirely overlaps the first insulating layer 7 in the thickness direction D1 of the silicon substrate 2. Furthermore, each of the plurality of conductors 5 entirely overlaps the second insulating layer 8 in the thickness direction D1 of the silicon substrate 2.

[0029] (2.5) Substrate Electrode The substrate electrode 6 is connected to the silicon substrate 2. "The substrate electrode 6 is connected to the silicon substrate 2" means that the substrate electrode 6 is electrically connected to the silicon substrate 2, and more specifically, that the substrate electrode 6 and the silicon substrate 2 are in ohmic contact.

[0030] The material of the substrate electrode 6 includes, for example, copper. The material of the substrate electrode 6 is the same as the material of the second external electrode 12. The material of the substrate electrode 6 may be a material different from the material of the second external electrode 12.

[0031] The substrate electrode 6 is disposed on the second main surface 22 of the silicon substrate 2, and is exposed through the second opening 82 in the second insulating layer 8. The thickness of the portion of the substrate electrode 6 that overlaps with the second insulating layer 8 in the thickness direction D1 of the silicon substrate 2 is, for example, not less than 2 μm and not more than 3 μm.

[0032] In a plan view from the thickness direction D1 of the silicon substrate 2, the outer edge of the substrate electrode 6 is, for example, rectangular (see FIG. 2A ), but is not limited to a rectangular shape and may be, for example, circular. In a plan view from the thickness direction D1 of the silicon substrate 2, the substrate electrode 6 does not overlap with the through-wiring portion 3. In addition, in a plan view from the thickness direction D1 of the silicon substrate 2, the substrate electrode 6 does not overlap with the dielectric film 4 and the plurality of pores 26. Therefore, in a plan view from the thickness direction D1 of the silicon substrate 2, the substrate electrode 6 does not overlap with the porous region 25.

[0033] (2.6) First Insulating Layer and Second Insulating Layer The first insulating layer 7 is disposed on the first main surface 21 of the silicon substrate 2. The first insulating layer 7 has electrical insulation properties. The first insulating layer 7 is, for example, a first silicon oxide layer (first SiO ２ layer), and a first silicon nitride layer (first Si layer) laminated on the first silicon oxide layer. ３ N ４The first insulating layer 7 includes a first silicon oxide layer (layer). The thickness of the first silicon oxide layer is, for example, 1 μm, but is not limited to 1 μm. The thickness of the first silicon nitride layer is, for example, 0.2 μm, but is not limited to 0.2 μm. The first insulating layer 7 has a laminated structure of a first silicon oxide layer and a first silicon nitride layer, but may be composed of, for example, only a first silicon oxide layer.

[0034] The second insulating layer 8 is disposed on the second main surface 22 of the silicon substrate 2. The second insulating layer 8 has electrical insulation properties. The second insulating layer 8 is, for example, a second silicon oxide layer (second SiO ２ layer), and a second silicon nitride layer (second Si layer) laminated on the second silicon oxide layer. ３ N ４ The second insulating layer 8 includes a second silicon oxide layer (layer). The thickness of the second silicon oxide layer is, for example, 1 μm, but is not limited to 1 μm. The thickness of the second silicon nitride layer is, for example, 0.2 μm, but is not limited to 0.2 μm. The second insulating layer 8 has a laminated structure of a second silicon oxide layer and a second silicon nitride layer, but may be composed of, for example, only a second silicon oxide layer.

[0035] (2.7) First External Electrode and Second External Electrode The first external electrode 11 is connected to the through wiring portion 3 and exposed through the opening 71 in the first insulating layer 7. "The first external electrode 11 is connected to the through wiring portion 3" means that the first external electrode 11 is connected to (the first end 31 of) the through wiring portion 3 and is electrically connected to the through wiring portion 3. In this embodiment, the first external electrode 11 is formed integrally with the through wiring portion 3. In other words, the first external electrode 11 is seamlessly connected to the through wiring portion 3. The material of the first external electrode 11 includes, for example, copper. The material of the first external electrode 11 is, for example, the same as the material of the through wiring portion 3, but may be a material different from the material of the through wiring portion 3. The thickness of the first external electrode 11 is, for example, 2 μm or more and 3 μm or less.

[0036] In a plan view from the thickness direction D1 of the silicon substrate 2, the first external electrode 11 is larger than the through wiring portion 3. In the present embodiment, in a plan view from the thickness direction D1 of the silicon substrate 2, a part of the first external electrode 11 overlaps the entire through wiring portion 3. In a plan view from the thickness direction D1 of the silicon substrate 2, the outer edge of the first external electrode 11 is, for example, rectangular, but is not limited to a rectangular shape and may be, for example, circular.

[0037] The second external electrode 12 is connected to the through wiring portion 3 and is exposed through the first opening 81 of the second insulating layer 8. "The second external electrode 12 is connected to the through wiring portion 3" means that the second external electrode 12 is connected to (the second end 32 of) the through wiring portion 3 and is electrically connected to the through wiring portion 3. The material of the second external electrode 12 includes, for example, copper. The material of the second external electrode 12 may be, for example, the same as the material of the through wiring portion 3 but may be a different material from the material of the through wiring portion 3 (for example, a copper alloy or an aluminum alloy). The material of the second external electrode 12 may also be the same as the material of the first external electrode 11 but may be a different material from the material of the first external electrode 11. The thickness of the second external electrode 12 is, for example, 2 μm or more and 3 μm or less.

[0038] In a plan view from the thickness direction D1 of the silicon substrate 2, the second external electrode 12 is larger than the through wiring portion 3. In the present embodiment, in a plan view from the thickness direction D1 of the silicon substrate 2, a part of the second external electrode 12 overlaps the entire through wiring portion 3. In a plan view from the thickness direction D1 of the silicon substrate 2, the outer edge of the second external electrode 12 is, for example, rectangular, but is not limited to a rectangular shape and may be, for example, circular.

[0039] (3) Method for Manufacturing Interposer A method for manufacturing the interposer 1 according to the first embodiment will be described with reference to FIGS. 6A to 11B.

[0040] The manufacturing method of the interposer 1 includes, for example, the first to seventeenth steps.

[0041] In the first step, a p-type silicon wafer 20 (see FIG. 6A ) that will become the silicon substrate 2 is prepared. The resistivity of the p-type silicon wafer 20 prepared in the first step is, for example, 0.1 Ωcm or more and 1 Ωcm or less. The p-type silicon wafer 20 has a first main surface 201 and a second main surface 202 opposite to the first main surface 201. The first main surface 201 of the p-type silicon wafer 20 corresponds to the first main surface 21 of the silicon substrate 2. The p-type silicon wafer 20 is thicker than the silicon substrate 2. The first main surface 201 of the p-type silicon wafer 20 is, for example, a (100) plane, but is not limited thereto and may be, for example, a (110) plane or a (111) plane. Furthermore, the first main surface 201 of the p-type silicon wafer 20 may be, for example, a crystal plane whose off-angle from the (100) plane is greater than 0° and less than or equal to 5°. Here, the "off angle" refers to the tilt angle of the first main surface 201 with respect to the (100) plane. Therefore, if the off angle is 0°, the first main surface 201 is a (100) plane.

[0042] In the second step, as shown in FIG. 6B , an insulating layer 70, which will become the first insulating layer 7, is formed on the first main surface 201 of the p-type silicon wafer 20, and an insulating layer 90 is formed on the second main surface 202 of the p-type silicon wafer 20. The insulating layer 70 includes a first silicon oxide layer and a first silicon nitride layer laminated on the first silicon oxide layer. The insulating layer 90 includes a third silicon oxide layer and a third silicon nitride layer laminated on the third silicon oxide layer. When forming the insulating layers 70 and 90, for example, a first step and a second step are performed sequentially. In the first step, for example, a first silicon oxide layer is formed on the first main surface 201 of the p-type silicon wafer 20, and a second silicon oxide layer is formed on the second main surface 202 of the p-type silicon wafer 20 by thermal oxidation. In the second step, a first silicon nitride layer is laminated on the first silicon oxide layer, and a second silicon nitride layer is laminated on the second silicon oxide layer, for example, by a CVD (Chemical Vapor Deposition) method.

[0043] In the third step, the insulating layer 70 is patterned using photolithography and etching techniques to form the first insulating layer 7 having the first opening 71 (see FIG. 6C ). Also in the third step, the insulating layer 90 is etched away.

[0044] In the fourth step, holes 230 are formed in the regions of the first main surface 201 of the p-type silicon wafer 20 where the through holes 23 are to be formed, for example, by deep reactive ion etching (Deep RIE) using the first insulating layer 7 as a mask (see FIG. 7A ). The depth of the holes 230 is deeper than the length of the through wiring portions 3 (see FIG. 1 ) and does not reach the second main surface 202 of the p-type silicon wafer 20. The opening shape of the holes 230 is, for example, circular. The inner diameter of the holes 230 is, for example, 200 μm.

[0045] In the fifth step, a metallization layer 9 is formed on the second main surface 202 of the p-type silicon wafer 20 (see FIG. 7B). The material of the metallization layer 9 includes, for example, aluminum. The thickness of the metallization layer 9 is, for example, 200 nm.

[0046] In the sixth step, the p-type silicon wafer 20 is anodized using the p-type silicon wafer 20 as an anode, thereby forming a plurality of pores 26 in the p-type silicon wafer 20 that communicate with the through-holes 23 (see FIG. 7C ). In the anodization process, platinum electrodes are placed opposite the first insulating layer 7 in an electrolyte, and a current of a predetermined current density is passed between the anode and the cathode, with the p-type silicon wafer 20 serving as the anode and the platinum electrode serving as the cathode, for a predetermined time. This anodization process thereby renders a portion of the p-type silicon wafer 20 porous, thereby forming the plurality of pores 26. The electrolyte is, for example, a mixture of hydrofluoric acid, ethanol, and water. The anodization process increases the inner diameter of the holes 230 compared to before the anodization process. In the sixth step, the shape and depth of the plurality of pores 26 can be controlled by changing at least one of the hydrogen fluoride concentration in the electrolyte, the predetermined current density, and the predetermined time. The concentration of hydrogen fluoride in the electrolyte is, for example, 1 wt % to 80 wt %, and more preferably 20 wt % to 40 wt %. In addition, in the method for manufacturing the interposer 1, the shape of the plurality of pores 26 can also be changed by changing the resistivity of the p-type silicon wafer 20, which is determined by the carrier concentration of the p-type silicon wafer 20.

[0047] In the seventh step, the metallization layer 9 is removed from the second main surface 202 of the p-type silicon wafer 20 (see FIG. 8A). In the seventh step, the metallization layer 9 is removed by, for example, wet etching.

[0048] In the eighth step, the dielectric film 4 is selectively formed on the inner circumferential surface of the hole 230 and the inner circumferential surface of each of the plurality of pores 26 by, for example, CVD (see FIG. 8B).

[0049] In the ninth step, a metal thin film 10 is formed by, for example, CVD to cover the first insulating layer 7 and the dielectric film 4 (see FIG. 8C). The material of the metal thin film 10 is, for example, copper, but may be a metal other than copper.

[0050] In the tenth step, a metal (e.g., copper) is deposited by electroplating using the thin metal film 10 as a seed layer to form a metal portion 14 in the hole 230 and the plurality of pores 26 (see FIG. 9A ). The metal portion 14 includes a first portion 141 overlapping the first insulating layer 7, a columnar portion 33 that will become the through wiring portion 3, and a plurality of conductor portions 5.

[0051] In the eleventh step, unnecessary portions of the metal portion 14 are removed by CMP (Chemical Mechanical Polishing), and then patterned to form the first external electrode 11 made of a part of the metal portion 14 (see FIG. 9B).

[0052] In the twelfth step, the p-type silicon wafer 20 is subjected to CMP from the second main surface 202 side to form the through-holes 23 and remove parts of the columnar sections 33 (see FIG. 9C ). In the state of FIG. 9C , the parts 41 of the dielectric film 4 and the columnar sections 33 are located within the through-holes 23 of the p-type silicon wafer 20. In the state of FIG. 9C , the second main surface 202 of the p-type silicon wafer 20 corresponds to the second main surface 22 of the silicon substrate 2.

[0053] In the thirteenth step, a part of the columnar section 33 is etched from the second main surface 202 side of the p-type silicon wafer 20 (see FIG. 10A).

[0054] In the fourteenth step, an insulating layer 80 that will become the second insulating layer 8 is formed (see FIG. 10B ). In the fourteenth step, the insulating layer 80 is formed so as to cover the second main surface 202 of the p-type silicon wafer 20 and the columnar section 33.

[0055] In the fifteenth step, the insulating layer 80 is patterned using photolithography and etching techniques to form a second insulating layer 8 having a first opening 81 and a second opening 82 (see FIG. 10C).

[0056] In the sixteenth step, a metal film 15 is formed by sputtering, vapor deposition, or CVD to cover the second insulating layer 8, the exposed portion of the second main surface 202 of the p-type silicon wafer 20, and the columnar portion 33 (see FIG. 11A).

[0057] In the seventeenth step, the metal film 15 is patterned using photolithography and etching techniques to form the substrate electrode 6 and the second external electrode 12 (see FIG. 11B ). The seventeenth step may include a heat treatment to obtain ohmic contact between the substrate electrode 6 and the p-type silicon wafer 20.

[0058] In the method for manufacturing the interposer 1, a p-type silicon wafer 20 is prepared in the first step, and then steps 2 to 17 are performed to obtain a wafer including a plurality of interposers 1. In the method for manufacturing the interposer 1, after step 17, the wafer is cut using, for example, a dicing saw or a laser dicing device, thereby obtaining a plurality of interposers 1.

[0059] (3) Module with Interposer As shown in FIG. 4A, in a module 500 with an interposer 1, the interposer 1 is disposed between the semiconductor chip 300 and the mounting substrate 400.

[0060] The semiconductor chip 300 includes, for example, a processor, a logic IC (Integrated Circuit), a memory (for example, a High Bandwidth Memory (HBM)), etc. The semiconductor chip 300 may also be a graphic IC (Integrated Circuit).

[0061] The mounting substrate 400 has, for example, a first main surface 401 and a second main surface 402 opposite to the first main surface 401. The mounting substrate 400 is, for example, a multilayer substrate. The multilayer substrate is, for example, a multilayer printed wiring board, but is not limited to a multilayer printed wiring board and may be, for example, a multilayer ceramic substrate.

[0062] As shown in FIG. 4A , the module 500 further includes a PMIC (Power Management Integrated Circuit) 100 and an inductor L1. The PMIC 100 includes, for example, a DC-DC converter that converts a first DC voltage input from outside the module 500 into a second DC voltage and outputs the second DC voltage. The semiconductor chip 300 has a first external connection terminal and a second external connection terminal. In the module 500, the interposer 1 is disposed on a first main surface 401 of a mounting substrate 400. In the module 500, the PMIC 100 and the inductor L1 are disposed on a second main surface 402 of the mounting substrate 400. The mounting substrate 400 has a power supply terminal T1, a first ground terminal G1, a second ground terminal G2, and a plurality of wiring portions W1, W2, W3, W4, and W5. Each of the wiring portions W1, W4, and W5 is a through wiring portion extending along the thickness direction of the mounting substrate 400. The module 500 has an external DC power supply connected between a power terminal T1 and a first ground terminal G1. The power terminal T1 is connected to an input electrode 111 of the PMIC 100 via a wiring portion W1. The first ground terminal G1 is connected to a ground electrode 112 of the PMIC 100 via a wiring portion W2. A first electrode of an inductor L1 is connected to an output electrode 113 of the PMIC 100 via a wiring portion W3. A second electrode of the inductor L1 is connected to a first external connection terminal of the semiconductor chip 300 via a wiring portion W4 and a through wiring portion 3 of the interposer 1. A substrate electrode 6 of the interposer 1 is connected to a second ground terminal G2 via a wiring portion W5.

[0063] 4B is another cross-sectional view of the module 500 showing the connection of the semiconductor chip 300. The semiconductor chip 300 has a first external connection terminal 301 and a second external connection terminal 302. The interposer 1 further includes a substrate electrode 56 connected to the silicon substrate 2 through an opening 82 provided in the first insulating layer 7 and exposed from the opening 82. The substrate electrode 56 is connected to the external connection terminal 302 of the semiconductor chip 300. The external connection terminal 302 of the semiconductor chip 300 is connected to the second ground terminal G2 through the substrate electrode 56, the silicon substrate 2, the substrate electrode 6, and the wiring portion W5.

[0064] 5 is an equivalent circuit diagram of the module 500 shown in FIGS. 4A and 4B . In the module 500, the through wiring portion 3 of the interposer 1 constitutes part of the power rail from the output electrode 113 of the PMIC 100 to the semiconductor chip 300, which is the load, and also constitutes part of the capacitor C1. In the module 500, the capacitor C1 functions as a decoupling capacitor connected between the first external connection terminal 301 and the second external connection terminal 302 of the semiconductor chip 300. The second external connection terminal 302 of the semiconductor chip 300 is connected to ground via the silicon substrate 2 of the interposer 1. In the module 500, the interposer 1 incorporates the capacitor C1, which improves the design flexibility of the mounting substrate 400 compared to when a surface-mounted capacitor is disposed on the mounting substrate 400 instead of the capacitor C1.

[0065] (4) Advantages The interposer 1 according to the first embodiment includes a silicon substrate 2, a through wiring portion 3, a plurality of conductor portions 5, a dielectric film 4, and a substrate electrode 6. The silicon substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. The through wiring portion 3 penetrates the silicon substrate 2 in a thickness direction D1 of the silicon substrate 2. The plurality of conductor portions 5 protrude from the through wiring portion 3 in a direction intersecting the thickness direction D1 of the silicon substrate 2. The dielectric film 4 is interposed between the side surface 30 of the through wiring portion 3 and the plurality of conductor portions 5 and the silicon substrate 2. The substrate electrode 6 is connected to the silicon substrate 2.

[0066] The above configuration makes it possible to increase the capacitance of the capacitor C1 (see FIG. 3) while miniaturizing it. More specifically, the above configuration realizes the capacitor C1 including the through wiring portion 3, the plurality of conductor portions 5, the dielectric film 4, and the silicon substrate 2, making it possible to increase the capacitance of the capacitor C1 while miniaturizing it.

[0067] In the interposer 1 according to the first embodiment, the material of the dielectric film 4 is hafnium oxide, tantalum oxide, or zirconium oxide.

[0068] According to the above configuration, the dielectric constant of the dielectric film 4 can be made larger than when the material of the dielectric film 4 is silicon oxide or silicon nitride, and the capacitance of the capacitor C1 can be made larger.

[0069] An interposer 1A according to embodiment 2 will be described with reference to Figures 12A and 12B. Regarding the interposer 1A according to embodiment 2, components similar to those of the interposer 1 according to embodiment 1 (see Figures 1, 2A, 2B, and 3) are designated by the same reference numerals and descriptions thereof will be omitted.

[0070] (1) Configuration The interposer 1A according to the second embodiment differs from the interposer 1 according to the first embodiment in that it further includes a plurality of signal wiring portions 17 that penetrate the silicon substrate 2 in the thickness direction D1 of the silicon substrate 2. Although the interposer 1A includes a plurality of signal wiring portions 17, it is sufficient that the interposer 1A includes at least one signal wiring portion 17.

[0071] The interposer 1A further includes a plurality of insulating films 17A interposed between each of the plurality of signal wiring portions 17 and the silicon substrate 2. The material of the insulating films 17A is electrically insulating. The material of the insulating films 17A may be the same as or different from the material of the dielectric film 4. When the material of the insulating films 17A is different from the material of the dielectric film 4, it may be, for example, silicon oxide.

[0072] (2) Advantages The interposer 1A of embodiment 2, like the interposer 1 of embodiment 1, realizes a capacitor C1 including a through wiring portion 3, multiple conductor portions 5, a dielectric film 4, and a silicon substrate 2, making it possible to increase the capacitance of the capacitor C1 while achieving miniaturization.

[0073] The interposer 1A according to the second embodiment further includes a plurality of signal wiring portions 17. The signal wiring portions 17 penetrate the silicon substrate 2 in the thickness direction D1 of the silicon substrate 2.

[0074] According to the above configuration, the plurality of signal wiring portions 17 can be used as transmission paths for a plurality of different signals.

[0075] (Embodiment 3) An interposer 1B according to embodiment 3 will be described with reference to Fig. 13. Regarding the interposer 1B according to embodiment 3, components similar to those of the interposer 1A according to embodiment 1 (see Figs. 1, 2A, 2B, and 3) are designated by the same reference numerals and descriptions thereof will be omitted.

[0076] (1) Configuration In the interposer 1B according to the third embodiment, the shape of the plurality of conductor portions 5 differs from the shape of the plurality of conductor portions 5 of the interposer 1 according to the first embodiment.

[0077] In the interposer 1B, the conductor portions 5 closer to the first main surface 21 of the silicon substrate 2 have a longer protrusion length from the side surface 30 of the through wiring portion 3, and the conductor portions 5 farther from the first main surface 21 have a shorter protrusion length from the side surface 30 of the through wiring portion 3. Furthermore, the distance between each of the conductor portions 5 and the second main surface 22 of the silicon substrate 2 decreases as the conductor portions 5 move away from the side surface 30 of the through wiring portion 3.

[0078] (2) Advantages The interposer 1B of embodiment 3, like the interposer 1 of embodiment 1, realizes a capacitor C1 (see Figure 3) including a through wiring portion 3, multiple conductor portions 5, a dielectric film 4, and a silicon substrate 2, making it possible to increase the capacitance of the capacitor C1 while achieving miniaturization.

[0079] An interposer 1C according to a fourth embodiment will be described with reference to Fig. 14. With respect to the interposer 1C according to the fourth embodiment, components similar to those of the interposer 1 according to the first embodiment (see Figs. 1, 2A, 2B, and 3) are designated by the same reference numerals and descriptions thereof will be omitted.

[0080] (1) Configuration The interposer 1C according to the fourth embodiment includes a plurality of through wiring portions 3, including the through wiring portion 3 of the interposer 1 according to the first embodiment and one or more through wiring portions 3 other than the through wiring portion 3. In the interposer 1C, the first external electrode 11 is commonly connected to the plurality of through wiring portions 3 and is exposed through a plurality of openings 71 in the first insulating layer 7. The plurality of openings 71 correspond one-to-one to the plurality of through wiring portions 3. The second external electrode 12 is commonly connected to the plurality of through wiring portions 3 and is exposed through a plurality of openings (first openings 81) in the second insulating layer 8. The plurality of first openings 81 correspond one-to-one to the plurality of through wiring portions 3.

[0081] In the interposer 1C, a plurality of conductor portions 5 protrude from each of the plurality of through wiring portions 3 in a direction intersecting the thickness direction D1 of the silicon substrate 2. The plurality of conductor portions 5 overlap the first insulating layer 7 in the thickness direction D1 of the silicon substrate 2, but do not overlap the plurality of openings 71. Therefore, in the interposer 1C, a plurality of capacitors C1 are formed.

[0082] (2) Advantages The interposer 1C of embodiment 4, like the interposer 1 of embodiment 1, realizes a capacitor C1 (see Figure 3) including a through wiring portion 3, multiple conductor portions 5, a dielectric film 4, and a silicon substrate 2, making it possible to increase the capacitance of the capacitor C1 while reducing its size.

[0083] Furthermore, the interposer 1C according to the fourth embodiment includes a plurality of through wiring portions 3. In the interposer 1C, the first external electrode 11 is commonly connected to the plurality of through wiring portions 3 and is exposed through a plurality of openings 71 in the first insulating layer 7. The second external electrode 12 is commonly connected to the plurality of through wiring portions 3 and is exposed through a plurality of first openings 81 in the second insulating layer 8.

[0084] The above configuration makes it possible to increase the power transmitted between the first external electrode 11 and the second external electrode 12. Furthermore, the above configuration makes it possible to increase the combined capacitance of the multiple capacitors C1 between the first external electrode 11 and the substrate electrode 6, since the multiple capacitors C1 are connected in parallel.

[0085] (Modifications) The above-described first to fourth embodiments are merely examples of various embodiments of the present disclosure. The above-described first to fourth embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0086] For example, in the interposer 1C, instead of the first external electrode 11 commonly connected to the plurality of through wiring portions 3, a plurality of first external electrodes 11 corresponding one-to-one to the plurality of through wiring portions 3 may be provided. Also, instead of the second external electrode 12 commonly connected to the plurality of through wiring portions 3, a plurality of second external electrodes 12 corresponding one-to-one to the plurality of through wiring portions 3 may be provided.

[0087] Furthermore, in the interposer 1, the silicon substrate 2 is not limited to a p-type silicon substrate, but may be an n-type silicon substrate.

[0088] Furthermore, although the substrate electrode 6 is disposed on the second main surface 22 of the silicon substrate 2 , it may be disposed on the first main surface 21 instead of the second main surface 22 .

[0089] (Aspects) The following aspects are disclosed in this specification.

[0090] The interposer (1; 1A; 1B: 1C) according to the first aspect comprises a silicon substrate (2), a through wiring portion (3), a plurality of conductor portions (5), a dielectric film (4), and a substrate electrode (6). The silicon substrate (2) has a first main surface (21) and a second main surface (22) opposite the first main surface (21). The through wiring portion (3) penetrates the silicon substrate (2) in a thickness direction (D1) of the silicon substrate (2). The plurality of conductor portions (5) protrude from the through wiring portion (3) in a direction intersecting the thickness direction (D1) of the silicon substrate (2). The dielectric film (4) is interposed between a side surface (30) of the through wiring portion (3) and the silicon substrate (2), and between the plurality of conductor portions (5) and the silicon substrate (2). The substrate electrode (6) is connected to the silicon substrate (2).

[0091] According to this aspect, it is possible to increase the capacitance of the capacitor (C1) while reducing its size.

[0092] In the interposer (1; 1A; 1B; 1C) according to the second aspect, the material of the dielectric film (4) in the first aspect is hafnium oxide, tantalum oxide or zirconium oxide.

[0093] According to this embodiment, the dielectric constant of the dielectric film (4) can be increased compared to when the material of the dielectric film (4) is silicon oxide or silicon nitride, and the capacitance of the capacitor (C1) can be increased.

[0094] The interposer (1; 1A; 1B; 1C) according to the third aspect is any one of the first and second aspects, further comprising a first insulating layer (7), a second insulating layer (8), a first external electrode (11), and a second external electrode (12). The first insulating layer (7) is disposed on a first main surface (21) of the silicon substrate (2). The second insulating layer (8) is disposed on a second main surface (22) of the silicon substrate (2). The first external electrode (11) is connected to the through wiring portion (3) and is exposed through an opening (71) in the first insulating layer (7). The second external electrode (12) is connected to the through wiring portion (3) and is exposed through a first opening (81) in the second insulating layer (8). The substrate electrode (6) is disposed on the second main surface (22) of the silicon substrate (2) and is exposed through a second opening (82) in the second insulating layer (8).

[0095] In the interposer (1; 1A; 1B; 1C) according to the fourth aspect, the material of the substrate electrode (6) is the same as the material of the second external electrode (12) in the third aspect.

[0096] According to this aspect, during manufacturing, the substrate electrode (6) and the second external electrode (12) can be formed in the same process.

[0097] In the interposer (1; 1A; 1B; 1C) according to the fifth aspect, in the third or fourth aspect, the material of the first external electrode (11) is the same as the material of the through wiring portion (3).

[0098] According to this aspect, it is possible to reduce costs.

[0099] An interposer (1C) according to a sixth aspect is based on the first or second aspect. The interposer (1C) includes a plurality of through-hole wiring portions (3). The interposer (1C) further includes a first insulating layer (7), a second insulating layer (8), a first external electrode (11), and a second external electrode (12). The first insulating layer (7) is disposed on a first main surface (21) of the silicon substrate (2). The second insulating layer (8) is disposed on a second main surface (22) of the silicon substrate (2). The first external electrode (11) is commonly connected to a plurality of through-hole wiring portions (3) through a plurality of openings (71) in the first insulating layer (7). The second external electrode (12) is commonly connected to a plurality of through-hole wiring portions (3) through a plurality of openings (first openings 81) in the second insulating layer (8).

[0100] That is, the interposer (1C) according to the sixth aspect further includes one or more additional through wiring portions (3) penetrating the silicon substrate (2) in the thickness direction (D1) of the silicon substrate (2), a first insulating layer (7), a second insulating layer (8), a first external electrode (11), and a second external electrode (12). The first insulating layer (7) is disposed on a first main surface (21) of the silicon substrate (2). The second insulating layer (8) is disposed on a second main surface (22) of the silicon substrate (2). The first external electrode (11) is commonly connected to the through wiring portion (3) and the one or more additional through wiring portions (3) through a plurality of openings (71) in the first insulating layer (7). The second external electrode (12) is commonly connected to the through wiring portion (3) and the one or more additional through wiring portions (3) through a plurality of openings (first openings 81) in the second insulating layer (8).

[0101] According to this aspect, it is possible to increase the power transmitted between the first external electrode (11) and the second external electrode (12). Also, according to this aspect, since a plurality of capacitors are connected in parallel, it is possible to increase the combined capacitance of the plurality of capacitors between the first external electrode (11) and the substrate electrode (6).

[0102] The interposer (1A) according to a seventh aspect is any one of the first to sixth aspects, further comprising a signal wiring portion (17). The signal wiring portion (17) penetrates the silicon substrate (2) in the thickness direction (D1) of the silicon substrate (2).

[0103] According to this aspect, the signal wiring portion (17) can be used as a signal transmission path.

[0104] In the interposer (1A) of the eighth aspect, in the seventh aspect, the cross-sectional area of ​​the through wiring portion (3) is larger than the cross-sectional area of ​​the signal wiring portion (17) in a cross section perpendicular to the thickness direction (D1) of the silicon substrate (2).

[0105] According to this aspect, the through wiring portion (3) can transmit a larger amount of power than the signal wiring portion (17).

[0106] In the interposer (1; 1A; 1B; 1C) according to the ninth aspect, in the first to eighth aspects, the silicon substrate (2) is a p-type silicon substrate.

[0107] REFERENCE SIGNS LIST 1, 1A, 1B, 1C Interposer 2 Silicon substrate 21 First main surface 22 Second main surface 3 Through wiring portion 30 Side surface 4 Dielectric film 5 Conductor portion 6 Substrate electrode 7 First insulating layer 71 Opening 8 Second insulating layer 81 First opening (opening) 82 Second opening 11 First external electrode 12 Second external electrode 17 Signal wiring portion D1 Thickness direction

Claims

1. A silicon substrate having a first main surface and a second main surface opposite to the first main surface, a through-wiring portion penetrating the silicon substrate in the thickness direction of the silicon substrate, a plurality of conductor portions protruding from the through-wiring portion in a direction intersecting the thickness direction of the silicon substrate, a dielectric film interposed between a side surface of the through-wiring portion and the silicon substrate and between the plurality of conductor portions and the silicon substrate, and a substrate electrode connected to the silicon substrate. An interposer.

2. The material of the dielectric film is hafnium oxide, tantalum oxide or zirconium oxide. The interposer according to claim 1.

3. A first insulating layer disposed on the first main surface of the silicon substrate, a second insulating layer disposed on the second main surface of the silicon substrate, a first external electrode connected to the through-wiring portion and exposed through an opening of the first insulating layer, and a second external electrode connected to the through-wiring portion and exposed through a first opening of the second insulating layer. The substrate electrode is disposed on the second main surface of the silicon substrate and exposed through a second opening of the second insulating layer. The interposer according to claim 1.

4. The material of the substrate electrode is the same as the material of the second external electrode. The interposer according to claim 3.

5. The material of the first external electrode is the same as the material of the through-wiring portion. The interposer according to claim 4.

6. The interposer includes a plurality of through-wiring portions. The interposer further includes a first insulating layer disposed on the first main surface of the silicon substrate, a second insulating layer disposed on the second main surface of the silicon substrate, a first external electrode commonly connected to the plurality of through-wiring portions through a plurality of openings of the first insulating layer, and a second external electrode commonly connected to the plurality of through-wiring portions through a plurality of openings of the second insulating layer. The interposer according to claim 1.

7. The interposer further includes a signal wiring portion penetrating the silicon substrate in the thickness direction of the silicon substrate. The interposer according to claim 1.

8. The cross-sectional area of the through-wiring portion in a cross-section orthogonal to the thickness direction of the silicon substrate is larger than the cross-sectional area of the signal-wiring portion, the interposer according to claim 7.

9. The silicon substrate is a p-type silicon substrate, the interposer according to any one of claims 1 to 8.

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