Imaging element and its control method

Abstract

[Problem] To expand a dynamic range without increasing the number of bits of a counter. [Solution] This imaging element comprising: an accumulation unit that accumulates signal charges obtained by photoelectric conversion; a signal processing unit that outputs a single pulse when a determination voltage value reaches a threshold, and counts the number of output pulses, the determination voltage value being a voltage value corresponding to the amount of the signal charges accumulated in the accumulation unit; a reset unit that resets the potential of the accumulation unit each time the signal processing unit counts a single pulse; and an adjustment unit that decreases or increases the determination voltage value by a specific proportion in accordance with a count value of the number of pulses.

Description

Image pickup device and control method thereof

[0001] The present disclosure relates to an imaging device and a control method thereof.

[0002] There is an image sensor that generates a single pulse when a certain amount of signal charge generated by a photoelectric conversion element accumulates, and obtains the amount of incident light by counting the generated single pulse with a counter. This image sensor resets the accumulated signal charge each time it counts a generated single pulse.

[0003] The dynamic range of the image sensor is limited by the number of bits of the counter, so to expand the dynamic range, it is necessary to increase the number of bits of the counter.

[0004] Japanese Patent Application Laid-Open No. 2019-4225

[0005] According to a first aspect of the present disclosure, the imaging element includes a photoelectric conversion unit that converts light into signal charges, a storage unit that accumulates the signal charges, a signal processing unit that outputs a single pulse when a voltage value corresponding to the amount of signal charge accumulated in the storage unit reaches a threshold value, a reset unit that counts the number of pulses output from the signal processing unit and resets the potential of the storage unit each time one single pulse is counted, and an adjustment unit that decreases or increases a judgment voltage value by a specific percentage according to the count value of the number of pulses.

[0006] According to a second aspect of the present disclosure, there is provided a method for controlling an imaging element, the method including: accumulating signal charges generated by photoelectric conversion; outputting a single pulse when a judgment voltage value, which is a voltage value corresponding to the amount of charge of the accumulated signal charges, reaches a threshold value; counting the number of pulses of the single pulse; and decreasing or increasing the judgment voltage value by a specific percentage according to the count value of the number of pulses.

[0007] FIG. 1 is a diagram illustrating an example of the configuration of an imaging element according to an embodiment; FIG. 2 is a schematic diagram illustrating an overview of the basic operation of a pixel unit according to an embodiment; FIG. 3 is a diagram illustrating a conventional one-control method; FIG. 4 is a diagram illustrating a conventional two-control method; FIG. 5 is a diagram illustrating a pixel unit according to an embodiment; FIG. 6 is a diagram illustrating a pixel unit according to an embodiment; FIG. 7 is a diagram illustrating an example of the configuration of a pixel unit according to the first embodiment; FIG. 8 is a timing chart of the operation of a pixel unit according to the first embodiment; FIG. 9 is a diagram illustrating an example of the configuration of a pixel unit according to a second embodiment; FIG. 10 is a timing chart of the operation of a pixel unit according to the second embodiment; FIG. 11 is a diagram illustrating an example of the configuration of a pixel unit according to a third embodiment; FIG. 12 is a timing chart of the operation of a pixel unit according to the third embodiment;

[0008] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In the drawings, identical or similar parts may be designated by the same reference numerals, and redundant description may be omitted. The shapes and sizes of elements in the drawings may be exaggerated for clearer explanation. Furthermore, all drawings used to describe the embodiments schematically illustrate components, and may be partially emphasized, enlarged, reduced, or omitted to facilitate understanding, and may not accurately represent the scale, shape, etc. of the components.

[0009] FIG. 1 is a diagram showing an example of the configuration of an image sensor 1 according to an embodiment. The image sensor according to this embodiment is, for example, a CMOS image sensor. The following description will be given taking as an example a case where the image sensor 1 is a CMOS image sensor. The image sensor 1 shown in FIG. 1 is a pixel-parallel AD conversion (pixel-parallel ADC) type image sensor having an A / D converter for each pixel.

[0010] The imaging element 1 is provided in, for example, an imaging unit of a digital camera, a digital video camera, or a portable information terminal with an imaging function (e.g., a smartphone, a tablet, or a mobile phone with a camera). The imaging element 1 captures an image formed by an imaging optical system provided in the imaging unit. The imaging result of the imaging element 1 includes, for example, information on the gradation value for each color of each pixel (e.g., RGB data). The imaging element 1 outputs, for example, the imaging result in the data format of a full-color image.

[0011] The imaging device 1 includes a circuit section 2 and a pixel section 3 .

[0012] The circuit unit 2 supplies power to the pixel unit 3. The circuit unit 2 controls the operation of the pixel unit 3. The circuit unit 2 reads out electrical signals from the pixel unit 3. The circuit unit 2 includes, for example, a vertical scanning circuit, a horizontal scanning circuit, a multiplexer, and the like.

[0013] The pixel section 3 includes a plurality of pixel units 10 .

[0014] The plurality of pixel units 10 are arranged along a plane (XY plane). The plurality of pixel units 10 are arranged in a matrix along the X direction and the Y direction. The plurality of pixel units 10 are arranged in a plurality of columns with or without gaps in the X direction. In each column, the plurality of pixel units 10 are arranged in a plurality of rows with or without gaps in the Y direction.

[0015] An outline of the basic operation of the pixel unit 10 according to this embodiment will be described below. Fig. 2 is a schematic diagram illustrating an outline of the basic operation of the pixel unit 10 according to this embodiment.

[0016] The pixel unit 10 employs, for example, a pulse frequency modulation (PFM) ADC system. The pixel unit 10 generates signal charges by photoelectrically converting incident light. The pixel unit 10 accumulates the generated signal charges (S10). When the accumulated signal charges reach a certain amount, the pixel unit 10 generates a single pulse (S11). More specifically, the pixel unit 10 generates a single pulse when a voltage value corresponding to the amount of accumulated signal charges (hereinafter referred to as a "determination voltage value") reaches a threshold voltage Vth.

[0017] The pixel unit 10 counts the generated single pulses using a counter and resets the accumulated signal charge (S12). After step S12, the pixel unit 10 returns to step S10. The pixel unit 10 repeats steps S10, S11, and S12. The pixel unit 10 obtains the amount of signal charge generated by photoelectric conversion by countering the generated single pulses. The amount of signal charge is proportional to the amount of light incident on the pixel unit 10. Therefore, the pixel unit 10 can obtain the amount of incident light by countering the generated single pulses.

[0018] One of the features of the pixel unit will be described below: First, a conventional pixel unit will be described.

[0019] FIG. 3 is a diagram illustrating a conventional control method (hereinafter referred to as "Conventional Control Method 1"). Conventional Control Method 1 counts single pulses using a 3-bit counter. Assume that 10 single pulses (PL1 to PL10) occur per frame. In this case, Conventional Control Method 1 can only count 7 pulses even if 10 single pulses PL occur per frame. In other words, the 3-bit counter cannot count the 8th, 9th, and 10th single pulses due to overflow, limiting the dynamic range.

[0020] FIG. 4 is a diagram showing another conventional control method (hereinafter referred to as the "conventional second control method"). As shown in FIG. 4, one possible method for expanding the dynamic range is to increase the number of bits of the counter from 3 bits to 4 bits (conventional second control method). In the conventional second control method, since the counter is 4 bits, it is possible to count all 10 single pulses PL without overflowing. However, increasing the number of bits of the counter increases the circuit size.

[0021] The pixel unit 10 according to the embodiment can expand the dynamic range without increasing the number of bits of the counter. Figures 5 and 6 are diagrams illustrating the pixel unit 10 according to the embodiment. For convenience of explanation, the upper part of Figure 5 shows pulses obtained by the conventional second control method, and the lower part of Figure 5 shows pulses obtained by the pixel unit 10.

[0022] As shown in Figure 5, the pixel unit 10 has, for example, a bit CB for counting a single pulse PL (hereinafter referred to as a "count bit") and a bit FB indicating that the count value has reached a predetermined value (e.g., a count threshold value) (hereinafter referred to as a "determination bit").

[0023] For example, the number of bits of the count bit CB is 2, and the number of bits of the decision bit FB is 1. In this case, for example, the upper limit of the count value (hereinafter referred to as the "count threshold") is set to "4." When the count value reaches the count threshold, the decision bit FB is set to "1." When the decision bit FB is set to "1," the pixel unit 10 resets the count value of the counter to "0."

[0024] For example, when the count value reaches a count threshold, the pixel unit 10 increases or decreases the judgment voltage value by a specific percentage. For example, when the judgment bit FB is set to "1," the pixel unit 10 determines that the count value has reached the count threshold and decreases the judgment voltage value by a specific percentage. For example, when the count value reaches the count threshold, the pixel unit 10 changes the gain Gr (hereinafter referred to as "conversion gain") used when generating the judgment voltage value. The conversion gain Gr is, for example, the gain used when converting the amount of charge of the accumulated signal charge into a judgment voltage value.

[0025] 6, it is assumed that the conversion gain Gr is initially set to a first conversion gain Gr1. When the determination voltage value when the conversion gain Gr is the first conversion gain Gr1 reaches a threshold voltage Vth, the pixel unit 10 generates a single pulse PL and counts the single pulse PL. Here, the count threshold is set to "4."

[0026] As shown in Figure 6, the pixel unit 10 counts single pulses PL1, PL2, and PL3 in sequence using the count bit CB. When the pixel unit 10 acquires a single pulse PL4, it sets the decision bit FB to "1" and resets the count bit CB. A state "00" in which the one-bit decision bit FB is "1" and the two-bit count bits CB are reset indicates that the count value N = 4 (a state in which a single pulse PL4 has been counted). For example, when the decision bit FB changes from "0" to "1," the pixel unit 10 determines that the count value N has reached the count threshold value of "4."

[0027] When the count value N reaches a count threshold, the pixel unit 10 switches the conversion gain Gr from the first conversion gain Gr1 to the second conversion gain Gr2. The second conversion gain Gr2 illustrated in Fig. 6 is a value lower than the first conversion gain Gr1, for example, Gr1 × (1 / 2).

[0028] After switching from the first conversion gain Gr1 to the second conversion gain Gr2, i.e., when the judgment voltage value when the conversion gain Gr is the second conversion gain Gr2, reaches the threshold voltage Vth, the pixel unit 10 generates a single pulse PL' and counts the single pulse PL'.

[0029] The single pulse PL' will now be described. Assume that the amount of signal charge required to generate the single pulse PL is signal charge amount S1. If the second conversion gain Gr2 is assumed to be Gr1×(½), then a signal charge amount S2 (=S1×2) that is twice the signal charge amount S1 is required to generate the single pulse PL'. In other words, assume that the pixel unit 10 generates signal charge amount S1 each time it counts a single pulse PL, and generates signal charge amount S2 each time it counts a single pulse PL'.

[0030] Therefore, as shown in Figure 6, when the pixel unit 10 counts three single pulses PL', namely, a single pulse PL5', a single pulse PL6', and a single pulse PL7' after changing the conversion gain Gr to the second conversion gain Gr2, the signal charge amount in one frame is obtained as signal charge amount S1 x 4 counts + signal charge amount S2 x 3 counts.

[0031] The amount of signal charge in one frame obtained in the pixel unit 10 is the same as the amount of signal charge obtained by counting the single pulses PL1 to PL10. That is, a single pulse PL' when the conversion gain Gr is the second conversion gain Gr2 corresponds to two single pulses PL when the conversion gain Gr is the first conversion gain Gr1. Therefore, the count value N=5 when the decision bit FB is "1" corresponds to the conventional count value "6." The count value N=6 when the decision bit FB is "1" corresponds to the conventional count value "8." Furthermore, the count value N=7 when the decision bit FB is "1" corresponds to the conventional count value "10."

[0032] The pixel unit 10 can detect the amount of incident light equivalent to the above-mentioned 10 pulses using 3 bits. That is, the pixel unit 10 can expand the dynamic range compared to the conventional first control method. Furthermore, the pixel unit 10 can reduce the circuit scale compared to the conventional second control method.

[0033] In this way, the pixel unit 10 can increase or decrease the determination voltage value by a specific percentage in accordance with the counter value, thereby increasing the detectable amount of incident light without increasing the number of bits required to detect the amount of incident light. In other words, the pixel unit 10 can expand the dynamic range without increasing the number of bits.

[0034] Note that the above content is merely an example, and the pixel unit 10 may increase the judgment voltage value by a specific percentage rather than decreasing it when the count value reaches the count threshold. That is, the second conversion gain Gr2 may be higher than the first conversion gain Gr1. The pixel unit 10 may be configured to decrease or increase the judgment voltage value by a specific percentage when some trigger occurs. This trigger may be, for example, when the counter value reaches a predetermined value. The predetermined value may be the count threshold, or any value less than the count threshold. The number of bits of the count bits CB and the number of bits of the judgment bits FB can each be set arbitrarily.

[0035] First Embodiment A first embodiment of the pixel unit 10 will be described below with reference to Fig. 7. Fig. 7 is a diagram showing an example of the configuration of the pixel unit 10 according to the first embodiment.

[0036] 7, the pixel unit 10 includes a pixel 11, an AD conversion unit 12, and a control unit 13. The AD conversion unit 12 is an example of a signal processing unit.

[0037] The pixel 11 includes a photoelectric conversion unit 20 and a readout unit 21 .

[0038] The photoelectric conversion unit 20 converts incident light (hereinafter referred to as "incident light") into signal charges. The photoelectric conversion unit 20 has a function of accumulating the signal charges obtained by photoelectric conversion. The photoelectric conversion unit 20 is a photoelectric conversion element, such as a photodiode.

[0039] The readout unit 21 reads out a signal based on the signal charge generated in the photoelectric conversion unit 20. As shown in Fig. 7 , the readout unit 21 includes a transfer unit 30, a first floating diffusion 31, a capacitance switching unit 32, a second floating diffusion 33, a reset unit 34, and an output unit 35.

[0040] The transfer unit 30 is controlled by the control unit 13. The signal charges photoelectrically converted in the photoelectric conversion unit 20 are transferred to the storage unit via the transfer unit 30. The storage unit stores the signal charges photoelectrically converted in the photoelectric conversion unit 20. The storage unit shown in FIG. 7 may be the first floating diffusion 31, or may be both the first floating diffusion 31 and the second floating diffusion 33.

[0041] The transfer unit 30 is connected between the photoelectric conversion unit 20 (e.g., the cathode of a photodiode) and the output unit 35. The transfer unit 30 includes a transfer transistor 30tr. The gate of the transfer transistor 30tr is connected to the control unit 13. When the transfer transistor 30tr is turned on, the signal charge converted by the photoelectric conversion unit 20 is transferred to the storage unit.

[0042] The first floating diffusion 31 is provided between the transfer section 30 and the output section 35. When the transfer transistor 30tr is turned on, the first floating diffusion 31 accumulates the signal charge converted by the photoelectric conversion section 20.

[0043] The capacity switching unit 32 switches the capacity of the storage unit. The switching of the capacity of the storage unit by the capacity switching unit 32 is controlled by the control unit 13. The capacity switching unit 32 is connected between the first floating diffusion 31 and the second floating diffusion 33. Note that the control unit 13 and the capacity switching unit 32 in the first embodiment are examples of an adjustment unit.

[0044] The capacitance switching unit 32 includes, for example, a transistor (hereinafter referred to as the "capacity switching transistor") 32tr. When the control unit 13 turns on the capacitance switching transistor 32tr, the first floating diffusion 31 and the second floating diffusion 33 are electrically connected in parallel. As a result, the first floating diffusion 31 and the second floating diffusion 33 function as a storage unit and store the signal charge photoelectrically converted by the photoelectric conversion unit 20.

[0045] When the capacitance switching transistor 32tr is turned on, the capacitance of the storage section is the sum of the capacitance of the first floating diffusion 31 and the capacitance of the second floating diffusion 33. When the capacitance switching transistor 32tr is turned off, the capacitance of the storage section is the capacitance of the first floating diffusion 31.

[0046] The reset unit 34 is controlled by the control unit 13. The reset unit 34 resets the voltage of the storage unit to a reset potential Vrs based on the control of the control unit 13. The reset unit 34 includes, for example, a reset transistor 34tr. When turned on by the control unit 13, the reset transistor 34tr discharges the signal charge stored in the storage unit and resets the voltage of the storage unit to the reset potential Vrs.

[0047] The reset transistor 34tr is connected, for example, between the capacitance switching transistor 32tr and the reset potential Vrs. The second floating diffusion 33 is provided, for example, between the capacitance switching transistor 32tr and the reset transistor 34tr.

[0048] The output unit 35 outputs a voltage (hereinafter referred to as the "output voltage") Vs generated by the signal charge accumulated in the accumulation unit to the AD conversion unit 12. The output voltage Vs may be, for example, the voltage of the accumulation unit (hereinafter referred to as the "charge accumulation unit voltage") Vx, or a voltage obtained by amplifying the charge accumulation unit voltage Vx by an arbitrary amplification factor. In the example shown in FIG. 7, the output unit 35 includes a source follower circuit 35a and a selection circuit 35b. The charge accumulation unit voltage Vx is an example of a first voltage signal. The output voltage Vs is an example of a second voltage signal.

[0049] The source follower circuit 35a has a MOS transistor, and when a charge storage voltage Vx equal to or greater than the gate-source threshold is input, the MOS transistor is turned on. When the source follower circuit 35a is turned on, an output voltage Vs is generated from the source follower circuit 35a.

[0050] The source follower circuit 35a shown in FIG. 7 has a voltage gain set to "1" and functions as a voltage buffer. The selection circuit 35b has a MOS transistor (hereinafter referred to as a "selection transistor"). When the selection transistor is off and the source follower circuit 35a is on, the source follower circuit 35a outputs an output voltage Vs to the AD conversion unit 12. In the example shown in FIG. 7, the output unit 35 outputs the charge storage unit voltage Vx as the output voltage Vs to the AD conversion unit 12. When the selection transistor is turned on by a current signal from the circuit unit 2, the source follower circuit 35a does not output the output voltage Vs.

[0051] The AD conversion unit 12 includes a coupling capacitor 40 , a voltage clearing circuit 41 , a comparison unit 42 , and a counter 43 .

[0052] The coupling capacitor 40 is provided between the output terminal of the output unit 35 and the input terminal of the comparison unit 42. The voltage clearing circuit 41 clears the voltage value of the voltage (filtering voltage) Vf output from the coupling capacitor 40 to a predetermined potential (hereinafter referred to as the "clearing potential") Vclr. The voltage clearing circuit 41 includes, for example, a transistor (hereinafter referred to as the "voltage clearing transistor") 41tr.

[0053] The voltage clearing transistor 41tr is controlled by the control unit 13. When the voltage clearing transistor 41tr is turned on by the control unit 13, it clears the filtering voltage Vf to the clear potential Vclr. The filtering voltage Vf is input to the comparison unit 42. The filtering voltage Vf is an example of a second voltage signal.

[0054] The filtering voltage Vf is a voltage that changes depending on the amount of signal charge. The filtering voltage Vf illustrated in Fig. 7 is a voltage obtained by adding the voltage corresponding to the change (AC component) in the output voltage Vs extracted by the coupling capacitor 40 to the voltage at the downstream side of the coupling capacitor 40. Therefore, for example, if the output voltage Vs decreases, the filtering voltage Vf is a voltage obtained by subtracting the amount of the decrease in the output voltage Vs from the voltage at the downstream side of the coupling capacitor 40.

[0055] The comparator 42 compares a determination voltage value input to an input terminal of the comparator 42 with a threshold voltage Vth. In the first embodiment, the determination voltage value is a filtering voltage Vf. The filtering voltage Vf is an example of a voltage value according to the amount of signal charge.

[0056] The comparison unit 42 compares the inputted determination voltage value with the threshold voltage Vth, and outputs a single pulse when the determination voltage value reaches the threshold voltage Vth. The output single pulse is output to the counter 43 and the control unit 13. Reaching the determination voltage value to the threshold voltage Vth may mean that the determination voltage value increases to the threshold voltage Vth, or that the determination voltage value decreases to the threshold voltage Vth. In the example shown in FIG. 7 , the comparison unit 42 outputs a single pulse when the determination voltage value decreases to reach the threshold voltage Vth.

[0057] The comparison unit 42 is, for example, a CMOS inverter, but is not limited to this. The comparison unit 42 may also include a comparator having an amplifier. The comparison unit 42 may also be a multi-stage CMOS inverter. That is, the comparison unit 42 is not particularly limited as long as it compares the determination voltage value with the threshold voltage Vth and outputs a single pulse when the determination voltage value reaches the threshold voltage Vth.

[0058] The counter 43 counts the single pulses output from the comparator 42. The counter 43 has a count bit CB and a decision bit FB. For example, if the counter 43 has three bits, two of the bits are assigned as the count bits CB, and the remaining bit (for example, the most significant bit) is assigned as the decision bit FB.

[0059] When the count value of the single pulses PL reaches the count threshold, the counter 43 outputs a signal indicating this (hereinafter referred to as a "switching signal") to the control unit 13. When the count value of the single pulses PL reaches the count threshold, the counter 43 sets the determination bit FB to "1" and resets the count value to "0."

[0060] When a single pulse is input, the control unit 13 performs a reset operation for a fixed period of time. The reset operation is an operation of temporarily resetting the potential of the storage unit to a reset potential and temporarily setting the filtering voltage Vf to a clear potential Vclr. The reset operation is, for example, an operation of controlling the transfer transistor 30tr to be OFF, the reset transistor 34tr to be ON, the capacitance switching transistor 32tr to be ON, and the voltage clear transistor 41tr to be ON.

[0061] When the control unit 13 receives a switching signal from the counter 43, it switches the capacity of the storage unit by turning on the capacity switching transistor 32tr. For example, turning on the capacity switching transistor 32tr increases the capacity of the storage unit. As a result, the conversion gain Gr decreases as the capacity of the storage unit increases. For example, when the capacity switching transistor 32tr is turned on, if the capacity of the storage unit is doubled, the conversion gain Gr is halved. When the conversion gain Gr is halved, the judgment voltage value is also halved. In this way, the control unit 13 reduces the judgment voltage value by a specific percentage by switching the capacity of the storage unit. Note that when the control unit 13 receives a switching signal, it may increase the judgment voltage value by a specific percentage by switching to reduce the capacity of the storage unit.

[0062] The flow of operations of the pixel unit 10 according to the first embodiment will be described below with reference to Fig. 8. Fig. 8 is a timing chart of the operations of the pixel unit 10 according to the first embodiment.

[0063] The pixel unit 10 will be described taking as an example a case where the conversion gain Gr is the first conversion gain Gr1 as an initial condition. In the first embodiment, the case where the conversion gain Gr is the first conversion gain Gr1 means that the capacitance of the storage unit is set to the capacitance of the first floating diffusion 31.

[0064] After performing the reset operation, the pixel unit 10 executes a first pulse generation operation, which is an operation of controlling the transfer transistor 30tr to be on, the reset transistor 34tr to be off, the capacitance switching transistor 32tr to be off, and the voltage clearing transistor 41tr to be off.

[0065] In the first pulse generating operation, the signal charge photoelectrically converted by the photoelectric conversion unit 20 is accumulated only in the first floating diffusion 31. During the first pulse generating operation, the charge accumulation unit voltage Vx gradually decreases from the reset potential Vrs due to incident light. The decrease in the charge accumulation unit voltage Vx is reflected in the determination voltage value. That is, the determination voltage value gradually decreases from the clear potential Vclr due to incident light. In other words, the determination voltage value gradually decreases from the clear potential Vclr depending on the amount of signal charge in the accumulation unit. When the determination voltage value decreases to the threshold voltage Vth, the comparator 42 outputs a single pulse to the counter 43 and the control unit 13.

[0066] The counter 43 counts the single pulses output from the comparison unit 42. When the count value of the single pulses reaches the count threshold, the counter 43 outputs a switching signal to the control unit 13. On the other hand, when the count value of the single pulses does not reach the count threshold, the counter 43 does not output a switching signal.

[0067] When the control unit 13 detects a single pulse from the comparison unit 42, the control unit 13 performs a reset operation for a certain period of time. Then, when the reset operation is completed, the control unit 13 starts a first pulse generation operation. The control unit 13 executes the reset operation and the first pulse generation operation every time it receives a single pulse until it receives a switching signal.

[0068] When the control unit 13 detects a single pulse and receives a switching signal from the counter 43, it performs a reset operation and then executes a second pulse generating operation. The second pulse generating operation is an operation of controlling the transfer transistor 30tr to be on (ON), the reset transistor 34tr to be off (OFF), the capacitance switching transistor 32tr to be on (ON), and the voltage clear transistor 41tr to be off (OFF). The second pulse generating operation differs from the first pulse generating operation in that the capacitance switching transistor 32tr is on (ON).

[0069] When the capacitance switching transistor 32tr is turned on, the first floating diffusion 31 and the second floating diffusion 33 are electrically connected. The signal charge photoelectrically converted by the photoelectric conversion unit 20 is accumulated in the first floating diffusion 31 and the second floating diffusion 33.

[0070] When the capacitance switching transistor 32tr is turned on, the capacitance of the storage unit increases, and the conversion gain Gr is changed from the first conversion gain Gr1 to the second conversion gain Gr2. That is, in the first embodiment, when the conversion gain Gr is the second conversion gain Gr2, the capacitance of the storage unit is set to the capacitance of the first floating diffusion 31 and the capacitance of the second floating diffusion 33.

[0071] During the second pulse generating operation, the capacitance of the charge storage unit is greater than that during the first pulse generating operation. Therefore, the rate of change of the charge storage unit voltage Vx during the second pulse generating operation is slower than that during the first pulse generating operation. As a result, the rate of change of the determination voltage value is slower than that during the first pulse generating operation.

[0072] For example, if the capacitance of the first floating diffusion 31 is the same as the capacitance of the second floating diffusion 33, the rate of change of the determination voltage value during the second pulse generating operation is half the rate of change during the first pulse generating operation. In this case, the single pulse output from the comparing unit 42 during the second pulse generating operation is equivalent to twice the single pulse output from the comparing unit 42 during the first pulse generating operation.

[0073] 7 , when the count value reaches the count threshold, the control unit 13 switches the storage capacity of the storage unit from the first storage capacity to the second storage capacity by turning on the capacity switching transistor 32tr. The first storage capacity is, for example, the capacity of the first floating diffusion 31. The second storage capacity is, for example, the sum of the capacity of the first floating diffusion 31 and the capacity of the second floating diffusion 33. In other words, when the count value reaches the count threshold, the control unit 13 switches the conversion gain Gr from the first conversion gain Gr1 to the second conversion gain Gr2 by turning on the capacity switching transistor 32tr. This allows the control unit 13 to reduce the determination voltage value by a specific percentage when the count value reaches the count threshold.

[0074] 7 , when the control unit 13 receives a switching signal, it executes the second pulse generation operation instead of the first pulse generation operation. However, this is not limited to this. For example, the control unit 13 may execute the reset operation and the second pulse generation operation each time it receives a single pulse until it receives a switching signal, and then execute the reset operation and the first pulse generation operation each time it receives a single pulse after it receives a switching signal. In this case, the first storage capacitance is the sum of the capacitances of the first floating diffusion 31 and the second floating diffusion 33, and the second storage capacitance is the capacitance of the first floating diffusion 31.

[0075] Second Embodiment A second embodiment of the pixel unit 10 will be described with reference to FIG. 9 . FIG. 9 is a diagram illustrating the second embodiment of the pixel unit 10. The pixel unit 10 of the second embodiment will be referred to as a "pixel unit 10A" to distinguish it from the first embodiment. The pixel unit 10A includes a pixel 11A, an AD conversion unit 12A, and a control unit 13A. The AD conversion unit 12A is an example of a signal processing unit. The control unit 13A is an example of an adjustment unit.

[0076] The pixel 11A includes a photoelectric conversion unit 20 and a readout unit 21A.

[0077] The readout unit 21A reads out a signal based on the signal charge generated in the photoelectric conversion unit 20. As shown in Fig. 9 , the readout unit 21A includes a transfer unit 30, a floating diffusion 31A, a reset unit 34, and an output unit 35. The floating diffusion 31A is the first floating diffusion 31 of the first embodiment.

[0078] The transfer unit 30 is controlled by the control unit 13A. The signal charges photoelectrically converted by the photoelectric conversion unit 20 are transferred to the floating diffusion 31A via the transfer unit 30. The floating diffusion 31A according to the second embodiment is an example of an accumulation unit.

[0079] The reset unit 34 is controlled by the control unit 13. The reset unit 34 resets the potential of the floating diffusion 31A to a reset potential Vrs under the control of the control unit 13A. When the reset transistor 34tr is turned on by the control unit 13, it discharges the signal charge accumulated in the floating diffusion 31A and resets the voltage of the floating diffusion 31A to the reset potential Vrs.

[0080] The output section 35 outputs an output voltage Vs generated by the signal charge accumulated in the floating diffusion 31 A to the AD conversion section 12 A. The output voltage Vs according to the second embodiment may be, for example, the output voltage of the floating diffusion 31 A (charge accumulation section voltage Vx), or a voltage obtained by amplifying the charge accumulation section voltage Vx by an arbitrary amplification factor.

[0081] The AD conversion unit 12A includes a coupling capacitor 40 , a voltage clearing circuit 41 , a gain applying unit 60 , a comparing unit 42 , and a counter 43 .

[0082] The gain applying unit 60 multiplies the voltage value of the filtered voltage Vf output from the coupling capacitor 40 by a gain Gk that is equal to or greater than 1. The gain Gk can be changed by the control unit 13. The gain applying unit 60 includes, for example, a high gain path 60H and a low gain path 60L.

[0083] The high gain path 60H includes a circuit that multiplies the filtered voltage Vf output from the coupling capacitor 40 by a high gain GkH. For example, the high gain path 60H includes an operational amplifier 70 and a first switch SW1.

[0084] The high gain GkH is, for example, the amplification factor of the operational amplifier 70. The first switch SW1 is connected to the high gain path 60H. The operational amplifier 70 amplifies the input filtered voltage Vf with the high gain GkH.

[0085] The first switch SW1 is controlled by the control unit 13. When the first switch SW1 is on, a voltage signal of the filtered voltage Vf passes through the high gain path 60H. When the first switch SW1 is on, the filtered voltage Vf amplified by the operational amplifier 70 is output to the input terminal of the comparison unit 42 as a determination voltage value.

[0086] The low-gain path 60L includes a circuit that multiplies the filtered voltage Vf output from the coupling capacitor 40 by a low-gain GkL that is lower than the high-gain GkH. The low-gain GkL includes "1." Therefore, when the low-gain GkL is "1," the low-gain path 60L may include an operational amplifier with an amplification factor of 1, or may not include an electronic component that amplifies voltage, such as an operational amplifier, as illustrated in FIG. 9.

[0087] 9 , the low-gain path 60L includes a second switch SW2. The second switch SW2 is controlled by the control unit 13. When the second switch SW2 is on, a voltage signal of the filtered voltage Vf passes through the low-gain path 60L and is output to the input terminal of the comparison unit 42. That is, the filtered voltage Vf amplified by the low-gain path 60L with a low gain GkL is output to the input terminal of the comparison unit 42 as a determination voltage value.

[0088] Each of the first switch SW1 and the second switch SW2 may be one or more semiconductor switches or may be a mechanical relay. Either the first switch SW1 or the second switch SW2 is controlled to be on, and the other is controlled to be off.

[0089] When the control unit 13A receives the single pulse, it performs a reset operation for a certain period of time. The reset operation is, for example, an operation of controlling the transfer transistor 30tr to be OFF, the reset transistor 34tr to be ON, and the voltage clear transistor 41tr to be ON.

[0090] When the control unit 13 receives a switching signal from the counter 43, it changes the gain Gk by which the voltage value of the filtered voltage Vf is multiplied in the gain providing unit 60. For example, when the control unit 13 receives a switching signal from the counter 43, it changes the gain Gk from the high gain GkH to the low gain GkL by switching on and off the first switch SW1 and the second switch SW2.

[0091] In this way, the control unit 13 reduces the determination voltage value by a specific percentage by changing the gain Gk from the high gain GkH to the low gain GkL. Note that, when the control unit 13 receives a switching signal, it may increase the determination voltage value by a specific percentage by changing the gain GkL from the low gain GkL to the high gain GkH. That is, when the control unit 13 receives a switching signal, it changes the gain Gk from the first gain to the second gain. The first gain may be different from the second gain and may be higher or lower than the second gain.

[0092] The flow of operations of the pixel unit 10A according to the second embodiment will be described below with reference to Fig. 10. Fig. 10 is a timing chart of the operations of the pixel unit 10A.

[0093] The pixel unit 10A will be described by taking as an example a case where the gain Gk is a high gain GkH as an initial condition. When the gain Gk is the high gain GkH, the first switch SW1 is on and the second switch SW2 is off.

[0094] After the reset operation, the pixel unit 10A executes a first pulse generation operation. The first pulse generation operation according to the second embodiment is an operation of controlling the transfer transistor 30tr to be on (ON), the reset transistor 34tr to be off (OFF), the voltage clear transistor 41tr to be off (OFF), the first switch SW1 to be on (ON), and the second switch SW2 to be off (OFF).

[0095] Because the first switch SW1 is on and the second switch SW2 is off, the filtered voltage Vf is amplified by the high gain GkH through the high gain path 60H. The filtered voltage Vf amplified by the high gain GkH is output as a determination voltage value to the comparison unit 42. When the determination voltage value from the gain application unit 60 reaches the threshold voltage Vth, the comparison unit 42 outputs a single pulse to the counter 43 and the control unit 13A.

[0096] When the control unit 13A detects a single pulse from the comparison unit 42, it performs a reset operation for a fixed period of time. Then, when the reset operation is completed, the control unit 13 starts a first pulse generation operation. The control unit 13A executes the reset operation and the first pulse generation operation every time it receives a single pulse until it receives a switching signal.

[0097] When the control unit 13A detects a single pulse and receives a switching signal from the counter 43, it performs a reset operation and then executes a second pulse generating operation. In other words, when the control unit 13A detects a single pulse and receives a switching signal from the counter 43, it performs a reset operation and then switches the gain Gk from the high gain GkH to the low gain GkL. The second pulse generating operation according to the second embodiment is an operation of controlling the transfer transistor 30tr to be on (ON), the reset transistor 34tr to be off (OFF), the voltage clear transistor 41tr to be off (OFF), the first switch SW1 to be off (OFF), and the second switch SW2 to be on (ON).

[0098] In the second pulse generating operation, the filtered voltage Vf is amplified by a low gain GkL (including 1x) by the low gain path 60L. The filtered voltage Vf amplified by the low gain GkL is output to the comparing unit 42 as a determination voltage value. When the determination voltage value from the gain applying unit 60 reaches the threshold voltage Vth, the comparing unit 42 outputs a single pulse to the counter 43 and the control unit 13A. The counter 43 counts the single pulses output from the comparing unit 42.

[0099] The rate of change of the filtered voltage Vf (decision voltage value) amplified by the low gain GkL is slower than the rate of change of the filtered voltage Vf (decision voltage value) amplified by the high gain GkH. For example, if the high gain GkH is set to 2x and the low gain GkL is set to 1x, the rate of change of the decision voltage value when amplified by the low gain GkL is half the rate of change of the decision voltage value when amplified by the high gain GkH. Therefore, the single pulse output from the comparison unit 42 during the second pulse generation operation corresponds to twice the single pulse output from the comparison unit 42 during the first pulse generation operation.

[0100] 9, when the count value reaches the count threshold, the control unit 13A switches the gain Gk from the high gain GkH to the low gain GkL. Note that the gain Gk is an example of the conversion gain Gr.

[0101] 9, when the control unit 13A receives a switching signal, it executes the second pulse generating operation instead of the first pulse generating operation. However, this is not limited to this. For example, the control unit 13A may execute the reset operation and the second pulse generating operation each time it receives a single pulse until it receives a switching signal, and then execute the reset operation and the first pulse generating operation each time it receives a single pulse after it receives a switching signal. In this case, when it receives a switching signal, the control unit 13A switches the gain Gk from the low gain GkL to the high gain GkH.

[0102] Third Embodiment A third embodiment of the pixel unit 10 will be described with reference to Fig. 11. Fig. 11 is a diagram illustrating the third embodiment of the pixel unit 10. Note that the pixel unit 10 of the third embodiment may be referred to as a "pixel unit 10B" to distinguish it from the first and second configuration examples.

[0103] The pixel unit 10B includes a pixel 11B, an AD conversion unit 12B, and a control unit 13B. The pixel 11B has the same configuration as the pixel 11 of the first embodiment, so a detailed description thereof will be omitted. The AD conversion unit 12B has the same configuration as the AD conversion unit 12A, so a detailed description thereof will be omitted. The AD conversion unit 12A according to the third embodiment is an example of a signal processing unit. The capacitance switching unit 32 and the control unit 13B according to the third embodiment are examples of an adjustment unit.

[0104] When the control unit 13B detects a single pulse from the comparison unit 42, the control unit 13B performs a reset operation for a fixed period of time. Then, when the reset operation is completed, the control unit 13B starts a first pulse generation operation. The control unit 13B executes the reset operation and the first pulse generation operation every time it receives a single pulse until it receives a switching signal.

[0105] The first pulse generation operation in the third embodiment is an operation of controlling the transfer transistor 30tr to be on (ON), the reset transistor 34tr to be off (OFF), the capacitance switching transistor 32tr to be off (OFF), the voltage clear transistor 41tr to be off (OFF), the first switch SW1 to be on (ON), and the second switch SW2 to be off (OFF).

[0106] In the first pulse generation operation according to the third embodiment, only the first floating diffusion 31 is selected as the storage section, and the gain Gk of the gain applying section 60 is set to a high gain GkH, thereby setting the conversion gain Gr to the first conversion gain Gr1.

[0107] When the control unit 13B receives the switching signal, it executes a reset operation and a second pulse generation operation. The second pulse generation operation according to the third embodiment is an operation of controlling the transfer transistor 30tr to be on (ON), the reset transistor 34tr to be off (OFF), the capacitance switching transistor 32tr to be on (ON), the voltage clear transistor 41tr to be off (OFF), the first switch SW1 to be off, and the second switch SW2 to be on (ON).

[0108] In the second pulse generation operation according to the third embodiment, the first floating diffusion 31 and the second floating diffusion 33 are selected as the storage section, and the gain Gk of the gain applying section 60 is set to a low gain GkL, thereby setting the conversion gain Gr to the second conversion gain Gr2.

[0109] In this way, in the third embodiment, changing the conversion gain Gr means switching the capacity of the storage unit and changing the gain Gk. For example, when the control unit 13B receives a switching signal, the control unit 13B changes the capacity of the storage unit from the first storage capacity to the second storage capacity and changes the gain Gk from the low gain GkL to the high gain GkH, thereby changing the conversion gain Gr from the first conversion gain Gr1 to the second conversion gain Gr2. As a result, the control unit 13B can reduce the determination voltage value by a specific percentage.

[0110] When the control unit 13B receives a switching signal, the control unit 13B may change the capacity of the storage unit from the second storage capacity to the first storage capacity and change the gain Gk from a high gain GkH to a low gain GkL, thereby changing the conversion gain Gr from the second conversion gain Gr2 to the first conversion gain Gr1. In this case, the control unit 13B can increase the determination voltage value by a specific rate.

[0111] The flow of operations of the pixel unit 10B in the third embodiment will be described below with reference to Fig. 12. Fig. 12 is a timing chart of the operations of the pixel unit 10B.

[0112] After performing the reset operation, the pixel unit 10B executes a first pulse generation operation. In the first pulse generation operation, the signal charge photoelectrically converted by the photoelectric conversion unit 20 is accumulated only in the first floating diffusion 31 as an accumulation unit.

[0113] Furthermore, in the first pulse generating operation, the first switch SW1 is on and the second switch SW2 is off, so the filtered voltage Vf is amplified by the high gain GkH through the high gain path 60H. The filtered voltage Vf amplified by the high gain GkH is output to the comparator 42 as a determination voltage value.

[0114] When the determination voltage value from the gain applying unit 60 reaches the threshold voltage Vth, the comparing unit 42 outputs a single pulse to the counter 43 and the control unit 13B. The counter 43 counts the single pulses output from the comparing unit 42. Then, when the count value of the single pulses reaches the count threshold, the counter 43 outputs a switching signal to the control unit 13B. On the other hand, when the count value of the single pulses does not reach the count threshold, the counter 43 does not output a switching signal.

[0115] The control unit 13B performs a reset operation for a certain period of time when it detects a single pulse from the comparison unit 42. When the control unit 13B detects a single pulse and receives a switching signal from the counter 43, it performs a reset operation and then executes a second pulse generation operation.

[0116] In the second pulse generating operation, the signal charges photoelectrically converted by the photoelectric conversion unit 20 are stored in the first floating diffusion 31 and the second floating diffusion 33 as storage units.

[0117] In the second pulse generating operation, the first switch SW1 is off and the second switch SW2 is on, so the filtered voltage Vf is amplified by the low gain GkL through the low gain path 60L. The filtered voltage Vf amplified by the low gain GkL is output to the comparison unit 42 as a determination voltage value. The counter 43 counts the single pulses output from the comparison unit 42.

[0118] In the example described above, the rate of change of the criterion voltage value during the second pulse generating operation is gentler than the rate of change of the criterion voltage value during the first pulse generating operation. For example, if the conversion gain Gr during the second pulse generating operation is half the conversion gain Gr during the first pulse generating operation, the rate of change of the criterion voltage value during the second pulse generating operation is half the rate of change of the criterion voltage value during the first pulse generating operation. Therefore, the single pulse output from the comparing unit 42 during the second pulse generating operation is equivalent to twice the single pulse output from the comparing unit 42 during the first pulse generating operation.

[0119] In the above-described embodiment, the detection voltage value is increased or decreased at a specific rate according to the counter value, thereby increasing the detectable amount of incident light without increasing the number of bits required to detect the amount of incident light, thereby expanding the dynamic range without increasing the number of bits.

[0120] In the first embodiment, one or both of the output unit 35 and the coupling capacitor 40 are not essential components. For example, in the first embodiment, the output terminal of the storage unit and the input terminal of the comparison unit 42 may be directly connected. Furthermore, if the pixel unit 10 does not have the coupling capacitor 40, it does not need to have the voltage clear circuit 41.

[0121] In the second or third embodiment, one or both of the output unit 35 and the coupling capacitor 40 are not essential components. For example, in the second or third embodiment, the output terminal of the storage unit and the input terminal of the gain applying unit 60 may be directly connected. Furthermore, if the pixel unit 10A, 10B does not have the coupling capacitor 40, it does not need to include the voltage clearing circuit 41.

[0122] Although the first embodiment has been described with reference to an example in which the determination voltage value is the filtering voltage Vf, the present invention is not limited to this. However, the determination voltage value in the first embodiment may be the charge storage section voltage Vx or the output voltage Vs.

[0123] Although the case where the determination voltage value in the second or third embodiment is a voltage obtained by amplifying the filtering voltage Vf by the gain providing unit 60 has been exemplified, the present invention is not limited to this. However, the determination voltage value in the second or third embodiment is not limited to this, and may be a voltage obtained by amplifying the charge storage unit voltage Vx by the gain providing unit 60, or a voltage obtained by amplifying the output voltage Vs by the gain providing unit 60.

[0124] In the first, second, and third embodiments, the counter 43 counts up the count value, but this is not limiting. The counter 43 may count down the count value. The case where the count value reaches a predetermined value (e.g., a count threshold) may be a case where the count value counts up to the predetermined value, or a case where the count value counts down to the predetermined value.

[0125] The execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings, is not specifically stated as "before," "prior to," or the like. It should also be noted that the execution order of each process can be implemented in any order, as long as the output of a previous process is not used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," or the like for convenience, this does not mean that the process must be implemented in this order. Furthermore, to the extent permitted by law, the disclosures of Japanese Patent Application No. 2024-004575 and all documents cited in the above embodiments are incorporated herein by reference.

[0126] 1...imaging element, 11...pixel, 12...AD conversion unit, 13...control unit, 32...capacitance switching unit, 34...reset unit, 43...counter

Claims

1. An image sensor comprising: an accumulation unit that accumulates signal charges obtained by photoelectric conversion; a signal processing unit that outputs a single pulse when a determination voltage value, which is a voltage value corresponding to the amount of signal charges accumulated in the accumulation unit, reaches a threshold value, and counts the number of output pulses; a reset unit that resets the potential of the accumulation unit each time the signal processing unit counts one of the single pulses; and an adjustment unit that decreases or increases the determination voltage value by a specific ratio according to the count value of the number of pulses.

2. The image sensor according to claim 1, wherein the adjustment unit decreases or increases the determination voltage value by the specific ratio by changing a gain when generating the determination voltage value when the count value reaches a predetermined value.

3. The accumulation unit converts the amount of the accumulated signal charges into a first voltage signal, the signal processing unit acquires the voltage value of the first voltage signal or the voltage value of a second voltage signal generated according to the first voltage signal as the determination voltage value, and the adjustment unit switches the accumulation capacity of the accumulation unit from a first accumulation capacity to a second accumulation capacity different from the first accumulation capacity when the count value reaches a predetermined value. The image sensor according to claim 1.

4. The accumulation unit is a floating diffusion. The image sensor according to claim 3.

5. The second accumulation capacity is larger than the first accumulation capacity. The image sensor according to claim 4.

6. The accumulation unit converts the amount of the accumulated signal charges into a first voltage signal, and the signal processing unit includes: a gain application unit that multiplies the voltage value of the first voltage signal or the voltage value of a second voltage signal generated according to the first voltage signal by a gain of 1 or more; and a comparison unit that outputs the single pulse when the voltage value multiplied by the gain by the gain application unit reaches the threshold value as the determination voltage value. The adjustment unit changes the gain when the count value reaches a predetermined value. The image sensor according to claim 1.

7. The adjustment unit changes the gain multiplied by the voltage value by the gain application unit from a first gain to a second gain different from the first gain when the count value reaches the predetermined value. The image sensor according to claim 6.

8. The second gain is lower than the first gain. The image sensor according to claim 7.

9. The storage unit converts the amount of the stored signal charge into a first voltage signal. The signal processing unit includes a gain application unit that multiplies the voltage value of the first voltage signal or the voltage value of a second voltage signal generated according to the first voltage signal by a gain of 1 or more, and a comparison unit that obtains the voltage value multiplied by the gain by the gain application unit as the determination voltage value and outputs the single pulse when the obtained determination voltage value reaches the threshold value. The adjustment unit switches the storage capacity of the storage unit from a first storage capacity to a second storage capacity different from the first storage capacity and changes the gain multiplied by the voltage value by the gain application unit from a first gain to a second gain different from the first gain when the count value reaches a predetermined value. The image sensor according to claim 1.

10. The second storage capacity is larger than the first storage capacity, and the second gain is lower than the first gain. The image sensor according to claim 9.

11. A control method for an image sensor, including accumulating signal charges generated by photoelectric conversion, outputting a single pulse when a determination voltage value, which is a voltage value corresponding to the amount of the accumulated signal charges, reaches a threshold value, counting the number of pulses of the single pulse, and decreasing or increasing the determination voltage value by a specific ratio according to the count value of the number of pulses.

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