Semiconductor device

Abstract

This semiconductor device includes a chip that has a first main surface on which an element region is formed, a plurality of first conductive structures that extend in stripes in a first direction in the element region and are formed of a first conductive material, a base insulating film that is positioned between the first conductive structures and the chip, a first impurity region that has a first conductivity type and is formed on the chip, a second impurity region that has a second conductivity type and is formed on a surface layer part on the first main surface side of the first impurity region, and a high concentration region that is formed on the surface layer part of the first main surface and has a higher second conductivity type impurity concentration than the second impurity region. The base insulating film is selectively thickened in a portion that covers the high concentration region.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-006734 filed with the Japan Patent Office on January 19, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Japanese Patent Application Laid-Open No. 2006-124493 discloses a semiconductor device including a semiconductor substrate, a plurality of trench structures, and a gate pad portion. The plurality of trench structures are formed on the surface of the semiconductor substrate. The gate pad portion is disposed on the semiconductor substrate so as to cover the plurality of trench structures.

[0004] US Patent Application Publication No. 2017 / 0040423

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device that can improve reliability in terms of insulation.

[0006] According to an embodiment of the present disclosure, there is provided a semiconductor device including: a chip having a first main surface on which an element region is formed; a plurality of first conductive structures extending in a stripe pattern in a first direction in the element region and formed of a first conductive material; an underlying insulating film between the first conductive structures and the chip; a first impurity region of a first conductivity type formed in the chip; a second impurity region of a second conductivity type formed in a surface layer portion of the first impurity region on the first main surface side; and a high-concentration region formed in a surface layer portion of the first main surface and having a higher impurity concentration of the second conductivity type than the second impurity region, wherein the underlying insulating film is selectively thickened in a portion covering the high-concentration region.

[0007] FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing a layout of a gate pad, a gate wiring, a source pad, and a source wiring. FIG. 4 is a plan view showing a layout of a polysilicon wiring layer. FIG. 5 is a plan view showing a chip layout. FIG. 6 is an enlarged view of a portion surrounded by dashed-dotted line VI in FIG. 5 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 6 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 6 . FIG. 9 is an enlarged view of a portion surrounded by dashed-dotted line IX in FIG. 7 . FIG. 10 is an enlarged view of a portion surrounded by dashed-dotted line X in FIG. 8 . FIG. 11 is an enlarged view of a portion surrounded by dashed-dotted line XI in FIG. 5 . FIG. 12 is an enlarged view of a portion surrounded by dashed-dotted line XII in FIG. 11 . FIG. 13A is an enlarged view of a portion surrounded by dashed-dotted line XIIIA in FIG. 12 . FIG. 13B is a plan view illustrating a first dummy structure according to a second embodiment, and corresponds to FIG. 13A . FIG. 13C is a plan view illustrating a first dummy structure according to a third embodiment, and corresponds to FIG. 13B . FIG. 13D is a plan view illustrating a first dummy structure according to a fourth embodiment, and corresponds to FIG. 13B . FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 13A . FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 13A . FIG. 16A is a cross-sectional view taken along line XVIA-XVIA in FIG. 13A . FIG. 16B is a cross-sectional view taken along line XVIB-XVIB in FIG. 13A . FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 13A . FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 13A . FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 13A . Fig. 20 is an enlarged view of a portion surrounded by dashed-dotted line XX in Fig. 15. Fig. 21 is an enlarged view of a portion surrounded by dashed-dotted line XXI in Fig. 18. Fig. 22A is a diagram for explaining a part of the manufacturing process of the semiconductor device, and shows a cross section corresponding to the portion surrounded by dashed-dotted line XXII in Fig. 20. Fig. 22B is a diagram showing a step subsequent to Fig. 22A. Fig. 22C is a diagram showing a step subsequent to Fig. 22B. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII shown in Fig. 11. Fig. 24 is an enlarged view of a portion surrounded by dashed-dotted line XXIV in Fig. 23.25 is a cross-sectional view taken along line XXV-XXV in FIG. 12. FIG. 26 is an enlarged view of a portion surrounded by dashed-dotted line XXVI in FIG. 23. FIG. 27 is an enlarged view of a portion surrounded by dashed-dotted line XXVII in FIG. 4. FIG. 28 is an enlarged view of a portion surrounded by dashed-dotted line XXVIII in FIG. 27. FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 28. FIG. 30 is a cross-sectional view taken along line XXX-XXX in FIG. 28. FIG. 31 is an enlarged view of a portion surrounded by dashed-dotted line XXXI in FIG. 27. FIG. 32 is an enlarged view of a portion surrounded by dashed-dotted line XXXII in FIG. 5. FIG. 33 is an enlarged view of a portion surrounded by dashed-dotted line XXXIII-XXXIII in FIG. 32. FIG. 34 is an enlarged view of a portion surrounded by dashed-dotted line XXXIV in FIG. 4. FIG. 35 is an enlarged view of a portion surrounded by dashed-dotted line XXXV in FIG. 34. FIG. 36 is a cross-sectional view taken along line XXXVI-XXXVI shown in FIG. 35 . FIG. 37 is a cross-sectional view taken along line XXXVII-XXXVII shown in FIG. 35 . FIG. 38 is a cross-sectional view taken along line XXXVIII-XXXVIII shown in FIG. 35 . FIG. 39A is a plan view of a second embodiment of the connection structure portion, corresponding to FIG. 35 . FIG. 39B is a plan view of a third embodiment of the connection structure portion, corresponding to FIG. 35 . FIG. 40 is an enlarged view of a portion surrounded by dashed-dotted line XL in FIG. 4 . FIG. 41 is an enlarged view of a portion surrounded by dashed-dotted line XLI in FIG. 4 . FIG. 42 is an enlarged view of a portion surrounded by dashed-dotted line XLII in FIG. 4 . FIG. 43 is a plan view illustrating an example of an arrangement of a plurality of connection wiring structures according to the second embodiment, corresponding to FIG. 40 . FIG. 44 is a plan view illustrating an example of an arrangement of a plurality of connection wiring structures according to the second embodiment, corresponding to FIG. 42 . Fig. 45 is a plan view illustrating an example of an arrangement of a plurality of connection wiring structures according to a third embodiment, and is a view corresponding to Fig. 40. Fig. 46 is a plan view illustrating an example of an arrangement of a plurality of connection wiring structures according to the third embodiment, and is a view corresponding to Fig. 42. Fig. 47 is a view illustrating a first modified example of a semiconductor device. Fig. 48 is a view illustrating a second modified example of a semiconductor device. Fig. 49 is a view illustrating a third modified example of a semiconductor device. Fig. 50A is a plan view illustrating another embodiment of a semiconductor device, and is a view corresponding to Fig. 12.FIG. 50B is a plan view corresponding to FIG. 6 , showing another embodiment of a semiconductor device. FIG. 50C is a cross-sectional view taken along line LE-LE in FIG. 50B , showing another embodiment of a semiconductor device. FIG. 50D is a cross-sectional view taken along line LF-LF in FIG. 50B , showing another embodiment of a semiconductor device. FIG. 50E is an enlarged view of a portion surrounded by dashed-dotted line LE in FIG. 50C , showing another embodiment of a semiconductor device. FIG. 50F is an enlarged view of a portion surrounded by dashed-dotted line LF in FIG. 50D , showing another embodiment of a semiconductor device. FIG. 50G is a cross-sectional view taken along line LG-LG in FIG. 50B , showing another embodiment of a semiconductor device. FIG. 50H is an enlarged view of a portion surrounded by dashed-dotted line LH in FIG. 50G , showing another embodiment of a semiconductor device. FIG. 50I is a cross-sectional view corresponding to FIG. 50H , illustrating a portion of the manufacturing process for the semiconductor device. FIG. 50J is a view illustrating a process subsequent to FIG. 50I , and FIG. 50K is a view illustrating a process subsequent to FIG. 50J . FIG. 51 is a cross-sectional view corresponding to FIG. 2 , showing another embodiment of a semiconductor device. Fig. 52 shows another embodiment of the semiconductor device and is a cross-sectional view corresponding to Fig. 6. Fig. 53 shows another embodiment of the semiconductor device and is a cross-sectional view corresponding to Fig. 2. Fig. 54 shows another embodiment of the semiconductor device and is a plan view corresponding to the portion surrounded by the dashed dotted line LIV in Fig. 12. Fig. 55 shows another embodiment of the semiconductor device and is a cross-sectional view taken along line LV-LV shown in Fig. 54. Fig. 56 shows another embodiment of the semiconductor device and is a cross-sectional view taken along line LVI-LVI shown in Fig. 54.

[0008] DETAILED DESCRIPTION Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0009] The accompanying drawings are all schematic diagrams and are not strictly illustrated, and the scale, ratio, angle, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated explanations have been omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the omission or simplification applies.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) that is substantially equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" is a conductivity type resulting from a pentavalent element, and "p-type" is a conductivity type resulting from a trivalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] FIG. 1 is a plan view showing a semiconductor device 1 according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing the layout of a gate pad 15, a gate wiring 16, a source pad 20, and a source wiring 23. FIG. 4 is a plan view showing the layout of a polysilicon wiring layer 33. FIG. 5 is a plan view showing the layout of a chip 2. The semiconductor device 1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure.

[0013] 1 to 5, semiconductor device 1 includes chip 2 including SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which chip 2 is made of 4H-SiC single crystal, but chip 2 may be made of other polytypes.

[0014] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape when viewed in a plan view.

[0015] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 is preferably formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is preferably formed by the carbon surface ((000-1) surface) of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and not more than 10°. The off-angle is preferably not more than 5°.

[0016] In the circumferential direction of the chip 2 (counterclockwise in FIG. 1 ) starting from the first side surface 5A, the second side surface (end face, first end face) 5B is connected to the first side surface 5A, the third side surface (second end face) 5C is connected to the second side surface 5B, and the fourth side surface (end face, first end face) 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0017] In this embodiment, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. Of course, the first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal.

[0018] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, the first direction X and the second direction Y may be referred to as the "horizontal direction." The horizontal direction is also the direction extending along the first main surface 3.

[0019] The first to fourth side surfaces 5A to 5D may have lengths of 0.5 mm or more and 20 mm or less in plan view. The lengths of the first to fourth side surfaces 5A to 5D may have a value that belongs to any one of the ranges of 0.5 mm or more and 1 mm or less, 1.5 mm or more and 2 mm or less, 2 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The lengths of the first to fourth side surfaces 5A to 5D may be 5 mm or more.

[0020] Referring to FIG. 2, chip 2 includes an n-type base layer 6 made of SiC single crystal. Base layer 6 may also be referred to as a "drain region," a "base SiC layer," a "base region," or the like. Base layer 6 extends horizontally in a layered manner and forms part of second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, base layer 6 is made of a substrate made of SiC single crystal (i.e., a SiC substrate). Base layer 6 has the off direction and off angle described above.

[0021] The base layer 6 is 1×10１８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration of the base layer 6 may have the following peak value. The base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted with a single pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted with a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted with nitrogen.

[0022] The base layer 6 has a thickness T1. The thickness T1 may be 5 μm or more and 300 μm or less. The thickness T1 is preferably 50 μm or more and 250 μm or less.

[0023] 2, chip 2 includes a semiconductor layer 7 made of single crystal SiC stacked on base layer 6. Semiconductor layer 7, which is an example of a first impurity region, may also be referred to as a "drift region," an "SiC layer," a "semiconductor region," or the like. Semiconductor layer 7 extends horizontally in a layered manner and forms part of first main surface 3 and first to fourth side surfaces 5A to 5D. Semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from base layer 6.

[0024] The semiconductor layer 7 has a lower end and an upper end. The lower end of the semiconductor layer 7 is the starting point of crystal growth, and the upper end of the semiconductor layer 7 is the ending point of crystal growth. The lower end of the semiconductor layer 7 is also the bottom of the semiconductor layer 7. Since the semiconductor layer 7 is grown continuously from the base layer 6, the lower end of the semiconductor layer 7 coincides with the upper end of the base layer 6.

[0025] The boundary between the base layer 6 and the semiconductor layer 7 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The semiconductor layer 7 has an off direction and an off angle that are approximately the same as those of the base layer 6.

[0026] The semiconductor layer 7 includes an n-type drift region 8. In this embodiment, the drift region 8 is formed by a part (n-type portion) of the semiconductor layer 7.

[0027] The semiconductor layer 7 has a thickness T2 that is less than the thickness T1. The thickness T2 may be 1 μm or more and 10 μm or less. The thickness T2 is preferably 2 μm or more and 8 μm or less.

[0028] 5, the semiconductor device 1 includes an active region 9 set in the chip 2. The active region 9 includes a device structure (i.e., a transistor structure Tr) and is a region (element region) where an output current (drain current) is generated. The active region 9 is set in an inner portion of the chip 2 and spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a planar view. The active region 9 is formed in a polygonal shape having sides parallel to the periphery of the chip 2 in a planar view.

[0029] In this embodiment, the active region 9 is formed in a polygonal shape in plan view, having a recess that is recessed along a gate pad 15 (described later). The active region 9 and the source pad 20 may be formed in a quadrangular shape in plan view. The planar area of ​​the active region 9 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0030] 5, semiconductor device 1 includes a peripheral region 10 set outside active region 9 in chip 2. Peripheral region 10 is provided in a region between the periphery of chip 2 and active region 9 in plan view. Peripheral region 10 extends in a band shape along active region 9 in plan view and is set in a polygonal ring shape (a substantially square ring shape in this embodiment) surrounding active region 9.

[0031] 2, in peripheral region 10, first main surface 3 has a flat surface extending in first direction X and second direction Y. First main surface 3 of peripheral region 10 is formed substantially parallel to first main surface 3 of active region 9. First main surface 3 of peripheral region 10 is continuous with first to fourth side surfaces 5A to 5D.

[0032] 5 , the semiconductor device 1 includes a plurality of trench gate structures 11 of a trench electrode type as an example of a first conductive structure and a first trench structure. The trench gate structures 11 are formed on the first main surface 3 in the active region 9. The trench gate structures 11 may also be referred to as "gate structures," "trench structures," etc. A gate potential from a gate pad 15 (described later) is applied to the plurality of trench gate structures 11 as a control potential.

[0033] The trench gate structures 11 are spaced apart from each other and arranged inward from the periphery of the active region 9. In this embodiment, the trench gate structures 11 are arranged at intervals in the second direction Y (m-axis direction) and formed in a strip shape extending in the first direction X (a-axis direction). That is, in this embodiment, the trench gate structures 11 are arranged in a stripe shape extending in the a-axis direction (first direction X). The extension direction of the trench gate structures 11 coincides with the off-direction of the semiconductor layer 7. Referring to FIG. 2 , the trench gate structures 11 are formed at intervals from the lower end (base layer 6) of the semiconductor layer 7 toward the first main surface 3 and face the base layer 6 with a portion of the semiconductor layer 7 interposed therebetween.

[0034] 2 , the semiconductor device 1 includes an insulating layer 13 covering the first main surface 3. The insulating layer 13 collectively covers the active region 9 and the peripheral region 10. The insulating layer 13 covers the trench gate structure 11 in the active region 9. The insulating layer 13 may also be referred to as an "interlayer insulating film," an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. The insulating layer 13 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating layer 13 includes a silicon oxide film.

[0035] 2 and 3 , semiconductor device 1 includes gate pad 15, which is an example of a pad, and is disposed on insulating layer 13. Gate pad 15 is an electrode to which a gate potential is applied from the outside. Gate pad 15 may also be referred to as a "pad," a "gate pad electrode," a "first pad electrode," or the like.

[0036] In this embodiment, the gate pad 15 is disposed on the peripheral region 10. Specifically, the gate pad 15 is disposed in a region close to the center of one side of the first main surface 3 (the first side surface 5A in this embodiment) in a plan view.

[0037] Of course, the gate pad 15 may be disposed in a region along the center of any of the first to fourth side surfaces 5A to 5D. The gate pad 15 may be disposed at any corner of the first main surface 3 in a plan view. The gate pad 15 may be disposed in the center of the first main surface 3 in a plan view. The gate pad 15 may be disposed on the active region 9.

[0038] 3 , in this embodiment, the gate pad 15 is formed in a quadrangular shape in a plan view. The gate pad 15 includes a first periphery 15A on the first side surface 5A side, a second periphery 15B on the second side surface 5B side, a third periphery 15C on the third side surface 5C side, and a fourth periphery 15D on the fourth side surface 5D side. The first periphery 15A and the third periphery 15C extend in the first direction X and face each other in the second direction Y. The second periphery 15B and the fourth periphery 15D extend in the second direction Y and face each other in the first direction X.

[0039] The gate pad 15 may also be called a "gate metal." The gate pad 15 may also be called a "wiring," a "wiring electrode," a "gate finger," a "gate finger electrode," etc. The gate pad 15 is a metal pad, and in this embodiment, the gate pad 15 is formed from a metal material containing Al (aluminum).

[0040] Specifically, the gate pad 15 may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The gate pad 15 may also be a metal film other than an Al-based metal film. Specifically, the gate pad 15 may include at least one of a Ti film, a TiN film, a W film, a Cu film, a Cu alloy film, and a conductive polysilicon film.

[0041] 3 , the semiconductor device 1 includes at least one gate wiring 16 (a plurality of gate wirings in this embodiment) electrically connected to the gate pad 15. The gate wiring 16 is an example of a second conductive structure and a metal wiring. The gate wiring 16 is selectively routed in the peripheral region 10 so as to transmit a gate potential applied to the gate pad 15 to the plurality of trench gate structures 11. In this embodiment, the plurality of gate wirings 16 include a first gate wiring 17, a second gate wiring 18, a third gate wiring 19, and a connection wiring 16A.

[0042] Referring to Figure 3, in this embodiment, the first gate wiring 17 is arranged on the second side surface 5B side of the gate pad 15 and extends in a line along the periphery of the first main surface 3 so as to intersect (specifically, perpendicular to) part of the multiple trench gate structures 11 (Figure 5) (specifically, terminal portions 11A (Figure 31, etc.)).

[0043] Specifically, the first gate wiring 17 includes a first portion 17A, a second portion 17B, and a connection portion 17C. The first portion 17A extends from the gate pad 15 along the first side surface 5A toward the second side surface 5B.

[0044] 3, first portion 17A is electrically connected to gate pad 15 in peripheral region 10 via connection wiring 16A and a resistive wiring structure 38 (FIG. 4), which will be described later. First portion 17A of first gate wiring 17 may be configured to be drawn out from gate pad 15 toward second side surface 5B, instead of being electrically connected to gate pad 15 via resistive wiring structure 38 (FIG. 4).

[0045] 3, the second portion 17B extends from an end 17E at a first outer edge position (first position) P1 of the first portion 17A along the second side surface 5B toward the third side surface 5C. The second portion 17B of the first gate wiring 17 is electrically connected to the plurality of trench gate structures 11 via a second structure 34B (FIG. 4) of a peripheral wiring structure 34 (FIG. 4) described later.

[0046] The second portion 17B has an end portion 17D at the corner C of the chip 2 on the third side surface 5C side. Therefore, in this embodiment, the first gate wiring 17 does not have a portion that extends along the third side surface 5C. In other words, in this embodiment, the first gate wiring 17 is not arranged in the region between the active region 9 and the third side surface 5C.

[0047] 3 , connection portion 17C extends from the base end of first portion 17A along the periphery of gate pad 15 and connects first portion 17A to third gate wiring 19. Connection portion 17C includes strip portion 17F and second strip portion 17G. Strip portion 17F extends from the base end of first portion 17A toward third side surface 5C along second periphery 15B of gate pad 15. Second strip portion 17G extends from the terminal end of strip portion 17F toward fourth side surface 5D along third periphery 15C of gate pad 15 and connects strip portion 17F to third gate wiring 19.

[0048] In this embodiment, the first portion 17A, the second portion 17B, and the connecting portion 17C have the same width. Of course, the first portion 17A may have a width different from at least one of the second portion 17B and the connecting portion 17C. The second portion 17B may have a width different from the connecting portion 17C.

[0049] In this embodiment, the second portion 17B is longer than the first portion 17A. The second portion 17B may be shorter than the first portion 17A or may have the same length as the first portion 17A.

[0050] In this embodiment, the connecting portion 17C is shorter than the first portion 17A. The connecting portion 17C may be shorter than the first portion 17A, or may have the same length as the first portion 17A.

[0051] Referring to Figure 3, in this embodiment, the second gate wiring 18 is arranged on the fourth side surface 5D side with respect to the gate pad 15, and extends in a line along the periphery of the first main surface 3 so as to intersect (specifically, perpendicular to) part of the multiple trench gate structures 11 (Figure 5) (specifically, terminal portions 11A).

[0052] Specifically, the second gate wiring 18 includes a first portion 18A, a second portion 18B, and a connection portion 18C. The first portion 18A extends from the gate pad 15 along the first side surface 5A toward the fourth side surface 5D.

[0053] 3, first portion 18A is electrically connected to gate pad 15 in peripheral region 10 via connection wiring 16A and a resistive wiring structure 38 (FIG. 4), which will be described later. First portion 18A of second gate wiring 18 may be extended from gate pad 15 toward fourth side surface 5D, instead of being electrically connected to gate pad 15 via resistive wiring structure 38 (FIG. 4).

[0054] 3, the second portion 18B extends from a terminal end 18E at a second outer edge position (first position) P2 of the first portion 18A along the fourth side surface 5D toward the third side surface 5C. The second portion 18B of the second gate wiring 18 is electrically connected to the plurality of trench gate structures 11 via a fourth structure 34D (FIG. 4) of a peripheral wiring structure 34 (FIG. 4) described later.

[0055] The second portion 18B has an end portion 18D at the corner C of the chip 2 on the third side surface 5C side. Therefore, in this embodiment, the second gate wiring 18 does not have a portion that extends along the third side surface 5C. In other words, in this embodiment, the second gate wiring 18 is not arranged in the region between the active region 9 and the third side surface 5C.

[0056] 3 , connection portion 18C extends from the base end of first portion 18A along the periphery of gate pad 15 and connects first portion 18A to third gate wiring 19. Connection portion 18C includes strip portion 18F and strip portion 18G. Strip portion 18F extends from the base end of first portion 18A toward third side surface 5C and along fourth periphery 15D of gate pad 15. Strip portion 18G extends from the terminal end of strip portion 18F toward fourth side surface 5D and along third periphery 15C of gate pad 15 and connects strip portion 18F to third gate wiring 19.

[0057] In this embodiment, the first portion 18A, the second portion 18B, and the connecting portion 18C have the same width. Of course, the first portion 18A may have a width different from at least one of the second portion 18B and the connecting portion 18C. The second portion 18B may have a width different from the connecting portion 18C.

[0058] In this embodiment, the second portion 18B is longer than the first portion 18A. The second portion 18B may be shorter than the first portion 18A or may have the same length as the first portion 18A.

[0059] In this embodiment, the connecting portion 18C is shorter than the first portion 18A. The connecting portion 18C may be shorter than the first portion 18A, or may have the same length as the first portion 18A.

[0060] 3, the connection wiring 16A connects a first portion 17A of the first gate wiring 17 and a first portion 18A of the second gate wiring 18. The connection wiring 16A is disposed in the region between the gate pad 15 and the first side surface 5A, and has a strip shape extending along the first side surface 5A.

[0061] In this configuration, the inner periphery of the connection wiring 16A coincides with an extension of the inner periphery of the first portion 17A of the first gate wiring 17. The inner periphery of the connection wiring 16A coincides with an extension of the inner periphery of the first portion 18A of the second gate wiring 18. The outer periphery of the connection wiring 16A coincides with an extension of the outer periphery of the first portion 17A of the first gate wiring 17. The outer periphery of the connection wiring 16A coincides with an extension of the outer periphery of the first portion 18A of the second gate wiring 18.

[0062] The wiring width of the connection wiring 16A is the same as the wiring width of the first portion 17A. Of course, the wiring width of the connection wiring 16A may be wider or narrower than the wiring width of the first portion 17A. The wiring width of the connection wiring 16A is the same as the wiring width of the first portion 18A. Of course, the wiring width of the connection wiring 16A may be wider or narrower than the wiring width of the first portion 18A.

[0063] 3 , in this embodiment, the third gate wiring (third portion) 19 is disposed on the third side surface 5C side of the gate pad 15, and extends in a line in the region between the gate pad 15 and the third side surface 5C toward the fourth side surface 5C along the second direction Y. The third gate wiring 19 is connected to the first gate wiring 17 and the second gate wiring 18 in the outer periphery region 10.

[0064] The third gate wiring 19 is electrically connected to the plurality of trench gate structures 11 in the active region 9. The third gate wiring 19 may be configured to be drawn from the gate pad 15 toward the third side surface 5C, instead of being connected to either the first gate wiring 17 or the second gate wiring 18. The plurality of gate wirings 16 (the first gate wiring 17, the second gate wiring 18, and the third gate wiring 19) may be referred to as "wiring," "wiring electrodes," "gate fingers," "gate finger electrodes," or the like. The gate wiring 16 is made of metal wiring, and in this embodiment, the gate wiring 16 is formed of a metal material (second conductive material) containing Al (aluminum). Specifically, the gate wiring 16 may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0065] The gate wiring 16 may be a metal film other than an Al-based metal film, specifically, the gate wiring 16 may include at least one of a Ti film, a TiN film, a W film, a Cu film, a Cu alloy film, and a conductive polysilicon film.

[0066] 3 , semiconductor device 1 includes a source pad 20 disposed on first main surface 3 at a distance from gate pad 15 and gate wiring 16. Source pad 20 is an electrode to which a source potential is applied from the outside. Source pad 20 may also be referred to as a "first main surface electrode," a "pad," a "source pad electrode," a "source metal," a "second pad electrode," or the like.

[0067] The source pad 20 is a metal pad, and in this embodiment, the source pad 20 is formed from a metal material containing Al (aluminum). That is, the source pad 20 includes an Al-based metal film. Specifically, the source pad 20 may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The source pad 20 may also be a metal film other than an Al-based metal film. Specifically, the source pad 20 may include at least one of a Ti film, a TiN film, a W film, a Cu film, a Cu alloy film, and a conductive polysilicon film.

[0068] In this embodiment, the source pad 20 is disposed on the active region 9 in a plan view. Specifically, the source pad 20 is formed in a polygonal shape having a recess that is recessed along the gate pad 15 in a plan view. Of course, the source pad 20 may also be formed in a quadrangular shape in a plan view.

[0069] In this embodiment, the source pad 20 includes a first source pad 21 arranged in a region closer to the second side surface 5B than the central position in the first direction X of the active region 9 (first main surface 3), and a second source pad 22 arranged in a region closer to the fourth side surface 5D than the central position.

[0070] 3, the first source pad 21 is disposed on a portion of the insulating layer 13 covering the active region 9, in a region between the gate pad 15 and the third gate wiring 19 and the first gate wiring 17. The first source pad 21 faces the plurality of trench gate structures 11 with the insulating layer 13 interposed therebetween. The first source pad 21 preferably has a planar area larger than that of the gate pad 15. A source potential is applied to the first source pad 21 from the outside.

[0071] 3, the second source pad 22 is disposed on a portion of the insulating layer 13 covering the active region 9, in a region between the gate pad 15 and the third gate wiring 19 and the second gate wiring 18. The second source pad 22 faces the plurality of trench gate structures 11 with the insulating layer 13 interposed therebetween. The second source pad 22 preferably has a planar area larger than that of the gate pad 15. A source potential is applied to the second source pad 22 from the outside.

[0072] The first source pad 21 and the second source pad 22 are connected to each other at the end on the third side surface 5 C. In this embodiment, the source pad 20 is partitioned into the first source pad 21 and the second source pad 22 by the third gate wiring 19.

[0073] 3 , the semiconductor device 1 includes at least one source wiring 23 (one in this embodiment) drawn out from the source pad 20. The source wiring 23 may also be referred to as a "wiring," a "wiring electrode," or the like. The source wiring 23 transmits a source potential applied to the source pad 20 to other regions. The source wiring 23 is routed from a portion of the source pad 20 (the first source pad 21 and the second source pad 22) on the third side surface 5C side onto a portion of the insulating layer 13 covering the outer periphery region 10.

[0074] The source wiring 23 may be referred to as a "wiring," a "wiring electrode," a "source finger," a "source finger electrode," or the like. The source wiring 23 is made of metal wiring, and in this embodiment, the source wiring 23 is formed from a metal material containing Al (aluminum). That is, the source wiring 23 includes an Al-based metal film. Specifically, the source wiring 23 may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The source wiring 23 may also be a metal film other than an Al-based metal film. Specifically, the source wiring 23 may include at least one of a Ti film, a TiN film, a W film, a Cu film, a Cu alloy film, and a conductive polysilicon film.

[0075] 2 , the semiconductor device 1 includes a drain pad 24 covering the second main surface 4. The drain pad 24 is an electrode to which a drain potential is applied from the outside. The drain pad 24 may also be referred to as a "drain pad electrode," a "third pad electrode," or the like. The drain pad 24 forms an ohmic contact with the base layer 6 exposed from the second main surface 4.

[0076] The drain pad 24 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 24 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0077] The breakdown voltage that can be applied between source pad 20 and drain pad 24 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0078] 1 and 2 , semiconductor device 1 includes an upper insulating film 25 that selectively covers gate pad 15, gate wiring 16, source pad 20, source wiring 23, and insulating layer 13 on first main surface 3. Upper insulating film 25 includes a gate pad opening 26 that exposes an inner portion of gate pad 15. Upper insulating film 25 covers the peripheral portion of gate pad 15 and the entire area of ​​gate wiring 16. Gate pad opening 26 is formed in a quadrangular shape in a plan view.

[0079] 1 , the upper insulating film 25 includes a first source pad opening 27 that exposes the inner portion of the first source pad 21 and a second source pad opening 28 that exposes the inner portion of the second source pad 22. The upper insulating film 25 covers the peripheral portion of the first source pad 21, the peripheral portion of the second source pad 22, and the entire area of ​​the source wiring 23.

[0080] The first source pad opening 27 is formed in a polygonal shape that follows the peripheral edge of the first source pad 21 in a plan view. The plane area of ​​the first source pad opening 27 is preferably larger than the plane area of ​​the gate pad opening 26. The second source pad opening 28 is formed in a polygonal shape that follows the peripheral edge of the second source pad 22 in a plan view. The plane area of ​​the second source pad opening 28 is preferably larger than the plane area of ​​the gate pad opening 26.

[0081] The upper insulating film 25 has an outer periphery at a position spaced apart from the first to fourth side surfaces 5A to 5D. The insulating layer 13 is exposed between the outer periphery of the upper insulating film 25 and the first to fourth side surfaces 5A to 5D. The exposed portion of the insulating layer 13 is annular (specifically, quadrangular).

[0082] 2 , the upper insulating film 25 preferably has a thickness greater than the thicknesses of the gate pad 15, the gate wiring 16, the source pad 20, and the source wiring 23. The thickness of the upper insulating film 25 is preferably less than the thickness of the chip 2. The thickness of the upper insulating film 25 may be 3 μm or more and 35 μm or less. The thickness of the upper insulating film 25 is preferably 25 μm or less.

[0083] The upper insulating film 25 may have a layered structure including an inorganic insulating film and an organic insulating film stacked in this order from the chip 2 side. The upper insulating film 25 may include at least one of an inorganic insulating film and an organic insulating film, and does not necessarily have to include both an inorganic insulating film and an organic insulating film at the same time. The inorganic insulating film may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film preferably includes an insulating material different from that of the insulating layer 13. The organic insulating film is preferably made of a polyimide film, a polyamide film, or a polybenzoxazole film. In this embodiment, the organic insulating film includes a polybenzoxazole film.

[0084] 4, the semiconductor device 1 includes a peripheral wiring structure 34. For clarity, the region in which the peripheral wiring structure 34 is formed is indicated by hatching in FIG. 4. The peripheral wiring structure 34 forms a ring (specifically, a substantially rectangular ring) along the periphery of the chip 2. In this embodiment, the peripheral wiring structure 34 is disposed in the outer periphery region 10. The peripheral wiring structure 34 surrounds the active region 9 in a plan view. The peripheral wiring structure 34 includes a first structure 34A, a second structure 34B, a third structure 34C, a fourth structure 34D, a fifth structure 34E, and a sixth structure 34F.

[0085] 4 , the first structure 34A and the third structure 34C face each other in the second direction Y with the active region 9 therebetween. The second structure 34B and the fourth structure 34D face each other in the first direction X with the active region 9 therebetween. The fifth structure 34E and the sixth structure 34F are arranged in a region of the peripheral region 10 around the gate pad 15 in a plan view.

[0086] The peripheral wiring structure 34 is formed of polysilicon as a first conductive material. That is, in this embodiment, the peripheral wiring structure 34 is formed of the same material as the trench gate structure 11. This polysilicon may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. This polysilicon is a material with higher resistance than the metal materials used for the gate pad 15, gate wiring 16, source pad 20, source wiring 23, etc.

[0087] 4 , the semiconductor device 1 includes a plurality of connection wiring structures 35. The plurality of connection wiring structures 35 extend in a stripe pattern in the second direction Y in the active region 9. The plurality of connection wiring structures 35 are arranged at intervals in the first direction X in a region between the second portion 17B of the first gate wiring 17 ( FIG. 3 ) and the second portion 18B of the second gate wiring 18 ( FIG. 3 ). The plurality of connection wiring structures 35 electrically connect the trench gate structure 11 ( FIG. 5 ) to the first portion 17A of the first gate wiring 17 ( FIG. 3 ) and the first portion 18A of the second gate wiring 18 ( FIG. 3 ).

[0088] The number of connection wiring structures 35 included in the semiconductor device 1 may be 5 or more and 50 or less. The number of connection wiring structures 35 included in the semiconductor device 1 is preferably 15 or more and 30 or less. The number of connection wiring structures 35 included in the semiconductor device 1 is more preferably 18 or more and 25 or less.

[0089] 4, the multiple connection wiring structures 35 are connected across portions of the annular peripheral wiring structure 34 that face each other in the second direction Y. Specifically, the connection wiring structures 35 connect the first structure 34A and the third structure 34C. Both end portions of the connection wiring structures 35 in the second direction Y are connected to the first structure 34A and the third structure 34C, respectively.

[0090] Furthermore, the connection wiring structure 35 connects the sixth structure 34F and the third structure 34C. Both end portions of the connection wiring structure 35 in the second direction Y are connected to the sixth structure 34F and the third structure 34C, respectively. The connection wiring structure 35 connects the third structure 34C to the first structure 34A and the sixth structure 34F. As a result, the connection wiring structure 35 electrically connects the third structure 34C not only to the first structure 34A and the sixth structure 34F, but also to the other structures of the peripheral wiring structure 34 (the second structure 34B, the fourth structure 34D, and the fifth structure 34E).

[0091] The connection wiring structure 35 is formed of polysilicon as the first conductive material and the third conductive material. This polysilicon may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. In this embodiment, the connection wiring structure 35 is formed of the same material as the trench gate structure 11. The connection wiring structure 35 is formed of the same material as the peripheral wiring structure 34.

[0092] 4, the semiconductor device 1 includes a resistive wiring structure 38 disposed midway through the first structure 34A of the peripheral wiring structure 34. In plan view, the resistive wiring structure 38 has a strip shape that extends along the first periphery 15A (FIG. 3) of the gate pad 15. In this embodiment, the resistive wiring structure 38 is disposed in the peripheral region 10. The resistive wiring structure 38 is formed of polysilicon as a first conductive material.

[0093] This polysilicon may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. In this embodiment, the resistive wiring structure 38 is formed of the same material as the trench gate structure 11. The resistive wiring structure 38 is formed of the same material as the peripheral wiring structure 34. The resistive wiring structure 38 is formed of the same material as the connecting wiring structure 35.

[0094] In this embodiment, the peripheral wiring structure 34, the connection wiring structure 35, and the resistance wiring structure 38 are integrally formed. The peripheral wiring structure 34, the connection wiring structure 35, and the resistance wiring structure 38 comprise a wiring layer disposed on the first main surface 3. That is, the peripheral wiring structure 34, the connection wiring structure 35, and the resistance wiring structure 38 form a polysilicon wiring layer 33. The peripheral wiring structure 34, the connection wiring structure 35, and the resistance wiring structure 38 may be collectively referred to as an "underlying wiring layer."

[0095] 4 and 5 , the semiconductor device 1 includes at least one p-type field region 36 (preferably two to twenty) formed in the peripheral region 10. The number of the field regions 36 is typically three to eight. The field regions 36 are formed in an electrically floating state and relieve the electric field within the chip 2 at the periphery of the first main surface 3. The number, width, depth, p-type impurity concentration, etc. of the field regions 36 are arbitrary and can take various values ​​depending on the electric field to be relieved. In this embodiment, the field regions 36 are arranged at intervals from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). In this embodiment, the field regions 36 are formed in a ring shape (specifically, a square ring shape) surrounding the active region 9 in a plan view.

[0096] Fig. 6 is an enlarged view of a portion surrounded by dashed line VI in Fig. 5. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6. Fig. 8 is a cross-sectional view taken along line VIII-VIII in Fig. 6. Fig. 9 is an enlarged view of a portion surrounded by dashed line IX in Fig. 7. Fig. 10 is an enlarged view of a portion surrounded by dashed line X in Fig. 8.

[0097] Semiconductor device 1 includes a p-type body region 40 as an example of a second impurity region formed in a surface layer portion of drift region 8. With reference to Figures 7 and 8, in this embodiment, body region 40 is formed in a layer shape extending along first main surface 3. Body region 40 is formed throughout active region 9. Body region 40 is formed at an interval from the lower end of semiconductor layer 7 toward first main surface 3.

[0098] The body region 40 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the body region 40 may have the following peak value: The p-type impurity concentration of the body region 40 is preferably adjusted by at least one trivalent element. The trivalent element of the body region 40 may be at least one of boron, aluminum, gallium, and indium.

[0099] As described above, the semiconductor device 1 includes a plurality of trench gate structures 11. Referring to FIGS. 6 to 8, each trench gate structure 11 has a trench width WT1 in the arrangement direction. The trench width WT1 is preferably less than the thickness T2 (FIG. 2) of the semiconductor layer 7. The trench width WT1 may be 0.1 μm or more and 5 μm or less.

[0100] The trench width WT1 may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0101] 6 to 8, the trench gate structures 11 are arranged at intervals of a trench pitch PT1 in the second direction Y. The trench pitch PT1 is preferably less than the thickness T2 (FIG. 2) of the semiconductor layer 7. The trench pitch PT1 is preferably less than a trench depth DT1 (FIGS. 9 and 10) described below. The trench pitch PT1 may be 0.1 μm or more and 5 μm or less.

[0102] The trench pitch PT1 may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The trench pitch PT1 is preferably 0.5 μm to 3 μm.

[0103] 9 and 10 , the trench gate structure 11 has a trench depth DT1 in the vertical direction Z. The trench depth DT1 is preferably less than the thickness T2 ( FIG. 2 ) of the semiconductor layer 7. The trench depth DT1 may be 0.1 μm or more and 5 μm or less. The trench depth DT1 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The trench depth DT1 is preferably 0.1 μm or more and 1.5 μm or less, and more preferably 0.5 μm or more and 1.5 μm or less.

[0104] The trench depth DT1 is preferably greater than the trench width WT1. That is, the trench gate structures 11 preferably each have an aspect ratio DT1 / WT1 such that they extend in a vertically elongated columnar shape. The aspect ratio DT1 / WT1 is the ratio of the trench width WT1 to the trench depth DT1. The aspect ratio DT1 / WT1 may be, for example, 1 or more and 5 or less, and is preferably 1 or more and 3 or less.

[0105] 9 and 10 , each trench gate structure 11 includes a trench 41 as a first trench, a trench insulating film 42 as an underlying insulating film, and a buried body 43. The trench 41 may be referred to as an "element trench," a "gate trench," or the like. The trench insulating film 42 may be referred to as an "element insulating film," a "gate insulating film," or the like. The buried body 43 may be referred to as a "connection electrode," a "gate electrode," or the like.

[0106] The trenches 41 are formed in the first main surface 3 and define the inner surfaces (side surfaces 44 and bottom surfaces 45 shown in FIGS. 9 and 10 ) of the trench gate structures 11. The bottom surfaces 45 of the trenches 41 preferably have flat portions. Between adjacent trenches 41, mesa portions 46 are formed from part of the semiconductor layer 7 and serve as an example of a cell portion. The mesa portions 46 may also be referred to as "element mesa portions." The width of the mesa portions 46 in the second direction Y is determined by the trench pitch PT1.

[0107] 7 and 8 , the trenches 41 and mesa portions 46 are strip-shaped and extend along the first direction X, and are arranged alternately in the second direction Y. The trenches 41 are arranged in a stripe pattern. The mesa portions 46 are arranged in a stripe pattern.

[0108] 9 and 10 , it is particularly preferable that the flat portion of bottom surface 45 of trench 41 extends substantially parallel to first main surface 3. Of course, bottom surface 45 of trench 41 may be curved in an arc shape toward the lower end side of semiconductor layer 7.

[0109] The trench insulating film 42 covers the inner surface of the trench 41. The trench insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the trench insulating film 42 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the trench insulating film 42 include a silicon oxide film made of an oxide of the chip 2.

[0110] 9 and 10 , the buried body 43 is buried in the trench 41 and faces the channel with the trench insulating film 42 interposed therebetween. In this embodiment, the buried body 43 faces the body region 40 with the trench insulating film 42 interposed therebetween. The buried body 43 is made of polysilicon. This polysilicon may be p-type or n-type conductive polysilicon.

[0111] The buried body 43 is buried up to the middle of the trench 41 in the depth direction. The buried body 43 has an upper surface 47 located closer to the second main surface 4 than the first main surface 3. A low step is formed on the second main surface 4 side between the upper surface 47 of the buried body 43 and the first main surface 3. This step forms a recess 48 in the upper part of the trench 41, which is defined by the upper surface 47 of the buried body 43 and the side surface 44 of the trench 41.

[0112] 9 and 10 , the recess 48 is a space sandwiched between both side surfaces 44 of the trench 41 and an upper surface 47 of the buried body 43. The recess 48 is formed in a continuous strip shape in the depth direction (first direction X) of the trench 41. The trench insulating film 42 is selectively formed in a region sandwiched between the inner surface of the trench 41 and the buried body 43, and the side surface of the recess 48 (part of the side surface 44 of the trench 41) is exposed from the trench insulating film 42.

[0113] The semiconductor device 1 includes a first electric field relaxation layer 51 formed at the bottom of the trench gate structure 11. More specifically, the first electric field relaxation layer 51 is formed at the bottom of the trench 41. The first electric field relaxation layer 51 is formed at the bottom of the trench 41 over the entire depth of the trench 41, and is formed in a strip shape extending in the depth direction of the trench 41.

[0114] 9 and 10 , the first electric field relaxation layer 51 is exposed from the bottom surface 45 of the trench 41 and is in contact with the trench insulating film 42. Therefore, the upper end of the first electric field relaxation layer 51 is exposed at the bottom surface 45 of the trench gate structure 11 (trench 41). The first electric field relaxation layer 51 faces the buried body 43 via the trench insulating film 42 in the depth direction of the trench 41. At the bottom of the trench 41, the trench insulating film 42 is sandwiched between the buried body 43 and the first electric field relaxation layer 51.

[0115] First electric field buffer layer 51 is formed across one end and the other end of trench 41 in the width direction of trench 41. With reference to Figures 9 and 10, in this embodiment, first electric field buffer layer 51 has, in the depth direction of trench 41, one side surface 52 formed on approximately the same plane as one side surface 44 of trench 41 in the width direction, and the other side surface 52 formed on approximately the same plane as the other side surface 44 of trench 41 in the width direction.

[0116] A side surface 52 of the first electric field relaxation layer 51 extends in the depth direction of the trench gate structure 11 and forms a boundary surface with the semiconductor layer 7 (drift region 8). The first electric field relaxation layer 51 is physically separated from the body region 40 in the depth direction of the trench gate structure 11 and forms the entire bottom surface 45 of the trench gate structure 11.

[0117] 9 and 10 , the first electric field reduction layer 51 in this embodiment has a laminated structure of a first layer 53 and a second layer 54. The first layer 53 is a layer formed away from the bottom of the trench 41 (bottom surface 45 in this embodiment) toward the second main surface 4. The second layer 54 is a layer formed between the first layer 53 and the bottom of the trench 41 (bottom surface 45 in this embodiment). The second layer 54 is exposed from the bottom surface 45 of the trench 41 and is in contact with the trench insulating film 42. The second layer 54 is sandwiched between the first layer 53 and the bottom of the trench 41.

[0118] In this embodiment, the second layer 54 has a laminated structure of an upper layer 54 a and a lower layer 54 b. The upper layer 54 a is exposed from the bottom of the trench 41 (the bottom surface 45 in this embodiment) and is in contact with the trench insulating film 42. The lower layer 54 b is in contact with the first layer 53 of the first electric field relaxation layer 51.

[0119] Regarding the impurity concentration of the first field relaxation layer 51, the first layer 53 has a first impurity concentration. The upper layer 54a of the second layer 54 has a second impurity concentration. The lower layer 54b of the second layer 54 has a third impurity concentration. In this embodiment, the second impurity concentration of the upper layer 54a and the third impurity concentration of the lower layer 54b are higher than the first impurity concentration of the first layer 53. The second impurity concentration of the upper layer 54a is higher than the third impurity concentration of the lower layer 54b. Furthermore, the first impurity concentration of the first layer 53 may be equal to the impurity concentration of the body region 40. The second impurity concentration of the upper layer 54a of the second layer 54 and the third impurity concentration of the lower layer 54b may be higher than the impurity concentration of the body region 40.

[0120] For example, the first impurity concentration of the first layer 53 is 1×10 １５ cm －３ 1x10 or more １６ cm －３ The second impurity concentration of the upper layer 54a of the second layer 54 may have a peak value of 1×10 １９ cm －３ 1x10 or more ２０ cm －３ The second impurity concentration of the lower layer 54b of the second layer 54 may have a peak value of 1×10 １６ cm －３ 1x10 or more １７ cm －３ The p-type impurity concentration may have the following peak value:

[0121] The second impurity concentration in the upper layer 54a of the second layer 54 and the third impurity concentration in the lower layer 54b of the second layer 54 may be the same. That is, the second layer 54 may be an impurity region having a single p-type impurity concentration as a peak value.

[0122] The p-type impurity concentrations of the first layer 53 and the second layer 54 are preferably adjusted by at least one trivalent element, which may be at least one of boron, aluminum, gallium, and indium.

[0123] The stacked structure of the first layer 53 and the second layer 54 is continuous in the depth direction of the trench 41. In this embodiment, the first electric field relaxation layer 51 is formed in a strip shape extending in the depth direction of the trench 41 so that the stacked structure of the first layer 53 and the second layer 54 is continuous throughout the entire depth direction of the trench 41. For example, the multiple first electric field relaxation layers 51 are arranged at intervals in the m-axis direction and extend in the a-axis direction of the SiC single crystal. The multiple first electric field relaxation layers 51 are formed in a stripe shape extending in the a-axis direction (first direction X), and the extending direction of the multiple first electric field relaxation layers 51 coincides with the off-direction of the semiconductor layer 7.

[0124] The multiple first electric field relaxation layers 51 overlap the multiple trench gate structures 11 in the depth direction of the trench 41. Specifically, the multiple first electric field relaxation layers 51 overlap the multiple trench gate structures 11 in a one-to-one correspondence in the vertical direction Z. In this embodiment, the multiple first electric field relaxation layers 51 are connected to the bottom surfaces 45 of the corresponding trench gate structures 11, respectively.

[0125] 9 and 10 , the first electric field reduction layer 51 has a first relaxation depth DR1 in the vertical direction Z. The first relaxation depth DR1 may be 0.25 μm or more and 5 μm or less. The first relaxation depth DR1 may have a value belonging to any one of the following ranges: more than 0.25 μm to 0.5 μm or less, 0.5 μm to 1 μm or less, 1 μm to 1.5 μm or less, 1.5 μm to 2 μm or less, 2 μm to 3 μm or less, 3 μm to 4 μm or less, and 4 μm to 5 μm or less. The first relaxation depth DR1 is preferably 1.5 μm to 2.5 μm or less.

[0126] Each of the first electric field reduction layers 51 has a first relaxation width WR1 in the arrangement direction. The first relaxation width WR1 may be 0.25 μm or more and 5 μm or less. The first relaxation width WR1 may have a value belonging to any one of the following ranges: 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0127] 7 and 9 , semiconductor device 1 includes a source region 55 as an example of a third impurity region formed in a surface layer portion of first main surface 3. Source region 55 is formed in a region between a plurality of trench gate structures 11. Source region 55 is formed in a surface layer portion of body region 40. In other words, trench 41 extends from first main surface 3 through source region 55 and body region 40 to reach semiconductor layer 7.

[0128] In this embodiment, a plurality of source regions 55 are formed across the mesa portion 46 in the width direction, from one side surface 44 to the other side surface 44 of the mesa portion 46 (one side surface 44 and the other side surface 44 of the trench 41).

[0129] The source region 55 has a higher n-type impurity concentration (peak value) than the semiconductor layer 7 (drift region 8). １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0130] 9 , source region 55 has a source thickness ST1. Source thickness ST1 may be the thickness of source region 55 in vertical direction Z from first main surface 3. Source thickness ST1 may be, for example, not less than 0.2 μm and not more than 1.0 μm, preferably not less than 0.4 μm and not more than 0.8 μm.

[0131] 8 and 10 , the semiconductor device 1 includes first contact regions 57 formed in a surface layer portion of the first main surface 3. The first contact regions 57 are formed in regions between the plurality of trench gate structures 11. In this embodiment, the plurality of first contact regions 57 are formed across the mesa portion 46 in the width direction, from one side surface 44 to the other side surface 44 of the mesa portion 46. The first contact regions 57 are formed adjacent to the source regions 55 in a surface layer portion of the body region 40.

[0132] 6 , in each mesa portion 46, the source regions 55 and the first contact regions 57 are alternately arranged along the depth direction of the trench 41. In each mesa portion 46, the lengths of the source regions 55 in the first direction X are the same. In each mesa portion 46, the lengths of the first contact regions 57 in the first direction X are the same. In each mesa portion 46, the source regions 55 are arranged at intervals along the depth direction of the trench 41. As a result, in each mesa portion 46, a plurality of channel sections 56 are arranged at intervals in the first direction X (depth direction of the trench 41). In the channel sections 56, channels are formed on both side surfaces 44 of the trench 41 on both sides of the mesa portion 46 in the second direction Y. In other words, channels are formed in the body region 40.

[0133] 9 and 10 , the body region 40 includes a first body portion 58 ( FIG. 9 ) formed directly below the source region 55 and a second body portion 59 ( FIG. 10 ) formed directly below the first contact region 57. The first body portion 58 is a portion of the body region 40 that is sandwiched between the source region 55 and the drift region 8 in the depth direction of the trench 41. The second body portion 59 is a portion of the body region 40 that is sandwiched between the first contact region 57 and the drift region 8 in the depth direction of the trench 41.

[0134] The first body portion 58 and the second body portion 59 are both part of the body region 40. Therefore, the first body portion 58 and the second body portion 59 have the same p-type impurity concentration as a peak value. The p-type impurity concentrations of the first body portion 58 and the second body portion 59 may be different from each other.

[0135] 9 and 10, the first body portion 58 has a first body thickness BT1, and the second body portion 59 has a second body thickness BT2. The second body thickness BT2 is greater than the first body thickness BT1.

[0136] 9 and 10 , the first body portion 58 has a first body depth BD1, and the second body portion 59 has a second body depth BD2. In this embodiment, the second body depth BD2 is the same as the first body depth BD1. The second body depth BD2 may be deeper or shallower than the first body depth BD1.

[0137] 9 , a first boundary surface 60 between the first body portion 58 and the source region 55 is located closer to the second main surface 4 than the upper surface 47 of the buried body 43. The first boundary surface 60 is formed at a position lower than the upper surface 47 of the buried body 43. A part of the source region 55 (for example, the lower end) faces the buried body 43 via the trench insulating film 42. This ensures the formation of a channel between the source and the drain.

[0138] 10 , a second boundary surface 61 between the second body portion 59 and the first contact region 57 is located closer to the first main surface 3 than the upper surface 47 of the buried body 43. A part (for example, an upper end) of the second body portion 59 protrudes toward the first main surface 3 (upper side) than the buried body 43. The first contact region 57 is not a region that directly contributes to the formation of a channel between the source and drain, and therefore, unlike the source region 55, it does not have to face the buried body 43 via the trench insulating film 42.

[0139] 8 and 10 , the semiconductor device 1 includes a second contact region 62 formed in a surface layer portion of the first main surface 3. The second contact region 62 connects the first contact region 57 and the first electric field reduction layer 51. The second contact region 62 is formed along the side surface 44 of the trench 41 from the first contact region 57 toward the second main surface 4 and is connected to the first electric field reduction layer 51. In this embodiment, the second contact region 62 is formed from the first contact region 57 exposed from both side surfaces 44 of the mesa portion 46 along both the one side surface 44 and the other side surface 44 of the mesa portion 46.

[0140] The second contact region 62 penetrates the body region 40 and straddles between the body region 40 and the first electric field relaxation layer 51. The second contact region 62 forms a boundary with the body region 40 and is connected to the body region 40. The second contact region 62 is also connected to the drift region 8 below the body region 40. That is, a pn junction is formed by the second contact region 62 and the drift region 8 in the section between the body region 40 and the first electric field relaxation layer 51.

[0141] 10 , the second contact region 62 is exposed from the side surface 44 of the trench 41 and is in contact with the trench insulating film 42 at the side surface 44 of the trench 41. The lower end of the second contact region 62 is in contact with the upper layer 54 a of the second layer 54 of the first electric field reduction layer 51.

[0142] In this embodiment, the first contact region 57 and the second contact region 62 have the same p-type impurity concentration as the upper layer 54a of the second layer 54. In this case, the first contact region 57, the second contact region 62, and the upper layer 54a of the second layer 54 may form an integral p-type impurity region.

[0143] As described above, the semiconductor device 1 includes the insulating layer 13. Referring to FIGS. 7 to 10 , the insulating layer 13 includes a first interlayer insulating layer 63 embedded in the recess 48 of the semiconductor layer 7. The first interlayer insulating layer 63 may also be referred to as an "interlayer insulating film," an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this embodiment, the first interlayer insulating layer 63 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0144] The first interlayer insulating layer 63 may have a multilayer structure or a single-layer structure. The first interlayer insulating layer 63 is embedded in the recess 48 over the entire depth direction of the trench 41 and is formed in a strip shape extending in the depth direction of the trench 41.

[0145] 9 and 10 , the first interlayer insulating layer 63 is embedded in the recess 48 so that an upper edge 64 of the trench 41 is exposed from the first main surface 3. The upper edge 64 of the trench 41 may be a portion at the top of the trench 41 where the side surface 44 of the trench 41 intersects with the first main surface 3. In other words, the first interlayer insulating layer 63 does not cover the periphery of the trench 41 on the first main surface 3, and is contained within the inner region of the trench 41 in the width direction of the trench 41.

[0146] The first interlayer insulating layer 63 contacts the source region 55 and the first contact region 57 on the side surface of the recess 48 (side surface 44 of the trench 41). In this embodiment, the upper surface 65 of the first interlayer insulating layer 63 is located closer to the bottom of the trench 41 than the first main surface 3 in the depth direction of the trench 41. The upper surface 65 of the first interlayer insulating layer 63 has a central portion recessed downward, the central portion being away from the side surface of the recess 48.

[0147] 7 to 10, source pad 20 is formed on first main surface 3 to cover first interlayer insulating layer 63. Source pad 20 has a laminated structure including a barrier layer 66 and a main body layer 67 laminated in this order from the first main surface 3 side.

[0148] The barrier layer 66 is formed in a film shape along the first main surface 3 and the inner surface of the recess 48 (the side surface of the recess 48 and the upper surface 65 of the first interlayer insulating layer 63). The barrier layer 66 is in contact with the source region 55 and the first contact region 57. The barrier layer 66 may include at least one of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer. The thickness of the barrier layer 66 may be 0.05 μm or more and 0.3 μm or less. The thickness of the barrier layer 66 is preferably 0.1 μm or more and 0.2 μm or less.

[0149] The main layer 67 is formed on the barrier layer 66. The main layer 67 covers the entire main surface of the barrier layer 66. The main layer 67 is electrically connected to the source region 55 and the first contact region 57 via the barrier layer 66. The thickness of the main layer 67 exceeds the thickness of the barrier layer 66. The thickness of the main layer 67 may be 1 μm or more and 10 μm or less. The thickness of the main layer 67 is preferably 3 μm or more and 6 μm or less.

[0150] In this embodiment, the source pad 20 is connected to the source region 55 and the first contact region 57 at the side surface of the recess 48 and the first main surface 3. Therefore, the first electric field reduction layer 51 is fixed to the source potential via the first contact region 57.

[0151] FIG. 11 is an enlarged view of a portion surrounded by dashed-dotted line XI in FIG. 5. FIG. 12 is an enlarged view of a portion surrounded by dashed-dotted line XII in FIG. 11. FIG. 13A is an enlarged view of a portion surrounded by dashed-dotted line XIII in FIG. 12. FIG. 13B is a plan view illustrating a first dummy structure 91 according to a second embodiment and corresponds to FIG. 13A. FIG. 13C is a plan view illustrating a first dummy structure 91 according to a third embodiment and corresponds to FIG. 13B. FIG. 13D is a plan view illustrating a first dummy structure 91 according to a fourth embodiment and corresponds to FIG. 13B. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 13A. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 13A. FIG. 16A is a cross-sectional view taken along line XVIA-XVIA in FIG. 13A. FIG. 16B is a cross-sectional view taken along line XVIB-XVIB in FIG. 13A. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 13A. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 13A. Fig. 19 is a cross-sectional view taken along line XIX-XIX shown in Fig. 13A. Fig. 20 is an enlarged view of a portion surrounded by dashed-dotted line XX in Fig. 15. Fig. 21 is an enlarged view of a portion surrounded by dashed-dotted line XXI in Fig. 18. Figs. 22A to 22C are diagrams for explaining part of the manufacturing process of the semiconductor device 1, and show a cross section corresponding to the portion surrounded by dashed-dotted line XXII in Fig. 20.

[0152] As described above, the semiconductor device 1 includes a plurality of connection wiring structures 35 extending in stripes in the second direction Y in the active region 9. Referring to Fig. 12, in this embodiment, the connection wiring structure 35 includes a connection wiring layer 130 arranged on the first main surface 3 in the active region 9. The connection wiring layer 130 extends in the second direction Y so as to cross the plurality of trench gate structures 11 and the plurality of mesas 46 formed between the plurality of trench gate structures 11. The extending direction of the connection wiring layer 130 is a direction intersecting the off-direction of the SiC single crystal.

[0153] In this embodiment, the connection wiring layer 130 is a part of the polysilicon wiring layer 33. When a polysilicon film is formed by CVD to fill the trench 41 and cover the first main surface 3, a part of the polysilicon film can be used to form the polysilicon wiring layer 33 ( FIG. 4 ), thereby forming the connection wiring layer 130.

[0154] This allows the connection wiring structure 35 (connection wiring layer 130) to be manufactured in the same process as the trench gate structure 11. Therefore, the number of manufacturing steps can be reduced compared to when the connection wiring structure 35 is formed from a material different from that of the trench gate structure 11. Furthermore, when the connection wiring structure 35 is formed from polysilicon, manufacturing efficiency can be improved compared to when the connection wiring structure 35 is formed from other materials.

[0155] In this embodiment, the connection wiring structure 35 includes a connection wiring layer 130 formed on the first main surface 3, and does not employ a trench structure. When the connection wiring structure 35 is realized using the connection wiring layer 130, it can be easily formed using deposition and patterning of a material film. This allows the connection wiring structure 35 to be created more efficiently than when the connection wiring structure 35 is realized using a trench structure.

[0156] 14 , the connection wiring layer 130 has a lower surface 133, an upper surface 134, a first side surface (side surface) 135 on one side in the first direction X, and a second side surface (side surface) 136 on the other side in the first direction X. The lower surface 133 is substantially parallel to the first main surface 3. In this embodiment, the first side surface 135 and the second side surface 136 extend perpendicular to the lower surface 133. That is, the connection wiring layer 130 is formed in a quadrangular shape (a flattened rectangular shape) in a cross-sectional view.

[0157] The connection wiring layer 130 may have a connection width W1 of 1 μm or more and 10 μm or less. The connection width W1 of the connection wiring layer 130 is the width in a direction perpendicular to the extending direction (i.e., the first direction X). The connection width W1 of the connection wiring layer 130 may have a value belonging to at least one of the ranges of 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, and 7.5 μm or more and 10 μm or less. The connection width W1 of the connection wiring layer 130 is preferably 1 μm or more and 5 μm or less.

[0158] The first side surface 135 and the second side surface 136 may be obliquely inclined toward the lower surface 133. In other words, the connection wiring layer 130 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in a cross-sectional view.

[0159] 14 , the connection wiring layer 130 is disposed on a first insulating film 131 that selectively covers the first main surface 3. On the upper surface of the mesa portion 46, the connection wiring layer 130 is disposed on a portion of the first insulating film 131 that covers the first contact region 57.

[0160] 12 and 14 , in this embodiment, the connection wiring layer 130 faces the first contact region 57 (second body portion 59) across the first insulating film 131. The connection wiring layer 130 is not disposed on a portion of the first insulating film 131 that covers the source region 55. In other words, the connection wiring layer 130 does not face the source region 55 (first body portion 58).

[0161] 12 and 14 , a region of the first contact region 57 that faces the connection wiring structure 35 in the vertical direction Z is referred to as an opposing contact region 57A. In other words, the opposing contact region 57A is a region of the first contact region 57 that overlaps with the connection wiring structure 35 in a plan view.

[0162] In this embodiment, the opposing contact region 57A has a length LC in the first direction X. The length LC is different from that of the other first contact regions 57 (for example, in FIG. 12 , the first contact region 57 that faces the opposing contact region 57A in the first direction X across the source region 55). The length LC of the opposing contact region 57A is longer than the length of the other first contact regions 57 in the first direction X. The length LC is longer than the width X1 of the connection wiring layer 130.

[0163] 12 and 14, the opposing contact region 57A includes an opposing portion 57C (FIG. 14) that faces the connection wiring layer 130 in the vertical direction Z, and a non-opposing portion 57B that does not face the connection wiring layer 130. The non-opposing portions 57B are formed at both end portions of the opposing contact region 57A in the first direction X.

[0164] The two non-opposing portions 57B sandwich the opposing portion 57C in the first direction X. The non-opposing portions 57B are drawn out to both sides in the first direction X from the opposing portion 57C ( FIG. 14 ) that faces the connection wiring layer 130. The non-opposing portions 57B extend from the opposing portion 57C toward the source region 55, and the bottom of the non-opposing portions 57B is covered by the source region 55.

[0165] 14 , a region of the second body portion 59 that faces the connection wiring structure 35 in the vertical direction Z with the first insulating film 131 sandwiched therebetween is referred to as an opposing body portion 59A. The opposing body portion 59A is a fourth impurity region. The opposing body portion 59A is a region below the opposing contact region 57A. In other words, the opposing body portion 59A is a region of the second body portion 59 that overlaps with the connection wiring structure 35 in a planar view.

[0166] In this embodiment, the opposing body portion 59A has a length LB in the first direction X. The length LB is different from that of the other second body portions 59 (for example, in FIG. 12 , the second body portion 59 that faces the opposing body portion 59A in the first direction X across the source region 55). The length LB of the opposing body portion 59A is longer than the length of the other second body portions 59 in the first direction X. The length LB is longer than the width X1 of the connection wiring layer 130. The length LB is shorter than the length LC.

[0167] 14 , the opposing portion 59C is sandwiched between the two non-opposing portions 59B in the first direction X. The non-opposing portions 59B are drawn out on both sides along the first direction X from the opposing portion 59C that faces the connection wiring layer 130.

[0168] Referring to FIG. 15 , at a connection portion 151 between the trench gate structure 11 and the connection wiring layer 130 , the connection wiring layer 130 is connected to the buried body 43 of the trench gate structure 11 via a contact hole 132 .

[0169] The contact hole 132 vertically penetrates the first insulating film 131 and the first interlayer insulating layer 63 in a region facing the connection wiring layer 130 in the vertical direction Z. The connection wiring layer 130 contacts the buried body 43 of the trench gate structure 11 from above via the contact hole 132. This electrically connects the connection wiring layer 130 to the trench gate structure 11.

[0170] 14 and 15 , the connection wiring layer 130 may have a connection thickness (thickness) T3 of 0.1 μm or more and 2 μm or less. The connection thickness T3 of the connection wiring layer 130 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. The connection thickness T3 of the connection wiring layer 130 is preferably 0.2 μm or more and 1 μm or less.

[0171] The connection wiring layer 130 includes a first contact 137 that extends from the lower surface 133 into the recess 48 of the trench 41 and contacts the buried body 43 of the trench gate structure 11. In this embodiment, the first contact 137 is part of the connection wiring layer 130.

[0172] 14 , on the upper surface of the mesa portion 46, a linear lower region 138 is set below the connection wiring layer 130. A first lateral region 139 and a second lateral region 140 are set on either side of the lower region 138, extending along the lower region 138. The first lateral region 139 and the second lateral region 140 sandwich the lower region 138 in the first direction X.

[0173] 14 , the first lateral region 139 is a region of the connection wiring layer 130 on the first side surface 135 side when viewed from the center of the connection wiring layer 130 in the first direction X. The outer edge of the first lateral region 139 is formed at a position spaced a distance W11 in the first direction X from the boundary with the lower region 138. The distance W11 may be 0.2 to 2 times the connection width W1. The distance W11 is preferably 0.5 to 0.5 times the connection width W1.

[0174] 14 , the second lateral region 140 is a region of the connection wiring layer 130 on the second side surface 136 side as viewed from the center of the connection wiring layer 130 in the first direction X. The outer edge of the second lateral region 140 is formed at a position spaced a distance W12 in the first direction X from the boundary with the lower region 138. The distance W12 may be 0.2 to 2 times the connection width W1. The distance W12 is preferably 0.5 to 0.5 times the connection width W1. The distance W12 may be the same size as the distance W11.

[0175] A first insulating film 131 is formed in the lower region 138, the first lateral region 139, and the second lateral region 140. The first insulating film 131 extends along the lower surface 133 of the connection wiring layer 130. The first insulating film 131 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first insulating film 131 may also be referred to as a main surface insulating film. The first insulating film 131 is not formed in the region between the connection wiring layer 130 and the trench gate structure 11. That is, the first insulating film 131 extends intermittently in the second direction Y.

[0176] The semiconductor device 1 includes a first silicide layer 141 formed on the surface of the connection wiring layer 130. The first silicide layer 141 covers the top surface 134, the first side surface 135, and the second side surface 136 of the connection wiring layer 130. The first silicide layer 141 is a polycide portion formed by silicidizing polysilicon of the connection wiring layer 130. The first silicide layer 141 may also be referred to as a "first metal semiconductor compound layer," a "first silicide layer (polycide layer)," a "first silicide region (polycide region)," or the like.

[0177] The first silicide layer 141 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The first silicide layer 141 is preferably made of Ti silicide, Ni silicide, or Co silicide.

[0178] The first silicide layer 141 includes a first covering layer 142 covering the top surface 134 of the connection wiring layer 130, a second covering layer 143 covering the first side surface 135 of the connection wiring layer 130, and a third covering layer 144 covering the second side surface 136 of the connection wiring layer 130. The first covering layer 142 is formed from the peripheral edge of the top surface 134 on the first side surface 135 side to the peripheral edge on the second side surface 136 side.

[0179] The first covering layer 142 is flat and extends along the upper surface 134. The thickness of the first covering layer 142 may be 0.01 to 0.2 times the connection width W1 of the connection wiring layer 130. The first silicide layer 141 is formed in a strip shape extending along the connection wiring layer 130 in a plan view.

[0180] The second covering layer 143 is formed from the upper edge to the lower edge of the first side surface 135 and is exposed from the lower surface 133 and the upper surface 134. The second covering layer 143 is flat and extends along the first side surface 135. The thickness of the second covering layer 143 is 0.01 to 0.2 times the connection width W1. The second covering layer 143 is formed in a strip shape extending along the connection wiring layer 130 in a cross-sectional view. The thickness of the second covering layer 143 may be the same as the thickness of the first covering layer 142.

[0181] The third covering layer 144 is formed from the upper edge to the lower edge of the second side surface 136 and is exposed from the lower surface 133 and the upper surface 134. The third covering layer 144 is flat and extends along the second side surface 136. The thickness of the third covering layer 144 is 0.01 to 0.2 times the connection width W1. The third covering layer 144 is formed in a strip shape extending along the connection wiring layer 130 in a cross-sectional view. The thickness of the third covering layer 144 may be the same as the thickness of the first covering layer 142. The thickness of the third covering layer 144 may be the same as the thickness of the second covering layer 143.

[0182] As described above, the semiconductor device 1 includes an insulating layer 13. Referring to FIGS. 14 and 15 , the insulating layer 13 includes a second interlayer insulating layer 145 that covers the upper and side surfaces of the connection wiring layer 130. The second interlayer insulating layer 145 is formed on the lower region 138, the first lateral region 139, and the second lateral region 140. The second interlayer insulating layer 145 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second interlayer insulating layer 145 may have a stacked structure. The second interlayer insulating layer 145 may have a single-layer structure.

[0183] The second interlayer insulating layer 145 includes a covering portion 146 that covers the upper and side surfaces of the connection wiring layer 130, a first protruding portion 147 that protrudes outward from the side of the first side surface 135 of the connection wiring layer 130 beyond the covering portion 146, and a second protruding portion 148 that protrudes outward from the side of the second side surface 136 of the connection wiring layer 130 beyond the covering portion 146. A thickness T4 of the covering portion 146 may be thinner than a connection thickness T3 of the connection wiring layer 130. The thickness T4 may be 0.5 times or less the connection thickness T3 of the connection wiring layer 130.

[0184] The first protruding portion 147 faces the first side region 139, with the first insulating film 131 sandwiched therebetween. In this embodiment, the outer edge of the first protruding portion 147 coincides with the outer edge of the first side region 139. The thickness T5 of the first protruding portion 147 may be thinner than the connection thickness T3 of the connection wiring layer 130. The thickness T5 may be thicker or thinner than the thickness T4 of the covering portion 146.

[0185] The second protruding portion 148 faces the second side region 140, with the first insulating film 131 sandwiched therebetween. In this embodiment, the outer edge of the second protruding portion 148 coincides with the outer edge of the second side region 140. The thickness T6 of the second protruding portion 148 may be thinner than the connection thickness T3 of the connection wiring layer 130. The thickness T6 may be thicker or thinner than the thickness T4 of the covering portion 146.

[0186] 15 , the trench insulating film 42 included in the trench gate structure 11 is selectively formed thick. In this embodiment, the trench insulating film 42 is formed thick in a connection portion 151 between the trench gate structure 11 and the connection wiring layer 130, and in a first connection side region 152 and a second connection side region 153 adjacent to the connection portion 151 in the first direction X. The first connection side region 152 and the second connection side region 153 are examples of side regions. Hereinafter, the connection portion 151, the first connection side region 152, and the second connection side region 153 may be collectively referred to as a "connection region E1."

[0187] The trench insulating film 42 has different thicknesses in the connection region E1 and in a region E2 other than the connection region E1. The region E2 other than the connection region E1 will be referred to as the "other region E2" hereinafter. The connection portion 151 is a region below the connection wiring layer 130. In this embodiment, the first connection side region 152 overlaps the first side region 139 in a planar view. The second connection side region 153 overlaps the second side region 140 in a planar view.

[0188] 9, 10, 17, 20, and 21, the trench insulating film 42 includes a thick film portion 154 and a thin film portion 155. The thick film portion 154 is selectively formed in the trench insulating film 42. The thin film portion 155 is formed in a region of the trench insulating film 42 where the thick film portion 154 is not formed. In this embodiment, the thick film portion 154 is formed in the connection region E1, and the thin film portion 155 is formed in the other region E2.

[0189] The thickness T11 of the thick portion 154 of the trench insulating film 42 (FIGS. 17, 20, and 21) is thicker than the thickness T12 of the thin portion 155 of the trench insulating film 42 (FIGS. 9, 10, and 20) (T11>T12). The thickness T11 of the thick portion 154 of the trench insulating film 42 is, for example, 2 μm or more and 10 μm or less. The thickness T12 of the thin portion 155 of the trench insulating film 42 is, for example, 1 μm or more and 5 μm or less. The thickness T11 of the thick portion 154 may be three times or less the thickness T12 of the thin portion 155. The thickness T11 of the thick portion 154 is preferably 1.5 times or more and 2.5 times or less the thickness T12 of the thin portion 155. The thickness T11 of the thick portion 154 is more preferably 1.7 times or more and 2.3 times or less the thickness T12 of the thin portion 155.

[0190] 20 , in this embodiment, the thick film portion 154 has a laminated structure of a first film 154A and a second film 154B laminated in this order from the inner surface (side surface and bottom surface 45) of the trench 41. The lamination interface between the first film 154A and the second film 154B does not necessarily appear in the thick film portion 154. For convenience, the lamination interface is indicated by a dashed line in FIG. 20 .

[0191] The first film 154A is a deposited film. The first film 154A includes an oxide film. The first film 154A may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first film 154A has a single-layer structure made of a silicon oxide film. The second film 154B may be a deposited film or a thermally oxidized film. The second film 154B includes an oxide film. In this embodiment, the second film 154B has a single-layer structure made of a silicon oxide film.

[0192] The trench insulating film 42 has a bottom insulating film 42a in contact with the bottom surface 45 of the trench 41. With reference to Figures 15 and 20, the surface of the bottom insulating film 42a is convex toward the first main surface 3 in a cross-sectional view taken along the first direction X.

[0193] Specifically, in the bottom insulating film 42a, the upper surface of the thick film portion 154 is closer to the first main surface 3 than the upper surface of the thin film portion 155. In other words, in the bottom insulating film 42a, a first step S1 that is higher on the first main surface 3 side is formed between the upper surface of the thick film portion 154 and the upper surface of the thin film portion 155.

[0194] 22A to 22C are diagrams for explaining a part (formation of trench insulating film 42) of the manufacturing process of semiconductor device 1. Figures 22A to 22C show a cross section corresponding to the part surrounded by dashed dotted line XXII in Figure 20.

[0195] 22A , first base insulating film 156, which serves as the base of thick film portion 154, is formed on the inner surface (side surface and bottom surface 45) of trench 41. First base insulating film 156 is formed by the CVD method. Since it is formed by the CVD method, the thickness of first base insulating film 156 can be controlled with high precision.

[0196] 22B, a hard mask 157 is formed on the first base insulating film 156. The hard mask 157 may be formed by a CVD method. The hard mask 157 covers the connection region E1 and exposes the other region E2. The first base insulating film 156 is then selectively removed by etching via the hard mask 157. As a result, the first base insulating film 156 is formed only in the connection region E1. The first film 154A is formed by the first base insulating film 156.

[0197] 22C , second base insulating film 158, which serves as a base for thick film portion 154 and thin film portion 155, is formed on the inner surface (side surface and bottom surface 45) of trench 41. Second base insulating film 158 may be formed by a CVD method or an oxidation method (for example, a thermal oxidation method).

[0198] The second base insulating film 158 is formed on the other region E2 and the first film 154A. The second base insulating film 158 covering the other region E2 forms the thin film portion 155. The second base insulating film 158 stacked on the first film 154A forms the second film 154B. This forms the trench insulating film 42 having the thick film portion 154 selectively in the connection region E1.

[0199] According to this embodiment, the trench insulating film 42 (bottom insulating film 42a) in the connection region E1 is selectively thick. That is, a thick film portion 154 is formed in the connection region E1. This improves the reliability of the trench gate structure 11. In this embodiment, the thick film portion 154 is formed not only in the connection region 151 but also in the first connection side region 152 and the second connection side region 153. This further improves the reliability of the trench gate structure 11.

[0200] Furthermore, while a thick film portion 154 is formed in the connection region E1, a thin film portion 155 is formed in the other region E2. That is, the thin film portion 155 is applied to most of the trench insulating film 42 of the trench gate structure 11 (FIGS. 9 and 10). Because the trench insulating film 42 is the thin film portion 155, the channel can be formed well. Therefore, the reliability of the trench gate structure 11 can be improved while the channel is formed well.

[0201] 20, the upper surface 43a of the embedded body 43 in the connection region E1 is closer to the first main surface 3 than the upper surface 43a of the embedded body 43 in the other region E2. In other words, a second step S2 (FIG. 20) that is higher on the first main surface 3 side is formed on the upper surface 43a of the embedded body 43 between the connection region E1 and the other region E2.

[0202] The lower surface 43b of the embedded body 43 in the connection region E1 is closer to the first main surface 3 than the lower surface 43b of the embedded body 43 in the other region E2. In other words, a third step S3 ( FIG. 20 ) that is higher on the first main surface 3 side is formed between the connection region E1 and the other region E2 on the lower surface 43b of the embedded body 43. The third step S3 is the same as the first step S1.

[0203] The first connection side region 152 and the second connection side region 153 may be provided with the thin film portion 155 instead of the thick film portion 154. That is, the thick film portion 154 may be formed only in the connection portion 151 in the trench insulating film 42.

[0204] 11 , the semiconductor device 1 includes a dummy structure 90 formed near the outer edge of the active region 9. When multiple trench gate structures are formed at once, the trench gate structure located near the outermost edge of the multiple (large number of) trench gate structures may lose its shape or its dimensional accuracy may decrease. That is, when multiple trench gate structures extending in the first direction X are formed in the semiconductor device 1, the trench gate structure formed near the outer edge in the second direction Y may include an unstable trench (a trench whose shape and / or dimensions are different from the intended shape and / or dimensions).

[0205] Therefore, in this embodiment, among the plurality of trench gate structures, the trench gate structure located near the outermost side in the second direction Y is not used as the transistor structure Tr, but is used as the dummy structure 90. Only the trench gate structure 11 formed on the inside of the dummy structure 90 in the second direction Y is used as the transistor structure Tr. This makes it possible to stabilize the shapes of the plurality of trench gate structures 11 in the active region 9. In other words, the dummy structure 90 (first dummy trench structure 92) is arranged near the outer edge of the active region 9.

[0206] 12 , the dummy structure 90 is formed in a dummy formation region 80. The dummy formation region 80 is set on the periphery of the active region 9 in the second direction Y on the first main surface 3. In this embodiment, the active region 9 is an element region in which the transistor structure Tr is formed. Therefore, the dummy formation region 80 is a part of the active region 9.

[0207] The connection wiring layer 130 may have a connection width W1 of 1 μm or more and 10 μm or less. It is also possible to define the region of the element region excluding the dummy formation region 80 as the active region 9. In this case, the region obtained by adding the dummy formation region 80 to the active region 9 becomes the element region.

[0208] The dummy formation region 80 includes a first dummy formation region 81 ( FIG. 12 ) arranged on one side in the second direction Y (the first side surface 5A side) of the plurality of trench gate structures 11. The first dummy formation region 81 is adjacent to the plurality of trench gate structures 11 and defines the boundary between the active region 9 and the peripheral region 10.

[0209] The dummy structure 90 includes a first dummy structure 91 and a second dummy structure 201 ( FIG. 31 ). The first dummy structure 91 will be described below, and the second dummy structure 201 ( FIG. 31 ) will be described later. The first dummy structure 91 includes at least one (a plurality in this embodiment) first dummy trench structure 92, a second dummy trench structure 93 arranged midway through the first dummy trench structure 92, and a third dummy trench structure 202 ( FIG. 31 ).

[0210] In this embodiment, a plurality of first dummy trench structures 92 extend in the first direction X through the active region 9 from a first outer edge position P1 ( FIG. 3 ) as an example of a first position to a second outer edge position P2 ( FIG. 3 ) as an example of a second position. A plurality of second dummy trench structures 93 are formed midway through the first dummy trench structures 92 at intervals from each other in the first direction X. Third dummy trench structures 202 ( FIG. 31 ) are formed at both ends of the first dummy trench structures 92.

[0211] As described above, in the active region 9, the multiple connection wiring layers 130 extend in stripes in the second direction Y. If the connection wiring layers 130 are connected to the first dummy trench structures 92, there is a possibility that a gate potential will be applied to the first dummy trench structures 92. In this configuration, the first dummy trench structures 92 are divided midway at positions that overlap with the connection wiring layers 130 in plan view so that the first dummy structures 91 and the second dummy structures 201 do not contribute to channel formation (to prevent malfunction).

[0212] In the first dummy trench structure 92, a second dummy trench structure 93 is disposed at a position overlapping with the connection wiring layer 130 in a plan view. The first dummy trench structure 92 is electrically isolated (insulated) from the second dummy trench structure 93. This allows the first dummy trench structure 92 to be electrically isolated (insulated) from the connection wiring structure 35.

[0213] In the first dummy trench structure 92, a third dummy trench structure 202 ( FIG. 31 ) is disposed at a position that overlaps with the peripheral wiring structure 34 in a plan view. The first dummy trench structure 92 is electrically separated (insulated) from the third dummy trench structure 202. In other words, the first dummy trench structure 92 is a floating trench structure to which no potential is applied.

[0214] The following describes the first dummy trench structure 92 and the second dummy trench structure 93. The third dummy trench structure 202 (FIG. 31) will be described later.

[0215] 12 and 13A, a plurality of first dummy trench structures 92 are formed in the first dummy forming region 81. The plurality of (three in this embodiment) first dummy trench structures 92 are formed in strip shapes extending in the first direction X and are arranged at intervals in the second direction Y. In other words, the plurality of first dummy trench structures 92 extend alongside the plurality of trench gate structures 11. The first dummy trench structures 92 may also be referred to as main dummy trenches.

[0216] 12, 13A, and 19, the first dummy trench structure 92 has a trench width WT2 in the second direction Y. The trench width WT2 is preferably less than the thickness T2 (FIG. 2) of the semiconductor layer 7. The trench width WT2 may be not less than 0.1 μm and not more than 5 μm. The trench width WT2 is preferably approximately equal to the aforementioned trench width WT1.

[0217] The multiple first dummy trench structures 92 are arranged at intervals of a trench pitch PT2 in the second direction Y. The trench pitch PT2 is preferably less than the thickness T2 ( FIG. 2 ) of the semiconductor layer 7. The trench pitch PT2 may be 0.1 μm or more and 5 μm or less. The trench pitch PT2 is preferably approximately equal to the trench pitch PT1 described above.

[0218] 16A and 19, the first dummy trench structure 92 has a trench depth DT2 in the vertical direction Z. The trench depth DT2 is preferably less than the thickness T2 (FIG. 2) of the semiconductor layer 7. The trench depth DT2 is preferably approximately equal to the trench depth DT1 described above. The trench depth DT2 is preferably equal to or greater than the trench pitch PT2.

[0219] 19 , the first dummy trench structure 92 includes a first dummy trench 100, a first dummy insulating film 101, and a first dummy buried body 102. The first dummy trench 100 is formed in the first main surface 3 and defines the inner surface of the first dummy trench structure 92. The bottom surface of the first dummy trench 100 preferably has a portion that extends flat. It is particularly preferable that the flat portion of the bottom surface of the first dummy trench 100 extends approximately parallel to the first main surface 3.

[0220] A first mesa portion 96 formed by a part of the semiconductor layer 7 is formed between two adjacent first dummy trenches 100. In addition, a first mesa portion 96 formed by a part of the semiconductor layer 7 is also formed between adjacent first dummy trenches 100 and trenches 41 of the trench gate structure 11.

[0221] The first mesa portion 96 does not have a source region 55 formed therein. Of the multiple first mesas 96, the first mesa portion 96 adjacent to the mesa portion 46 has a source region 55 partially formed therein. The first mesa portion 96 adjacent to the mesa portion 46 has a source region 55 formed in a region on the mesa portion 46 side in the second direction Y. The source region 55 is not formed in a region on the mesa portion 46 side in the second direction Y. A third body portion 84, which will be described later, is formed on the surface of the first mesa portion 96. A first high-concentration p-region 83, which will be described later, is formed in a surface layer portion of the third body portion 84.

[0222] 19 , the first dummy insulating film 101 covers the inner surface of the first dummy trench 100. The first dummy insulating film 101 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first dummy insulating film 101 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first dummy insulating film 101 includes a silicon oxide film made of an oxide of the chip 2.

[0223] 19 , the first dummy buried body 102 is buried in the first dummy trench 100 and faces the body region 40 across the first dummy insulating film 101. The first dummy buried body 102 is made of polysilicon. This polysilicon may be p-type or n-type conductive polysilicon.

[0224] The first dummy buried body 102 is buried up to the middle in the depth direction of the first dummy trench 100. The first dummy buried body 102 has an upper surface located on the second main surface 4 side relative to the first main surface 3. A first dummy recess 121 defined by the upper surface of the first dummy buried body 102 and the side surface of the first dummy trench 100 is formed in the upper part of the first dummy trench 100.

[0225] 19 , the semiconductor device 1 includes a second electric field relaxation layer 103 formed in the bottom of the first dummy trench structure 92. More specifically, the second electric field relaxation layer 103 is formed in the bottom of the first dummy trench 100. The second electric field relaxation layer 103 is formed in the bottom of the first dummy trench 100 over the entire depth direction of the first dummy trench 100, and is formed in a strip shape extending in the depth direction of the first dummy trench 100.

[0226] 19 , the second electric field relaxation layer 103 is exposed from the bottom surface of the first dummy trench 100 and is in contact with the first dummy insulating film 101. The second electric field relaxation layer 103 faces the first dummy buried body 102 via the first dummy insulating film 101 in the depth direction of the first dummy trench 100. At the bottom of the first dummy trench 100, the first dummy insulating film 101 is sandwiched between the first dummy buried body 102 and the second electric field relaxation layer 103.

[0227] The second electric field relaxation layer 103 is formed across the width direction of the first dummy trench 100 between one end and the other end of the first dummy trench 100. In this embodiment, the second electric field relaxation layer 103 has, in the depth direction of the first dummy trench 100, one side surface formed on approximately the same plane as one side surface of the first dummy trench 100 in the width direction, and the other side surface formed on approximately the same plane as the other side surface of the first dummy trench 100 in the width direction.

[0228] The side surface of the second electric field relaxation layer 103 extends in the depth direction of the first dummy trench structure 92 and forms a boundary surface with the semiconductor layer 7 (drift region 8). The second electric field relaxation layer 103 is physically separated from the body region 40 in the depth direction of the first dummy trench structure 92 and forms the entire bottom surface of the first dummy trench structure 92.

[0229] 19 , in this embodiment, the second electric field reduction layer 103 has a stacked structure of a third layer 104 and a fourth layer 105. The third layer 104 is a layer formed away from the bottom of the first dummy trench 100 toward the second main surface 4. The fourth layer 105 is a layer formed between the third layer 104 and the bottom of the first dummy trench 100. The fourth layer 105 is exposed from the bottom surface of the first dummy trench 100 and is in contact with the first dummy insulating film 101. The fourth layer 105 is sandwiched between the third layer 104 and the bottom of the first dummy trench 100.

[0230] In this embodiment, the fourth layer 105 has a stacked structure of an upper layer 105 a and an upper layer 105 b. The upper layer 105 a is exposed from the bottom of the first dummy trench 100 and is in contact with the first dummy insulating film 101. The upper layer 105 b is in contact with the third layer 104 of the second electric field reduction layer 103.

[0231] For example, the first impurity concentration of the fourth layer 105 is 1×10 １５ cm －３ 1x10 or more １６ cm －３ The second impurity concentration of the upper layer 105a of the fourth layer 105 may have a peak value of 1×10 １９ cm －３ 1x10 or more ２０ cm －３ The second impurity concentration of the upper layer 105b of the fourth layer 105 may have a peak value of 1×10 １６ cm －３ 1x10 or more １７ cm －３ The p-type impurity concentration may have the following peak value:

[0232] The second impurity concentration in the upper layer 105a of the fourth layer 105 and the third impurity concentration in the upper layer 105b of the fourth layer 105 may be the same. That is, the fourth layer 105 may be an impurity region having a single p-type impurity concentration as a peak value.

[0233] The p-type impurity concentrations of the third layer 104 and the fourth layer 105 are preferably adjusted by at least one trivalent element, which may be at least one of boron, aluminum, gallium, and indium.

[0234] The stacked structure of the third layer 104 and the fourth layer 105 is continuous in the depth direction of the first dummy trench 100. In this embodiment, the second electric field reduction layer 103 is formed in a strip shape extending in the depth direction of the first dummy trench 100 so that the stacked structure of the third layer 104 and the fourth layer 105 is continuous throughout the first dummy trench 100 in the depth direction.

[0235] The multiple second electric field relaxation layers 103 overlap the multiple first dummy trench structures 92 in the depth direction of the first dummy trench 100. Specifically, the multiple second electric field relaxation layers 103 overlap the multiple first dummy trench structures 92 in a one-to-one correspondence in the thickness direction of the chip 2. In this embodiment, the multiple second electric field relaxation layers 103 are connected to the bottom surfaces of the corresponding first dummy trench structures 92.

[0236] 19 , second electric field reduction layer 103 has a second relaxation depth DR2 in vertical direction Z. Second relaxation depth DR2 is preferably 1.5 μm or more and 2.5 μm or less. Second relaxation depth DR2 is preferably approximately equal to first relaxation depth DR1 described above.

[0237] Each of the second electric field reduction layers 103 has a second relaxation width WR2 in the arrangement direction. The second relaxation width WR2 may be 0.25 μm or more and 5 μm or less. The second relaxation width WR2 is preferably approximately equal to the first relaxation width WR1.

[0238] 19 , the semiconductor device 1 includes a first high-concentration p-type region 83 in a surface layer portion of the first main surface 3 in a first dummy formation region 81. The first high-concentration p-type region 83 is formed in a region between a plurality of first dummy trench structures 92. The first high-concentration p-type region 83 is formed in a surface layer portion of the body region 40, adjacent to the source region 55 and the first contact region 57 in the second direction Y. The first high-concentration p-type region 83 is connected to the source region 55 and the first contact region 57.

[0239] The impurity concentration of the first high-concentration p-type region 83 is 1×10 １９ cm －３ 1x10 or more ２０ cm －３ The first high-concentration p region 83 may have a p-type impurity concentration of approximately equal to that of the first contact region 57. The first high-concentration p region 83 may have a depth approximately equal to that of the first contact region 57. In this embodiment, the connection wiring layer 130 faces the first high-concentration p region 83 with the first insulating film 131 interposed therebetween. In other words, the first high-concentration p region 83 overlaps with the connection wiring layer 130 (connection wiring structure 35) in plan view.

[0240] 19 , body region 40 includes a third body portion 84 formed directly below first high-concentration p-type region 83. Third body portion 84 is a portion of body region 40 sandwiched between first high-concentration p-type region 83 and drift region 8 in the depth direction of first dummy trench 100. The thickness of third body portion 84 may be the same as second body thickness BT2 ( FIGS. 9 and 10 ).

[0241] In this embodiment, the third body portion 84 is a fourth impurity region. The connection wiring layer 130 faces the third body portion 84 with the first insulating film 131 interposed therebetween. In other words, the third body portion 84 overlaps with the connection wiring layer 130 (connection wiring structure 35) in plan view.

[0242] 19 , the semiconductor device 1 includes a fourth contact region 86 formed in a surface layer portion of the first main surface 3. The fourth contact region 86 connects the first high-concentration p-type region 83 and the second electric field relaxation layer 103. The fourth contact region 86 is formed along the side surfaces of the first dummy trench 100 from the first high-concentration p-type region 83 toward the second main surface 4, and is connected to the second electric field relaxation layer 103. In this embodiment, the fourth contact region 86 is formed from the first high-concentration p-type region 83 exposed from both side surfaces of the surface layer portion of the first main surface 3, along both one side surface and the other side surface of the first mesa portion 96.

[0243] The fourth contact region 86 penetrates the body region 40 and straddles between the body region 40 and the second electric field relaxation layer 103. The fourth contact region 86 forms a boundary with the body region 40 and is connected to the body region 40. The fourth contact region 86 is further connected to the drift region 8 below the body region 40. That is, a pn junction is formed by the fourth contact region 86 and the drift region 8 in the section between the body region 40 and the second electric field relaxation layer 103.

[0244] 19 , the fourth contact region 86 is exposed from the side surface of the first dummy trench 100 and is in contact with the first dummy insulating film 101 at the side surface of the first dummy trench 100. The lower end of the fourth contact region 86 is in contact with the upper layer 105 a of the fourth layer 105 of the second electric field reduction layer 103.

[0245] In this embodiment, the fourth contact region 86 has the same p-type impurity concentration as the upper layer 105a of the fourth layer 105. In this case, the first high-concentration p-type region 83, the fourth contact region 86, and the upper layer 105a of the fourth layer 105 may form an integral p-type impurity region.

[0246] 19 , insulating layer 13 includes a first dummy interlayer insulating layer 122 embedded in a first dummy recess 121 of semiconductor layer 7. First dummy interlayer insulating layer 122 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. First dummy interlayer insulating layer 122 is embedded in first dummy recess 121 throughout the entire depth direction of first dummy trench 100, and is formed in a strip shape extending in the depth direction of first dummy trench 100.

[0247] 19 , the first dummy interlayer insulating layer 122 is embedded in the first dummy recess 121 so that the upper edges of the first dummy trenches 100 are exposed from the first main surface 3. The upper edges of the first dummy trenches 100 may be portions where the side surfaces of the first dummy trenches 100 intersect with the first main surface 3 at the tops of the first dummy trenches 100. In other words, the first dummy interlayer insulating layer 122 does not cover the peripheral portions of the first dummy trenches 100 at the first main surface 3, and is contained within the inner regions of the first dummy trenches 100 in the width direction of the first dummy trenches 100. In this embodiment, the upper surfaces of the first dummy interlayer insulating layer 122 are located closer to the bottom of the first dummy trenches 100 than the first main surface 3 in the depth direction of the first dummy trenches 100. The first dummy interlayer insulating layer 122 is in contact with the first high-concentration p-type region 83 on the side surface of the first dummy recess 121 (the side surface of the first dummy trench 100 ).

[0248] 12 and 13A, etc., as described above, a plurality of second dummy trench structures 93 (only one is shown in FIGS. 12 and 13A, etc.) are formed in the middle of the first dummy trench structure 92. Figures 12 and 13A show the second dummy trench structure 93 according to the first embodiment.

[0249] The first dummy trench structure 92 is divided in the first direction X by second dummy trench structures 93 at multiple intersection positions where the first dummy trench structure 92 intersects with multiple connection wiring structures 35 in a plan view. By being divided in the first direction X, the first dummy trench structure 92 forms multiple first dummy band-shaped structures 94 extending in the first direction X. Two adjacent first dummy band-shaped structures 94 face each other in the first direction X, with one second dummy trench structure 93 sandwiched between them.

[0250] 13A , the second dummy trench structure 93 has a first termination portion 106 and a second termination portion 107. The multiple (e.g., three) second dummy trench structures 93 have a first trench length L1 in the first direction X. The first trench length L1 may be shorter than the length of one first dummy strip structure 94 in the first direction X. The first trench length L1 is wider than the connection width W1 of the connection wiring layer 130. The first termination portion 106 is spaced apart from the connection wiring layer 130 on one side in the first direction X (the second side surface 5B side) in plan view. The second termination portion 107 is spaced apart from the connection wiring layer 130 on the other side in the first direction X (the fourth side surface 5D side) in plan view. In this embodiment, the first trench length L1 is shorter than the length LC of the opposing contact region 57A in the first direction X ( FIG. 14 ). The second trench length L2 is shorter than the length LB (FIG. 14) of the opposing body portion 59A in the first direction X.

[0251] The multiple (e.g., three) second dummy trench structures 93 face each other in the second direction Y. In the second dummy trench structures 93, the first terminations 106 of the multiple second dummy trench structures 93 are aligned in the first direction X. The multiple first terminations 106 are on the same line along the second direction Y. The second terminations 107 of the multiple second dummy trench structures 93 are aligned in the first direction X. The multiple second terminations 107 are on the same line along the second direction Y. The multiple second dummy trench structures 93 have the same length.

[0252] 13A , the second dummy trench structure 93 is disposed between two first dummy strip structures 94 adjacent to each other in the first direction X, with a distance I1 therebetween. The second dummy trench structure 93 is electrically isolated (insulated) from the first dummy trench structure 92.

[0253] 13A and 19, the second dummy trench structure 93 has a trench width WT3 in the second direction Y. The trench width WT3 is preferably less than the thickness T2 (FIG. 2) of the semiconductor layer 7. The trench width WT3 may be 0.1 μm or more and 5 μm or less. The trench width WT3 is preferably approximately equal to the trench width WT2 described above. The trench width WT3 is preferably approximately equal to the trench width WT1 described above.

[0254] The second dummy trench structures 93 are arranged in the second direction Y at intervals of a trench pitch PT3. The trench pitch PT3 is preferably less than the thickness T2 (FIG. 2) of the semiconductor layer 7. The trench pitch PT3 is preferably less than the trench depth DT2 (FIG. 2). The trench pitch PT3 may be 0.1 μm or more and 5 μm or less. The trench pitch PT3 is preferably approximately equal to the trench pitch PT2 described above. The trench pitch PT3 is preferably approximately equal to the trench pitch PT1 described above.

[0255] The interval I1 between the second dummy trench structure 93 and the first dummy strip structure 94 is narrower than the trench pitch PT3. The interval I1 is preferably 0.5 times or more and less than 0.8 times the trench pitch PT3. The interval I1 is narrower than the trench pitch PT2. The interval I1 is preferably 0.5 times or more and less than 0.8 times the trench pitch PT2. The interval I1 is narrower than the trench pitch PT1. The interval I1 is preferably 0.5 times or more and less than 0.8 times the trench pitch PT1.

[0256] 17 , the second dummy trench structure 93 has a trench depth DT3 in the vertical direction Z. The trench depth DT3 is preferably less than the thickness T2 ( FIG. 2 ) of the semiconductor layer 7. The trench depth DT3 may be 0.1 μm or more and 5 μm or less. The trench depth DT3 is preferably approximately equal to the trench depth DT1 described above. The trench depth DT3 is preferably approximately equal to the trench depth DT2 described above.

[0257] 17 , the second dummy trench structure 93 includes a second dummy trench 110, a second dummy insulating film 111, and a second dummy buried body 112. The second dummy trench 110 is formed in the first main surface 3 and defines the inner surface of the second dummy trench structure 93. The bottom surface of the second dummy trench 110 preferably has a portion that extends flat. It is particularly preferable that the flat portion of the bottom surface of the second dummy trench 110 extends approximately parallel to the first main surface 3.

[0258] 13A and 17 , a second mesa portion 109 formed by a part of the semiconductor layer 7 is formed between two adjacent second dummy trench structures 93. In addition, a second mesa portion 109 formed by a part of the semiconductor layer 7 is also formed between the second dummy trench structures 93 and the trench gate structure 11 adjacent to each other in the second direction Y. The width of the second mesa portion 109 in the second direction Y is determined by the trench pitch PT3.

[0259] 17 , the second dummy insulating film 111 covers the inner surface of the second dummy trench 110. The second dummy insulating film 111 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second dummy insulating film 111 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second dummy insulating film 111 includes a silicon oxide film made of an oxide of the chip 2.

[0260] 17 , the second dummy buried body 112 is buried in the second dummy trench 110 and faces the body region 40 with the second dummy insulating film 111 interposed therebetween. The second dummy buried body 112 is made of polysilicon. This polysilicon may be p-type or n-type conductive polysilicon.

[0261] The second dummy buried body 112 is buried up to the middle in the depth direction of the second dummy trench 110. The second dummy buried body 112 has an upper surface located on the second main surface 4 side with respect to the first main surface 3.

[0262] 17 , the semiconductor device 1 includes a third electric field relaxation layer 113 formed in the bottom of the second dummy trench structure 93. More specifically, the third electric field relaxation layer 113 is formed in the bottom of the second dummy trench 110. The third electric field relaxation layer 113 is formed in the bottom of the second dummy trench 110 over the entire depth direction of the second dummy trench 110, and is formed in a strip shape extending in the depth direction of the second dummy trench 110.

[0263] 17 , the third electric field relaxation layer 113 is exposed from the bottom surface of the second dummy trench 110 and is in contact with the second dummy insulating film 111. The third electric field relaxation layer 113 faces the second dummy buried body 112 via the second dummy insulating film 111 in the depth direction of the second dummy trench 110. At the bottom of the second dummy trench 110, the second dummy insulating film 111 is sandwiched between the second dummy buried body 112 and the third electric field relaxation layer 113.

[0264] The third electric field relaxation layer 113 is formed across the width direction of the second dummy trench 110, between one end and the other end of the second dummy trench 110. In this embodiment, the third electric field relaxation layer 113 has, in the depth direction of the second dummy trench 110, one side surface formed on approximately the same plane as one side surface of the second dummy trench 110 in the width direction, and the other side surface formed on approximately the same plane as the other side surface of the second dummy trench 110 in the width direction.

[0265] The side surface of the third electric field relaxation layer 113 extends in the depth direction of the second dummy trench structure 93 and forms a boundary surface with the drift region 8. The third electric field relaxation layer 113 is physically separated from the body region 40 in the depth direction of the second dummy trench structure 93 and forms the entire bottom surface of the second dummy trench structure 93.

[0266] 17 , in this embodiment, the third electric field reduction layer 113 has a stacked structure of a fifth layer 114 and a sixth layer 115. The fifth layer 114 is a layer formed away from the bottom of the second dummy trench 110 toward the second main surface 4. The sixth layer 115 is a layer formed between the fifth layer 114 and the bottom of the second dummy trench 110. The sixth layer 115 is exposed from the bottom surface of the second dummy trench 110 and is in contact with the second dummy insulating film 111. The sixth layer 115 is sandwiched between the fifth layer 114 and the bottom of the second dummy trench 110.

[0267] In this embodiment, the sixth layer 115 has a stacked structure of an upper layer 115 a and an upper layer 115 b. The upper layer 115 a is exposed from the bottom of the second dummy trench 110 and is in contact with the second dummy insulating film 111. The upper layer 115 b is in contact with the fifth layer 114 of the third electric field reduction layer 113.

[0268] For example, the first impurity concentration of the sixth layer 115 is 1×10 １５ cm －３ 1x10 or more １６ cm －３ The second impurity concentration of the upper layer 115a of the sixth layer 115 may have a peak value of 1×10 １９ cm －３ 1x10 or more ２０ cm －３ The second impurity concentration of the upper layer 115b of the sixth layer 115 may have a peak value of 1×10 １６ cm －３ 1x10 or more １７ cm －３ The p-type impurity concentration may have the following peak value:

[0269] The second impurity concentration in the upper layer 115a of the sixth layer 115 and the third impurity concentration in the upper layer 115b of the sixth layer 115 may be the same. That is, the sixth layer 115 may be an impurity region having a single p-type impurity concentration as a peak value.

[0270] The p-type impurity concentrations of the fifth layer 114 and the sixth layer 115 are preferably adjusted by at least one trivalent element, which may be at least one of boron, aluminum, gallium, and indium.

[0271] The stacked structure of the fifth layer 114 and the sixth layer 115 is continuous in the depth direction of the second dummy trench 110. In this embodiment, the third electric field reduction layer 113 is formed in a strip shape extending in the depth direction of the second dummy trench 110 so that the stacked structure of the fifth layer 114 and the sixth layer 115 is continuous throughout the entire second dummy trench 110 in the depth direction.

[0272] The plurality of third electric field relaxation layers 113 overlap the plurality of second dummy trench structures 93 in the depth direction of the second dummy trench 110. Specifically, the plurality of third electric field relaxation layers 113 overlap the plurality of second dummy trench structures 93 in a one-to-one correspondence in the thickness direction of the chip 2. In this embodiment, the plurality of third electric field relaxation layers 113 are connected to the bottom surfaces of the corresponding second dummy trench structures 93.

[0273] 17 , third electric field reduction layer 113 has a third relaxation depth DR3 in vertical direction Z. Third relaxation depth DR3 is preferably 1.5 μm or more and 2.5 μm or less. Third relaxation depth DR3 is preferably approximately equal to second relaxation depth DR2 described above. Third relaxation depth DR3 is preferably approximately equal to first relaxation depth DR1 described above.

[0274] Each of the third electric field relaxation layers 113 has a third relaxation width WR3 in the arrangement direction. The third relaxation width WR3 may be 0.25 μm or more and 5 μm or less. The third relaxation width WR3 is preferably approximately equal to the second relaxation width WR2 described above. The third relaxation width WR3 is preferably approximately equal to the first relaxation width WR1 described above.

[0275] 18 , the fourth contact region 86 connects the first high-concentration p-type region 83 and the third electric field relaxation layer 113. The fourth contact region 86 is formed along the side surfaces of the second dummy trench 110 from the first high-concentration p-type region 83 toward the second main surface 4, and is connected to the third electric field relaxation layer 113. In this embodiment, the fourth contact region 86 is formed from the first high-concentration p-type region 83 exposed from both side surfaces of the surface layer portion of the first main surface 3, along both one side surface and the other side surface of the second mesa portion 109.

[0276] The fourth contact region 86 penetrates the body region 40 and straddles between the body region 40 and the third electric field relaxation layer 113. The fourth contact region 86 forms a boundary with the body region 40 and is connected to the body region 40. The fourth contact region 86 is further connected to the drift region 8 below the body region 40. That is, a pn junction is formed by the fourth contact region 86 and the drift region 8 in the section between the body region 40 and the third electric field relaxation layer 113.

[0277] 18 , the fourth contact region 86 is exposed from the side surface of the second dummy trench 110 and is in contact with the second dummy insulating film 111 at the side surface of the second dummy trench 110. The lower end of the fourth contact region 86 is in contact with the upper layer 115 a of the sixth layer 115 of the third electric field reduction layer 113.

[0278] In this embodiment, the fourth contact region 86 has the same p-type impurity concentration as the upper layer 105a of the fourth layer 105. In this case, the first high-concentration p-type region 83, the fourth contact region 86, and the upper layer 115a of the sixth layer 115 may form an integral p-type impurity region.

[0279] 18 , the insulating layer 13 includes a second dummy interlayer insulating layer 124 embedded in the second dummy recess 123 of the semiconductor layer 7. The second dummy interlayer insulating layer 124 may be referred to as an "interlayer insulating film," an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this embodiment, the second dummy interlayer insulating layer 124 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second dummy interlayer insulating layer 124 is embedded in the second dummy recess 123 throughout the entire depth direction of the second dummy trench 110, and is formed in a strip shape extending in the depth direction of the second dummy trench 110.

[0280] 18 , the second dummy interlayer insulating layer 124 is embedded in the second dummy recess 123 so that the upper edges of the second dummy trenches 110 are exposed from the first main surface 3. The upper edges of the second dummy trenches 110 may be portions where the side surfaces of the second dummy trenches 110 intersect with the first main surface 3 at the tops of the second dummy trenches 110. In other words, the second dummy interlayer insulating layer 124 does not cover the peripheral portions of the second dummy trenches 110 at the first main surface 3, and is contained within the inner regions of the second dummy trenches 110 in the width direction of the second dummy trenches 110. In this embodiment, the upper surfaces of the second dummy interlayer insulating layer 124 are located closer to the bottom of the second dummy trenches 110 than the first main surface 3 in the depth direction of the second dummy trenches 110. The second dummy interlayer insulating layer 124 is in contact with the first high-concentration p-type region 83 on the side surface of the second dummy recess 123 (the side surface of the second dummy trench 110 ).

[0281] 13A , a third mesa portion 108 formed by a part of the semiconductor layer 7 is formed between the first dummy strip structure 94 and the second dummy trench structure 93. The width of the third mesa portion 108 in the first direction X is determined by the interval I1. The width of the third mesa portion 108 in the first direction X (interval I1) is narrower than the width of the second mesa portion 109 in the second direction Y (trench pitch PT3). The width of the third mesa portion 108 in the first direction X (interval I1) is 0.5 to less than 0.8 times the width of the second mesa portion 109 in the second direction Y (trench pitch PT3).

[0282] The third mesa portion 108 electrically and physically separates the first dummy strip structure 94 from the second dummy trench structure 93. The third mesa portion 108 connects adjacent first mesas 96 to each other. The third mesa portions 108 are aligned in the first direction X. The ends of the multiple third mesas 108 on one side in the first direction X are on the same line along the second direction Y. The ends of the multiple third mesas 108 on the other side in the first direction X are on the same line along the second direction Y.

[0283] As described above, in the first dummy trench structure 92, the second electric field relaxation layer 103 is formed at the bottom of the first dummy trench 100. The second electric field relaxation layer 103 relaxes the electric field on the bottom wall of the first dummy trench structure 92, thereby suppressing electric field concentration and improving the breakdown voltage of the first dummy trench structure 92. Therefore, the first dummy trench structure 92 has a high breakdown voltage. In the first dummy formation region 81 (dummy formation region 80), the breakdown voltage is high in the region near the first dummy trench structure 92 and decreases with increasing distance from the first dummy trench structure 92.

[0284] As described above, in the second dummy trench structure 93, the third electric field relaxation layer 113 is formed at the bottom of the second dummy trench 110. The third electric field relaxation layer 113 relaxes the electric field on the bottom wall of the second dummy trench structure 93, thereby suppressing electric field concentration and improving the breakdown voltage of the second dummy trench structure 93. Therefore, the second dummy trench structure 93 has a high breakdown voltage. In the first dummy formation region 81 (dummy formation region 80), the region near the second dummy trench structure 93 has a high breakdown voltage. In the first dummy formation region 81 (dummy formation region 80), the region near the second dummy trench structure 93 has a high breakdown voltage, and the breakdown voltage decreases with increasing distance from the second dummy trench structure 93.

[0285] Consider a configuration in which the first dummy trench structure 92 is divided in the first direction X midway through the first dummy trench structure 92 and no second dummy trench structure 93 is disposed. In this case, the end portions of two first dummy strip structures 94 face each other with a gap between them in the first direction X.

[0286] The first dummy band structures 94 need to be electrically isolated from the connection wiring structure 35 so that the first dummy trench structures 92 do not contribute to the formation of a channel. Therefore, the terminal ends of the two first dummy band structures 94 face each other with a wide gap in the first direction X. In this case, in the first dummy formation region 81 (dummy formation region 80), there is a risk that a region with a significantly reduced breakdown voltage will be formed over a wide area in the region between the first dummy band structures 94 and in the surrounding region.

[0287] In this embodiment, a second dummy trench structure 93 is formed midway through the first dummy trench structure 92, extending parallel to the trench gate structure 11 and electrically isolated from the first dummy trench structure 92. As described above, the second dummy trench structure 93 has a high breakdown voltage. Therefore, it is possible to reduce the region where the breakdown voltage is significantly reduced in the region between the two first dummy strip structures 94 and the region therearound. This makes it possible to reduce the region where the breakdown voltage is significantly reduced in the first dummy formation region 81 (dummy formation region 80).

[0288] As described above, the first dummy trench structure 92 is a floating trench structure. This makes it possible to reduce the capacitance of the first dummy trench structure 92. In other words, it is possible to achieve both a reduction in capacitance of the first dummy trench structure 92 and an improvement in the breakdown voltage of the first dummy formation region 81 (dummy formation region 80).

[0289] The second dummy trench structure 93 according to the first embodiment ( FIG. 13A ) has been described above. Next, a second dummy trench structure 93A according to the second embodiment ( FIG. 13B ) will be described with reference to FIG. 13B . The second dummy trench structure 93A is used in place of the second dummy trench structure 93. There are multiple (for example, three) second dummy trench structures 93A.

[0290] The second dummy trench structure 93A differs from the second dummy trench structure 93 according to the first embodiment ( FIG. 13A ) in that the terminal ends (third terminal end 243, fourth terminal end 244, fifth terminal end 245, and sixth terminal end 246) of the second dummy trench structure 93A are arranged so as to be shifted with respect to the first direction X.

[0291] 13B, similarly to the first embodiment (FIG. 13A), the first dummy trench structure 92 is divided in the first direction X by a second dummy trench structure 93A. The second dummy trench structure 93A is electrically connected to the connecting wiring structure 35.

[0292] The second dummy trench structure 93A includes a long trench structure 241 and a short trench structure 242. The long trench structure 241 has a second trench length L2. The short trench structure 242 has a third trench length L3 that is shorter than the second trench length L2 (L3<L2). The long trench structures 241 and the short trench structures 242 are alternately arranged in the second direction Y. The long trench structures 241 and the short trench structures 242 face each other in the second direction Y.

[0293] The long trench structure 241 has a third termination 243 and a fourth termination 244. The second trench length L2 is shorter than the length of one first dummy strip structure 94 in the first direction X. The second trench length L2 is wider than the connection width W1 of the connection wiring layer 130. The third termination 243 is spaced apart from the connection wiring layer 130 on one side in the first direction X (the second side surface 5B side) in plan view. The fourth termination 244 is spaced apart from the connection wiring layer 130 on the other side in the first direction X (the fourth side surface 5D side) in plan view. In this embodiment, the second trench length L2 is shorter than the length LC of the opposing contact region 57A in the first direction X ( FIG. 14 ). The second trench length L2 is shorter than the length LB of the opposing body portion 59A in the first direction X ( FIG. 14 ).

[0294] The short trench structure 242 has a fifth termination 245 and a sixth termination 246. The third trench length L3 is shorter than the length of one first dummy strip structure 94 in the first direction X. The second trench length L2 is wider than the connection width W1 of the connection wiring layer 130. The fifth termination 245 is spaced apart from the connection wiring layer 130 on one side in the first direction X (the second side surface 5B side) in plan view. The sixth termination 246 is spaced apart from the connection wiring layer 130 on the other side in the first direction X (the fourth side surface 5D side) in plan view. In this embodiment, the third trench length L3 is shorter than the length LC of the opposing contact region 57A in the first direction X ( FIG. 14 ). The third trench length L3 is shorter than the length LB of the opposing body portion 59A in the first direction X ( FIG. 14 ).

[0295] The ratio of the third trench length L3 to the second trench length L2 may be 0.1 or more and 0.8 or less. The ratio of the third trench length L3 to the second trench length L2 may have a value belonging to any one of the ranges of 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, and 0.7 or more and 0.8 or less. The ratio of the third trench length L3 to the second trench length L2 is preferably 0.3 or more and 0.6 or less.

[0296] The third termination 243 of the long trench structure 241 is offset in the first direction X from the fifth termination 245 of the short trench structure 242 adjacent to the long trench structure 241 in the second direction Y. The fourth termination 244 of the long trench structure 241 is offset in the first direction X from the sixth termination 246 of the short trench structure 242 adjacent to the long trench structure 241 in the second direction Y.

[0297] The sixth terminations 246 of the two short trench structures 242 that face each other in the second direction Y with the long trench structure 241 in between are aligned with each other in the first direction X. The sixth terminations 246 of the two short trench structures 242 that face each other in the second direction Y with the long trench structure 241 in between are aligned with each other in the first direction X.

[0298] 13B , the second dummy trench structure 93A is disposed between two first dummy band structures 94 adjacent to each other in the first direction X, with a gap therebetween. Therefore, the second dummy trench structure 93A is electrically isolated (insulated) from the first dummy trench structure 92. The second dummy trench structure 93A is disposed at a gap I3 from the first dummy band structures 94 in the first direction X.

[0299] 13B, the second dummy trench structure 93A has a trench width WT3 in the second direction Y. The second dummy trench structures 93A are arranged in the second direction Y at intervals of a trench pitch PT3.

[0300] The interval I3 is narrower than the trench pitch PT3. The interval I3 is preferably 0.5 to less than 0.8 times the trench pitch PT3. The interval I3 is narrower than the trench pitch PT2. The interval I3 is preferably 0.5 to less than 0.8 times the trench pitch PT2. The interval I3 is narrower than the trench pitch PT1. The interval I3 is preferably 0.5 to less than 0.8 times the trench pitch PT1.

[0301] 13B , a fourth mesa portion 248 formed by a part of the semiconductor layer 7 is formed between the first dummy strip structure 94 and the second dummy trench structure 93A. In this embodiment, the width of the fourth mesa portion 248 in the first direction X is defined by the interval I3. In this embodiment, the multiple fourth mesas 248 are shifted in the first direction X.

[0302] 13B , a fifth mesa portion 249 formed by a part of the semiconductor layer 7 is formed between two second dummy trench structures 93A adjacent to each other in the second direction Y. In addition, a fifth mesa portion 249 formed by a part of the semiconductor layer 7 is also formed between the second dummy trench structures 93A and the trench gate structure 11 adjacent to each other in the second direction Y. The fifth mesa portion 249 extends in a strip shape in the first direction X. The width of the fifth mesa portion 249 in the second direction Y is determined by the trench pitch PT3.

[0303] The width in the first direction X of the fourth mesa portion 248 (spacing I3) is narrower than the width in the second direction Y of the fifth mesa portion 249 (trench pitch PT3). The width in the first direction X of the fourth mesa portion 248 (spacing I3) is 0.5 to less than 0.8 times the width in the second direction Y of the fifth mesa portion 249 (trench pitch PT3).

[0304] The second dummy trench structure 93A has the same structure as the second dummy trench structure 93 except for its length. That is, the second dummy trench structure 93A includes a second dummy trench 110, a second dummy insulating film 111, and a second dummy buried body 112. Referring to FIG. 16B , the connection wiring layer 130 contacts the second dummy buried body 112 of the second dummy trench structure 93A from above. Furthermore, a third electric field relaxation layer 113 ( FIG. 17 ) is formed in the second dummy trench 110 of the second dummy trench structure 93A. Therefore, the second dummy trench structure 93A has a high breakdown voltage. On the first main surface 3, the breakdown voltage is high in a region near the second dummy trench structure 93A, and the breakdown voltage significantly decreases with increasing distance from the second dummy trench structure 93A.

[0305] 13B , there is one long trench structure 241 and two short trench structures 242. The outermost second dummy trench structure 93A (opposite the plurality of trench gate structures 11) is the short trench structure 242. The innermost second dummy trench structure 93A (on the side of the plurality of trench gate structures 11) is the short trench structure 242.

[0306] The number of long trench structures 241 may be two, and the number of short trench structures 242 may be one. In this case, the outermost second dummy trench structure 93A (opposite the plurality of trench gate structures 11) is the long trench structure 241, and the innermost second dummy trench structure 93A (on the side of the plurality of trench gate structures 11) is the long trench structure 241.

[0307] The number of second dummy trench structures 93A may be less than two, or may be four or more.

[0308] The second embodiment ( FIG. 13B ) also achieves the same effects as the first embodiment ( FIGS. 12 and 13A ). That is, a second dummy trench structure 93A is formed midway through the first dummy trench structure 92, extending parallel to the trench gate structure 11 and electrically isolated from the first dummy trench structure 92. As described above, the second dummy trench structure 93A has a high breakdown voltage. Therefore, it is possible to reduce the area where the breakdown voltage is significantly reduced in the area between the two first dummy strip structures 94 and the area surrounding it. This makes it possible to reduce the area where the breakdown voltage is significantly reduced in the first dummy formation region 81 (dummy formation region 80).

[0309] In the first embodiment ( FIGS. 12 and 13A ), if the first terminations 106 and second terminations 107 of the plurality of second dummy trench structures 93 are aligned in the first direction X, a region with significantly reduced breakdown voltage may be generated in a region around the first terminations 106 and second terminations 107 of the second dummy trench structures 93 that does not face the second dummy trench structures 93 or the first dummy band structures 94 in both the first direction X and the second direction Y (for example, region R1 shown in FIG. 13A ).

[0310] Therefore, in the first embodiment (FIGS. 12 and 13A), when improving the breakdown voltage of the first dummy forming region 81 (dummy forming region 80), there are constraints on the layout dimensions, such as the need to set the distance between the first dummy strip structure 94 extremely narrow.

[0311] In contrast, in the second embodiment ( FIG. 13B ), the terminations (third termination 243, fourth termination 244, fifth termination 245, and sixth termination 246) of the multiple second dummy trench structures 93A are arranged with a shift in the first direction X. Therefore, even if the width (interval I3) of the fourth mesa portion 248 in the first direction X is not set to be extremely narrow, the above-described region with significantly reduced breakdown voltage is not formed. This makes it possible to reduce the region with significantly reduced breakdown voltage in the first dummy formation region 81 (dummy formation region 80) without constraints on layout dimensions.

[0312] Fig. 13C is a plan view illustrating a first dummy structure according to a third embodiment, and corresponds to Fig. 13B. Fig. 13D is a plan view illustrating a first dummy structure according to a fourth embodiment, and corresponds to Fig. 13B. The third and fourth embodiments are both modified versions of the second embodiment (Fig. 13B).

[0313] In this embodiment, the distance in the first direction X between the long trench structure 241 and the first dummy strip structure 94 and the distance in the first direction X between the short trench structure 242 and the first dummy strip structure 94 are both the same distance I3, but may be different.

[0314] In the third embodiment (FIG. 13C), the distance I31 in the first direction X between the long trench structure 241 and the first dummy strip structure 94 is wider than the distance I32 in the first direction X between the short trench structure 242 and the first dummy strip structure 94 (I31>I32).

[0315] In the fourth embodiment (FIG. 13D), the distance I31 in the first direction X between the long trench structure 241 and the first dummy strip structure 94 is narrower than the distance I32 in the first direction X between the short trench structure 242 and the first dummy strip structure 94 (I31<I32).

[0316] 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 11 . FIG. 24 is an enlarged view of a portion surrounded by dashed-dotted line XXIV in FIG. 23 . FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. 12 . FIG. 26 is an enlarged view of a portion surrounded by dashed-dotted line XXVI in FIG. 23 . FIG. 27 is an enlarged view of a portion surrounded by dashed-dotted line XXVII in FIG. 4 . FIG. 28 is an enlarged view of a portion surrounded by dashed-dotted line XXVIII in FIG. 27 . FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 28 . FIG. 30 is a cross-sectional view taken along line XXX-XXX in FIG. 28 . FIG. 31 is an enlarged view of a portion surrounded by dashed-dotted line XXXI in FIG. 27 . FIG. 32 is an enlarged view of a portion surrounded by dashed-dotted line XXXII in FIG. 5 . FIG. 33 is an enlarged view of a portion surrounded by dashed-dotted line XXXIII-XXXIII in FIG. 32 .

[0317] 31 and 33 , the dummy formation region 80 includes a second dummy formation region 82 arranged on the other side in the second direction Y (the third side surface 5C side) of the plurality of trench gate structures 11. The semiconductor device 1 also includes a dummy structure 90. The dummy structure 90 includes a second dummy structure 201 formed in the second dummy formation region 82.

[0318] The second dummy structure 201 includes at least one (plural in this embodiment) first dummy trench structure 92, a plurality of second dummy trench structures 93 ( FIG. 13A ) arranged midway through the first dummy trench structure 92, and two third dummy trench structures 202 arranged at the end portions of the first dummy trench structure 92. Hereinafter, the first dummy trench structure 92 and the second dummy trench structure 93 of the second dummy structure 201 have the same configuration as the first dummy trench structure 92 and the second dummy trench structure 93 ( FIG. 13A ) of the first dummy structure 91, and therefore are denoted by the same reference numerals and description thereof will be omitted.

[0319] 31 shows only the third dummy trench structure 202 on one side in the first direction X (the side of the second side surface 5B) of the two third dummy trench structures 202. The third dummy trench structure 202 faces the end portion of the first dummy trench structure 92. Specifically, the third dummy trench structure 202 is arranged with a distance I2 in the first direction X between it and the first dummy strip structure 94 included in the first dummy trench structure 92. The third dummy trench structure 202 is arranged on the first main surface 3 so as to straddle the active region 9 and the peripheral region 10.

[0320] In this embodiment, the plurality of (e.g., three) third dummy trench structures 202 have a seventh termination 206 and an eighth termination 207. The seventh termination 206 faces the first dummy strip structure 94 in the first direction X in the active region 9. The eighth termination 207 is connected to the second structure 34B and the fourth structure 34D (the second structure 34B in the example of FIG. 31 ) of the peripheral wiring structure 34 in the peripheral region 10.

[0321] The seventh termination portion 206 of the third dummy trench structure 202 is formed with a gap between it and the first dummy strip structure 94. Therefore, the third dummy trench structure 202 is electrically isolated (insulated) from the first dummy trench structure 92. That is, the first dummy trench structure 92 is electrically isolated (insulated) from the second portions 17B, 18B of the gate wiring 16. Also, as described above, the first dummy trench structure 92 is electrically isolated (insulated) from the connection wiring structure 35. By arranging the third dummy trench structure 202 with a gap between it and the termination portion of the first dummy trench structure 92, the first dummy trench structure 92 can be maintained as a floating trench structure to which no potential is applied.

[0322] The plurality of third dummy trench structures 202 have a fourth length L4 in the first direction X. The fourth length L4 is shorter than the length of one first dummy strip structure 94 in the first direction X. In this embodiment, the fourth length L4 may be equal to the first trench length L1 ( FIG. 13A ) of the second dummy trench structure 93. The fourth length L4 may be longer or shorter than the first trench length L1 ( FIG. 13A ). In this embodiment, the third trench length L3 is shorter than the length LC ( FIG. 14 ) of the opposing contact region 57A in the first direction X. The third trench length L3 is shorter than the length LB ( FIG. 14 ) of the opposing body portion 59A in the first direction X.

[0323] The plurality of (e.g., three) third dummy trench structures 202 face each other in the second direction Y. The seventh terminations 206 of the plurality of third dummy trench structures 202 are aligned in the first direction X. The plurality of seventh terminations 206 are on the same line along the second direction Y. The eighth terminations 207 of the plurality of third dummy trench structures 202 are aligned in the first direction X. The plurality of eighth terminations 207 are on the same line along the second direction Y. The lengths of the plurality of third dummy trench structures 202 are the same.

[0324] 31 , the third dummy trench structure 202 has a trench width WT4 in the second direction Y. The trench width WT4 is preferably approximately equal to the aforementioned trench width WT2. The trench width WT4 is preferably approximately equal to the aforementioned trench width WT3.

[0325] The multiple third dummy trench structures 202 are arranged at intervals of a trench pitch PT4 in the second direction Y. The trench pitch PT4 is preferably less than the thickness T2 of the semiconductor layer 7. The trench pitch PT4 is preferably approximately equal to the trench pitch PT3 described above. The trench pitch PT4 is preferably approximately equal to the trench pitch PT2 described above.

[0326] The interval I2 is narrower than the trench pitch PT4. The interval I2 is preferably 0.5 to less than 0.8 times the trench pitch PT4. The interval I2 is narrower than the trench pitch PT2. The interval I2 is preferably 0.5 to less than 0.8 times the trench pitch PT2. The interval I2 is narrower than the trench pitch PT1. The interval I2 is preferably 0.5 to less than 0.8 times the trench pitch PT1.

[0327] 31 , a sixth mesa portion 208 formed by a part of the semiconductor layer 7 is formed between the first dummy strip structure 94 and the third dummy trench structure 202. A seventh mesa portion 209 formed by a part of the semiconductor layer 7 is formed between two third dummy trench structures 202 adjacent to each other in the second direction Y.

[0328] The sixth mesa portion 208 electrically and physically separates the first dummy strip structure 94 from the third dummy trench structure 202. The sixth mesa portion 208 connects adjacent seventh mesa portions 209 to each other. The sixth mesa portions 208 are aligned in the first direction X. The ends of the plurality of sixth mesa portions 208 on one side in the first direction X are on the same line along the second direction Y. The ends of the plurality of sixth mesa portions 208 on the other side in the first direction X are on the same line along the second direction Y.

[0329] The third dummy trench structure 202 has the same structure as the second dummy trench structure 93 except for its length. That is, the third dummy trench structure 202 includes a dummy trench (corresponding to the second dummy trench 110 ( FIG. 17 )), a dummy insulating film (corresponding to the second dummy insulating film 111 ( FIG. 17 )), and a dummy buried body (corresponding to the second dummy buried body 112 ( FIG. 17 )). Therefore, a detailed description of the third dummy trench structure 202 will be omitted.

[0330] The semiconductor device 1 includes a fourth electric field relaxation layer formed at the bottom of the third dummy trench structure 202. The fourth electric field relaxation layer has a configuration equivalent to that of the third electric field relaxation layer 113 ( FIG. 17 ). The fourth electric field relaxation layer is formed at the bottom of the dummy trench over the entire depth direction of the bottom of the dummy trench of the third dummy trench structure 202, and is formed in a strip shape extending in the depth direction of the dummy trench. The fourth electric field relaxation layer relaxes the electric field with respect to the bottom wall of the third dummy trench structure 202, thereby suppressing electric field concentration and improving the breakdown voltage of the third dummy trench structure 202.

[0331] The second dummy structure 201 may include the second dummy trench structure 93A ( FIG. 13B ) of the second embodiment instead of the second dummy trench structure 93 ( FIG. 13A ) of the first embodiment. In this case, in this embodiment, the fourth length L4 may be equal to the third length L3 ( FIG. 13B ) of the short trench structure 242 of the second dummy trench structure 93A. The fourth length L4 may be longer than the third length L3 ( FIG. 13B ) or shorter than the third length L3 ( FIG. 13B ).

[0332] 11 , 23 , 27 , 32 , etc., semiconductor device 1 includes a p-type outer body region 170 formed in a surface layer portion of first main surface 3 in peripheral region 10. Outer body region 170 has a density of 1×10 １５ cm －３ 1x10 or more １８ cm －３The outer body region 170 may have a peak p-type impurity concentration of the following: The outer body region 170 preferably has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 40. Of course, the p-type impurity concentration of the outer body region 170 may be less than the p-type impurity concentration of the body region 40, or may be higher than the p-type impurity concentration of the body region 40.

[0333] The outer body region 170 is formed in a band shape and is spaced from the periphery (first to fourth side faces 5A to 5D) of the first main surface 3 toward the active region 9. In this embodiment, the outer body region 170 surrounds the active region 9 in a plan view and is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. In other words, the outer body region 170 includes a region that forms the boundary between the active region 9 and the outer peripheral region 10.

[0334] The outer body region 170 has an inner edge portion on the active region 9 side and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer body region 170 is connected to the plurality of body regions 40 in a portion extending in the first direction X. In this way, the outer body region 170 is electrically connected to the plurality of body regions 40.

[0335] The outer body region 170 is formed in a surface layer portion of the first main surface 3. The outer body region 170 is formed at a distance from the bottom of the semiconductor layer 7 toward the first main surface 3, and faces the base layer 6 across a part of the semiconductor layer 7. The outer body region 170 is preferably formed at a distance from the middle of the semiconductor layer 7 toward the first main surface 3.

[0336] 11 , 27 , 32 , etc., semiconductor device 1 includes a p-type termination region 175 formed on first main surface 3 in peripheral region 10. Termination region 175 may also be referred to as a “well region,” “termination well region,” etc. Termination region 175 may have a p-type impurity concentration different from the p-type impurity concentration of outer body region 170. The p-type impurity concentration of termination region 175 may be higher than the p-type impurity concentration of outer body region 170. The p-type impurity concentration of termination region 175 may also be lower than the p-type impurity concentration of outer body region 170. Of course, the p-type impurity concentration of termination region 175 may be approximately equal to the p-type impurity concentration of outer body region 170.

[0337] In this embodiment, the termination region 175 surrounds the outer body region 170 in a plan view and is defined as a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. As shown in Fig. 27 , in this embodiment, the termination region 175 has an arc corner portion 175A that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view.

[0338] Termination region 175 is formed at a distance from the bottom of semiconductor layer 7 toward first main surface 3, and faces base layer 6 across a part of semiconductor layer 7. Termination region 175 is preferably formed at a distance from the middle of semiconductor layer 7 toward first main surface 3. Termination region 175 may have a thickness (depth) approximately equal to the thickness (depth) of outer body region 170.

[0339] 27 , termination region 175 is formed in a region between the periphery of first main surface 3 and outer body region 170, spaced inward from the periphery (first to fourth side surfaces 5A to 5D) of first main surface 3. Termination region 175 extends in a band-like shape along outer body region 170 in a plan view. Termination region 175 has a portion that extends in a band-like shape in first direction X and a portion that extends in a band-like shape in second direction Y in a plan view, and defines active region 9 from multiple directions.

[0340] 11 , 27 , 32 , etc., termination region 175 has an inner edge portion on the active region 9 side and an outer edge portion on the peripheral side of first main surface 3. The inner edge portion of termination region 175 is connected to the outer edge portion of outer body region 170. This electrically connects termination region 175 to outer body region 170. That is, in this embodiment, termination region 175 is electrically connected to multiple body regions 40 via outer body region 170. In this embodiment, the inner edge portion of termination region 175 is connected to the outer edge portion of outer body region 170 along the entire periphery.

[0341] 11 , 27 , 32 , etc., termination region 175 (inner edge portion) has overlap region 176 that overlaps the outer edge portion of outer body region 170. Overlap region 176 is a high-concentration region that includes the outer edge portion of outer body region 170 and the inner edge portion of termination region 175. In other words, overlap region 176 includes both the p-type impurities of outer body region 170 and the p-type impurities of termination region 175, and has a p-type impurity concentration that is higher than both the p-type impurity concentration of outer body region 170 and the p-type impurity concentration of termination region 175.

[0342] The overlap region 176 extends in a band-like shape along the outer body region 170 in a plan view. The overlap region 176 has a portion that extends in a band-like shape in the first direction X and a portion that extends in a band-like shape in the second direction Y in a plan view. In this embodiment, the overlap region 176 is defined in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 (the first to fourth side surfaces 5A to 5D).

[0343] The semiconductor device 1 may have a relatively high-concentration p-type well region (176) instead of the overlap region 176. In this case, the well region (176) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer body region 170 and the p-type impurity concentration of the termination region 175. The p-type impurity concentration of the well region (176) is higher than the p-type impurity concentration of the body region 40.

[0344] 24 to 26 , 29 , 30 , etc., semiconductor device 1 includes, in peripheral region 10, second high-concentration p region 177 formed in a surface layer portion of first main surface 3. In this embodiment, second high-concentration p region 177 is formed in first main surface 3. Second high-concentration p region 177 is formed in peripheral region 10 to straddle a surface layer portion of outer body region 170 and a surface layer portion of termination region 175.

[0345] The second high-concentration p-region 177 is formed adjacent to the first high-concentration p-region 83 in the second direction Y in the surface layer portion of the boundary between the body region 40 and the outer body region 170. The second high-concentration p-region 177 is connected to the first high-concentration p-region 83. The impurity concentration of the second high-concentration p-region 177 is 1×10 １９ cm －３ 1x10 or more ２０ cm －３ The second heavily doped p-type region 177 may have a p-type impurity concentration at a peak value equal to or less than the concentration of the first heavily doped p-type region 83. ... depth at a peak value equal to or less than the depth of the first heavily doped p-type region 83.

[0346] The semiconductor device 1 includes, in the peripheral region 10, a third high-concentration p-region 178 formed in a surface layer portion of the first main surface 3. The third high-concentration p-region 178 is embedded in the peripheral region 10 between the outer body region 170 and the termination region 175 and between the drift region 8 and the third high-concentration p-region 178. The third high-concentration p-region 178 extends in a layered form along the first main surface 3. The third high-concentration p-region 178 is connected to the outer body region 170, the termination region 175, and the drift region 8.

[0347] The third high concentration p-region 178 is 1×10 １９ cm －３ 1x10 or more ２０ cm －３The third heavily doped p-type region 178 may have a p-type impurity concentration at a peak value equal to or less than the value specified above. The third heavily doped p-type region 178 may have a p-type impurity concentration substantially equal to that of the first heavily doped p-type region 83. The third heavily doped p-type region 178 may have a p-type impurity concentration substantially equal to that of the second heavily doped p-type region 177. The depletion layer extending from the third heavily doped p-type region 178 can improve the breakdown voltage (for example, breakdown voltage).

[0348] 17 and 18 , third high-concentration p-type region 178 is formed not only in peripheral region 10 but also in part of active region 9. Specifically, third high-concentration p-type region 178 is formed in first dummy formation region 81 of active region 9.

[0349] As described above, the semiconductor device 1 includes a ring-shaped (specifically, a substantially square ring-shaped) peripheral wiring structure 34 along the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. For clarity, the formation region of the peripheral wiring structure 34 is indicated by hatching in Figures 11, 28, 32, etc.

[0350] 24, 29, etc., the peripheral wiring structure 34 includes a peripheral wiring layer 195 arranged on the first main surface 3. The peripheral wiring layer 195 is arranged on the outer periphery region 10. The peripheral wiring layer 195 is not arranged on the active region 9.

[0351] In this embodiment, the peripheral wiring layer 195 is a part of the polysilicon wiring layer 33. When a polysilicon film is formed by CVD to fill the trench 41 and cover the first main surface 3, a part of the polysilicon film can be used to form the polysilicon wiring layer 33 ( FIG. 4 ), thereby forming the peripheral wiring layer 195.

[0352] This allows the peripheral wiring structure 34 (peripheral wiring layer 195) to be manufactured in the same process as the trench gate structure 11. Therefore, the number of manufacturing steps can be reduced compared to when the peripheral wiring structure 34 is formed from a material different from that of the trench gate structure 11. Furthermore, when the peripheral wiring structure 34 is formed from polysilicon, manufacturing efficiency can be improved compared to when it is formed from other materials.

[0353] In this embodiment, the peripheral wiring structure 34 includes a peripheral wiring layer 195 formed on the first main surface 3, and does not employ a trench structure. When the peripheral wiring structure 34 is realized by the peripheral wiring layer 195, it can be easily formed by depositing and patterning a material film. This allows the peripheral wiring structure 34 to be created more efficiently than when the peripheral wiring structure 34 is realized by a trench structure.

[0354] 24, 29, etc., the peripheral wiring layer 195 is disposed on a second insulating film 179 that selectively covers the first main surface 3. The second insulating film 179 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second insulating film 179 may also be referred to as a main surface insulating film.

[0355] Referring to FIG. 4, the peripheral wiring structure 34 (i.e., the peripheral wiring layer 195) has approximately the same thickness at each location of the peripheral wiring structure 34 (first structure 34A, second structure 34B, third structure 34C, fourth structure 34D, fifth structure 34E, and sixth structure 34F).

[0356] In other words, the first structure 34A, the second structure 34B, the third structure 34C, the fourth structure 34D, the fifth structure 34E, and the sixth structure 34F have the same thickness. The height positions of the top surfaces of the first structure 34A, the second structure 34B, the third structure 34C, the fourth structure 34D, the fifth structure 34E, and the sixth structure 34F are the same. The depth positions of the bottoms of the first structure 34A, the second structure 34B, the third structure 34C, the fourth structure 34D, the fifth structure 34E, and the sixth structure 34F are the same.

[0357] 24, 29, etc., the peripheral thickness TA of the peripheral wiring layer 195 may be equal to or greater than the thickness of the buried body 43 of the trench gate structure 11. The peripheral thickness TA may be equal to or greater than the trench depth DT1 (FIG. 9) of the trench 41 of the trench gate structure 11. The peripheral thickness TA may be less than the trench depth DT1. The peripheral thickness TA of the peripheral wiring layer 195 may be equal to the connection thickness T3 (FIG. 24) of the connection wiring layer 130. The peripheral thickness TA of the peripheral wiring layer 195 may be equal to or greater than 2 μm and equal to or less than 10 μm.

[0358] Referring to Figures 11, 28 and 32, the peripheral wiring layer 195 (peripheral wiring structure 34) is formed at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 9, and extends in a strip shape along the active region 9.

[0359] 11 , the first structure 34A as an example of the second structure portion extends in a strip shape in the first direction X on one side in the second direction Y (the first side surface 5A side) of the active region 9. The first structure 34A faces the outer body region 170 with a second insulating film 179 ( FIG. 24 , etc.) sandwiched therebetween. The first structure 34A does not face the termination region 175.

[0360] 11 , the first structure 34A overlaps with the first portion 17A of the first gate wiring 17 and the first portion 18A of the second gate wiring 18 in a plan view (only the first portion 17A is shown in FIG. 11 ). The inner periphery of the first structure 34A is located closer to the active region 9 than the inner peripheries of the first portion 17A and the first portion 18A. The outer periphery of the first structure 34A is located closer to the periphery of the first main surface 3 than the outer peripheries of the first portion 17A and the first portion 18A.

[0361] The first wiring width WW1 of the first structure 34A is wider than the wiring width of the gate wiring 16 (first portion 17A and first portion 18A). The first wiring width WW1 is wider than the wiring width of the source wiring 23. The first wiring width WW1 may be 10 μm or more and 100 μm or less.

[0362] 27 and 28 , the second structure 34B as an example of a first wiring portion extends in a band shape in the second direction Y on one side in the first direction X (the second side surface 5B side) of the active region 9. The second structure 34B overlaps with the second portion 17B of the first gate wiring 17 in a plan view. That is, the second structure 34B is formed below the second portion 17B of the first gate wiring 17. The second structure 34B faces the outer body region 170 with a second insulating film 179 ( FIG. 29 ) interposed therebetween. The second structure 34B does not face the termination region 175.

[0363] The inner periphery of the second structure 34B is located closer to the active region 9 than the inner periphery of the second portion 17B of the first gate wiring 17. The outer periphery of the second structure 34B is located closer to the periphery of the first main surface 3 than the outer periphery of the second portion 17B of the first gate wiring 17. The second wiring width (first width) WW2 of the second structure 34B is wider than the wiring width of the gate wiring 16 (the second portion 17B of the first gate wiring 17).

[0364] The second wiring width WW2 is wider than the wiring width of the source wiring 23. In this embodiment, the second wiring width WW2 of the second structure 34B is substantially equal to the first wiring width WW1. The second wiring width WW2 may be wider than the first wiring width WW1 or narrower than the first wiring width WW1. The second wiring width WW2 may be 10 μm or more and 100 μm or less.

[0365] 31 and other figures, the second structure 34B of the peripheral wiring structure 34 covers the termination 11A of the trench gate structure 11 and the eighth termination 207 of the third dummy trench structure 202 in the peripheral region 10 of the first main surface 3. In this way, the second structure 34B is electrically connected to the trench gate structure 11 and the third dummy trench structure 202.

[0366] 29 and 30 , the second structure 34B of the peripheral wiring structure 34 includes a connection wiring portion 194 that connects to the buried bodies 43 at the end portions of the plurality of trench gate structures 11. The connection wiring portion 194 extends in the vertical direction Z and connects the inner periphery of the peripheral wiring layer 195 to the buried bodies 43 at the end portions of the plurality of trench gate structures 11.

[0367] 27 , a third structure 34C as an example of a second wiring portion extends in a strip shape in the first direction X on the other side in the second direction Y (the third side surface 5C side) of the active region 9. Both end portions of the third structure 34C are connected to the second structure 34B and the fourth structure 34D, respectively (only the second structure 34B is shown in FIG. 27 ).

[0368] The third structure 34C extends along the third side surface 5C in plan view from the end of the second structure 34B on the third side surface 5C side. In other words, the third structure 34C extends along the third side surface 5C in plan view from the terminal end 18D ( FIG. 3 ) of the second portion 18B of the second gate wiring 18.

[0369] 32, third structure 34C faces outer body region 170 with second insulating film 179 (FIG. 29) interposed therebetween. Third structure 34C does not face termination region 175.

[0370] 31 , in this embodiment, the third wiring width (second width) WW3 of the third structure 34C is narrower than the first wiring width WW1 ( FIG. 11 ) (WW3<WW1). The third wiring width WW3 is narrower than the second wiring width WW2 (WW3<WW2). The third wiring width WW3 is narrower than the wiring width W17 of the second portion 17B of the first gate wiring 17 ( FIG. 28 ) and the wiring width W18 of the second portion 18B of the second gate wiring 18 ( FIG. 3 ). The third wiring width WW3 may be approximately equal to the wiring widths W17 and W18 of the second portion 18B, or may be wider than the wiring widths W17 and W18 of the second portion 18B. The third wiring width WW3 is narrower than the wiring width of the source wiring 23.

[0371] The third wiring width WW3 may be 0.1 to 0.8 times the second wiring width WW2. The third wiring width WW3 may have a value that belongs to any one of the following ranges of 0.1 to 0.2 times, 0.2 to 0.3 times, 0.3 to 0.4 times, 0.4 to 0.5 times, 0.5 to 0.6 times, or 0.6 to 0.8 times the second wiring width WW2 (fourth wiring width WW4). The third wiring width WW3 is preferably 0.3 to 0.6 times the second wiring width WW2.

[0372] Although not shown, the fourth structure 34D ( FIG. 4 ) of the peripheral wiring structure 34 covers the termination 11A of the trench gate structure 11 and the eighth termination 207 of the third dummy trench structure 202 in the peripheral region 10 of the first main surface 3. In this way, the fourth structure 34D is electrically connected to the trench gate structure 11 and the third dummy trench structure 202.

[0373] 4, the fourth structure 34D as an example of a first wiring portion extends in a strip shape in the second direction Y on the other side in the first direction X (the fourth side surface 5D side) with respect to the active region 9. Although not shown, the fourth structure 34D overlaps with the second portion 18B ( FIG. 3 ) of the second gate wiring 18 in a plan view.

[0374] The fourth structure 34D and the second structure 34B have a shape that is symmetrical with respect to a center line (not shown) that extends in the second direction Y and passes through the center of the active region 9. Therefore, detailed illustrations of the fourth structure 34D will be omitted, and the description of the second structure 34B will be used.

[0375] Just to be sure, the structure of the fourth structure 34D will be described. Referring to FIG. 4, the fourth structure 34D is formed below the second portion 18B (FIG. 3) of the second gate wiring 18. The fourth structure 34D faces the outer body region 170 with the second insulating film 179 (FIG. 29) interposed therebetween. The fourth structure 34D does not face the termination region 175 (FIG. 28).

[0376] 4, the inner periphery of the fourth structure 34D is located closer to the active region 9 than the inner periphery of the second portion 18B (FIG. 3) of the second gate wiring 18. The outer periphery of the fourth structure 34D is located closer to the periphery of the first main surface 3 than the outer periphery of the second portion 18B of the second gate wiring 18. The fourth wiring width WW4 of the fourth structure 34D is wider than the wiring width W18 (FIG. 3) of the gate wiring 16 (second portion 18B of the second gate wiring 18).

[0377] Referring to FIG. 4, the fourth wiring width (first width) WW4 is wider than the wiring width of the source wiring 23. In this embodiment, the fourth wiring width WW4 is wider than the third wiring width WW3 (FIG. 31) (WW4>WW3). The fourth wiring width WW4 is substantially equal to the first wiring width WW1 (FIG. 11) (WW4=WW1). The fourth wiring width WW4 may be wider or narrower than the first wiring width WW1. The fourth wiring width WW4 is substantially equal to the second wiring width WW2 (FIG. 31) (WW4=WW2). The fourth wiring width WW4 may be wider or narrower than the second wiring width WW2. The fourth wiring width WW4 may be 10 μm or more and 100 μm or less.

[0378] 25, 26, etc., the peripheral wiring layer 195 includes an upper wiring layer 181 and a lower wiring layer 182 that are located at different depth positions in the vertical direction Z. The lower wiring layer 182 is disposed on the active region 9 side, and the upper wiring layer 181 is disposed on the edge surface side of the chip 2. The upper wiring layer 181 and the lower wiring layer 182 are flat and extend along the first direction X and the second direction Y. The peripheral wiring layer 195 includes connection wiring that electrically and mechanically connects the upper wiring layer 181 and the lower wiring layer 182. The connection wiring extends in the vertical direction Z and connects the outer periphery of the lower wiring layer 182 with the inner periphery of the upper wiring layer 181.

[0379] As described above, in the peripheral region 10, the second insulating film 179 is arranged below the peripheral wiring layer 195. The second insulating film 179 includes a thick film 185 arranged below the upper wiring layer 181 and a thin film 186 formed below the lower wiring layer 182. The thin film 186 is thinner than the thick film 185. The thin film 186 may have the same thickness as the first insulating film 131. Referring to FIG. 24 , the thin film 186 is connected to the first insulating film 131 at the boundary between the peripheral region 10 and the active region 9.

[0380] 25, 26, etc., the semiconductor device 1 includes a second silicide layer 184 formed on the surface of a peripheral wiring layer 195. The second silicide layer 184 covers an upper surface 187A, an inner side surface 187B, and an outer side surface 187C ( FIG. 37 ) of the peripheral wiring layer 195. The second silicide layer 184 is a polycide portion formed by silicidizing polysilicon of the peripheral wiring layer 195. The second silicide layer 184 may be referred to as a "second metal semiconductor compound layer," a "second silicide layer (polycide layer)," a "second silicide region (polycide region)," etc.

[0381] The second silicide layer 184 includes a first covering layer covering an upper surface 187A of the peripheral wiring layer 195, a second covering layer covering an inner surface 187B of the peripheral wiring layer 195, and a third covering layer covering an outer surface 187C ( FIG. 37 ) of the peripheral wiring layer 195. The first covering layer of the second silicide layer 184 covers the entire upper surface 187A of the peripheral wiring layer 195. The inner periphery of the first covering layer of the second silicide layer 184 is exposed to the inner surface 187B of the peripheral wiring layer 195.

[0382] The second covering layer of the second silicide layer 184 covers the entire inner surface 187B of the peripheral wiring layer 195. The upper end of the second covering layer of the second silicide layer 184 is exposed at the upper surface 187A of the peripheral wiring layer 195. The third covering layer of the second silicide layer 184 covers the entire outer surface 187C ( FIG. 37 ) of the peripheral wiring layer 195. The upper end of the third covering layer of the second silicide layer 184 is exposed at the upper surface 187A of the peripheral wiring layer 195.

[0383] The second silicide layer 184 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The second silicide layer 184 is preferably made of Ti silicide, Ni silicide, or Co silicide. The thickness of the second silicide layer 184 may be flat and aligned along the surfaces (top surface 187A, inner side surface 187B, and outer side surface 187C) of the peripheral wiring layer 195.

[0384] As described above, the semiconductor device 1 includes an insulating layer 13. Referring to FIGS. 24, 29, etc., the insulating layer 13 includes a third interlayer insulating layer 180 that covers the peripheral region 10. The third interlayer insulating layer 180 may be referred to as an "insulating film," an "interlayer film," an "intermediate insulating film," etc. The third interlayer insulating layer 180 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The third interlayer insulating layer 180 may have a stacked structure. The third interlayer insulating layer 180 may have a single-layer structure.

[0385] 24, 29, etc., third interlayer insulating layer 180 covers the upper, inner, and outer sides of peripheral wiring layer 195. That is, third interlayer insulating layer 180 covers upper surface 187A and inner side surface 187B of peripheral wiring layer 195 via second silicide layer 184. Although not shown, third interlayer insulating layer 180 collectively covers outer body region 170, termination region 175, and multiple field regions 36 in peripheral region 10.

[0386] The semiconductor device 1 includes at least one (a plurality of, in this embodiment) gate openings 188 formed in the third interlayer insulating layer 180 in the peripheral region 10. With reference to Figures 23, 26, etc., the plurality of gate openings 188 are formed in portions of the third interlayer insulating layer 180 that cover the peripheral wiring layer 195. The plurality of gate openings 188 penetrate the third interlayer insulating layer 180 and expose an upper surface 187A of the peripheral wiring layer 195 via the second silicide layer 184.

[0387] 11 and 28 , the plurality of gate openings 188 are formed at intervals along the peripheral wiring structure 34 (peripheral wiring layer 195). The plurality of gate openings 188 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view. The plurality of gate openings 188 may be formed in a strip shape extending along the peripheral wiring structure 34 in a plan view. The semiconductor device 1 may have a single gate opening 188. The single gate opening 188 may be formed in a strip shape extending along the peripheral wiring structure 34.

[0388] 11 and 28 , semiconductor device 1 includes at least one outer opening 190 (a plurality of outer openings in this embodiment) formed in third interlayer insulating layer 180 in peripheral region 10. The plurality of outer openings 190 are formed in a portion of third interlayer insulating layer 180 that covers termination region 175. The plurality of outer openings 190 penetrate third interlayer insulating layer 180 to expose termination region 175. In this embodiment, the plurality of outer openings 190 are formed in a portion of third interlayer insulating layer 180 that covers overlap region 176 of termination region 175, exposing overlap region 176. The plurality of outer openings 190 may expose outer body region 170 instead of or in addition to termination region 175 (overlap region 176).

[0389] 11 and 28 , the outer openings 190 are spaced apart along the terminal region 175 (overlap region 176). The outer openings 190 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in plan view. The outer openings 190 may be formed in a band shape extending along the terminal region 175 (overlap region 176) in plan view.

[0390] The semiconductor device 1 may have a single outer opening 190. The single outer opening 190 may be formed in a strip shape extending along the termination region 175 (overlap region 176). The single outer opening 190 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0391] The gate wiring 16 is selectively routed over the third interlayer insulating layer 180 and transmits a gate potential to the peripheral wiring structure 34. The gate wiring 16 is routed over a portion of the third interlayer insulating layer 180 that covers the peripheral wiring structure 34 (i.e., over the outer periphery region 10), and is electrically connected to the peripheral wiring structure 34 (peripheral wiring layer 195) through a plurality of gate openings 188.

[0392] The gate wiring 16 is formed on the first main surface 3 so as to cover the third interlayer insulating layer 180. With reference to Fig. 26, the gate wiring 16 has a laminated structure including a barrier layer 196 and a main body layer 197 laminated in this order from the first main surface 3 side.

[0393] The barrier layer 196 is formed in a film shape along the first main surface 3. The barrier layer 196 is in contact with the second high-concentration p-region 177. The barrier layer 196 may include at least one of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer. The thickness of the barrier layer 196 may be 0.05 μm or more and 0.3 μm or less. The thickness of the barrier layer 196 is preferably 0.1 μm or more and 0.2 μm or less.

[0394] 26 , main body layer 197 is formed on barrier layer 196. Main body layer 197 covers the entire main surface of barrier layer 196. The thickness of main body layer 197 exceeds the thickness of barrier layer 196. The thickness of barrier layer 196 may be 1 μm or more and 10 μm or less. The thickness of main body layer 197 is preferably 3 μm or more and 6 μm or less.

[0395] 26 , the gate wiring 16 (first gate wiring 17, second gate wiring 18) is disposed to face the peripheral wiring layer 195 with the third interlayer insulating layer 180 interposed therebetween, and extends in a strip shape along the peripheral wiring layer 195. The gate wiring 16 (first gate wiring 17, second gate wiring 18) collectively covers, in a film-like manner, the region of the third interlayer insulating layer 180 where the plurality of gate openings 188 are formed.

[0396] 26 , the gate wiring 16 includes a plurality of first connection electrode portions 191 that enter the plurality of gate openings 188 and are connected to the peripheral wiring layer 195. The plurality of first connection electrode portions 191 correspond one-to-one to the plurality of gate openings 188. The first connection electrode portions 191 have portions that cover the second silicide layer 184 of the peripheral wiring layer 195 in a film-like manner at the bottom of each gate opening 188, and are mechanically and electrically connected to the second silicide layer 184.

[0397] In this embodiment, the plurality of first connection electrode portions 191 are formed in the first structure 34A, the second structure 34B, the fourth structure 34D, and the fifth structure 34E (FIG. 35) of the peripheral wiring structure 34.

[0398] As described above, the semiconductor device 1 includes the source wiring 23. The source wiring 23 is drawn out onto the third interlayer insulating layer 180 up to above the termination region 175 and is electrically connected to the termination region 175 through a plurality of outer openings 190. The source wiring 23 transmits the source potential applied to the source pad 20 to the termination region 175. The source wiring 23 extends in a strip shape along the termination region 175 (overlap region 176).

[0399] 23 , the source wiring 23 has a plurality of second connection electrode portions 192 that enter the plurality of outer openings 190. The plurality of second connection electrode portions 192 correspond one-to-one to the plurality of outer openings 190. The second connection electrode portions 192 cover the first main surface 3 in the form of a film at the bottom of the outer opening 190, and are electrically connected to the first main surface 3 (chip 2).

[0400] 11 and 28, the second connection electrode portion 192 is electrically connected to the termination region 175 (overlapping region 176 ) at the bottom of the outer opening 190 .

[0401] 27 , in this embodiment, the first gate wiring 17 and the second gate wiring 18 have terminations 17D, 18D at the corner C of the chip 2. Therefore, the first gate wiring 17 and the second gate wiring 18 do not have portions that extend along the third side surface 5C from the terminations 17D, 18D of the second portions 17B, 18B. If a portion extending along the third side surface 5C is to be provided, the first gate wiring 17 and the second gate wiring 18 need to be bent at the corner C of the chip 2.

[0402] There is a difference in the coefficient of linear expansion between the first gate wiring 17 and the second gate wiring 18 made of metal wiring and the insulating film such as the upper insulating film 25. If the bent portions of the first gate wiring 17 and the second gate wiring 18 are located at the corners C of the chip 2, the insulating film may be damaged due to the difference in the amount of deformation between the bent portions and the insulating film.

[0403] In contrast, in this embodiment, there is no need to bend the first gate wiring 17 and the second gate wiring 18 at the corner C of the chip 2, so that the occurrence of such a problem can be avoided.

[0404] In this embodiment, the terminal ends 17D, 18D of the gate wiring 16 (first gate wiring 17 and second gate wiring 18) are not disposed in the region between the periphery of the active region 9 on the third side face 5C side and the third side face 5C of the chip 2. More specifically, referring to Fig. 27, the terminal ends 17D, 18D of the gate wiring 16 (first gate wiring 17 and second gate wiring 18) are retracted to the first side face 5A side (opposite the third side face 5C (second end face) side) at the corner C of the chip 2 so as not to face the arc corner portion 45A in the first direction X in plan view.

[0405] Therefore, the periphery of the active region 9 on the third side surface 5C side can be positioned closer to the third side surface 5C, thereby increasing the area ratio of the active region 9 to the entire chip 2. The surface of the chip 2 can be effectively utilized, and loss can be improved.

[0406] In this embodiment, as described above, the third wiring width WW3 is narrower than the first wiring width WW1, the second wiring width WW2, and the fourth wiring width WW4 (WW3<WW1, WW3<WW2, WW3<WW4). Therefore, the periphery of the active region 9 on the third side surface 5C side can be positioned even closer to the third side surface 5C. This makes it possible to more effectively increase the area ratio of the active region 9 to the entire first main surface 3.

[0407] Figure 34 is an enlarged view of a portion surrounded by dashed dotted line XXXIV in Figure 4. Figure 35 is an enlarged view of a portion surrounded by dashed dotted line XXXV in Figure 34. Figure 36 is a cross-sectional view taken along line XXXVI-XXXVI in Figure 35. Figure 37 is a cross-sectional view taken along line XXXVII-XXXVII in Figure 35. Figure 38 is a cross-sectional view taken along line XXXVIII-XXXVIII in Figure 35. Figure 39A is a plan view of a second embodiment of the connecting structure portion 216, corresponding to Figure 35. Figure 39B is a plan view of a third embodiment of the connecting structure portion 216, corresponding to Figure 35.

[0408] As described above, the peripheral wiring structure 34 includes the fifth structure 34E and the sixth structure 34F that are arranged in the region surrounding the gate pad 15 in the outer periphery region 10. For clarity, the formation region of the peripheral wiring structure 34 is shown hatched in Figures 34 and 35.

[0409] 34 , a fifth structure 34E as an example of a second structure portion is a pair of structures. The fifth structure 34E is formed in a strip shape extending in the second direction Y from the first structure 34A toward the third side surface 5C. The fifth structure 34E sandwiches the active region 9 in the first direction X between the second structure 34B and the fourth structure 34D.

[0410] 34 , the fifth structure 34E on one side in the first direction X (the second side surface 5B side) overlaps in plan view with a strip portion 17F of the connection portion 17C of the first gate wiring 17 that extends along the second direction Y. The fifth structure 34E on the other side in the first direction X (the fourth side surface 5D side) overlaps in plan view with a strip portion 18F of the connection portion 18C of the second gate wiring 18 that extends along the second direction Y.

[0411] The inner periphery of the fifth structure 34E (the periphery on the active region 9 side) is located closer to the active region 9 than the inner peripheries of the strip portions 17F and 18F (the peripheries on the active region 9 side). The outer periphery of the fifth structure 34E (the periphery on the opposite side to the active region 9 side) is located closer to the active region 9 than the outer peripheries of the strip portions 17F and 18F (the peripheries on the opposite side to the active region 9 side). The wiring width of the fifth structure 34E is wider than the wiring width of the gate wiring 16 (strip portions 17F and 18F). The wiring width of the fifth structure 34E is wider than the wiring width of the source wiring 23.

[0412] 35 , the fifth structure 34E of the peripheral wiring structure 34 covers the termination 11A of the trench gate structure 11 and the eighth termination 207 of the third dummy trench structure 202 in the peripheral region 10 of the first main surface 3. In this way, the fifth structure 34E is electrically connected to the trench gate structure 11 and the third dummy trench structure 202.

[0413] 34 , the gate wiring 16 includes a plurality of first connection electrode portions 191 that enter the plurality of gate openings 188 and are connected to the peripheral wiring structure 34 (peripheral wiring layer 195). In other words, the peripheral wiring structure 34 has contact portions (third contact portions) 193 that are electrically connected to the first structure portion 215. The contact portions (third contact portions) 193 are formed in the first structure 34A, the second structure 34B, the fourth structure 34D, and the fifth structure 34E of the peripheral wiring structure 34.

[0414] 34 , the sixth structure 34F connects inner ends (on the third side surface 5C side) of the pair of fifth structures 34E and is formed in a band shape extending in the first direction X. Referring to Fig. 34 , the sixth structure 34F overlaps, in plan view, with a second band-shaped portion 17G of the connection portion 17C of the first gate wiring 17 that extends along the first direction X, and a band-shaped portion 18G of the connection portion 18C of the second gate wiring 18 that extends along the first direction X.

[0415] The inner periphery of the sixth structure 34F (the periphery on the active region 9 side) is located closer to the active region 9 than the inner peripheries of the second strip portion 17G and strip portion 18G (the periphery on the active region 9 side). The outer periphery of the sixth structure 34F (the periphery on the opposite side from the active region 9 side) is located closer to the active region 9 than the outer peripheries of the second strip portion 17G and strip portion 18G. The wiring width of the sixth structure 34F is wider than the wiring width of the gate wiring 16 (strip portion 17F and strip portion 18F). The wiring width of the sixth structure 34F is wider than the wiring width of the source wiring 23.

[0416] 34 and 35 , the semiconductor device 1 includes a resistive wiring structure 38 arranged midway through the first structure 34A of the peripheral wiring structure 34, as described above. In this embodiment, the resistive wiring structure 38 includes a resistive wiring layer 210 arranged on the first main surface 3 in the peripheral region 10. The resistive wiring structure 38 has a strip shape along the first periphery 15A of the gate pad 15 in a plan view. The resistive wiring structure 38 is connected to the first structure 34A of the peripheral wiring structure 34.

[0417] 34 , the resistive wiring layer 210 is in a strip shape along the first periphery 15A of the gate pad 15. The resistive wiring layer 210 is formed across the region below the periphery of the first periphery 15A of the gate pad 15 and the region below the connection wiring 16A. The resistive wiring layer 210 is arranged in the outer periphery region 10. The resistive wiring layer 210 is not arranged in the active region 9.

[0418] The resistive wiring layer 210 includes a conductive semiconductor polycrystalline. In this embodiment, the resistive wiring layer 210 is formed of polysilicon as a first conductive material. This polysilicon may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. This polysilicon is a material with higher resistance than the metal materials used for the gate pad 15, the gate wiring 16, the source pad 20, the source wiring 23, etc.

[0419] In this embodiment, the resistive wiring layer 210 is a part of the polysilicon wiring layer 33 (FIG. 4). When a polysilicon film is formed by CVD to fill the trench 41 and cover the first main surface 3, a part of the polysilicon film can be used to form the polysilicon wiring layer 33, thereby forming the resistive wiring layer 210.

[0420] This allows the resistive wiring structure 38 (resistive wiring layer 210) to be manufactured in the same process as the trench gate structure 11. Therefore, the number of manufacturing steps can be reduced compared to when the resistive wiring structure 38 is formed from a material different from that of the trench gate structure 11. Furthermore, when the resistive wiring structure 38 is formed from polysilicon, manufacturing efficiency can be improved compared to when the resistive wiring structure 38 is formed from other materials.

[0421] In this embodiment, the resistive wiring structure 38 includes a resistive wiring layer 210 formed on the first main surface 3, and does not employ a trench structure. When the resistive wiring structure 38 is realized using the resistive wiring layer 210, it can be easily formed by depositing and patterning a material film. This allows the resistive wiring structure 38 to be created more efficiently than when the resistive wiring structure 38 is realized using a trench structure.

[0422] 34 , the outer periphery of the resistive wiring layer 210 is aligned with the outer periphery of the first structure 34A. The resistive wiring layer 210 is connected to the first structure 34A. The resistive wiring layer 210 is disposed midway through the first structure 34A of the peripheral wiring structure 34, dividing the first structure 34A in the first direction X. In other words, the resistive wiring layer 210 is sandwiched in the first direction X between two portions of the first structure 34A.

[0423] 36 and 38 , the resistive wiring layer 210 is disposed on the second insulating film 179 (thick film 185). The resistive wiring layer 210 faces the outer body region 170 with the second insulating film 179 interposed therebetween. An upper surface 212 of the resistive wiring layer 210 is located at the same depth as the upper surface of the upper wiring layer 181 of the peripheral wiring structure 34. With reference to FIG. 38 , the resistive wiring layer 210 is connected to the peripheral wiring layer 195 of the peripheral wiring structure 34.

[0424] 36 , the semiconductor device 1 includes a third silicide layer 211 formed on the surface of the resistive wiring layer 210. The third silicide layer 211 covers an upper surface 212 and an outer side surface 213 of the resistive wiring layer 210. The third silicide layer 211 is a polycide portion formed by silicidizing polysilicon of the resistive wiring layer 210. The third silicide layer 211 may be referred to as a "third metal semiconductor compound layer," a "third silicide layer (polycide layer)," a "third silicide region (polycide region)," or the like.

[0425] The third silicide layer 211 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The third silicide layer 211 is preferably made of Ti silicide, Ni silicide, or Co silicide. The third silicide layer 211 may be flat and extend along the surfaces (top surface 212 and outer side surface 213) of the resistance wiring layer 210.

[0426] 36 , the resistive wiring layer 210 is covered with a third interlayer insulating layer 180. The third interlayer insulating layer 180 covers not only the peripheral wiring layer 95 but also the upper and side surfaces of the resistive wiring layer 210. In other words, the third interlayer insulating layer 180 covers the upper surface 212 and outer surface 213 of the resistive wiring layer 210 via the third silicide layer 211.

[0427] 34 , the resistive wiring layer 210 includes a first structural portion 215 and two (a pair of) connecting structure portions 216 that sandwich the first structural portion 215 in the first direction X. The first structural portion 215 and the two connecting structure portions 216 are integrally formed. The outer periphery of the first structural portion 215 and the outer periphery of the connecting structure portion 216 are aligned with each other.

[0428] The first structural portion 215 is incorporated into the chip 2 as a resistor electrically connected to the trench gate structure 11. That is, in this configuration, the first structural portion 215, which is part of the polysilicon wiring layer 33, functions as a gate resistor. The first structural portion 215 slows down the switching speed during switching operation to suppress surge currents. That is, the first structural portion 215 suppresses noise caused by surge currents.

[0429] 34 , in this embodiment, the first structural portion 215 is disposed on a portion of the third interlayer insulating layer 180 that covers the outer periphery region 10, and faces the first peripheral edge 15A of the gate pad 15 in the second direction Y in a planar view. In this embodiment, the first structural portion 215 is formed in a strip shape extending in the first direction X in a planar view. The first structural portion 215 has a resistance length L11 in the first direction X. The planar shape of the first structural portion 215 is arbitrary.

[0430] 35 , the first structural portion 215 has a first opposing width IF1 in the direction in which the gate pad 15 and the gate wiring 16 (connection wiring 16A) face each other (i.e., the second direction Y). In this embodiment, the first opposing width IF1 may be wider than the first wiring width WW1.

[0431] 36 , the first structural portion 215 has a resistor thickness TR in the vertical direction Z. The resistor thickness TR is adjusted as appropriate depending on the resistance value to be achieved. That is, the resistance value of the first structural portion 215 is adjusted by increasing or decreasing the resistor thickness TR and the resistor length L11.

[0432] 34 and 36 , the semiconductor device 1 includes at least (a plurality of in this embodiment) first contact openings 217 formed in the third interlayer insulating layer 180 in the peripheral region 10. In this embodiment, the plurality of first contact openings 217 are arranged in a line along the first direction X at intervals from one another. The plurality of first contact openings 217 are formed in portions of the third interlayer insulating layer 180 that cover the first structural portions 215.

[0433] The multiple first contact openings 217 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in plan view. The semiconductor device 1 may have a single first contact opening 217. The single first contact opening 217 may be formed in a strip shape extending in the first direction X along the first structural portion 215 in plan view.

[0434] 36 , the gate pad 15 includes a plurality of third connection electrode portions 218 that penetrate into the plurality of first contact openings 217 and are connected to the first structural portion 215. The plurality of third connection electrode portions 218 correspond one-to-one to the plurality of first contact openings 217. The third connection electrode portion 218 has a portion that covers the third silicide layer 211 of the resistance wiring layer 210 in a film-like manner at the bottom of the first contact opening 217, and is mechanically and electrically connected to the third silicide layer 211. In other words, the first structural portion 215 has a first contact portion 219 that is electrically connected to the gate pad 15 in a region defined by the first contact openings 217.

[0435] 34 and 36 , the semiconductor device 1 includes at least (a plurality of in this embodiment) second contact openings 220 formed in the third interlayer insulating layer 180 in the peripheral region 10. In this embodiment, the plurality of second contact openings 220 are arranged in a line along the first direction X with spaces between each other. The plurality of second contact openings 220 are formed in portions of the third interlayer insulating layer 180 that cover the first structural portions 215.

[0436] The multiple second contact openings 220 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in plan view. The semiconductor device 1 may have a single second contact opening 220. The single second contact opening 220 may be formed in a strip shape extending in the first direction X along the first structural portion 215 in plan view.

[0437] 36 , the gate wiring 16 (connection wiring 16A) includes a plurality of fourth connection electrode portions 221 that enter the plurality of second contact openings 220 and are connected to the first structural portion 215. The plurality of fourth connection electrode portions 221 correspond one-to-one to the plurality of second contact openings 220. The fourth connection electrode portion 221 has a portion that covers the third silicide layer 211 of the resistance wiring layer 210 in a film-like manner at the bottom of the second contact opening 220, and is mechanically and electrically connected to the third silicide layer 211. In other words, the first structural portion 215 has, in a region defined by the second contact opening 220, a second contact portion 222 that is electrically connected to the gate wiring 16 (connection wiring 16A).

[0438] Referring to FIG. 35 , the second facing distance WF2 is adjusted appropriately depending on the resistance value to be achieved. That is, the resistance value of the first structural portion 215 is adjusted not only by increasing or decreasing the resistor thickness TR and the resistor length L11, but also by increasing or decreasing the second facing distance WF2. The second facing distance WF2 may be less than 0.5 times the second facing width IF2. The second facing distance WF2 may have a value that falls within any one of the following ranges: 0.1 times or more and 0.2 times or less, 0.2 times or more and 0.3 times or less, or 0.4 times or more and less than 0.5 times the second facing width IF2. The second facing distance WF2 may be 0.5 times or more the second facing width IF2.

[0439] 35 , the connection structure portion 216 is a region sandwiched in the first direction X by the first structure portion 215 and the first structure 34A. In this embodiment, the connection structure portion 216 has an outer shape that is rectangular in plan view. In this embodiment, the connection structure portion 216 faces the first periphery 15A of the gate pad 15 in the second direction Y in plan view. The connection structure portion 216 may be aligned with the first periphery 15A in plan view.

[0440] The connecting structure portion 216 is adjacent to the first structure 34A on the second side surface 5B (fourth side surface 5D) side. The connecting structure portion 216 is mechanically and electrically connected to the first structure 34A. In other words, the first structure portion 215 is mechanically and electrically connected to the first structure 34A by the connecting structure portion 216. In yet another word, the first structure portion 215 is electrically connected to the fifth structure 34E via the connecting structure portion 216 and the first structure 34A.

[0441] 35 , in this embodiment, the connection structure portion 216, the first structure portion 215, the first structure 34A, and the fifth structure 34E are included in the wiring structure 230, which is part of the polysilicon wiring layer 33 ( FIG. 4 ). As described above, the connection structure portion 216 and the first structure portion 215 are included in the resistive wiring layer 210, and the first structure 34A and the fifth structure 34E are included in the surrounding wiring layer 195. That is, the wiring structure 230 includes a wiring layer formed on the first main surface 3.

[0442] 35 , the connection structure portion 216 has a second opposing width IF2 in the direction in which the gate pad 15 and the gate wiring 16 (connection wiring 16A) oppose each other (i.e., the second direction Y). The second opposing width IF2 may be different from the first opposing width IF1. In this embodiment, the second opposing width IF2 is narrower than the first opposing width IF1. The second opposing width IF2 is wider than the first wiring width WW1.

[0443] 35 , in this embodiment, a first opposing distance WF1 between the first contact portion 219 and the outer edge 215A of the first structural portion 215 is narrower than the first opposing width IF1 and wider than the second opposing width IF2 (IF2<WF1<IF1). That is, the first contact portion 219 does not oppose the connecting structural portion 216 in the first direction X (a direction intersecting with the second direction Y).

[0444] 35 , the second opposing distance WF2 between the second contact portion 222 and the outer edge 215A of the first structural portion 215 is smaller than the second opposing width IF2 (WF2<IF2). That is, the second contact portion 222 faces the connecting structural portion 216 in the first direction X.

[0445] 38 , in this embodiment, a lower surface 223 of the first structural portion 215, a lower surface 224 of the connecting structural portion 216, and a lower surface 225 of the first structure 34A are all in the same plane (a plane parallel to the first main surface 3). In other words, the lower portion (lower surface 224) of the connecting structural portion 216, the lower portion (lower surface 223) of the first structural portion 215, and the lower portion (lower surface 225) of the first structure 34A are all at the same depth position.

[0446] Specifically, a lower surface 223 of the first structural portion 215 is flush with and continuous to a lower surface 224 of the connecting structural portion 216. A lower surface 224 of the connecting structural portion 216 is flush with and continuous to a lower surface 225 of the first structure 34A.

[0447] Although not shown in the figure, the lower surface of the fifth structure 34E is at the same depth as the lower surface 225 of the first structure 34A. Therefore, the lower surface of the fifth structure 34E is coplanar (a plane parallel to the first main surface 3) with the lower surface 223 of the first structure portion 215, the lower surface 224 of the connecting structure portion 216, and the lower surface 225 of the first structure 34A. In other words, the lower surfaces of the wiring structures 230 are coplanar.

[0448] 38, as described above, the resistor thickness TR has a thickness equivalent to the peripheral thickness TA. The resistor thickness TR may be thicker or thinner than the peripheral thickness TA.

[0449] 34 , the number of first structural portions 215 is not limited to one (single) and may be two or more. The number of connecting structural portions 216 is not limited to two and may be one (single) or three or more.

[0450] In semiconductor device 1, an external gate potential applied to gate pad 15 is transmitted to the plurality of trench gate structures 11. With reference to Figures 35 and 38, in this embodiment, there are at least two current paths, a first path RT1 and a second path RT2, from gate pad 15 to the plurality of trench gate structures 11. First path RT1 is a current path that runs from gate pad 15 to the plurality of trench gate structures 11 through first structure portion 215, gate wiring 16 (connection wiring 16A), and at least one of first structure 34A and fifth structure 34E.

[0451] Referring to Figures 35 and 38, the second path RT2 is a current path that runs from the gate pad 15 through the first structure portion 215, the connection structure portion 216, and at least one of the first structure 34A and the fifth structure 34E of the peripheral wiring structure 34 to the multiple trench gate structures 11.

[0452] The gate wiring 16 (connection wiring 16A) made of metal wiring has a lower resistance than the connection structure portion 216 made of polysilicon. Moreover, the second opposing width IF2 of the connection structure portion 216 is narrow (narrower than the first opposing width IF1). Therefore, the current that reaches the first structure portion 215 from the gate pad 15 is more likely to flow through the gate wiring 16 (connection wiring 16A) than through the connection structure portion 216. In other words, the first path RT1 is selected with priority over the second path RT2 as the current path from the gate pad 15 to the multiple trench gate structures 11.

[0453] Let us consider the case where the connection structure portion 216 is eliminated from the wiring structure 230. In this case, polysilicon is removed from the wiring structure 230 at the formation position of the connection structure portion 216, and the first structure portion 215 is separated from the first structure 34A and the fifth structure 34E in the first direction X. The third interlayer insulating layer 180 then enters between the first structure portion 215 and the first structure 34A and the fifth structure 34E. In this case, the removal of the polysilicon layer results in an uneven shape in the wiring structure 230. However, if the wiring structure 230 has an uneven shape, there is a risk that uneven stress distribution will occur in the wiring structure 230 (polysilicon wiring layer 33).

[0454] In contrast, in this embodiment, the first structure portion 215 is connected to the first structure 34A and the fifth structure 34E by the connecting structure portion 216. Since the first structure portion 215 and the first structure 34A are not separated, it is possible to reduce the uneven shape of the wiring structure 230. This makes it possible to suppress or prevent bias in the stress distribution in the wiring structure 230 (part of the polysilicon wiring layer 33).

[0455] Furthermore, as described above, the lower surface of the wiring structure 230 has the same plane, which makes it possible to more effectively suppress or prevent the stress distribution in the wiring structure 230 (polysilicon wiring layer 33) from becoming uneven.

[0456] Furthermore, as described above, the first path RT1 is selected preferentially over the second path RT2 as the current path from the gate pad 15 to the plurality of trench gate structures 11. This ensures an optimal current path. Therefore, even if the first structure portion 215 is electrically connected to the first structure 34A and the fifth structure 34E, no problems associated with this connection occur.

[0457] The connecting structure portion 216 according to the first embodiment (FIG. 35) has been described above.

[0458] 39A , in a second embodiment of the connecting structure portion 216, the second facing width IF2 is wider than both the first facing distance WF1 and the second facing distance WF2. That is, the first facing distance WF1 is narrower than the second facing width IF2. The second facing width IF2 may be equal to the first facing distance WF1. That is, the first facing distance WF1 may be approximately the same as the second facing width IF2.

[0459] 39B , in the third embodiment of the connecting structure portion 216, the second facing width IF2 is equal to the first facing width IF1. In this case, the second facing width IF2 is also wider than both the first facing distance WF1 and the second facing distance WF2. That is, the first facing distance WF1 is narrower than the second facing width IF2.

[0460] In the case of FIGS. 39A and 39B, both the first contact portion 219 and the second contact portion 222 face the connecting structure portion 216 in the first direction X.

[0461] Fig. 40 is an enlarged view of a portion surrounded by dashed dotted line XL in Fig. 4. Fig. 41 is an enlarged view of a portion surrounded by dashed dotted line XLI in Fig. 4. Fig. 42 is an enlarged view of a portion surrounded by dashed dotted line XLII in Fig. 4.

[0462] 40 and 41 , as described above, both terminal ends 11A of the plurality of trench gate structures 11 are electrically connected to the second structure 34B and the fourth structure 34D of the peripheral wiring structure 34, respectively. The terminal ends 11A of both trench gate structures 11 are portions at a first outer edge position (first position) P1 of the trench gate structure 11 in the first direction X and portions at a second outer edge position (first position) P2 of the trench gate structure 11 in the first direction X. That is, both terminal ends 11A of the trench gate structure 11 are electrically connected to the second portions 17B and 18B of the gate wiring 16 via both the second structure 34B and the fourth structure 34D, respectively.

[0463] In this embodiment, as described above, the plurality of connection wiring structures 35 cross the plurality of mesa portions 46 extending in a stripe pattern in the second direction Y in a line shape. With reference to FIGS. 40 to 42 , the plurality of connection wiring structures 35 are connected to the trench gate structure 11 extending in a stripe pattern. The plurality of connection wiring structures 35 are connected to an intermediate portion 11M of the trench gate structure 11. The intermediate portion 11M is a portion at an intermediate position PM of the trench gate structure 11 in the first direction X.

[0464] 40 to 42, a plurality of connection wiring structures 35 electrically connect the trench gate structure 11 to the first portions 17A, 18A (FIG. 3) of the gate wiring 16. A plurality of connection portions 151 to the connection wiring structures 35 are formed in the intermediate portion 11M of the trench gate structure 11. The plurality of connection portions 151 are formed at a plurality of locations in the first direction X in the trench gate structure 11.

[0465] In this embodiment, a gate signal applied from the gate pad 15 to the first portions 17A, 18A of the gate wiring 16 (FIG. 3) is transmitted to the plurality of trench gate structures 11 through the plurality of connection wiring structures 35 and one of the first portions 17A, 18A of the gate wiring 16.

[0466] In other words, in this embodiment, by arranging a plurality of connection wiring structures 35, the gate signal applied to the first portions 17A, 18A of the gate wiring 16 (FIG. 3) is transmitted to the trench gate structure 11 not only through the second portions 17B, 18B of the gate wiring 16 but also through the plurality of connection wiring structures 35.

[0467] 40 and 41 , the multiple connection wiring structures 35 arranged in a region close to the second portion 17B of the gate wiring 16 are referred to as a first connection wiring structure 35A, a second connection wiring structure 35B, a third connection wiring structure 35C, and a fourth connection wiring structure 35D, respectively, in order from the second portion 17B side of the gate wiring 16. Also, referring to Fig. 41 , the multiple connection wiring structures 35 arranged in a region close to the second portion 18B of the gate wiring 16 are arranged symmetrically with the multiple connection wiring structures 35 arranged in a region close to the second portion 17B of the gate wiring 16, with the third gate wiring 19 as the center. Therefore, common components are denoted by the same reference numerals as in Fig. 40 , and description thereof will be omitted.

[0468] Although not shown in the figure, the third gate wiring 19 is electrically connected to a plurality of trench gate structures 11. As described above, the third gate wiring 19 extends in the second direction Y from a gate pad position (third position) P3, which is the same as the gate pad 15 in the first direction X. In this embodiment, the gate pad position P3 is the center position of the gate pad 15 in the first direction X. Specifically, the third gate wiring 19 is connected to all trench gate structures 11 that face the third gate wiring 19 in the vertical direction Z in a plan view at the gate pad position P3. The third gate wiring 19 may be connected to the trench gate structures 11 using a part of the polysilicon wiring layer 33. The third gate wiring 19 may also be connected to the trench gate structures 11 using another wiring layer.

[0469] 40 and 41 , the first connection wiring structure 35A is arranged at an interval I11 in the first direction X on the third gate wiring 19 side (gate pad 15 side) relative to the second structure 34B (fourth structure 34D). The second connection wiring structure 35B is arranged at an interval I12 in the first direction X on the third gate wiring 19 side (gate pad 15 side) relative to the first connection wiring structure 35A. The third connection wiring structure 35C is arranged at an interval I13 in the first direction X on the third gate wiring 19 side (gate pad 15 side) relative to the second connection wiring structure 35B. The fourth connection wiring structure 35D is arranged at an interval I14 in the first direction X on the third gate wiring 19 side (gate pad 15 side) relative to the third connection wiring structure 35C.

[0470] In this embodiment (first embodiment), the intervals I13 and I14 are both the first interval IA. The intervals I11 and I12 are both the second interval IB. The second interval IB is wider than the first interval IA. That is, the intervals I11 and I12 are wider than the intervals I13 and I14 (I11>I13, I11>I14, I12>I13, I12>I14). Furthermore, the interval I10 between the first connection wiring structure 35A and the second portion 17B of the first gate wiring 17 (the second portion 18B of the second gate wiring 18) is wider than the intervals I11 and I12 (I10>I11, I10>I12).

[0471] The first interval IA may be 100 μm or more and 300 μm or less. The first interval IA is preferably 150 μm or more and 250 μm or less.

[0472] The second interval IB may be 1.2 to 2.5 times the first interval IA. The second interval IB may have a value that belongs to any one of the following ranges: 1.2 to 1.5 times, 1.5 to 1.8 times, 1.8 to 2 times, 2 to 2.3 times, or 2.3 to 2.5 times the first interval IA.

[0473] Referring to Figure 42, the multiple connection wiring structures 35 arranged in the region close to the third gate wiring 19 between the third gate wiring 19 and the second part 17B of the gate wiring 16 are referred to as the fifth connection wiring structure 35E, the sixth connection wiring structure 35F, the seventh connection wiring structure 35G, and the eighth connection wiring structure 35H, respectively, in order from the third gate wiring 19 side.

[0474] 42 , the fifth connection wiring structure 35E is arranged on the second structure 34B side (fourth structure 34D side) with a distance I15 in the first direction X from the third gate wiring 19. The sixth connection wiring structure 35F is arranged on the second structure 34B side (fourth structure 34D side) with a distance I16 in the first direction X from the fifth connection wiring structure 35E. The seventh connection wiring structure 35G is arranged on the second structure 34B side (fourth structure 34D side) with a distance I17 in the first direction X from the sixth connection wiring structure 35F. The eighth connection wiring structure 35H is arranged on the second structure 34B side (fourth structure 34D side) with a distance I18 in the first direction X from the seventh connection wiring structure 35G.

[0475] In this embodiment (first embodiment), the interval I16 is the third interval IC. The intervals I17 and I18 are both the first interval IA. The third interval IC is wider than the first interval IA. That is, the interval I16 is wider than the intervals I17 and I18 (I16>I17, I16>I18). Furthermore, the interval I15 is wider than the interval I16 (I15>I16).

[0476] The third interval IC may be 1.2 to 2.5 times the first interval IA. The third interval IC may have a value that falls within one of the following ranges: 1.2 to 1.5 times, 1.5 to 1.8 times, 1.8 to 2 times, 2 to 2.3 times, or 2.3 to 2.5 times the second interval IB.

[0477] According to this embodiment, the plurality of connection wiring structures 35 cross the plurality of mesa portions 46 extending in a stripe shape in the second direction Y in a line shape. The plurality of connection wiring structures 35 are connected to the trench gate structures 11 extending in a stripe shape, and electrically connect the trench gate structures 11 and the gate wiring 16.

[0478] By connecting the plurality of connection wiring structures 35 to the trench gate structure 11, connection portions 151 with the connection wiring structures 35 are formed in the trench gate structure 11 at a plurality of locations in the first direction X. A gate signal is transmitted from the gate wiring 16 to the trench gate structure 11 using a path that passes through the connection wiring structures 35 and reaches the connection portion 151 of the trench gate structure 11.

[0479] In the trench gate structure 11, the gate signal is transmitted through a plurality of connection portions 151 formed at a plurality of locations in the first direction X, so that the signal transmission distance from the gate wiring 16 can be shortened in each portion of the trench gate structure 11. This allows the gate signal from the gate wiring 16 to be transmitted to each portion of the trench gate structure 11 in a short time. Therefore, even if the chip 2 becomes larger and the trench gate structure 11 becomes longer in the first direction X accordingly, signal delay can be suppressed.

[0480] In this configuration, if the multiple connection wiring structures 35 were not provided, the gate signal would be transmitted to the trench gate structure 11 only through the second portions 17B and 18B of the gate wiring 16 connected to the terminal end 11A of the trench gate structure 11. In this case, the distance from the gate wiring 16 becomes long in the portion of the trench gate structure 11 far from the terminal end 11A (the portion close to the third gate wiring 19), and signal delay may occur. In particular, if the trench gate structure 11 becomes longer in the first direction X as the chip 2 becomes larger, the problem of signal delay may become apparent.

[0481] In contrast to this, in this embodiment, by arranging a plurality of connection wiring structures 35, a gate signal is transmitted to the trench gate structure 11 not only through the second portions 17B, 18B of the gate wiring 16 but also through the plurality of connection wiring structures 35. Since the gate signal is transmitted through a plurality of connection parts 151 formed at a plurality of locations in the first direction X in the trench gate structure 11, the signal transmission distance from the gate wiring 16 can be shortened in each part of the trench gate structure 11.

[0482] Therefore, the gate signal from the gate wiring 16 can be transmitted in a short time to the portion of the trench gate structure 11 far from the second portions 17B and 18B of the gate wiring 16 (the portion close to the third gate wiring 19). This makes it possible to suppress the occurrence of signal delay. Therefore, even if the chip 2 becomes larger and the trench gate structure 11 becomes longer in the first direction X, signal delay can be suppressed.

[0483] Furthermore, as described above, in this embodiment, the terminations (terminations 17D, 18D ( FIG. 3 )) of the gate wiring 16 (first gate wiring 17 and second gate wiring 18) are not disposed in the region between the periphery of the active region 9 on the third side surface 5C side and the third side surface 5C of the chip 2. In this case, there is a risk of signal delay of the gate signal occurring in the trench gate structure 11 near the periphery of the active region 9 on the third side surface 5C side.

[0484] In this embodiment, by arranging the multiple connection wiring structures 35, it is possible to suppress the occurrence of signal delay in the trench gate structure 11 near the periphery on the third side surface 5C side of the active region 9. This makes it possible to increase the area ratio of the active region 9 to the entire chip 2 while suppressing the occurrence of signal delay.

[0485] Furthermore, according to this embodiment, the terminal end 11A of the trench gate structure 11 is connected to the second portions 17B and 18B of the gate wiring 16, and the intermediate portion 11M of the trench gate structure 11 is connected to the connecting wiring structure 35.

[0486] The second portions 17B and 18B of the gate wiring 16 have low resistance. Therefore, the transmission speed of the gate signal is fast in the second portions 17B and 18B of the gate wiring 16 to which the terminal portion 11A of the trench gate structure 11 is connected. On the other hand, the connection wiring structure 35 has high resistance. Therefore, the transmission speed of the gate signal is slow in the first portions 17A and 18A of the gate wiring 16 to which the intermediate portion 11M of the trench gate structure 11 is connected ( FIG. 3 ).

[0487] Furthermore, the terminal end 11A of the trench gate structure 11 is far from the gate pad 15 (FIG. 3), and therefore the signal transmission distance between the terminal end 11A and the gate pad 15 is long. On the other hand, the intermediate portion 11M of the trench gate structure 11 is closer to the gate pad 15 (third gate wiring 19) than the terminal end 11A of the trench gate structure 11, and therefore the signal transmission distance between the intermediate portion 11M and the gate pad 15 (FIG. 3) is short.

[0488] In this embodiment, the second portions 17B and 18B of the gate wiring 16, which have a high signal transmission speed, are used to transmit gate signals to the terminal end 11A of the trench gate structure 11, which has a long signal transmission distance, and the connection wiring structure 35, which has a low signal transmission speed, is used to transmit gate signals to the intermediate portion 11M of the trench gate structure 11, which has a short signal transmission distance.

[0489] By utilizing the difference in transmission speed between the second portions 17B, 18B of the gate wiring 16 and the connection wiring structure 35, it is possible to uniformize the timing at which the gate signal arrives at each point in the trench gate structure 11. Therefore, it is possible to improve the balance of signal transmission within the surface of the chip 2.

[0490] Furthermore, according to this embodiment, in the region between the second portions 17B, 18B of the gate wiring 16 and the gate pad 15, the plurality of connection wiring structures 35 are arranged at intervals in the first direction X. The plurality of connection wiring structures 35 cross the plurality of mesa portions 46 extending in a stripe shape in the second direction Y in a line shape. Therefore, connection portions 151 between the trench gate structure 11 and the connection wiring structures 35 are formed at a plurality of locations in the first direction X of the trench gate structure 11.

[0491] Since the gate signal is transmitted through the multiple connection parts 151 formed at multiple locations in the first direction X in the trench gate structure 11, the signal transmission distance from the gate wiring 16 can be shortened in each part of the trench gate structure 11. This allows the gate signal from the gate wiring 16 to be transmitted to each part of the trench gate structure 11 in a short time. This further improves the balance of signal transmission within the surface of the chip 2.

[0492] Furthermore, according to this embodiment (first embodiment example of the plurality of connection wiring structures 35), between the second portions 17B, 18B of the gate wiring 16 and the gate pad 15 ( FIG. 3 ), the intervals I13, I14 between the connection wiring structures 35 farther from the second portions 17B, 18B are narrower than the interval I12 between the connection wiring structures 35 closer to the second portions 17B, 18B. In this case, in the intermediate portion 11M of the trench gate structure 11, the arrangement density of the connection portions 151 is higher in the portion of the connection wiring structure 35 farther from the second portions 17B, 18B than in the portion of the connection wiring structure 35 near the second portions 17B, 18B.

[0493] Since the arrangement density of the connection parts 151 can be increased in the part of the intermediate part 11M of the trench gate structure 11 that is far from the second parts 17B and 18B, the signal transmission distance to the gate wiring 16 can be more effectively shortened in this part, thereby further improving the balance of signal transmission within the surface of the chip 2.

[0494] Fig. 43 is a plan view for explaining an example of the arrangement of a plurality of connection wiring structures 35 according to the second embodiment, and is a view corresponding to Fig. 40. Fig. 44 is a plan view for explaining an example of the arrangement of a plurality of connection wiring structures 35 according to the second embodiment, and is a view corresponding to Fig. 42.

[0495] In the second embodiment, the intervals I11, I12, I13, and I14 are all the first interval IA (I11=I12=I13=I14). The interval I10 is wider than the intervals I11, I12, I13, and I14 (I10>I11, I10>I12, I10>I13, I10>I14).

[0496] In the second embodiment, the intervals I16, I17, and I18 are all the first interval IA (I16 = I17 = I18). In the second embodiment, the interval I15 is the first interval IA (I15 = I16, I15 = I17, I15 = I18). The interval I15 may be wider than the first interval IA (I15 > I16, I15 > I17, I15 > I18).

[0497] Fig. 45 is a plan view illustrating an example of the arrangement of a plurality of connection wiring structures 35 according to the third embodiment, and corresponds to Fig. 40. Fig. 46 is a plan view illustrating an example of the arrangement of a plurality of connection wiring structures 35 according to the third embodiment, and corresponds to Fig. 42.

[0498] In the third embodiment, in the region between the second portions 17B, 18B of the gate wiring 16 and the third gate wiring 19, the wiring pitch of the multiple connection wiring structures 35 becomes narrower toward the center of the region between the second portions 17B, 18B and the third gate wiring 19 in the first direction X.

[0499] 45, the interval I12 is narrower than the interval I11. The interval I13 is narrower than the interval I12. The interval I14 is narrower than the interval I13 (I11>I12>I13>I14). In the third embodiment, the interval I10 may be wider than the interval I11 (I10>I11).

[0500] 46, the interval I17 is narrower than the interval I16. The interval I18 is narrower than the interval I17 (I16>I17>I18). In the third embodiment, the interval I15 may be wider than the interval I16 (I15>I16).

[0501] 47 shows a first modified example in which the configuration of the first silicide layer 141 is changed. Referring to Fig. 47, in the first modified example, a first silicide layer 141A is formed on the surface of the connection wiring layer 130 instead of the first silicide layer 141 (Fig. 14 etc.). The first silicide layer 141A differs from the first silicide layer 141 (Fig. 14 etc.) in that it is formed partially on the surface of the connection wiring layer 130.

[0502] The first silicide layer 141A covers the upper surface 134 of the connection wiring layer 130. The first silicide layer 141A exposes a first side surface 135 and a second side surface 136 of the connection wiring layer 130.

[0503] The first silicide layer 141A may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The first silicide layer 141A is preferably made of Ti silicide, Ni silicide, or Co silicide. The first silicide layer 141A is flat and extends along the upper surface 134 of the connection wiring layer 130.

[0504] The thickness of the first silicide layer 141A is 0.01 to 0.2 times the connection width W1 ( FIG. 13 ) of the connection wiring layer 130. The first silicide layer 141A is formed in a strip shape extending along the connection wiring layer 130 in a plan view. In other words, the extending direction of the first silicide layer 141A intersects with the off-direction of the SiC single crystal.

[0505] The first silicide layer 141A is formed at a distance inward from both the first side surface 135 and the second side surface 136 of the connection wiring layer 130, and exposes both the peripheral edge portion on the first side surface 135 side and the peripheral edge portion on the second side surface 136 side on the upper surface 134 of the connection wiring layer 130.

[0506] 47, the first silicide layer 141A is not exposed from either the first side surface 135 or the second side surface 136. The first silicide layer 141A is formed over the entire upper surface 134 at an interval inward from both the first side surface 135 and the second side surface 136 in a plan view.

[0507] The first silicide layer 141A is formed by forming a metal film of Ti, Ni, Co, or the like on the upper surface 134 of the connection wiring layer 130 made of polysilicon, and then the metal film reacts with the polysilicon of the connection wiring layer 130 to be silicided. Thereafter, unnecessary portions of the connection wiring layer 130 (connection wiring structure 35) are removed (polysilicon etching process).

[0508] If the first silicide layer 141A is formed on at least one of the first side surface 135 and the second side surface 136, there is a risk that the first silicide layer 141A will also be etched (removed) along with the etching (removal) of the connection wiring layer 130 (connection wiring structure 35) during the polysilicon etching process.

[0509] In contrast, according to the first modification, the first silicide layer 141A is not formed on either the first side surface 135 or the second side surface 136. As a result, in the manufacturing process (polysilicon etching step) of the connection wiring layer 130 (connection wiring structure 35), the first silicide layer 141A is not removed from the first side surface 135 or the second side surface 136. This suppresses metal contamination (metal particle contamination) of other structures on the first main surface 3 and metal contamination (metal particle contamination) of the manufacturing equipment caused by etching the first silicide layer 141A.

[0510] In particular, in the case of the semiconductor device 1 having SiC, due to its characteristics (physical properties), an extremely high voltage is applied, unlike lateral type Si semiconductor devices such as LSIs. Metal contamination on the first main surface 3 may have an unexpected effect on the electrical characteristics of the semiconductor device 1 due to the high voltage. Therefore, by eliminating the possibility of metal contamination on the first main surface 3, a semiconductor device 1 having appropriate electrical characteristics is provided.

[0511] 48 shows a second modified example in which the region where the connection wiring structure 35 is arranged is changed. Referring to FIG. 48 , in the second modified example, the connection wiring layer 130 faces the opposing body portion 59A with a first insulating film 131 sandwiched therebetween. In the second modified example, the first contact region 57 does not exist between the first insulating film 131 and the opposing body portion 59A. In the embodiment of FIG. 48 , the p-type impurity concentration of the opposing body portion 59A may be higher than the p-type impurity concentration of the other body regions 40.

[0512] 49 shows a third modified example in which the region in which the connection wiring structure 35 (connection wiring layer 130) is arranged is changed. Referring to Fig. 49, in the third modified example, the connection wiring layer 130 faces the source region 55 (i.e., the n-type impurity region) with the first insulating film 131 interposed therebetween. That is, the connection wiring layer 130 overlaps the source region 55 in plan view.

[0513] 50A shows another embodiment of the semiconductor device 1 and is a cross-sectional view corresponding to FIG. 12. The connection wiring structure 35 has a trench wiring structure 300. The trench wiring structure 300 includes a trench 301, an insulating film 302 covering the side surfaces of the trench 301, and a conductor 303 embedded in the trench 301 with the insulating film 302 sandwiched therebetween.

[0514] The conductor 303 is formed of polysilicon as a first conductive material. This polysilicon may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0515] The trench 301 of the trench wiring structure 300 is connected to the trench 41 of the trench gate structure 11. The trench wiring structure 300 is connected to the buried body 43 of the trench gate structure 11 at the intersection of the trench 301 and the trench 41.

[0516] In this embodiment, the peripheral wiring structure 34 also includes a trench-type peripheral wiring 304. The end of the trench wiring structure 300 is connected to the trench-type peripheral wiring 304.

[0517] FIG. 50B is a plan view corresponding to FIG. 6 , showing another embodiment of the semiconductor device 1. FIG. 50C is a cross-sectional view (cross-sectional view corresponding to FIG. 7 ) taken along line LC-LC in FIG. 50B , showing another embodiment of the semiconductor device 1. FIG. 50D is a cross-sectional view (cross-sectional view corresponding to FIG. 8 ) taken along line LD-LD in FIG. 50B , showing another embodiment of the semiconductor device 1. FIG. 50E is an enlarged view (cross-sectional view corresponding to FIG. 9 ) of the portion surrounded by dashed-dotted line LE in FIG. 50C , showing another embodiment of the semiconductor device 1. FIG. 50F is an enlarged view (cross-sectional view corresponding to FIG. 10 ) of the portion surrounded by dashed-dotted line LF in FIG. 50D , showing another embodiment of the semiconductor device 1. FIG. 50G is a cross-sectional view (cross-sectional view) taken along line LG-LG in FIG. 50B , showing another embodiment of the semiconductor device 1. FIG. 50H is an enlarged view (cross-sectional view) of the portion surrounded by dashed-dotted line LH in FIG. 50G , showing another embodiment of the semiconductor device 1.

[0518] 50B to 50G, the trench insulating film 42 includes a first thick film portion 254 that covers the p-type high concentration region 250 formed in the first main surface 3. The first thick film portion 254 is a portion of the trench insulating film 42 that covers the high concentration region 250. In other words, the trench insulating film 42 included in the trench gate structure 11 is selectively thickened in the portion that covers the p-type high concentration region 250 formed in the first main surface 3. In this respect, the embodiments shown in FIGS. 50B to 50G differ from the embodiments shown in FIGS. 1 to 49.

[0519] 50B , as described above, in each mesa portion 46, a plurality of channel sections 56 are arranged at intervals in the first direction X (depth direction of the trench 41). In the channel section 56, a channel is formed on both side surfaces 44 of the trench 41 on both sides of the mesa portion 46 in the second direction Y.

[0520] 50E , a channel is formed in body region 40 (first body portion 58) included in channel section 56. Of side surface 44 and bottom surface 45 of trench 41, a region that is the same as channel section 56 in first direction X is referred to as a channel corresponding region 41C.

[0521] 50F , no channel is formed in the body region 40 (second body portion 59) that is not included in the channel section 56. Of the side surface 44 and the bottom surface 45 of the trench 41, a region that is adjacent to the channel corresponding region 41C in the first direction X and does not correspond to the channel section 56 in the first direction X is referred to as a non-channel corresponding region 41H.

[0522] As described above, the semiconductor device 1 includes the first electric field relaxation layer 51 formed in the bottom of the trench gate structure 11. The first electric field relaxation layer 51 has a second layer 54. The second layer 54 has an upper layer 54a serving as a first high-concentration layer. The upper layer 54a is exposed from the bottom (bottom surface 45) of the trench 41.

[0523] 50E and 50F, in this embodiment, the second layer 54 of the first electric field buffer layer 51 is formed in the non-channel corresponding region 41H of the bottom surface 45 of the trench 41 (FIG. 50F). The second layer 54 of the first electric field buffer layer 51 is not formed in the channel corresponding region 41C of the bottom surface 45 of the trench 41 (FIG. 50E). In other words, the upper layer 54a is formed only in the non-channel corresponding region 41H of the bottom surface 45 of the trench 41 (FIG. 50F).

[0524] The p-type impurity concentration (second impurity concentration) of the upper layer 54a is 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The second impurity concentration may have a peak value of 1×10 １８cm －３ 1x10 or more １９ cm －３ It is preferable that the p-type impurity concentration has the following peak value.

[0525] In this embodiment, the second layer 54 of the first electric field reduction layer 51 does not have the lower layer 54b. Therefore, in the non-channel corresponding region 41H, the first layer 53 contacts the lower surface of the upper layer 54a of the second layer 54 (FIG. 50F). In the channel corresponding region 41C, the first layer 53 is exposed at the bottom surface 45 of the trench 41 (FIG. 50E).

[0526] 50F , as described above, the semiconductor device 1 includes the second contact region 62 formed in the surface layer portion of the first main surface 3. The second contact region 62 is formed along the side surface 44 of the trench 41 from the first contact region 57 toward the second main surface 4. The second contact region 62 is exposed from the side surface 44 of the trench 41.

[0527] 50E and 50F, the second contact region 62 is formed in the non-channel corresponding region 41H of the side surface 44 of the trench 41 (FIG. 50F). The second contact region 62 is not formed in the channel corresponding region 41C of the side surface 44 of the trench 41 (FIG. 50E). In other words, the second contact region 62 is formed only in the non-channel corresponding region 41H of the side surface 44 of the trench 41 (FIG. 50F).

[0528] Referring to FIG. 50F, the second contact region 62 is 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The second impurity concentration may have a peak value of 1×10 １８ cm －３ 1x10 or more １９ cm －３ It is preferable that the p-type impurity concentration has the following peak value.

[0529] In this embodiment, a high-concentration region 250 of the second conductivity type (p-type) is formed by the second contact region 62 and the upper layer 54a of the first electric field reduction layer 51. The high-concentration region 250 is formed in the non-channel corresponding region 41H of the side surface 44 and bottom surface 45 of the trench 41. The high-concentration region 250 is not formed in the channel corresponding region 41C of the side surface 44 and bottom surface 45 of the trench 41.

[0530] 50C to 50F, in this embodiment, the trench insulating film 42 includes a first thick film portion 254 (FIGS. 50D and 50F), a second thick film portion (thick film portion 154 (FIG. 21, etc.)), and a thin film portion 155 (FIGS. 50C and 50E). The second thick film portion (thick film portion 154) has already been described, so its description will be omitted.

[0531] 50D, 50F, and 50G, in this embodiment, the first thick film portion 254 is formed in a non-channel corresponding region 41H of the side surface 44 and the bottom surface 45 of the trench 41. The non-channel corresponding region 41H is a region where the high-concentration region 250 is exposed to the side surface 44 and the bottom surface 45.

[0532] 50F , the first thick film portion 254 includes a first thick film 261 covering the bottom surface 45 of the trench 41 and a second thick film 262 covering the side surface 44 of the trench 41. The first thick film 261 is in contact with the upper layer 54a exposed at the bottom surface 45 of the trench 41 and covers the upper layer 54a. The second thick film 262 is in contact with the second contact region 62 exposed at the side surface 44 of the trench 41 and covers the second contact region 62. The first thick film 261 and the second thick film 262 have the same thickness.

[0533] 50C, 50E, and 50G, in this embodiment, thin film portion 155 is formed in channel corresponding region 41C of side surface 44 and bottom surface 45 of trench 41. In channel corresponding region 41C, high concentration region 250 is not exposed to side surface 44 or bottom surface 45.

[0534] 50E , the thin film portion 155 includes a first thin film 155A covering the bottom surface 45 of the trench 41 and a second thin film 155B covering the side surface 44 of the trench 41. In this embodiment, the first thin film 155A contacts the first layer 53 of the first electric field reduction layer 51 exposed at the bottom surface 45 of the trench 41 and covers the first layer 53. The second thin film 155B contacts the source region 55 and the body region 40 (first body portion 58) exposed at the side surface 44 of the trench 41 and covers the source region 55 and the body region 40 (first body portion 58). The first thin film 155A and the second thin film 155B have the same thickness.

[0535] 50E and 50F, the thickness T13 (FIG. 50F) of the first thick portion 254 of the trench insulating film 42 is thicker than the thickness T12 (FIGS. 10, 50E, etc.) of the thin portion 155 of the trench insulating film 42 (T13>T12). The thickness T13 of the first thick portion 254 of the trench insulating film 42 is, for example, 2 μm or more and 10 μm or less. The thickness T12 of the thin portion 155 of the trench insulating film 42 is, for example, 1 μm or more and 5 μm or less. The thickness T13 of the first thick portion 254 may be three times or less the thickness T12 of the thin portion 155. The thickness T13 of the first thick portion 254 is preferably 1.5 times or more and 2.5 times or less the thickness T12 of the thin portion 155. The thickness T13 of the first thick portion 254 is more preferably 1.7 times or more and 2.3 times or less the thickness T12 of the thin portion 155. The thickness T13 (FIG. 50F) of the first thick film portion 254 of the trench insulating film 42 may be the same as the thickness T11 (FIG. 20, etc.) of the second thick film portion (thick film portion 154) (T13=T11).

[0536] 50G , near a first boundary B1 in the first direction X between the non-channel corresponding region 41H and the channel corresponding region 41C, the first thick film portion 254 extends from the non-channel corresponding region 41H across the first boundary B1, and its end reaches the channel corresponding region 41C. That is, the first thick film portion 254 includes a first film portion 271 formed in the non-channel corresponding region 41H and a second film portion 272 formed in the channel corresponding region 41C. The first film portion 271 is sandwiched in the first direction X between two adjacent second film portions 272. In other words, the first thick film portion 254 is formed not only in the non-channel corresponding region 41H but also in the peripheral portion of the channel corresponding region 41C on the non-channel corresponding region 41H side.

[0537] Furthermore, in other words, a second boundary B2 between a thick film formation region 273 where the first thick film portion 254 is formed on the inner surface (side surface 44 and bottom surface 45) of the trench 41 and a non-thick film formation region 274 where the first thick film portion 254 is not formed on the inner surface (side surface 44 and bottom surface 45) of the trench 41 is closer to the channel corresponding region 41C than the first boundary B1. In other words, the second boundary B2 is formed in the channel corresponding region 41C.

[0538] 50H , in this embodiment, the first thick film portion 254 has a laminated structure of a first film 254A and a second film 254B laminated in this order from the inner surface (side surface and bottom surface 45) of the trench 41. In the first thick film portion 254, the laminated interface between the first film 254A and the second film 254B does not necessarily appear. For convenience, the laminated interface is indicated by a dashed line in FIG. 50H .

[0539] The first film 254A is a deposited film. The first film 254A includes an oxide film. The first film 254A may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second film 254B has a single-layer structure made of a silicon oxide film. The second film 254B may be a deposited film or a thermally oxidized film. The second film 254B includes an oxide film. In this embodiment, the second film 254B has a single-layer structure made of a silicon oxide film.

[0540] The trench insulating film 42 has a bottom insulating film 42a in contact with the bottom surface 45 of the trench 41. With reference to Figure 50G, the surface of the bottom insulating film 42a is convex toward the first main surface 3 in a cross-sectional view along the first direction X.

[0541] Specifically, in the bottom insulating film 42a, the upper surface of the first thick film portion 254 is closer to the first main surface 3 than the upper surface of the thin film portion 155. Referring to Fig. 50H, in the bottom insulating film 42a, a fourth step S4 that is higher on the first main surface 3 side is formed between the upper surface of the first thick film portion 254 and the upper surface of the thin film portion 155.

[0542] As shown in Fig. 50G, the end face of the first thick film portion 254 is an inclined surface that is inclined with respect to the vertical direction Z. In Fig. 50H, for ease of illustration, the end face of the first thick film portion 254 is represented as a vertical surface extending in the vertical direction Z. The end face of the first thick film portion 254 may not be an inclined surface but may be a vertical surface.

[0543] 50I to 50K are diagrams for explaining part of the manufacturing process (formation of trench insulating film 42) of semiconductor device 1. Figures 50I to 50K are cross-sectional views corresponding to Figure 50H.

[0544] 50I , third base insulating film 256, which serves as the base of first thick film portion 254, is formed on the inner surface (side surface and bottom surface 45) of trench 41. Third base insulating film 256 is formed by the CVD method. Since it is formed by the CVD method, the thickness of third base insulating film 256 can be controlled with high precision.

[0545] 50J , a hard mask 257 is formed on the third base insulating film 256. The hard mask 257 may be formed by a CVD method. The hard mask 257 covers the thick film formation region 273 and exposes the non-thick film formation region 274. The third base insulating film 256 is then selectively removed by etching via the hard mask 257. As a result, the third base insulating film 256 is formed only in the thick film formation region 273. The third base insulating film 256 forms the second film 254B.

[0546] 50K , fourth base insulating film 258, which serves as a base for first thick film portion 254 and thin film portion 155, is formed on the inner surface (side surface and bottom surface 45) of trench 41. Fourth base insulating film 258 may be formed by a CVD method or an oxidation method (for example, a thermal oxidation method).

[0547] The fourth base insulating film 258 is formed on the non-thick film formation region 274 and the first film 254A. The fourth base insulating film 258 covering the non-thick film formation region 274 forms the thin film portion 155. The fourth base insulating film 258 stacked on the first film 254A forms the second film 254B. This makes it possible to form the trench insulating film 42 in which the first thick film portion 254 is selectively formed in the thick film formation region 273.

[0548] The first thick film portion 254 may be formed simultaneously with the second thick film portion (thick film portion 154 (see FIG. 20, etc.)). In this case, the process of FIG. 50I may be performed in parallel with the process of FIG. 22A. The process of FIG. 50J may be performed in parallel with the process of FIG. 22B. The process of FIG. 50K may be performed in parallel with the process of FIG. 22C.

[0549] 50G , the upper surface 43 a of the embedded body 43 in the thick film formation region 273 is closer to the first main surface 3 than the upper surface 43 a of the embedded body 43 in the non-thick film formation region 274. In other words, a fifth step S5 that is higher on the first main surface 3 side is formed on the upper surface 43 a of the embedded body 43 between the thick film formation region 273 and the non-thick film formation region 274.

[0550] In the thick film formation region 273, the lower surface 43b of the embedded body 43 is closer to the first main surface 3 than the lower surface 43b of the embedded body 43 in the non-thick film formation region 274. Referring to Figure 50H, on the lower surface 43b of the embedded body 43, a sixth step S6 that is higher on the first main surface 3 side is formed between the thick film formation region 273 and the non-thick film formation region 274. The sixth step S6 is the same as the fourth step S4.

[0551] According to this embodiment, the trench insulating film 42 covering the high-concentration region 250 is selectively made thick. That is, the trench insulating film 42 includes a first thick film portion 254 covering the p-type high-concentration region 250 formed in the first main surface 3.

[0552] The crystallinity of the SiC single crystal (chip 2) may be reduced in the high-concentration region 250. If the crystallinity of the SiC single crystal is reduced in the high-concentration region 250, the durability of the trench insulating film 42 covering the high-concentration region 250 may be affected.

[0553] According to this embodiment, the trench insulating film 42 includes a first thick film portion 254 that covers the p-type high concentration region 250 formed in the first main surface 3. Because the portion of the trench insulating film 42 that covers the high concentration region 250 (the first thick film portion 254) is thick, the durability of the first thick film portion 254 can be maintained high even if the crystallinity of the SiC single crystal deteriorates in the high concentration region 250. In other words, the durability of the trench insulating film 42 including the first thick film portion 254 can be improved. This can improve the reliability of insulation in the trench gate structure 11.

[0554] Furthermore, on the inner surface of the trench 41, a first thick film portion 254 is formed in the non-channel corresponding region 41H, while a thin film portion 155 is formed in the channel corresponding region 41C. That is, the trench insulating film 42 has the thin film portion 155 in most of the region corresponding to the channel section 56 (see FIG. 50B ). Because the trench insulating film 42 is the thin film portion 155, the channel can be formed well. Therefore, the reliability of the insulating properties of the trench gate structure 11 can be improved while the channel can be formed well.

[0555] Furthermore, the first thick film portion 254 is formed not only in the non-channel corresponding region 41H but also in the peripheral portion of the channel corresponding region 41C on the non-channel corresponding region 41H side. This further increases the durability of the first thick film portion 254, thereby improving the durability of the trench insulating film 42 including the first thick film portion 254. This further improves the reliability of insulation in the trench gate structure 11.

[0556] FIG. 51 shows another embodiment of the semiconductor device 1 and is a cross-sectional view corresponding to FIG. 2. FIG. 52 shows another embodiment of the semiconductor device 1 and is a cross-sectional view corresponding to FIG. 6. The element structure of the semiconductor device 1 may be an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure. In this case, a p-type collector region 400 ( FIG. 51 ) may be formed instead of the base layer 6. Furthermore, a p-type base region 401 ( FIG. 52 ) may be formed by the body region 40, and an n-type emitter region 402 ( FIG. 52 ) may be formed by the source region 55.

[0557] Fig. 53 shows another embodiment of the semiconductor device 1 and is a cross-sectional view corresponding to Fig. 2. Fig. 54 shows another embodiment of the semiconductor device 1 and is a plan view corresponding to the portion surrounded by the dashed dotted line LIV shown in Fig. 12. Fig. 55 shows another embodiment of the semiconductor device 1 and is a cross-sectional view taken along line LV-LV shown in Fig. 54. Fig. 56 shows another embodiment of the semiconductor device 1 and is a cross-sectional view taken along line LVI-LVI shown in Fig. 54.

[0558] The gate structure of the semiconductor device 1 may be a planar electrode type planar gate structure (first conductive structure, gate structure) 500, different from the trench gate structure 11. In this case, the semiconductor device 1 includes a plurality of planar gate structures 500 arranged on the first main surface 3 in the active region 9. The plurality of planar gate structures 500 are arranged in stripes extending in the first direction X.

[0559] In this case, the semiconductor device 1 includes a plurality of p-type body regions (corresponding to the body regions 40 in the embodiment of FIGS. 1 to 49 ) formed in a surface layer portion of the first main surface 3 in the active region 9. A source region 55 may be formed in each of the surface layer portions of the plurality of body regions (corresponding to the body regions 40). A first contact region 57 may be formed in the surface layer portion of the body region (corresponding to the body region 40). The first contact region 57 is formed in a region different from the source region 55 in the surface layer portion of the body region (corresponding to the body region 40). A channel is formed between the body region (corresponding to the body region 40) and the source region 55. A plurality of channel sections 56 are arranged at intervals in the first direction X (depth direction of the trench 41) on the first main surface 3.

[0560] The planar gate structure 500 may include a gate electrode 502 formed on an insulating film 501 serving as an underlying insulating film. The insulating film 501 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, and may cover the first main surface 3.

[0561] 54 , the connection wiring layer 130 (connection wiring structure 35) extends in the second direction Y to cross the plurality of planar gate structures 500 and the plurality of cell portions 503 formed between the plurality of planar gate structures 500. The connection wiring layer 130 may be arranged to face the first contact region 57 (body region 40) in the vertical direction Z. The connection wiring layer 130 does not face the source region 55 in the vertical direction Z.

[0562] 55 , the connection wiring layer 130 may be in contact with the gate electrode 502 of the planar gate structure 500 from above. This electrically connects the connection wiring layer 130 and the gate electrode 502. The insulating film 501 includes a thick film portion 504 and a thin film portion 505. The thick film portion 504 is selectively formed in the insulating film 501. The thin film portion 505 is formed in a region of the insulating film 501 where the thick film portion 504 is not formed.

[0563] In this embodiment, a thick film portion 504 is formed in the insulating film 501 below a connection portion 506 between the trench gate structure 11 and the planar gate structure 500 and below a lateral region 507 of the connection portion 506. The surface of the insulating film 501 is convex toward the first main surface 3 in a cross-sectional view along the first direction X.

[0564] The thickness T21 of the thick film portion 504 (second thick film portion) of the insulating film 501 is, for example, 2 μm or more and 10 μm or less. The thickness T22 of the thin film portion 505 of the insulating film 501 is, for example, 1 μm or more and 5 μm or less. The thickness T21 of the thick film portion 504 may be three times or less the thickness T22 of the thin film portion 505. The thickness T21 of the thick film portion 504 is preferably 1.5 times or more and 2.5 times or less the thickness T22 of the thin film portion 505. The thickness T21 of the thick film portion 504 is more preferably 1.7 times or more and 2.3 times or less the thickness T22 of the thin film portion 505.

[0565] The thick film portion 504 may be formed below the connecting portion 506 but may not be formed below the side region 507 .

[0566] A region of the first main surface 3 that is the same as the channel section 56 in the first direction X (a region where a channel is formed) is referred to as a channel corresponding region 509 C. A region of the first main surface 3 that is adjacent to the channel corresponding region 509 C in the first direction X and does not correspond to the channel section 56 in the first direction X is referred to as a non-channel corresponding region 509 H.

[0567] 56 , p-type high concentration regions 510 are selectively formed in the first main surface 3. The p-type high concentration regions 510 are formed in the non-channel corresponding regions 509H of the first main surface 3. The p-type high concentration regions 510 are not formed in the channel corresponding regions 509C of the first main surface 3. In other words, the p-type high concentration regions 510 are formed only in the non-channel corresponding regions 509H of the first main surface 3.

[0568] The p-type impurity concentration of the high concentration region 510 is 1×10 １８ cm －３ 1x10 or more ２０ cm －３The p-type impurity concentration of the high concentration region 510 may have a peak value of 1×10 １８ cm －３ 1x10 or more １９ cm －３ It is preferable that the p-type impurity concentration of the high concentration region 510 has a peak value of the following: The p-type impurity concentration of the high concentration region 510 is preferably adjusted by at least one trivalent element. The trivalent element of the high concentration region 510 may be at least one of boron, aluminum, gallium, and indium.

[0569] The insulating film 501 includes a first thick film portion 514 in addition to the thick film portion (second thick film portion) 504 and the thin film portion 505. The first thick film portion 514 is a portion of the insulating film 501 that covers the high concentration region 510. In other words, the insulating film 501 included in the trench gate structure 11 is selectively made thicker in a portion that covers the p-type high concentration region 510 formed in the first main surface 3. The first thick film portion 514 is a portion of the insulating film 501 that covers the high concentration region 510.

[0570] The thickness T23 of the first thick film portion 514 of the insulating film 501 is thicker than the thickness T22 of the thin film portion 505 of the insulating film 501 (T23 > T22). The thickness T23 of the first thick film portion 514 of the insulating film 501 is, for example, 2 μm or more and 10 μm or less. The thickness T22 of the thin film portion 505 of the insulating film 501 is, for example, 1 μm or more and 5 μm or less. The thickness T23 of the first thick film portion 514 may be three times or less the thickness T22 of the thin film portion 505. The thickness T23 of the first thick film portion 514 is preferably 1.5 times or more and 2.5 times or less the thickness T22 of the thin film portion 505. The thickness T23 of the first thick film portion 514 is more preferably 1.7 times or more and 2.3 times or less the thickness T22 of the thin film portion 505.

[0571] The thickness T23 of the first thick film portion 514 of the insulating film 501 may be the same as the thickness T21 ( FIG. 55 ) of the thick film portion 504 (second thick film portion) (T23=T21). The first thick film portion 514 may be formed simultaneously with the thick film portion 504 (second thick film portion). By forming the first thick film portion 514, the surface of the insulating film 501 is convex toward the first main surface 3 in a cross-sectional view along the first direction X.

[0572] On the first main surface 3, near a third boundary B3 in the first direction X between the non-channel corresponding region 509H and the channel corresponding region 509C, the first thick film portion 514 extends from the non-channel corresponding region 509H across the third boundary B3, and its end reaches the channel corresponding region 509C. That is, the first thick film portion 514 includes a first film portion 521 formed in the non-channel corresponding region 509H and a second film portion 522 formed in the channel corresponding region 509C. The first film portion 521 is sandwiched in the first direction X between two adjacent second film portions 522. In other words, the first thick film portion 514 is formed not only in the non-channel corresponding region 509H but also in the peripheral portion of the channel corresponding region 509C on the non-channel corresponding region 509H side.

[0573] Furthermore, in other words, a fourth boundary B4 between a thick film formation region 523 of the first main surface 3 where the first thick film portion 514 is formed and a non-thick film formation region 524 of the first main surface 3 where the first thick film portion 514 is not formed is closer to the channel corresponding region 509C than the third boundary B3. In other words, the fourth boundary B4 is formed in the channel corresponding region 509C. The end face of the first thick film portion 514 may be an inclined surface inclined with respect to the vertical direction Z, or may be a vertical surface extending in the vertical direction Z.

[0574] The embodiments of FIGS. 53 to 56 have the same effects as those described in relation to the embodiments (FIGS. 1 to 50K, etc.) in which the trench gate structure 11 is employed.

[0575] While the present disclosure has been described in terms of embodiments, it is possible to embody the present disclosure in other forms.

[0576] In the above-described embodiments (including modified examples), examples have been described in which the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing n-type regions with p-type regions and p-type regions with n-type regions in the above description and accompanying drawings.

[0577] In the above-described embodiment (including the modified examples), the chip 2 includes a SiC single crystal. However, the chip 2 may include a wide bandgap semiconductor single crystal other than a SiC single crystal.

[0578] For example, in each of the above-described embodiments, the base layer 6 and the semiconductor layer 7 each include a SiC single crystal. However, at least one of the base layer 6 and the semiconductor layer 7 or all of them may include a single crystal of a wide bandgap semiconductor other than a SiC single crystal.

[0579] Wide bandgap semiconductors are semiconductors that have a bandgap larger than that of silicon. Wide bandgap semiconductor single crystals include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga ２ O ３ ) are examples. The base layer 6 and the semiconductor layer 7 may be made of the same type of single crystal, or may be made of different types of single crystal. Furthermore, at least one of the base layer 6 and the semiconductor layer 7 or all of them may be made of silicon (Si).

[0580] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0581] [Appendix A-1] A chip (2) having a first main surface (3) on which an element region (9) is formed; a plurality of first conductive structures (11, 500) extending in a stripe shape in a first direction (X) in the element region (9) and formed of a first conductive material; a cell section (46, 503) formed between the plurality of first conductive structures (11, 500); an insulating layer (13) formed on the first main surface (3) so as to cover the first conductive structures (11, 500); and a second conductive structure (16) formed on the insulating layer (13) so as to surround the element region (9) in a planar view and formed of a second conductive material having a lower resistance than the first conductive material. a plurality of connection wiring structures (35) formed on the first main surface (3) so as to be covered by the insulating layer (13), extending in a line shape from the second conductive structure (16) in a second direction (Y) intersecting the first direction (X) across the cell portion (46, 503), and electrically connecting the first conductive structure (11, 500) and the second conductive structure (16).

[0582] According to this configuration, a plurality of connection wiring structures (35) cross the stripe-shaped cell portion (46, 503) in a line shape in the second direction (Y). The plurality of connection wiring structures (35) are connected to the stripe-shaped first conductive structure (11, 500) and electrically connect the first conductive structure (11, 500) and the second conductive structure (16).

[0583] By connecting a plurality of connection wiring structures (35) to the first conductive structure (11,500), connection portions (151) with the connection wiring structures (35) are formed in the first conductive structure (11,500) at a plurality of locations in the first direction (X). Signal transmission from the second conductive structure (16) to the first conductive structure (11,500) is performed using a path from the second conductive structure (16) through the connection wiring structures (35) to the connection portions (151) of the first conductive structure (11,500).

[0584] Since signals are transmitted through a plurality of connection portions (151) formed at a plurality of locations in the first direction (X) in the first conductive structure (11,500), the signal transmission distance from the second conductive structure (16) can be shortened at each portion of the first conductive structure (11,500). This allows signals from the second conductive structure (16) to be transmitted to each portion of the first conductive structure (11,500) in a short time. Therefore, even if the chip (2) becomes larger and the first conductive structure (11,500) becomes longer in the first direction (X), signal delay can be suppressed.

[0585] [Appendix A-2] The semiconductor device (1) according to appendix A-1, wherein the connection wiring structure (35) is formed from the first conductive material.

[0586] [Appendix A-3] The semiconductor device (1) according to appendix A-2, wherein the first conductive material is polysilicon.

[0587] [Appendix A-4] The semiconductor device (1) according to any one of Appendices A-1 to A-3, wherein the connection wiring structure (35) includes a connection wiring layer (130) formed on the first main surface (3).

[0588] [Appendix A-5] The semiconductor device (1) according to any one of Appendices A-1 to A-4, further comprising: a first impurity region (7) of a first conductivity type formed in the chip (2); a second impurity region (40) of a second conductivity type formed in a surface layer portion of the first impurity region (7) on the first main surface (3) side; and a third impurity region (55) of the first conductivity type formed in a surface layer portion of the second impurity region (40) on the first main surface (3) side, wherein the first conductive structure (11,500) faces the second impurity region (40) and includes a gate structure (11,500) that forms a channel in the second impurity region (40).

[0589] [Appendix A-6] The semiconductor device (1) according to appendix A-5, wherein the gate structure (11, 500) is a trench gate structure (11) formed in the element region (9), and the second conductive structure (16) is a gate wiring (16).

[0590] [Appendix A-7] The semiconductor device (1) according to appendix A-6, wherein the trench gate structure (11) includes a trench (41) extending from the first main surface (3) through the third impurity region (55) and the second impurity region (40) to the first impurity region (7), a trench insulating film (42) formed on the inner surface of the trench (41), and a buried body (43) buried in the trench (41) via the trench insulating film (42), and the connection wiring structure (35) includes a connection wiring layer (130) formed on the first main surface (3), and the connection wiring layer (130) is in contact with the buried body (43) at an upper portion of the trench (41).

[0591] [Appendix A-8] The semiconductor device (1) according to Appendix A-7, wherein the insulating layer (13) includes a first interlayer insulating layer (63) buried in the upper part of the trench (41) and covering the buried body (43), and a second interlayer insulating layer (145) covering the surface of the connection wiring layer (130).

[0592] [Appendix A-9] The semiconductor device (1) according to Appendix A-7 or A-8, wherein the cell portion (46, 503) includes a mesa portion (46) formed by being sandwiched between a plurality of adjacent trenches (41), and further includes a first insulating film (131) covering an upper surface of the mesa portion (46), and the connection wiring layer (130) is disposed on the mesa portion (46) via the first insulating film (131).

[0593] [Appendix A-10] The semiconductor device (1) according to any one of appendices A-7 to A-9, wherein the thickness (T3) of the connection wiring layer (130) is greater than the depth (DT1) of the trench (41).

[0594] [Appendix A-11] The semiconductor device (1) according to any one of Appendices A-1 to A-10, further comprising a peripheral wiring structure (34) formed on the first main surface (3) so as to be covered by the insulating layer (13) and so as to surround the element region (9) in a planar view, and electrically connected to the first conductive structure (11, 500), wherein the connecting wiring structure (35) is connected to the peripheral wiring structure (34).

[0595] [Appendix A-12] The semiconductor device (1) according to appendix A-11, wherein the connection wiring structure (35) is connected across the mutually opposing portions (34A, 34C; 34A, 34E) of the peripheral wiring structure (34).

[0596] [Appendix A-13] The semiconductor device (1) according to appendix A-11 or appendix A-12, wherein the peripheral wiring structure (34) includes a first wiring portion (34B, 34D) formed below the second conductive structure (16).

[0597] [Appendix A-14] The semiconductor device (1) according to any one of Appendices A-1 to A-13, wherein the chip (2) is a SiC chip.

[0598] [Appendix A-15] The semiconductor device (1) according to any one of Appendices A-1 to A-14, wherein the second conductive material is a metal containing aluminum.

[0599] [Appendix A-16] The semiconductor device (1) according to appendix A-5, wherein the gate structure (11, 500) is a planar gate structure (500), and the second conductive structure (16) is a gate wiring (16).

[0600] [Appendix A-17] The semiconductor device (1) according to any one of Appendices A-5 to A-10, including a fourth impurity region (59A) of a second conductivity type formed in a surface layer portion of the first main surface (3) of the chip (2) and facing the connection wiring structure (35) in a thickness direction (Z) of the chip (2).

[0601] [Appendix A-18] The semiconductor device (1) according to appendix A-17, wherein the fourth impurity region (59A) has the same depth as the second impurity region (40).

[0602] [Appendix A-19] The semiconductor device (1) according to appendix A-17 or A-18, wherein the fourth impurity region (59A) has the same impurity concentration as the second impurity region (40).

[0603] [Appendix A-20] The semiconductor device (1) according to any one of Appendices A-5 to A-10 and A-16, wherein the chip (2) has a second main surface (4) opposite to the first main surface (3), and further includes a drain region (6) of a first conductivity type formed on the second main surface side of the first impurity region (7), a body region (40) formed by the second impurity region (40), and a source region (55) formed by the third impurity region (55).

[0604] [Appendix A-21] The semiconductor device (1) according to any one of Appendices A-5 to A-10 and A-16, wherein the chip (2) further has a second main surface (4) opposite to the first main surface (3), and further includes a collector region (400) of a second conductivity type formed on the second main surface (4) side of the first impurity region (7), a base region (401) formed by the second impurity region (40), and an emitter region (402) formed by the third impurity region (55).

[0605] [Appendix B-1] A chip (2) having a first main surface (3) on which an element region (9) is formed; a pad (15) formed on the first main surface (3) of the chip (2); a plurality of f...

Claims

1. A semiconductor device, comprising: a chip having a first main surface on which an element region is formed; a plurality of first conductive structures extending in a stripe shape in a first direction in the element region and formed of a first conductive material; an underlying insulating film between the first conductive structure and the chip; a first impurity region of a first conductivity type formed in the chip; a second impurity region of a second conductivity type formed in a surface layer portion on the first main surface side of the first impurity region; and a high-concentration region formed in a surface layer portion of the first main surface and having a higher impurity concentration of the second conductivity type than the second impurity region, wherein the underlying insulating film is selectively thickened in a portion covering the high-concentration region.

2. The semiconductor device according to claim 1, further comprising a third impurity region of a first conductivity type formed in a surface layer portion on the first main surface side of the second impurity region, wherein the first conductive structure includes a gate structure that faces the second impurity region and forms a channel in the second impurity region.

3. The semiconductor device according to claim 2, wherein the underlying insulating film includes a first thick film portion formed in a portion covering the high-concentration region, and the first thick film portion is not formed in a channel corresponding region corresponding to a channel section in which a channel is formed in the second impurity region.

4. The semiconductor device according to claim 2 or 3, wherein the gate structure is a trench gate structure, the trench gate structure includes a trench reaching the first impurity region from the first main surface through the third impurity region and the second impurity region, and the underlying insulating film includes a trench insulating film formed on an inner surface of the trench.

5. The semiconductor device according to claim 4, wherein the trench insulating film includes a first thick film portion covering the high-concentration region and a thin film portion thinner than the first thick film portion and not covering the high-concentration region, and the thin film portion is formed in a non-channel corresponding region not corresponding to a channel section in which a channel is formed in the second impurity region.

6. The semiconductor device according to claim 5, wherein the trench gate structure further includes an embedded body embedded in the trench with the trench insulating film interposed therebetween, and an upper surface height of a portion of the embedded body in contact with the first thick film portion is higher than an upper surface height of a portion of the embedded body in contact with the thin film portion.

7. The semiconductor device according to claim 5 or 6, wherein the first thick film portion has a thickness of 1.5 times or more the thickness of the thin film portion.

8. The semiconductor device according to any one of claims 5 to 7, wherein the high-concentration region includes a first high-concentration layer exposed on the bottom surface of the trench, and the first thick film portion includes a first thick film covering the first high-concentration layer.

9. The semiconductor device according to claim 8, wherein the high-concentration region further includes a second high-concentration layer exposed on the side surface of the trench, and the first thick film portion further includes a second thick film covering the second high-concentration layer.

10. The semiconductor device according to claim 9, wherein the first high-concentration layer and the second high-concentration layer have the same concentration as each other.

11. The semiconductor device according to any one of claims 3 and 5 to 10, wherein the upper surface of the base insulating film is convex toward the first main surface side in a cross-sectional view along the first direction in the first thick film portion.

12. The semiconductor device according to any one of claims 3 and 5 to 11, wherein the first thick film portion includes a first film portion covering the high-concentration region and a second film portion covering a region adjacent to the high-concentration region in the first direction.

13. An insulating layer formed on the first main surface so as to cover the first conductive structure; a second conductive structure formed on the insulating layer so as to surround the element region in a plan view and made of a second conductive material having a lower resistance than the first conductive material; and a plurality of connection wiring structures formed on the first main surface so as to be covered by the insulating layer, extending linearly across the first conductive structure in a second direction intersecting the first direction from the second conductive structure, and electrically connecting the first conductive structure and the second conductive structure, wherein the base insulating film further includes a second thick film portion selectively formed thick at a connection portion between the first conductive structure and the connection wiring structure. The semiconductor device according to any one of claims 3 and 5 to 12.

14. The semiconductor device according to claim 13, wherein the first thick film portion has the same thickness as the second thick film portion.

15. The semiconductor device according to any one of claims 1 to 14, wherein the chip is a SiC chip.

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