Bitstream processing method and apparatus

Abstract

The present application relates to the technical field of media. Provided are a bitstream processing method and apparatus, enabling the smooth extraction of sub-bitstreams and specifying a means for indicating layering information. The method comprises: acquiring a bitstream of a target image, the bitstream comprising first layering information, the first layering information comprising first indicating information used for indicating the number of layers contained in the bitstream and second indicating information used for indicating layer identifiers of the layers contained in the bitstream; constructing a target layer list corresponding to target layers to be extracted from the target image; processing the bitstream of the target image on the basis of the target layer list and outputting a sub-bitstream, the sub-bitstream comprising a bitstream of a layer in the target layer list and second layering information, the second layering information comprising second indicating information used for indicating the number of layers contained in the sub-bitstream and third indicating information used for indicating layer identifiers, in the target image, of the layers contained in the sub-bitstream.

Description

A bit stream processing method and device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 24, 2024, with application number 202410102813.5 and application name “A method and device for bitstream processing”, and claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 23, 2024, with application number 202410211671.6 and application name “A method and device for bitstream processing”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of media technology, and in particular to a method and device for processing a bit stream. Background Art

[0003] During the video / image encoding and decoding process, the image to be encoded can be encoded in layers, and layer-related information (such as the number of layers and inter-layer dependency information) can be transmitted in the encoded bit stream (or code stream).

[0004] In some cases, the decoder can extract the bitstream of a specific layer from the bitstream for independent decoding. After extracting the bitstream of a specific layer, the layer-related information of the bitstream changes. Therefore, how to extract the bitstream and how to process the layer-related information urgently need to be solved.

[0005] Summary of the Invention

[0006] The present application provides a bitstream processing method and apparatus, which can smoothly implement sub-bitstream extraction and clarify the indication method of layered information.

[0007] This application adopts the following technical solutions:

[0008] In a first aspect, the present application provides a bitstream processing method, comprising: obtaining a bitstream of a target image, the bitstream comprising at least one layered bitstream after layered encoding of the target image, the bitstream comprising first layer information, the first layer information comprising first indication information for indicating the number of layered layers contained in the bitstream and second indication information for indicating a layer identifier of the layer contained in the bitstream; and constructing a target layer list corresponding to the target layer, the target layer being the layer to be extracted in the target image, the target layer list comprising the target layer; when at least one layer in the target layer has an inter-layer reference layer, the target layer list further comprises at least one inter-layer reference layer; and processing the bitstream of the target image based on the target layer list, and outputting a sub-bitstream; the sub-bitstream comprising the layered bitstream in the target layer list and the second layer information, the second layer information comprising third indication information and fourth indication information; wherein the third indication information is used to indicate the number of layered layers contained in the sub-bitstream, and the fourth indication information is used to indicate the layer identifier of the layer contained in the sub-bitstream.

[0009] The bitstream processing method provided in the present application can create a target layer list based on the layer to be extracted, and then extract the bitstream of the layer in the target layer list to obtain a sub-bitstream. The sub-bitstream can also carry the layer information after the bitstream extraction, so that the sub-bitstream extraction can be smoothly realized and the indication method of the layer information can be clarified.

[0010] In one possible implementation, the supplemental enhancement information in the target image bitstream includes first layer information; and / or the supplemental enhancement information in the sub-bitstream includes second layer information. Specifically, the first layer information or the second layer information is carried in a payload with a nal_unit_type of 6 (a NAL unit with a nal_unit_type of 6 includes supplemental enhancement information) and a PayloadType of 25.

[0011] In a possible implementation, the second layer information is layer information that updates the first layer information. By updating the layer information in the bitstream, the layer information contained in the bitstream can be known based on the updated layer information, thereby improving encoding and decoding performance.

[0012] In one possible implementation, a target layer list corresponding to the target layer is constructed, including: parsing the bit stream of the target image, obtaining at least one layered layer-independent coding identifier and at least one layered reference layer identifier; a layered layer-independent coding identifier is used to indicate independent coding or inter-layer dependency coding of the layer; and adding the layer identifier of the target layer to the target layer list. If the layered independent coding identifier of the target layer indicates inter-layer dependency coding of the target layer, the reference layer identifier of the target layer is added to the target layer list.

[0013] In one possible implementation, processing the bitstream of the target image based on the target layer list includes: removing from the bitstream of the target image NAL units whose network abstraction layer NAL unit type is not 5, 6, 7, 8, 9, 10, 11, or 16 in the bitstream of the layer not present in the target layer list. Since the NAL units whose nal_unit_type is 5, 6, 7, 8, 9, 10, 11, or 16 contain common information for decoding the bitstream, they need to be retained (i.e., need to be extracted into the sub-bitstream).

[0014] In a possible implementation, the authentication flag of the network abstraction layer NAL unit containing the first layer information or the second layer information is a first value, and the first value is used to indicate that the NAL unit containing the first layer information or the second layer information is not authenticated.

[0015] The first value is specifically used to indicate to the decoding end that the NAL unit containing the first layer information or the second layer information is not to be authenticated. In this way, the decoding end does not need to authenticate the NAL unit containing the first layer information or the second layer information.

[0016] In a possible implementation, the encryption flag of the network abstraction layer NAL unit containing the first layer information or the second layer information is a second value, and the second value is used to indicate that the NAL unit containing the first layer information or the second layer information is not encrypted.

[0017] The second value is specifically used to indicate to the decoder that the encoder has not encrypted the NAL unit containing the first layer information or the second layer information. In this way, the decoder does not need to decrypt the NAL unit containing the first layer information or the second layer information.

[0018] In a possible implementation, the network abstraction layer NAL unit containing the first layer information or the second layer information is carried in the bit stream of the first layer of the target image.

[0019] In a second aspect, the present application provides a bitstream processing device, comprising modules for implementing the method described in the first aspect and any one of its possible implementations. The bitstream processing device has the functionality to implement the behaviors described in the method examples of any one of the first aspect and its possible implementations. The functionality may be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the functionality described above.

[0020] In a third aspect, the present application provides a bitstream processing device, comprising at least one processor and a memory, wherein the at least one processor executes a program or instruction stored in the memory so that the bitstream processing device implements the method described in the first aspect or any one of its possible implementations.

[0021] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium for storing a computer program, wherein the computer program includes methods for implementing the method described in the first aspect or any possible implementation thereof.

[0022] In a fifth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to implement the method described in the first aspect or any possible implementation thereof.

[0023] In a sixth aspect, embodiments of the present application further provide a chip comprising: an input interface, an output interface, and at least one processor. Optionally, the chip further comprises a memory. The at least one processor is configured to execute code in the memory. When the at least one processor executes the code, the chip implements the method described in the first aspect or any possible implementation thereof.

[0024] Optionally, the chip may also be an integrated circuit.

[0025] The bitstream processing device, computer storage medium, computer program product and chip provided in this application are all used to execute the bitstream processing method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the bitstream processing method provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1a is an exemplary block diagram of a decoding system provided in an embodiment of the present application;

[0027] FIG1b is an exemplary block diagram of a video decoding system provided in an embodiment of the present application;

[0028] FIG2 is an exemplary block diagram of a video encoder provided in an embodiment of the present application;

[0029] FIG3 is an exemplary block diagram of a video decoder provided in an embodiment of the present application;

[0030] FIG4 is an exemplary schematic diagram of candidate image blocks provided in an embodiment of the present application;

[0031] FIG5 is an exemplary block diagram of a video decoding device provided in an embodiment of the present application;

[0032] FIG6 is an exemplary block diagram of a device provided in an embodiment of the present application;

[0033] FIG7 is a schematic flow chart of a bit stream processing method provided in an embodiment of the present application;

[0034] FIG8 is a schematic diagram of a bit stream processing device provided in an embodiment of the present application;

[0035] FIG9 is a schematic structural diagram of a chip provided in an embodiment of the present application;

[0036] FIG10 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0037] FIG11 is a schematic structural diagram of a bit stream processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the embodiments of this application.

[0039] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0040] The terms "first" and "second" and the like in the description and drawings of the embodiments of the present application are used to distinguish different objects, or to distinguish different processing of the same object, rather than to describe a specific order of objects.

[0041] Furthermore, the terms "including," "having," and any variations thereof, mentioned in the description of the embodiments of the present application are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not limited to the listed steps or units but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to the process, method, product, or apparatus.

[0042] It should be noted that in the description of the embodiments of this application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be interpreted as having priority or advantage over other embodiments or designs. Rather, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a concrete manner.

[0043] Data encoding and decoding includes two parts: data encoding and data decoding. Data encoding is performed on the source side (or commonly referred to as the encoder side), and generally includes processing (e.g., compressing) the original data to reduce the amount of data required to represent the original data (thereby more efficiently storing and / or transmitting). Data decoding is performed on the destination side (or commonly referred to as the decoder side), and generally includes inverse processing relative to the encoder side to reconstruct the original data. The "encoding and decoding" of the data involved in the embodiments of the present application should be understood as the "encoding" or "decoding" of the data. The encoding part and the decoding part are also collectively referred to as encoding and decoding (encoding and decoding, CODEC).

[0044] In the case of lossless data encoding, the original data can be reconstructed, that is, the reconstructed original data has the same quality as the original data (assuming there is no transmission loss or other data loss during storage or transmission). In the case of lossy data encoding, further compression is performed through quantization, etc. to reduce the amount of data required to represent the original data, but the decoder side cannot fully reconstruct the original data, that is, the quality of the reconstructed original data is lower or worse than the quality of the original data.

[0045] The embodiments of the present application can be applied to video data and other data with compression / decompression requirements. The following uses the encoding of video data (referred to as video encoding) as an example to illustrate the embodiments of the present application. Other types of data (such as image data, audio data, integer data, and other data with compression / decompression requirements) can refer to the following description, and the embodiments of the present application will not be repeated here. It should be noted that, compared to video encoding, the encoding process of data such as audio data and integer data does not require data to be divided into blocks, but the data can be directly encoded.

[0046] Video coding generally refers to processing a sequence of images to form a video or video sequence. In the field of video coding, the terms "picture", "frame" or "image" can be used as synonyms.

[0047] Several video coding standards fall under the category of "lossy hybrid video codecs" (i.e., combining spatial and temporal prediction in the pixel domain with 2D transform coding in the transform domain for applying quantization). Each image in a video sequence is typically divided into a set of non-overlapping blocks, which are typically coded at the block level. In other words, the encoder typically processes, i.e., encodes, the video at the block (video block) level, for example, by generating a prediction block through spatial (intra-frame) and temporal (inter-frame) prediction; subtracting the prediction block from the current block (currently processed / to-be-processed block) to obtain a residual block; transforming and quantizing the residual block in the transform domain to reduce the amount of data to be transmitted (compressed), while the decoder applies the inverse of the encoder's processing to the coded or compressed block to reconstruct the current block for representation. Furthermore, the encoder needs to repeat the decoder's processing steps so that the encoder and decoder generate the same predictions (e.g., intra-frame predictions and inter-frame predictions) and / or reconstructed pixels for processing, i.e., encoding, the subsequent block.

[0048] In the following embodiment of the decoding system 10 , the encoder 20 and the decoder 30 are described with reference to FIG. 1 a to FIG. 3 .

[0049] FIG1a is an exemplary block diagram of a decoding system 10 provided in an embodiment of the present application, such as a video decoding system 10 (or simply, decoding system 10) that can utilize the techniques of the embodiments of the present application. The video encoder 20 (or simply, encoder 20) and video decoder 30 (or simply, decoder 30) in the video decoding system 10 represent devices that can be used to perform various techniques according to the various examples described in the embodiments of the present application.

[0050] As shown in FIG. 1 a , a decoding system 10 includes a source device 12 for providing encoded image data 21 such as an encoded image to a destination device 14 for decoding the encoded image data 21 .

[0051] The source device 12 includes an encoder 20 , and optionally, may include an image source 16 , a preprocessor (or preprocessing unit) 18 such as an image preprocessor, and a communication interface (or communication unit) 22 .

[0052] Image source 16 may include or may be any type of image capture device for capturing real-world images, etc., and / or any type of image generation device, such as a computer graphics processor for generating computer-animated images, or any type of device for acquiring and / or providing real-world images, computer-generated images (e.g., screen content, virtual reality (VR) images, and / or any combination thereof (e.g., augmented reality (AR) images). The image source may be any type of memory or storage for storing any of the above images.

[0053] In order to distinguish the processing performed by the pre-processor (or pre-processing unit) 18 , the image (or image data) 17 may also be referred to as a raw image (or raw image data) 17 .

[0054] The preprocessor 18 is configured to receive raw image data 17 and preprocess the raw image data 17 to obtain a preprocessed image (or preprocessed image data) 19. For example, the preprocessing performed by the preprocessor 18 may include cropping, color format conversion (e.g., from RGB to YCbCr), color grading, or denoising. It will be appreciated that the preprocessor 18 may be an optional component.

[0055] The video encoder (or encoder) 20 is used to receive the pre-processed image data 19 and provide encoded image data 21 (which will be further described below with reference to FIG. 2 and the like).

[0056] The communication interface 22 in the source device 12 can be used to receive the encoded image data 21 and send the encoded image data 21 (or any other processed version) to another device such as the destination device 14 or any other device through the communication channel 13 for storage or direct reconstruction.

[0057] The destination device 14 includes a decoder 30 and, in addition or alternatively, may include a communication interface (or communication unit) 28 , a post-processor (or post-processing unit) 32 , and a display device 34 .

[0058] The communication interface 28 in the destination device 14 is used to receive the encoded image data 21 (or any other processed version) directly from the source device 12 or from any other source device such as a storage device, for example, the storage device is a encoded image data storage device, and provide the encoded image data 21 to the decoder 30.

[0059] The communication interface 22 and the communication interface 28 can be used to send or receive encoded image data (or encoded data) 21 through a direct communication link between the source device 12 and the destination device 14, such as a direct wired or wireless connection, or through any type of network, such as a wired network, a wireless network or any combination thereof, any type of private network and public network or any combination thereof.

[0060] For example, the communication interface 22 may be used to encapsulate the encoded image data 21 into a suitable format such as a message, and / or process the encoded image data using any type of transmission coding or processing for transmission over a communication link or network.

[0061] The communication interface 28 corresponds to the communication interface 22 , and can be used, for example, to receive transmission data and process the transmission data using any type of corresponding transmission decoding or processing and / or decapsulation to obtain the encoded image data 21 .

[0062] Both the communication interface 22 and the communication interface 28 can be configured as a unidirectional communication interface as indicated by the arrow pointing from the source device 12 to the corresponding communication channel 13 of the destination device 14 in Figure 1a, or a bidirectional communication interface, and can be used to send and receive messages, etc. to establish a connection, confirm and exchange any other information related to the communication link and / or data transmission such as encoded image data transmission, etc.

[0063] The video decoder (or decoder) 30 is used to receive the encoded image data 21 and provide decoded image data (or decoded image data) 31 (which will be further described below with reference to FIG. 3 and the like).

[0064] The post-processor 32 is configured to post-process the decoded image data 31 (also referred to as reconstructed image data) such as the decoded image to obtain post-processed image data 33 such as the post-processed image. The post-processing performed by the post-processing unit 32 may include, for example, color format conversion (e.g., from YCbCr to RGB), color grading, cropping, or resampling, or any other processing for generating the decoded image data 31 for display on a display device 34 or the like.

[0065] The display device 34 is configured to receive the post-processed image data 33 and display the image to a user or viewer. The display device 34 may be or include any type of display for displaying the reconstructed image, such as an integrated or external display screen or monitor. For example, the display screen may include a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a plasma display, a projector, a micro-LED display, a liquid crystal on silicon (LCoS) display, a digital light processor (DLP), or any other type of display screen.

[0066] The decoding system 10 also includes a training engine 25, which is used to train the encoder 20 (especially the entropy encoding unit 270 in the encoder 20) or the decoder 30 (especially the entropy decoding unit 304 in the decoder 30) to perform entropy encoding on the image block to be encoded based on the estimated probability distribution. For a detailed description of the training engine 25, please refer to the following method test example.

[0067] Although FIG1a shows source device 12 and destination device 14 as separate devices, device embodiments may also include both source device 12 and destination device 14 or the functions of both source device 12 and destination device 14, that is, both source device 12 or the corresponding functions and destination device 14 or the corresponding functions. In these embodiments, source device 12 or the corresponding functions and destination device 14 or the corresponding functions may be implemented using the same hardware and / or software or through separate hardware and / or software or any combination thereof.

[0068] According to the description, the existence and (accurate) division of different units or functions in the source device 12 and / or the destination device 14 shown in FIG. 1 a may vary depending on actual devices and applications, which is obvious to those skilled in the art.

[0069] Please refer to Figure 1b, which is an exemplary block diagram of a video decoding system 40 provided in an embodiment of the present application. The encoder 20 (e.g., video encoder 20) or the decoder 30 (e.g., video decoder 30), or both, can be implemented by processing circuitry in the video decoding system 40 shown in Figure 1b, such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, hardware, video encoding-specific processors, or any combination thereof. Please refer to Figures 2 and 3, Figure 2 is an exemplary block diagram of a video encoder provided in an embodiment of the present application, and Figure 3 is an exemplary block diagram of a video decoder provided in an embodiment of the present application. The encoder 20 can be implemented by processing circuitry 46 to include the various modules discussed with reference to the encoder 20 in Figure 2 and / or any other encoder systems or subsystems described herein. The decoder 30 can be implemented by processing circuitry 46 to include the various modules discussed with reference to the decoder 30 in Figure 3 and / or any other decoder systems or subsystems described herein. The processing circuitry 46 described above can be used to perform the various operations discussed below. As shown in Figure 5, if part of the technology is implemented in software, the device can store the software instructions in a suitable non-transitory computer-readable storage medium and use one or more processors to execute the instructions in hardware, thereby performing the technology of the embodiment of the present application. One of the video encoder 20 and the video decoder 30 can be integrated into a single device as part of a combined codec (encoder / decoder, CODEC), as shown in Figure 1b.

[0070] The source device 12 and the destination device 14 may include any of a variety of devices, including any type of handheld or fixed device, such as a notebook computer or laptop, a mobile phone, a smart phone, a tablet or a tablet computer, a camera, a desktop computer, a set-top box, a television, a display device, a digital media player, a video game console, a video streaming device (e.g., a content service server or a content distribution server), a broadcast receiving device, a broadcast transmitting device, and a monitoring device, etc., and may not use or use any type of operating system. The source device 12 and the destination device 14 may also be devices in a cloud computing scenario, such as a virtual machine in a cloud computing scenario. In some cases, the source device 12 and the destination device 14 may be equipped with components for wireless communication. Therefore, the source device 12 and the destination device 14 may be wireless communication devices.

[0071] The source device 12 and the destination device 14 may be installed with virtual scene applications (APPs) such as virtual reality (VR), augmented reality (AR), or mixed reality (MR), and may run the VR, AR, or MR applications based on user operations (e.g., click, touch, slide, shake, voice control, etc.). The source device 12 and the destination device 14 may capture images / videos of any objects in the environment through cameras and / or sensors, and then display virtual objects on a display device based on the captured images / videos. The virtual objects may be virtual objects in the VR, AR, or MR scenes (i.e., objects in the virtual environment).

[0072] It should be noted that in the embodiment of the present application, the virtual scene application in the source device 12 and the destination device 14 can be an application built into the source device 12 and the destination device 14 themselves, or it can be an application provided by a third-party service provider and installed by the user. There is no specific limitation on this.

[0073] In addition, the source device 12 and the destination device 14 may be installed with a real-time video transmission application, such as a live broadcast application. The source device 12 and the destination device 14 may capture images / videos through cameras and then display the captured images / videos on a display device.

[0074] In some cases, the video decoding system 10 shown in FIG1a is merely exemplary, and the techniques provided in embodiments of the present application may be applicable to video encoding settings (e.g., video encoding or video decoding) that do not necessarily include any data communication between an encoding device and a decoding device. In other examples, data is retrieved from a local memory, sent over a network, and so on. A video encoding device may encode data and store the data in a memory, and / or a video decoding device may retrieve data from a memory and decode the data. In some examples, encoding and decoding are performed by devices that do not communicate with each other but simply encode data to a memory and / or retrieve and decode data from a memory.

[0075] Please refer to Figure 1b, which is an exemplary block diagram of a video decoding system 40 provided in an embodiment of the present application. As shown in Figure 1b, the video decoding system 40 may include an imaging device 41, a video encoder 20, a video decoder 30 (and / or a video encoder / decoder implemented by a processing circuit 46), an antenna 42, one or more processors 43, one or more memory storage devices 44 and / or a display device 45.

[0076] 1b, imaging device 41, antenna 42, processing circuit 46, video encoder 20, video decoder 30, processor 43, memory 44, and / or display device 45 are capable of communicating with one another. In different embodiments, video decoding system 40 may include only video encoder 20 or only video decoder 30.

[0077] In some instances, antenna 42 can be used to transmit or receive an encoded bitstream of video data. Additionally, in some instances, display device 45 can be used to present the video data. Processing circuitry 46 can include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, and the like. Video decoding system 40 can also include an optional processor 43, which can similarly include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, and the like. Furthermore, memory storage 44 can be any type of memory, such as volatile memory (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), etc.) or non-volatile memory (e.g., flash memory, etc.). In a non-limiting example, memory storage 44 can be implemented as cache memory. In other instances, processing circuitry 46 can include memory (e.g., cache memory, etc.) for implementing an image buffer, etc.

[0078] In some examples, video encoder 20 implemented by logic circuitry may include an image buffer (e.g., implemented by processing circuitry 46 or memory storage 44) and a graphics processing unit (e.g., implemented by processing circuitry 46). The graphics processing unit may be communicatively coupled to the image buffer. The graphics processing unit may include video encoder 20 implemented by processing circuitry 46 to implement the various modules discussed with reference to FIG. 2 and / or any other encoder systems or subsystems described herein. Logic circuitry may be used to perform the various operations discussed herein.

[0079] In some examples, the video decoder 30 may be implemented by processing circuitry 46 in a similar manner to implement the various modules discussed with reference to the video decoder 30 of FIG. 3 and / or any other decoder systems or subsystems described herein. In some examples, the logic circuit implementation of the video decoder 30 may include an image buffer (implemented by processing circuitry 46 or memory storage 44) and a graphics processing unit (e.g., implemented by processing circuitry 46). The graphics processing unit may be communicatively coupled to the image buffer. The graphics processing unit may include the video decoder 30 implemented by processing circuitry 46 to implement the various modules discussed with reference to FIG. 3 and / or any other decoder systems or subsystems described herein.

[0080] In some examples, antenna 42 may be used to receive an encoded bitstream of video data. As discussed, the encoded bitstream may include data related to the encoded video frames, indicators, index values, mode selection data, etc., as discussed herein, such as data related to encoding partitions (e.g., transform coefficients or quantized transform coefficients, optional indicators (as discussed), and / or data defining encoding partitions). Video decoding system 40 may also include video decoder 30 coupled to antenna 42 and configured to decode the encoded bitstream. Display device 45 is configured to present the video frames.

[0081] It should be understood that for the examples described herein with reference to video encoder 20, video decoder 30 can be configured to perform the reverse process. With respect to signaling syntax elements, video decoder 30 can be configured to receive and parse such syntax elements and decode the associated video data accordingly. In some examples, video encoder 20 can entropy encode the syntax elements into an encoded video bitstream. In such examples, video decoder 30 can parse such syntax elements and decode the associated video data accordingly.

[0082] For ease of description, the embodiments of the present application are described with reference to the universal video coding (VVC) reference software or the high-efficiency video coding (HEVC) developed by the joint collaboration team on video coding (JCT-VC) of the ITU-T video coding experts group (VCEG) and the ISO / IEC motion picture experts group (MPEG). Those skilled in the art will understand that the embodiments of the present application are not limited to HEVC or VVC.

[0083] Encoders and encoding methods

[0084] As shown in FIG2 , the video encoder 20 includes an input terminal (or input interface) 201, a residual calculation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a loop filter 220, a decoded picture buffer (DPB) 230, a mode selection unit 260, an entropy coding unit 270, and an output terminal (or output interface) 272. The mode selection unit 260 may include an inter-frame prediction unit 244, an intra-frame prediction unit 254, and a segmentation unit 262. The inter-frame prediction unit 244 may include a motion estimation unit and a motion compensation unit (not shown). The video encoder 20 shown in FIG2 may also be referred to as a hybrid video encoder or a video encoder based on a hybrid video codec.

[0085] 2 , the inter-frame prediction unit is a trained target model (also known as a neural network) that processes an input image, image region, or image block to generate a prediction value for the input image block. For example, the neural network for inter-frame prediction receives an input image, image region, or image block and generates a prediction value for the input image, image region, or image block.

[0086] The residual calculation unit 204, the transform processing unit 206, the quantization unit 208, and the mode selection unit 260 constitute the forward signal path of the encoder 20, while the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the buffer 216, the loop filter 220, the decoded picture buffer (DPB) 230, the inter-frame prediction unit 244, and the intra-frame prediction unit 254 constitute the backward signal path of the encoder, where the backward signal path of the encoder 20 corresponds to the signal path of the decoder (see decoder 30 in Figure 3). The inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the loop filter 220, the decoded picture buffer 230, the inter-frame prediction unit 244, and the intra-frame prediction unit 254 also constitute the "internal decoder" of the video encoder 20.

[0087] Images and image segmentation (images and blocks)

[0088] Encoder 20 is operable to receive, via input 201 or the like, an image (or image data) 17, for example, an image from a sequence of images forming a video or video sequence. The received image or image data may also be a pre-processed image (or pre-processed image data) 19. For simplicity, the following description uses image 17. Image 17 may also be referred to as a current image or image to be encoded (particularly when distinguishing the current image from other images in video encoding, such as previously encoded and / or decoded images in the same video sequence, i.e., a video sequence that also includes the current image).

[0089] A (digital) image is, or can be considered to be, a two-dimensional array or matrix of pixels with intensity values. The pixels in the array are also referred to as pixels (or pels, short for picture elements). The number of pixels in the array or image in the horizontal and vertical directions (or axes) determines the image size and / or resolution. To represent color, three color components are typically used, meaning that an image can be represented as or include three pixel arrays. In the RBG format or color space, an image includes corresponding arrays of red, green, and blue pixels. However, in video coding, each pixel is typically represented in a luma / chroma format or color space, such as YCbCr, which includes a luma component indicated by Y (sometimes also indicated by L) and two chroma components, indicated by Cb and Cr. The luma component Y represents the brightness or grayscale level intensity (for example, in grayscale images, both are the same), while the two chroma components (abbreviated as chroma) Cb and Cr represent the chroma or color information components. Accordingly, an image in YCbCr format includes a luma pixel array of luma pixel values ​​(Y) and two chroma pixel arrays of chroma values ​​(Cb and Cr). An image in RGB format can be converted or transformed into YCbCr format, and vice versa, a process also known as color conversion or transformation. If the image is black and white, the image may include only a luma pixel array. Accordingly, the image may be, for example, a luma pixel array in monochrome format or a luma pixel array and two corresponding chroma pixel arrays in 4:2:0, 4:2:2, and 4:4:4 color formats.

[0090] In one embodiment, an embodiment of the video encoder 20 may include an image segmentation unit (not shown in FIG. 2 ) for segmenting the image 17 into a plurality of (typically non-overlapping) image blocks 203. These blocks may also be referred to as root blocks, macroblocks (H.264 / AVC) or coding tree blocks (CTBs), or coding tree units (CTUs) in the H.265 / HEVC and VVC standards. The segmentation unit may be used to use the same block size for all images in a video sequence and a corresponding grid of defined block sizes, or to vary the block size between images or subsets or groups of images, and to segment each image into corresponding blocks.

[0091] In other embodiments, the video encoder may be configured to directly receive a block 203 of the image 17, for example, one, several or all blocks constituting the image 17. The image block 203 may also be referred to as a current image block or an image block to be encoded.

[0092] Like image 17, image block 203 is also or can be considered to be a two-dimensional array or matrix of pixels having intensity values ​​(pixel values), but image block 203 is smaller than image 17. In other words, block 203 may include one pixel array (e.g., a luminance array in the case of monochrome image 17, or a luminance array or chrominance array in the case of a color image), or three pixel arrays (e.g., one luminance array and two chrominance arrays in the case of a color image 17), or any other number and / or type of arrays depending on the color format used. The number of pixels in the horizontal and vertical directions (or axes) of block 203 defines the size of block 203. Accordingly, a block may be an M×N (M columns×N rows) pixel array, or an M×N transform coefficient array, etc.

[0093] In one embodiment, the video encoder 20 shown in FIG. 2 is configured to encode the image 17 block by block, for example, performing encoding and prediction on each block 203 .

[0094] In one embodiment, the video encoder 20 shown in FIG2 may also be configured to partition and / or encode an image using slices (also referred to as video slices), where an image may be partitioned or encoded using one or more slices (typically non-overlapping). Each slice may include one or more blocks (e.g., coding tree units (CTUs)) or one or more groups of blocks (e.g., tiles in the H.265 / HEVC / VVC standard and bricks in the VVC standard).

[0095] In one embodiment, the video encoder 20 shown in Figure 2 can also be used to segment and / or encode an image using slices / coding block groups (also called video coding block groups) and / or coding blocks (also called video coding blocks), where the image can be segmented or encoded using one or more slices / coding block groups (usually non-overlapping), each slice / coding block group may include one or more blocks (e.g., CTUs) or one or more coding blocks, etc., where each coding block can be in a shape such as a rectangle and may include one or more complete or partial blocks (e.g., CTUs).

[0096] Residual calculation

[0097] The residual calculation unit 204 is used to calculate the residual block 205 (the prediction block 265 is described in detail later) based on the image block (or original block) 203 and the prediction block 265 in the following manner: for example, the pixel value of the prediction block 265 is subtracted from the pixel value of the image block 203 pixel by pixel (pixel by pixel) to obtain the residual block 205 in the pixel domain.

[0098] Transform

[0099] The transform processing unit 206 is configured to perform a discrete cosine transform (DCT) or a discrete sine transform (DST) on the pixel values ​​of the residual block 205 to obtain transform coefficients 207 in the transform domain. The transform coefficients 207 may also be referred to as transform residual coefficients, representing the residual block 205 in the transform domain.

[0100] The transform processing unit 206 may be used to apply an integerized approximation of the DCT / DST, such as the transform specified for H.265 / HEVC. This integerized approximation is typically scaled by a factor compared to the orthogonal DCT transform. In order to maintain the norm of the residual block after the forward and inverse transforms, additional scaling factors are used as part of the transform process. The scaling factors are typically selected based on certain constraints, such as whether the scaling factor is a power of 2 for the shift operation, the bit depth of the transform coefficients, a trade-off between accuracy and implementation cost, etc. For example, a specific scaling factor is specified for the inverse transform on the encoder 20 side by the inverse transform processing unit 212 (and for the corresponding inverse transform on the decoder 30 side by, for example, the inverse transform processing unit 312), and correspondingly, a corresponding scaling factor may be specified for the forward transform on the encoder 20 side by the transform processing unit 206.

[0101] In one embodiment, the video encoder 20 (correspondingly, the transform processing unit 206) may be configured to output transform parameters such as one or more transform types, for example, directly output or output after being encoded or compressed by the entropy coding unit 270, such that the video decoder 30 may receive and use the transform parameters for decoding.

[0102] Quantification

[0103] The quantization unit 208 is configured to quantize the transform coefficients 207 by, for example, scalar quantization or vector quantization to obtain quantized transform coefficients 209 . The quantized transform coefficients 209 may also be referred to as quantized residual coefficients 209 .

[0104] The quantization process may reduce the bit depth associated with some or all of the transform coefficients 207. For example, during quantization, an n-bit transform coefficient may be rounded down to an m-bit transform coefficient, where n is greater than m. The degree of quantization may be modified by adjusting a quantization parameter (QP). For example, for scalar quantization, varying degrees of scaling may be applied to achieve finer or coarser quantization. A smaller quantization step size corresponds to finer quantization, while a larger quantization step size corresponds to coarser quantization. The appropriate quantization step size may be indicated by a quantization parameter (QP). For example, the quantization parameter may be an index into a predefined set of appropriate quantization step sizes. For example, a smaller quantization parameter may correspond to fine quantization (a smaller quantization step size), while a larger quantization parameter may correspond to coarse quantization (a larger quantization step size), or vice versa. Quantization may include dividing by the quantization step size, while the corresponding or inverse dequantization performed by the inverse quantization unit 210, etc., may include multiplying by the quantization step size. Embodiments according to some standards, such as HEVC, may be used to determine the quantization step size using the quantization parameter. Generally, the quantization step size may be calculated based on the quantization parameter using a fixed-point approximation of an equation involving division. Additional scaling factors can be introduced for quantization and dequantization to restore the norm of the residual block that may have been modified by the scaling used in the fixed-point approximation of the equations for the quantization step size and quantization parameter. In one exemplary implementation, the scaling of the inverse transform and dequantization can be combined. Alternatively, a custom quantization table can be used and indicated from the encoder to the decoder in the bitstream, etc. Quantization is a lossy operation, where larger quantization step sizes result in greater losses.

[0105] In one embodiment, the video encoder 20 (correspondingly, the quantization unit 208) may be configured to output a quantization parameter (QP), for example, directly or after being encoded or compressed by the entropy coding unit 270, such that the video decoder 30 may receive and use the quantization parameter for decoding.

[0106] Dequantization

[0107] The inverse quantization unit 210 is configured to perform inverse quantization performed by the quantization unit 208 on the quantized coefficients to obtain dequantized coefficients 211. For example, the inverse quantization scheme performed by the quantization unit 208 may be performed according to or using the same quantization step size as the quantization unit 208. The dequantized coefficients 211 may also be referred to as dequantized residual coefficients 211, which correspond to the transform coefficients 207. However, due to the loss caused by quantization, the dequantized coefficients 211 are generally not identical to the transform coefficients.

[0108] Inverse transform

[0109] The inverse transform processing unit 212 is configured to perform the inverse transform of the transform performed by the transform processing unit 206, such as an inverse discrete cosine transform (DCT) or an inverse discrete sine transform (DST), to obtain a reconstructed residual block 213 (or corresponding dequantized coefficients 213) in the pixel domain. The reconstructed residual block 213 may also be referred to as a transform block 213.

[0110] reconstruction

[0111] The reconstruction unit 214 (e.g., the summer 214) is used to add the transform block 213 (i.e., the reconstructed residual block 213) to the prediction block 265 to obtain the reconstructed block 215 in the pixel domain, for example, by adding the pixel point values ​​of the reconstructed residual block 213 and the pixel point values ​​of the prediction block 265.

[0112] Filtering

[0113] The loop filter unit 220 (or simply "loop filter" 220) is used to filter the reconstructed block 215 to obtain a filter block 221, or generally to filter the reconstructed pixels to obtain filtered pixel values. For example, the loop filter unit is used to smoothly perform pixel conversion or improve video quality. The loop filter unit 220 may include one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or one or more other filters, such as an adaptive loop filter (ALF), a noise suppression filter (NSF), or any combination thereof. For example, the loop filter unit 220 may include a deblocking filter, an SAO filter, and an ALF filter. The order of the filtering process can be a deblocking filter, an SAO filter, and an ALF filter. For another example, a process called luma mapping with chroma scaling (LMCS) (i.e., an adaptive in-loop reshaper) is added. This process is performed before deblocking. For another example, the deblocking filtering process can also be applied to internal sub-block edges, such as affine sub-block edges, ATMVP sub-block edges, sub-block transform (SBT) edges, and intra sub-partition (ISP) edges. Although the loop filter unit 220 is shown as a loop filter in FIG2 , in other configurations, the loop filter unit 220 can be implemented as a post-loop filter. The filter block 221 can also be referred to as a filter reconstruction block 221.

[0114] In one embodiment, the video encoder 20 (correspondingly, the loop filter unit 220) may be configured to output loop filter parameters (e.g., SAO filter parameters, ALF filter parameters, or LMCS parameters), for example, directly or after being entropy-encoded by the entropy coding unit 270, such that the decoder 30 may receive and use the same or different loop filter parameters for decoding.

[0115] Decoded Image Buffer

[0116] The decoded picture buffer (DPB) 230 may be a reference picture memory that stores reference picture data for use by the video encoder 20 when encoding video data. The DPB 230 may be formed from any of a variety of memory devices, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. The decoded picture buffer 230 may be used to store one or more filter blocks 221. The decoded picture buffer 230 may also be used to store other previously filtered blocks, such as previously reconstructed and filtered blocks 221, for the same current picture or a different picture, such as a previously reconstructed picture, and may provide a complete previously reconstructed, i.e., decoded picture (and corresponding reference blocks and pixels) and / or a partially reconstructed current picture (and corresponding reference blocks and pixels), for example, for inter-frame prediction. The decoded image buffer 230 may also be used to store one or more unfiltered reconstructed blocks 215, or generally to store unfiltered reconstructed pixels, for example, reconstructed blocks 215 that have not been filtered by the loop filtering unit 220, or reconstructed blocks or reconstructed pixels that have not undergone any other processing.

[0117] Mode selection (segmentation and prediction)

[0118] The mode selection unit 260 includes a segmentation unit 262, an inter-frame prediction unit 244, and an intra-frame prediction unit 254, which are configured to receive or obtain original image data, such as an original block 203 (current block 203 of the current image 17) and reconstructed image data, such as filtered and / or unfiltered reconstructed pixels or reconstructed blocks of the same (current) image and / or one or more previously decoded images, from the decoded image buffer 230 or other buffer (e.g., a column buffer, not shown in FIG. 2). The reconstructed image data is used as reference image data required for prediction, such as inter-frame prediction or intra-frame prediction, to obtain a prediction block 265 or a prediction value 265.

[0119] The mode selection unit 260 may be used to determine or select a partitioning for the current block (including no partitioning) and prediction mode (eg, intra-frame or inter-frame prediction mode), generate a corresponding prediction block 265 , and calculate the residual block 205 and reconstruct the reconstruction block 215 .

[0120] In one embodiment, the mode selection unit 260 may be configured to select a segmentation and prediction mode (e.g., from prediction modes supported or available by the mode selection unit 260) that provides the best match or minimum residual (minimum residual means better compression during transmission or storage), or provides minimum signaling overhead (minimum signaling overhead means better compression during transmission or storage), or simultaneously considers or balances both. The mode selection unit 260 may be configured to determine the segmentation and prediction mode based on rate distortion optimization (RDO), i.e., select the prediction mode that provides the minimum rate distortion optimization. Terms such as "best," "lowest," and "optimal" herein do not necessarily refer to "best," "lowest," or "optimal" overall, but may also refer to situations where termination or selection criteria are met, e.g., values ​​exceeding or falling below a threshold or other limit may result in a "suboptimal selection" but reduce complexity and processing time.

[0121] In other words, the partitioning unit 262 may be configured to partition an image in a video sequence into a sequence of coding tree units (CTUs), the CTU 203 being further partitioned into smaller block portions or sub-blocks (again forming blocks), e.g., by iteratively using quad-tree partitioning (QT), binary-tree partitioning (BT), or triple-tree partitioning (TT), or any combination thereof, and for, e.g., performing prediction on each of the block portions or sub-blocks, wherein the mode selection comprises selecting a tree structure for partitioning the block 203 and selecting a prediction mode to be applied to each of the block portions or sub-blocks.

[0122] The segmentation (eg, performed by segmentation unit 262) and prediction processes (eg, performed by inter-prediction unit 244 and intra-prediction unit 254) performed by video encoder 20 are described in detail below.

[0123] segmentation

[0124] The partitioning unit 262 can partition (or divide) an image block (or CTU) 203 into smaller parts, such as square or rectangular blocks. For an image with three pixel arrays, a CTU consists of N×N luminance pixel blocks and two corresponding chrominance pixel blocks. The maximum allowed size of a luminance block in a CTU is specified as 128×128 in the developing Universal Video Coding (VVC) standard, but may be specified to a value other than 128×128, such as 256×256, in the future. The CTUs of an image can be grouped / collected into slices / coding block groups, coding blocks, or bricks. A coding block covers a rectangular area of ​​an image and can be divided into one or more bricks. A brick consists of multiple CTU rows within a coding block. A coding block that is not partitioned into multiple bricks can be called a brick. However, a brick is a true subset of a coding block and is therefore not called a coding block. VVC supports two coding block group modes: raster scan slice / coding block group mode and rectangular slice mode. In raster scan CBG mode, a slice / CBG contains a sequence of CBs from a raster scan of the CBs of an image. In rectangular slice mode, a slice contains multiple bricks of an image that together form a rectangular region of the image. The bricks within a rectangular slice are arranged in the slice's brick raster scan order. These smaller blocks (also called sub-blocks) can be further split into smaller parts. This is also known as tree partitioning or hierarchical tree partitioning, where a root block at, for example, root tree level 0 (hierarchy level 0, depth 0) can be recursively split into two or more blocks at the next lower tree level, such as nodes at tree level 1 (hierarchy level 1, depth 1). These blocks can be further split into two or more blocks at the next lower level, such as nodes at tree level 2 (hierarchy level 2, depth 2), and so on, until the partitioning is completed (because the end criteria are met, such as reaching the maximum tree depth or minimum block size). Blocks that are not further split are also called leaf blocks or leaf nodes of the tree. A tree divided into two parts is called a binary tree (BT), a tree divided into three parts is called a ternary tree (TT), and a tree divided into four parts is called a quadtree (QT).

[0125] For example, a coding tree unit (CTU) may be or include a CTB for luma pixels, two corresponding CTBs for chroma pixels of an image with a three-pixel array, or a CTB for pixels of a monochrome image, or a CTB for pixels of an image encoded using three independent color planes and syntax structures for encoding pixels. Accordingly, a coding tree block (CTB) may be an N×N block of pixels, where N may be set to a value such that a component is divided into CTBs, which is known as partitioning. A coding unit (CU) may be or include a coding block of luma pixels, two corresponding coding blocks for chroma pixels of an image with a three-pixel array, or a coding block of pixels of a monochrome image, or a coding block of pixels of an image encoded using three independent color planes and syntax structures for encoding pixels. Accordingly, a coding block (CB) may be an M×N block of pixels, where M and N may be set to a value such that a CTB is divided into coding blocks, which is known as partitioning.

[0126] For example, in an embodiment, according to HEVC, a coding tree unit (CTU) can be divided into multiple CUs using a quadtree structure represented as a coding tree. A decision is made at the leaf-CU level whether to use inter-frame (temporal) prediction or intra-frame (spatial) prediction to encode an image region. Each leaf-CU can be further divided into one, two, or four PUs according to the PU partition type. The same prediction process is used within a PU, and relevant information is transmitted to the decoder in units of PUs. After applying the prediction process according to the PU partition type to obtain a residual block, the leaf-CU can be divided into transform units (TUs) according to other quadtree structures similar to the coding tree for the CU.

[0127] For example, in an embodiment, according to the latest video coding standard currently under development (called Versatile Video Coding (VVC), a combined quadtree of nested multi-type trees (such as binary trees and ternary trees) is used to divide the segment structure for partitioning the coding tree unit. In the coding tree structure within the coding tree unit, the CU can be square or rectangular. For example, the coding tree unit (CTU) is first partitioned by the quadtree structure. The quadtree leaf nodes are further partitioned by the multi-type tree structure. The multi-type tree structure has four partition types: vertical binary tree partition (SPLIT_BT_VER), horizontal binary tree partition (SPLIT_BT_HOR), vertical ternary tree partition The tree nodes of the multi-type tree are called coding units (CUs), unless the CU is too large for the maximum transform length, in which case such segmentation is used for prediction and transform processing without any other splitting. In most cases, this means that the block sizes of CUs, PUs, and TUs in the coding block structure of the quadtree nested multi-type tree are the same. This exception occurs when the maximum supported transform length is less than the width or height of the color components of the CU. VVC has developed a unique signaling mechanism for the split partitioning information in the coding structure with quadtree nested multi-type trees. In the signaling mechanism, the coding The tree unit (CTU) as the root of the quadtree is first split by the quadtree structure. Then each quadtree leaf node (when large enough) is further split into a multi-type tree structure. In the multi-type tree structure, the first flag (mtt_split_cu_flag) is used to indicate whether the node is further split. When the node is further split, the second flag (mtt_split_cu_vertical_flag) is used to indicate the division direction, and the third flag (mtt_split_cu_binary_flag) is used to indicate whether the division is a binary tree division or a ternary tree division. According to mtt_split_c The values ​​of u_vertical_flag and mtt_split_cu_binary_flag allow the decoder to derive the multi-type tree split mode (MttSplitMode) of the CU based on predefined rules or tables. It should be noted that for certain designs, such as the 64×64 luma block and 32×32 chroma pipeline design in the VVC hardware decoder, TT splitting is not allowed when the width or height of the luma coding block is greater than 64. TT splitting is also not allowed when the width or height of the chroma coding block is greater than 32. The pipeline design divides the image into multiple virtual pipeline data units (VPDUs), each of which is defined as a non-overlapping unit in the image. In the hardware decoder, consecutive VPDUs are processed simultaneously in multiple pipeline stages. In most pipeline stages, the VPDU size is roughly proportional to the buffer size, so it is desirable to keep the VPDU small.In most hardware decoders, the VPDU size can be set to the maximum transform block (TB) size. However, in VVC, the ternary tree (TT) and binary tree (BT) partitioning may increase the VPDU size.

[0128] In addition, it should be noted that when a part of the tree node block exceeds the bottom or the right boundary of the image, the tree node block is forcibly divided until all pixels of each coding CU are located within the image boundary.

[0129] For example, the intra sub-partitions (ISP) tool may vertically or horizontally divide the luma intra prediction block into two or four sub-partitions according to the block size.

[0130] In one example, mode select unit 260 of video encoder 20 may be used to perform any combination of the segmentation techniques described above.

[0131] As described above, the video encoder 20 is configured to determine or select the best or optimal prediction mode from a (predetermined) prediction mode set. The prediction mode set may include, for example, an intra-frame prediction mode and / or an inter-frame prediction mode.

[0132] Intra-frame prediction

[0133] The intra prediction mode set may include 35 different intra prediction modes, for example, non-directional modes like DC (or mean) mode and planar mode, or directional modes as defined in HEVC, or may include 67 different intra prediction modes, for example, non-directional modes like DC (or mean) mode and planar mode, or directional modes as defined in VVC. For example, several traditional angle intra prediction modes are adaptively replaced by wide-angle intra prediction modes for non-square blocks defined in VVC. For another example, in order to avoid the division operation of DC prediction, only the longer side is used to calculate the average value of the non-square block. In addition, the intra prediction result of the planar mode can also be modified using the position dependent intra prediction combination (PDPC) method.

[0134] The intra prediction unit 254 is configured to generate an intra prediction block 265 by reconstructing pixels in adjacent blocks of the same current image according to an intra prediction mode in the intra prediction mode set.

[0135] The intra-frame prediction unit 254 (or generally the mode selection unit 260) is also used to output intra-frame prediction parameters (or generally information indicating the selected intra-frame prediction mode for the block) in the form of syntax elements 266 to the entropy coding unit 270 for inclusion in the encoded image data 21, so that the video decoder 30 can perform operations, such as receiving and using the prediction parameters for decoding.

[0136] The intra prediction modes in HEVC include DC prediction mode, plane prediction mode and 33 angular prediction modes, with a total of 35 candidate prediction modes. The current block can use the pixels of the reconstructed image blocks on the left and above as references for intra prediction. The image blocks in the surrounding area of ​​the current block used for intra prediction of the current block are called reference blocks, and the pixels in the reference blocks are called reference pixels. Among the 35 candidate prediction modes, the DC prediction mode is applicable to areas with flat textures in the current block. All pixels in this area use the average value of the reference pixels in the reference block as prediction; the plane prediction mode is applicable to image blocks with smoothly changing textures. The current block that meets this condition uses the reference pixels in the reference block for bilinear interpolation as the prediction of all pixels in the current block; the angular prediction mode uses the characteristic that the texture of the current block is highly correlated with the texture of the adjacent reconstructed image blocks, and copies the values ​​of the reference pixels in the corresponding reference block along a certain angle as the prediction of all pixels in the current block.

[0137] The HEVC encoder selects an optimal intra-frame prediction mode for the current block from 35 candidate prediction modes and writes this optimal intra-frame prediction mode into the video bitstream. To improve the coding efficiency of intra-frame prediction, the encoder / decoder derives three most probable modes from the optimal intra-frame prediction modes of the reconstructed image blocks in the surrounding area using intra-frame prediction. If the optimal intra-frame prediction mode selected for the current block is one of these three most probable modes, a first index is encoded to indicate that the selected optimal intra-frame prediction mode is one of these three most probable modes; if the selected optimal intra-frame prediction mode is not one of these three most probable modes, a second index is encoded to indicate that the selected optimal intra-frame prediction mode is one of the other 32 modes (other than the aforementioned three most probable modes among the 35 candidate prediction modes). The HEVC standard uses a 5-bit fixed-length code as the aforementioned second index.

[0138] The HEVC encoder derives the three most probable modes by selecting the optimal intra-frame prediction mode of the image block to the left and the image block above the current block and adding them to a set. If these two optimal intra-frame prediction modes are the same, only one is retained in the set. If these two optimal intra-frame prediction modes are the same and both are angular prediction modes, two angular prediction modes adjacent to the angular direction are selected and added to the set. Otherwise, the planar prediction mode, the DC mode, and the vertical prediction mode are selected and added to the set in sequence until the number of modes in the set reaches three.

[0139] After the HEVC decoder performs entropy decoding on the bitstream, it obtains the mode information of the current block, which includes an indicator indicating whether the optimal intra-frame prediction mode of the current block is among the three most probable modes, and the index of the optimal intra-frame prediction mode of the current block among the three most probable modes or the index of the optimal intra-frame prediction mode of the current block among the other 32 modes.

[0140] Inter-frame prediction

[0141] In a possible implementation, the set of inter-prediction modes depends on the available reference picture (i.e., at least part of the previously decoded picture stored in the DBP 230 as mentioned above) and other inter-prediction parameters, e.g., on whether the entire reference picture is used or only a part of the reference picture is used, e.g., a search window area around the area of ​​the current block, to search for the best matching reference block, and / or on whether pixel interpolation such as half-pixel, quarter-pixel and / or 1 / 16 interpolation is performed, for example.

[0142] In addition to the above prediction modes, skip mode and / or direct mode may also be employed.

[0143] For example, in extended merge prediction, the merge candidate list of this mode consists of the following five candidate types in order: spatial MVP from spatially neighboring CUs, temporal MVP from collocated CUs, history-based MVP from the FIFO table, pairwise average MVP, and zero MV. Decoder-side motion vector refinement (DMVR) based on bilateral matching can be used to increase the accuracy of the MV in merge mode. Merge mode with MVD (MMVD) is derived from merge mode with motion vector difference. The MMVD flag is sent immediately after the skip flag and merge flag to specify whether the CU uses MMVD mode. A CU-level adaptive motion vector resolution (AMVR) scheme can be used. AMVR supports encoding the CU's MVD with different precisions. The MVD of the current CU is adaptively selected based on the prediction mode of the current CU. When the CU is encoded in merge mode, the combined inter / intra prediction (CIIP) mode can be applied to the current CU. The CIIP prediction is obtained by weighted averaging the inter and intra prediction signals. For affine motion compensation prediction, the affine motion field of the block is described by the motion information of 2 control points (4 parameters) or 3 control points (6 parameters) motion vectors. Subblock-based temporal motion vector prediction (SbTMVP) is similar to the temporal motion vector prediction (TMVP) in HEVC, but it predicts the motion vector of the sub-CU within the current CU. Bidirectional optical flow (BDOF), formerly known as BIO, is a simplified version that reduces calculations, especially in terms of the number of multiplications and the size of the multipliers. In the triangle partitioning mode, the CU is evenly divided into two triangular parts using diagonal partitioning and anti-diagonal partitioning. In addition, the bidirectional prediction mode is extended based on the simple average to support the weighted average of the two prediction signals.

[0144] The inter-frame prediction unit 244 may include a motion estimation (ME) unit and a motion compensation (MC) unit (both not shown in FIG. 2 ). The motion estimation unit may be configured to receive or obtain an image block 203 (the current image block 203 of the current image 17 ) and a decoded image 231 , or at least one or more previously reconstructed blocks, e.g., reconstructed blocks of one or more other / different previously decoded images 231 , to perform motion estimation. For example, a video sequence may include the current image and the previously decoded image 231 , or in other words, the current image and the previously decoded image 231 may be part of or form a sequence of images forming the video sequence.

[0145] For example, the encoder 20 may be configured to select a reference block from a plurality of reference blocks of the same or different images among a plurality of other images, and provide the reference image (or reference image index) and / or the offset (spatial offset) between the position (x, y coordinates) of the reference block and the position of the current block as an inter-frame prediction parameter to the motion estimation unit. This offset is also referred to as a motion vector (MV).

[0146] The motion compensation unit is configured to obtain, for example, receive, inter-frame prediction parameters and perform inter-frame prediction based on or using the inter-frame prediction parameters to obtain an inter-frame prediction block 246. The motion compensation performed by the motion compensation unit may include extracting or generating a prediction block based on a motion / block vector determined by motion estimation, and may also include performing interpolation with sub-pixel accuracy. Interpolation filtering can generate pixel points of other pixels from pixel points of known pixels, thereby potentially increasing the number of candidate prediction blocks that can be used to encode the image block. Upon receiving a motion vector corresponding to a PU of the current image block, the motion compensation unit may locate the prediction block pointed to by the motion vector in one of the reference picture lists.

[0147] The motion compensation unit may also generate syntax elements associated with blocks and video slices for use by video decoder 30 when decoding image blocks of a video slice. In addition to, or in lieu of, slices and corresponding syntax elements, coding block groups and / or coding blocks and corresponding syntax elements may be generated or used.

[0148] In the process of obtaining a candidate motion vector list in an advanced motion vector prediction (AMVP) mode, motion vectors (MVs) that can be added to the candidate motion vector list as alternatives include MVs of spatially and temporally adjacent image blocks of a current block, wherein the MVs of spatially adjacent image blocks can further include the MVs of a left candidate image block located to the left of the current block and the MVs of an upper candidate image block located above the current block. For example, please refer to FIG. 4 , which is an exemplary schematic diagram of candidate image blocks provided in an embodiment of the present application. As shown in FIG. 4 , the set of left candidate image blocks includes {A0, A1}, the set of upper candidate image blocks includes {B0, B1, B2}, and the set of temporally adjacent candidate image blocks includes {C, T}. All three sets can be added to the candidate motion vector list as alternatives. However, according to existing coding standards, the maximum length of the candidate motion vector list for AMVP is 2. Therefore, it is necessary to determine the MVs of up to two image blocks to be added to the candidate motion vector list from the three sets according to a prescribed order. The order may be to give priority to the set of candidate image blocks {A0, A1} to the left of the current block (consider A0 first, and then consider A1 if A0 is not available), then consider the set of candidate image blocks {B0, B1, B2} above the current block (consider B0 first, and then consider B1 if B0 is not available, and then consider B2 if B1 is not available), and finally consider the set of candidate image blocks {C, T} that are adjacent to the current block in the time domain (consider T first, and then consider C if T is not available).

[0149] After obtaining the candidate motion vector list, the optimal MV is determined from the candidate motion vector list using the rate distortion cost (RD cost), and the candidate motion vector with the smallest RD cost is used as the motion vector predictor (MVP) of the current block. The rate distortion cost is calculated using the following formula:

[0150] J=SAD+λR

[0151] Wherein, J represents RD cost, SAD is the sum of absolute differences (SAD) between the pixel values ​​of the predicted block obtained after motion estimation using the candidate motion vector and the pixel values ​​of the current block, R represents the bit rate, and λ represents the Lagrange multiplier.

[0152] The encoder passes the index of the determined MVP in the candidate motion vector list to the decoder. Furthermore, a motion search can be performed within a neighborhood centered on the MVP to obtain the actual motion vector of the current block. The encoder calculates the motion vector difference (MVD) between the MVP and the actual motion vector and also passes the MVD to the decoder. The decoder parses the index, finds the corresponding MVP in the candidate motion vector list based on the index, parses the MVD, and adds the MVD to the MVP to obtain the actual motion vector of the current block.

[0153] When obtaining the candidate motion information list in Merge mode, the motion information that can be added to the candidate motion information list includes the motion information of spatially or temporally adjacent image blocks to the current block. For spatially and temporally adjacent image blocks, refer to Figure 4. The spatially adjacent candidate motion information in the candidate motion information list comes from five spatially adjacent blocks (A0, A1, B0, B1, and B2). If the spatially adjacent blocks are unavailable or are intra-predicted, their motion information is not added to the candidate motion information list. The temporal candidate motion information for the current block is obtained by scaling the MV of the corresponding block in the reference frame based on the picture order count (POC) of the reference frame and the current frame. The block at position T in the reference frame is first determined to be available. If not, the block at position C is selected. After obtaining the candidate motion information list, the optimal motion information from the candidate motion information list is determined using the RD cost as the motion information for the current block. The encoder transmits the index of the optimal motion information in the candidate motion information list (denoted as the merge index) to the decoder.

[0154] Entropy Coding

[0155] The entropy coding unit 270 is configured to apply an entropy coding algorithm or scheme (e.g., a variable length coding (VLC) scheme, a context adaptive VLC (CALVC) scheme, an arithmetic coding scheme, a binarization algorithm, context adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or other entropy coding methods or techniques) to the quantized residual coefficients 209, inter-frame prediction parameters, intra-frame prediction parameters, loop filter parameters, and / or other syntax elements, resulting in coded image data 21 that can be output via an output terminal 272 in the form of a coded bitstream 21, etc., so that the video decoder 30, etc. can receive and use the parameters for decoding. The coded bitstream 21 can be transmitted to the video decoder 30 or stored in a memory for later transmission or retrieval by the video decoder 30.

[0156] Other structural variations of the video encoder 20 may be used to encode the video stream. For example, a non-transform-based encoder 20 may directly quantize the residual signal without a transform processing unit 206 for certain blocks or frames. In another implementation, the encoder 20 may have the quantization unit 208 and the inverse quantization unit 210 combined into a single unit.

[0157] Decoder and decoding method

[0158] As shown in FIG3 , a video decoder 30 is configured to receive coded image data 21 (e.g., coded bitstream 21) encoded by, for example, an encoder 20, and generate a decoded image 331. The coded image data or bitstream includes information used to decode the coded image data, such as data representing image blocks of a coded video slice (and / or coding block group or coding block) and related syntax elements.

[0159] 3 , decoder 30 includes an entropy decoding unit 304, an inverse quantization unit 310, an inverse transform processing unit 312, a reconstruction unit 314 (e.g., summer 314), a loop filter 320, a decoded picture buffer (DBP) 330, a mode application unit 360, an inter-prediction unit 344, and an intra-prediction unit 354. Inter-prediction unit 344 may be or include a motion compensation unit. In some examples, video decoder 30 may perform a decoding process that is generally the reverse of the encoding process described with reference to video encoder 100 of FIG. 2 .

[0160] As described above with respect to encoder 20, inverse quantization unit 210, inverse transform processing unit 212, reconstruction unit 214, loop filter 220, decoded picture buffer DPB 230, inter-frame prediction unit 344, and intra-frame prediction unit 354 also constitute the "built-in decoder" of video encoder 20. Accordingly, inverse quantization unit 310 may be functionally identical to inverse quantization unit 110, inverse transform processing unit 312 may be functionally identical to inverse transform processing unit 122, reconstruction unit 314 may be functionally identical to reconstruction unit 214, loop filter 320 may be functionally identical to loop filter 220, and decoded picture buffer 330 may be functionally identical to decoded picture buffer 230. Therefore, the explanations of the corresponding units and functions of video encoder 20 apply accordingly to the corresponding units and functions of video decoder 30.

[0161] Entropy decoding

[0162] The entropy decoding unit 304 is configured to parse the bitstream 21 (or generally, the encoded image data 21) and perform entropy decoding on the encoded image data 21 to obtain quantization coefficients 309 and / or decoded coding parameters (not shown in FIG. 3 ), such as any or all of inter-frame prediction parameters (e.g., reference image indices and motion vectors), intra-frame prediction parameters (e.g., intra-frame prediction modes or indices), transform parameters, quantization parameters, loop filter parameters, and / or other syntax elements. The entropy decoding unit 304 may be configured to apply a decoding algorithm or scheme corresponding to the coding scheme of the entropy coding unit 270 of the encoder 20. The entropy decoding unit 304 may also be configured to provide inter-frame prediction parameters, intra-frame prediction parameters, and / or other syntax elements to the mode application unit 360, as well as to provide other parameters to other units of the decoder 30. The video decoder 30 may receive syntax elements at the video slice and / or video block level. In addition to, or in lieu of, slices and corresponding syntax elements, coding block groups and / or coding blocks and corresponding syntax elements may also be received or used.

[0163] In some implementations, the video decoder 30 may include multiple entropy decoding units 304. For example, in a privacy protection scenario, the bitstream obtained by encoding the video image includes a private bitstream and a non-private bitstream. Therefore, the video decoder 30 may include two entropy decoding units 304, where one entropy decoding unit 304 is used to parse the private bitstream in the bitstream, and the other entropy decoding unit 304 is used to parse the non-private bitstream in the bitstream.

[0164] Dequantization

[0165] The inverse quantization unit 310 may be configured to receive a quantization parameter (QP) (or generally information related to inverse quantization) and quantization coefficients from the encoded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304), and inverse quantize the decoded quantization coefficients 309 based on the quantization parameter to obtain inverse quantization coefficients 311. The inverse quantization coefficients 311 may also be referred to as transform coefficients 311. The inverse quantization process may include using the quantization parameter calculated by the video encoder 20 for each video block in the video slice to determine a degree of quantization, and thus a degree of inverse quantization to be performed.

[0166] Inverse transform

[0167] The inverse transform processing unit 312 may be configured to receive the dequantized coefficients 311, also referred to as transform coefficients 311, and apply a transform to the dequantized coefficients 311 to obtain a reconstructed residual block 213 in the pixel domain. The reconstructed residual block 213 may also be referred to as a transform block 313. The transform may be an inverse transform, such as an inverse DCT, an inverse DST, an inverse integer transform, or a conceptually similar inverse transform process. The inverse transform processing unit 312 may also be configured to receive transform parameters or corresponding information from the encoded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304) to determine the transform to be applied to the dequantized coefficients 311.

[0168] reconstruction

[0169] The reconstruction unit 314 (eg, summer 314 ) is configured to add the reconstructed residual block 313 to the prediction block 365 to obtain the reconstructed block 315 in the pixel domain, eg, by adding the pixel values ​​of the reconstructed residual block 313 and the pixel values ​​of the prediction block 365 .

[0170] Filtering

[0171] The loop filter unit 320 (in or after the encoding loop) is used to filter the reconstructed block 315 to obtain a filter block 321, thereby smoothly performing pixel conversion or improving video quality. The loop filter unit 320 may include one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or one or more other filters, such as an adaptive loop filter (ALF), a noise suppression filter (NSF), or any combination. For example, the loop filter unit 220 may include a deblocking filter, an SAO filter, and an ALF filter. The order of the filtering process can be a deblocking filter, an SAO filter, and an ALF filter. For another example, a process called luma mapping with chroma scaling (LMCS) (i.e., an adaptive in-loop reshaper) is added. This process is performed before deblocking. For another example, the deblocking filtering process can also be applied to internal sub-block edges, such as affine sub-block edges, ATMVP sub-block edges, sub-block transform (SBT) edges, and intra sub-partition (ISP) edges. Although the loop filter unit 320 is shown as a loop filter in Figure 3, in other configurations, the loop filter unit 320 can be implemented as a post-loop filter.

[0172] Decoded Image Buffer

[0173] The decoded video blocks 321 of one picture are then stored in a decoded picture buffer 330 which stores the decoded picture 331 as a reference picture for subsequent motion compensation of other pictures and / or for respective output displays.

[0174] The decoder 30 is used to output the decoded image 311 through the output terminal 312, etc., for display to the user or for the user to view.

[0175] predict

[0176] The inter-frame prediction unit 344 may be functionally identical to the inter-frame prediction unit 244 (particularly the motion compensation unit), and the intra-frame prediction unit 354 may be functionally identical to the inter-frame prediction unit 254 and may determine the partitioning or segmentation and perform prediction based on the segmentation and / or prediction parameters or corresponding information received from the coded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304). The mode application unit 360 may be configured to perform prediction (intra-frame or inter-frame prediction) for each block based on the reconstructed image, block, or corresponding pixel point (filtered or unfiltered), resulting in a prediction block 365.

[0177] When the video slice is encoded as an intra-coded (I) slice, the intra-prediction unit 354 in the mode application unit 360 is configured to generate a prediction block 365 for the image block of the current video slice based on the indicated intra-prediction mode and data from previously decoded blocks of the current image. When the video image is encoded as an inter-coded (i.e., B or P) slice, the inter-prediction unit 344 (e.g., a motion compensation unit) in the mode application unit 360 is configured to generate a prediction block 365 for the video block of the current video slice based on the motion vector and other syntax elements received from the entropy decoding unit 304. For inter-prediction, these prediction blocks can be generated from one of the reference pictures in one of the reference picture lists. Video decoder 30 can construct reference frame list 0 and list 1 using a default construction technique based on the reference pictures stored in DPB 330. The same or similar processes may be applied to embodiments of coding block groups (e.g., video coding block groups) and / or coding blocks (e.g., video coding blocks) in addition to or instead of slices (e.g., video slices), e.g., video may be encoded using I, P, or B coding block groups and / or coding blocks.

[0178] Mode application unit 360 is configured to determine prediction information for video blocks of a current video slice by parsing motion vectors and other syntax elements, and to use the prediction information to generate a prediction block for the current video block being decoded. For example, mode application unit 360 uses received syntax elements to determine a prediction mode (e.g., intra prediction or inter prediction) used to encode the video blocks of the video slice, an inter-prediction slice type (e.g., a B slice, a P slice, or a GPB slice), construction information for one or more reference picture lists for the slice, a motion vector for each inter-coded video block in the slice, an inter-prediction state for each inter-coded video block in the slice, and other information to decode the video blocks within the current video slice. In addition to or in lieu of slices (e.g., video slices), the same or similar processes may be applied to embodiments of coding block groups (e.g., video coding block groups) and / or coding blocks (e.g., video coding blocks), for example, video may be encoded using I, P, or B coding block groups and / or coding blocks.

[0179] In one embodiment, the video decoder 30 of FIG3 may also be configured to partition and / or decode an image using slices (also referred to as video slices), where an image may be partitioned or decoded using one or more (typically non-overlapping) slices. Each slice may include one or more blocks (e.g., CTUs) or one or more groups of blocks (e.g., coding blocks in the H.265 / HEVC / VVC standard and bricks in the VVC standard).

[0180] In one embodiment, the video decoder 30 shown in Figure 3 can also be used to segment and / or decode an image using slices / coding block groups (also called video coding block groups) and / or coding blocks (also called video coding blocks), where the image can be segmented or decoded using one or more slices / coding block groups (usually non-overlapping), each slice / coding block group may include one or more blocks (e.g., CTUs) or one or more coding blocks, etc., where each coding block can be in a shape such as a rectangle and may include one or more complete or partial blocks (e.g., CTUs).

[0181] Other variations of the video decoder 30 may be used to decode the encoded image data 21. For example, the decoder 30 may generate an output video stream without the loop filter unit 320. For example, a non-transform-based decoder 30 may directly inverse quantize the residual signal without the inverse transform processing unit 312 for certain blocks or frames. In another implementation, the video decoder 30 may have the inverse quantization unit 310 and the inverse transform processing unit 312 combined into a single unit.

[0182] It should be understood that the processing result of the current step can be further processed in the encoder 20 and the decoder 30 and then output to the next step. For example, after interpolation filtering, motion vector derivation, or loop filtering, the processing result of interpolation filtering, motion vector derivation, or loop filtering can be further operated on, such as clipping or shifting operations.

[0183] It should be noted that further operations can be performed on the derived motion vector of the current block (including but not limited to control point motion vectors in affine mode, sub-block motion vectors in affine, planar, ATMVP modes, temporal motion vectors, etc.). For example, the value of the motion vector can be limited to a predefined range based on the representation bit of the motion vector. If the representation bit of the motion vector is bitDepth, the range is -2^(bitDepth-1) to 2^(bitDepth-1)-1, where "^" represents a power. For example, if bitDepth is set to 16, the range is -32768 to 32767; if bitDepth is set to 18, the range is -131072 to 131071. For example, the value of the derived motion vector (e.g., the MVs of four 4×4 sub-blocks in an 8×8 block) is limited so that the maximum difference between the integer parts of the above four 4×4 sub-block MVs does not exceed N pixels, for example, not more than 1 pixel. Two methods of limiting motion vectors based on bitDepth are provided here.

[0184] Although the above embodiments primarily describe video coding, it should be noted that embodiments of the decoding system 10, encoder 20, and decoder 30, as well as other embodiments described herein, may also be used for still image processing or coding, i.e., processing or coding a single image in a video codec that is independent of any previous or subsequent images. In general, if image processing is limited to a single image 17, the inter-frame prediction unit 244 (encoder) and the inter-frame prediction unit 344 (decoder) may not be available. All other functionalities (also referred to as tools or techniques) of the video encoder 20 and video decoder 30, such as residual calculation 204 / 304, transform 206, quantization 208, inverse quantization 210 / 310, (inverse) transform 212 / 312, segmentation 262 / 362, intra-frame prediction 254 / 354, and / or loop filtering 220 / 320, entropy coding 270, and entropy decoding 304, may also be used for still image processing.

[0185] Please refer to Figure 5, which is an exemplary block diagram of a video decoding device 500 provided in an embodiment of the present application. Video decoding device 500 is suitable for implementing the disclosed embodiments described herein. In one embodiment, video decoding device 500 can be a decoder, such as the video decoder 30 in Figure 1a, or an encoder, such as the video encoder 20 in Figure 1a.

[0186] Video decoding device 500 includes: an input port 510 (or input port 510) and a receiver unit (Rx) 520 for receiving data; a processor, logic unit, or central processing unit (CPU) 530 for processing data; for example, processor 530 may be a neural network processor 530; a transmitter unit (Tx) 540 and an output port 550 (or output port 550) for transmitting data; and a memory 560 for storing data. Video decoding device 500 may also include optical-to-electrical (OE) components and electrical-to-optical (EO) components coupled to input port 510, receiver unit 520, transmitter unit 540, and output port 550 for outputting or transmitting optical or electrical signals.

[0187] The processor 530 is implemented in hardware and software. The processor 530 can be implemented as one or more processor chips, cores (e.g., multi-core processors), FPGAs, ASICs, and DSPs. The processor 530 communicates with the input port 510, the receiving unit 520, the transmitting unit 540, the output port 550, and the memory 560. The processor 530 includes a decoding module 570 (e.g., a neural network-based decoding module 570). The decoding module 570 implements the embodiments disclosed above. For example, the decoding module 570 performs, processes, prepares, or provides various encoding operations. Therefore, the decoding module 570 provides substantial improvements to the functionality of the video decoding device 500 and affects the switching of the video decoding device 500 to different states. Alternatively, the decoding module 570 is implemented by instructions stored in the memory 560 and executed by the processor 530.

[0188] Memory 560 includes one or more disks, tape drives, and solid-state drives and can be used as overflow data storage for storing programs when such programs are selected for execution, and for storing instructions and data read during program execution. Memory 560 can be volatile and / or non-volatile and can be read-only memory (ROM), random access memory (RAM), ternary content-addressable memory (TCAM), and / or static random-access memory (SRAM).

[0189] Please refer to FIG. 6 , which is an exemplary block diagram of an apparatus 600 provided in an embodiment of the present application. The apparatus 600 may be used as either or both of the source device 12 and the destination device 14 in FIG. 1 a .

[0190] The processor 602 in the apparatus 600 may be a central processing unit (CPU). Alternatively, the processor 602 may be any other type of device or devices, now available or developed in the future, capable of manipulating or processing information. While the disclosed implementations may be implemented using a single processor, such as the processor 602 shown in FIG. 6 , using more than one processor may provide greater speed and efficiency.

[0191] In one implementation, the memory 604 in the apparatus 600 may be a read-only memory (ROM) device or a random access memory (RAM) device. Any other suitable type of storage device may be used as the memory 604. The memory 604 may include code and data 606 accessed by the processor 602 via a bus 612. The memory 604 may also include an operating system 608 and application programs 610, which include at least one program that allows the processor 602 to perform the methods described herein. For example, the application programs 610 may include applications 1 through N, as well as a video decoding application that performs the methods described herein.

[0192] The apparatus 600 may also include one or more output devices, such as a display 618. In one example, the display 618 may be a touch-sensitive display that combines a display with touch-sensitive elements that can be used to sense touch input. The display 618 may be coupled to the processor 602 via the bus 612.

[0193] Although bus 612 in device 600 is described herein as a single bus, bus 612 may include multiple buses. Furthermore, secondary storage may be directly coupled to other components of device 600 or accessed via a network, and may include a single integrated unit such as a memory card or multiple units such as multiple memory cards. Thus, device 600 may have a variety of configurations.

[0194] In conjunction with the above, embodiments of the present application relate to processing a bitstream (also referred to as a codestream) obtained by encoding a video / image. Specifically, they relate to bitstream extraction, i.e., extracting a bitstream of a specific layer from the bitstream to obtain a sub-bitstream (or substream). It is understood that during the encoding process, images in a video sequence can be processed in layers, and the layered images can be encoded to obtain a bitstream. In other words, the bitstream includes multiple layered bitstreams.

[0195] First, the related content of layering is introduced. The layering of video sequences can include spatial layering and temporal layering.

[0196] Among them, spatial layering means that within the spatial domain, an image includes multiple images of different resolutions, that is, within the spatial domain, an image includes multiple layered images (or multiple layers). Each layer is set with a layer identifier (layer id). For example, if an image includes 4 spatial layers, the values ​​of the layer identifiers (layer_id[i], where i represents the i-th layer) of the 4 layers can be 0, 1, 2, and 3 respectively, that is, layer_id[0] = 0, layer_id[1] = 1, layer_id[2] = 2, and layer_id[3] = 3.

[0197] Temporal layering refers to the division of images into multiple temporal layers within the time domain to effectively reflect the dependencies between images. Each image has a temporal layer identification number (also referred to as the temporal layer number, i.e., temporal_id) that identifies the temporal layer to which it belongs. A temporal layer can include one or more images. It should be noted that lower-layer images (with smaller temporal layer identification numbers) do not use images with higher temporal layer identification numbers as references, that is, lower-layer images do not rely on higher-layer images for encoding and decoding. Based on the principle that lower-layer images do not rely on higher-layer images, for example, for images with picture order counts (POCs) of 0-8, images with POCs of 0, 4, and 8 are grouped into one temporal layer with a temporal_id of 0. It can be seen that images with POCs of 0, 4, and 8 have the same temporal_id; images with POCs of 2 and 6 are grouped into one temporal layer with a temporal_id of 1; and images with POCs of 1, 3, 5, and 7 are grouped into one temporal layer with a temporal_id of 2.

[0198] Currently, during video / image encoding, the video sequence parameter set (SPS) transmits layer-related information, including the number of layers and inter-layer dependencies, and supports extracting the bitstream of a specific layer for independent decoding. However, after extracting a substream (also known as a sub-bitstream, which refers to the bitstream of a specific layer extracted from the complete bitstream), the layer information of the bitstream changes. Currently, there is no information indicating the layer information of the extracted substream.

[0199] Refer to Table 1 below, which shows layer-related information transmitted by the raw byte sequence payload (RBSP) of the SPS in the current layered coding scenario.

[0200] Table 1. Sequence parameter set RBSP definition

[0201] The “...” in the above Table 1 indicates omitted content, and Table 1 only illustrates several syntax elements related to layered coding.

[0202] num_of_layers_minus1 represents the number of spatial layers and is a 2-bit unsigned integer. It is incremented by 1 to indicate the number of layers in the spatial hierarchy. num_of_layers_minus1 is transmitted in the bitstream only if the profile is 0xXX. NumOfLayers (number of layers) equals num_of_layers_minus1 + 1. If num_of_layers_minus1 is not present in the bitstream, NumOfLayers equals 1. NumOfLayers should range from 1 to MAX_LAYER.

[0203] sps_all_independent_layers_flag indicates the overall flag for spatial layer independent coding, a binary variable. A value of '1' indicates that all spatial layers are independently coded and inter-layer dependency coding is not used. A value of '0' indicates that inter-layer dependency coding is used. The value of spsAllIndependentLayersFlag is equal to the value of sps_all_independent_layers_flag. If sps_all_independent_layers_flag does not exist in the bitstream, the value of SpsAllIndependentLayersFlag is equal to 1.

[0204] sps_independent_layer_flag[i] indicates the independent coding flag of the spatial layer i, a binary variable. A value of '1' indicates that the spatial layer with LayerId (layer identifier) ​​equal to i is independently coded and does not use inter-layer dependency coding. A value of '0' indicates that the spatial layer with LayerId equal to i can use inter-layer dependency coding. The value of spsIndependentLayerFlag[i] is equal to the value of sps_independent_layer_flag[i]. If sps_independent_layer_flag[i] does not exist in the bitstream, the value of SpsIndependentLayerFlag[i] is equal to 1.

[0205] ref_layer_id[i] represents the spatial dependency layer number of layer i, a 2-bit unsigned integer. It specifies the LayerId value of the reference layer for inter-layer dependency coding of the spatial layer whose LayerId is equal to i, that is, the reference layer identifier of the spatial layer whose LayerId is equal to i. The value of ref_layer_id[i] ranges from 0 to NumOfLayers-1. The value of refLayerId[i] is equal to ref_layer_id[i].

[0206] In response to the above-mentioned layered coding scenario, when extracting the bitstream of a specific layer from the bitstream for independent decoding, how to perform sub-bitstream extraction and how to handle changes in layer information are addressed, embodiments of the present application provide a bitstream processing method that can implement bitstream extraction and indicate new layer information in the sub-bitstream.

[0207] During the video / image encoding process, the bitstream received by the bitstream processing device (e.g., the decoding end) may be a bitstream (which can be understood as the original bitstream) after the encoding end encodes the video / image without any other processing (or editing), and the bitstream received by the decoding end may also be a bitstream after the encoding end processes the original bitstream, or a bitstream processed by other devices. The bitstream processing device can extract a sub-bitstream from the bitstream according to the bitstream processing method provided in the embodiment of the present application. It should be understood that the bitstream contains syntax elements that act on the encoded video sequence or image, such as syntax elements related to layered coding, such as the above-mentioned num_of_layers_minus1, sps_all_independent_layers_flag, sps_independent_layer_flag[i], ref_layer_id[i], etc.

[0208] In combination with the above, the following describes in detail the bitstream processing method provided by the embodiment of the present application, taking the bitstream processing device as a decoding end as an example. The bitstream processing method provided by the embodiment of the present application can be applied to the decoder 30 (or video decoder 30) in Figures 1a, 1b, or 3 above.

[0209] As shown in FIG7 , an embodiment of the present application provides a bitstream processing method, which can be applied to a decoding end or other devices capable of editing or processing a bitstream. The method includes S701 - S703 .

[0210] S701. Obtain a bit stream (inBitStream) of a target image, where the bit stream includes at least one layered code stream after layered encoding of the target image, and the bit stream includes first layer information, where the first layer information includes first indication information for indicating the number of layers included in the bit stream and second indication information for indicating a layer identifier of the layer included in the bit stream.

[0211] In the embodiment of the present application, the bit stream obtained by the decoding end may be the original bit stream, and the bit stream obtained above is the bit stream obtained by layered encoding of the target image. The bit stream obtained by the decoding end may be a processed code stream, for example, a bit stream after bit stream extraction performed by other devices.

[0212] Optionally, the first layer information (including the first indication information and the second indication information) is carried in the supplemental enhancement information (SEI) in the bitstream, refer to the following Table 2 and Table 3. Table 2 is the syntax definition of the supplemental enhancement payload, and Table 3 is the syntax definition of the layer information payload.

[0213] Table 2

[0214] Table 3

[0215] In this embodiment of the present application, first indication information and second indication information are added to the supplemental enhancement information. As shown in Table 2, in the payload of the supplemental enhancement information, the payload with a payload type (i.e., PayloadType) of 25 contains layer information (e.g., layer_info). As shown in Table 3, layer_info includes first indication information indicating the number of layers and second indication information indicating the layer identifier. Combining Tables 2 and 3, the first indication information can be a layer number flag (sei_num_of_layers_minus1 in Table 3), and the second indication information can be the Layer ID of the i-th layer in the bitstream in the target image (sei_layer_id[i] in Table 3).

[0216] The above sei_num_of_layers_minus1 is a 2-bit unsigned integer. 1 is added to identify the number of layers in the hierarchical structure. The value of sei_num_of_layers_minus1 should be less than NumOfLayers.

[0217] sei_layer_id[i], a 2-bit unsigned integer. Indicates the Layer ID (layer identifier) ​​of layer i. sei_layer_id[i] should be less than NumOfLayers. For any unsigned integers k and m, when k is less than m, sei_layer_id[k] should be less than sei_layer_id[m].

[0218] For example, the target image's bitstream contains four layers, with layer_ids 0-3 respectively. The bitstream obtained by the decoder contains all the layers of the target image. In this case, the number of layers in the bitstream is 4, and sei_num_of_layers_minus1 is 3. sei_layer_id[0] = 0, sei_layer_id[1] = 1, sei_layer_id[2] = 2, and sei_layer_id[3] = 3.

[0219] As you can understand, encoding a video or image generates a bitstream, which consists of one or more consecutive access units (AUs). Typically, an AU contains coded data for one or more images. An AU consists of a set of network abstraction layer units (NAL units), or NAL units, that are associated with each other according to specified rules.

[0220] Optionally, if the bit stream obtained (such as received) by the decoding end is a bit stream of a video sequence (including multiple images), the decoding end extracts the bit stream of the target image from the bit stream according to a preset target time domain layer number (which can be called the target highest time domain layer number, targetTId), that is, extracts part of the bit stream from the bit stream of the video sequence to obtain the bit stream of the target image.

[0221] For example, all NAL units with temporal_id greater than targetTId are removed from the bit stream of the video sequence (which can be understood as the input bit stream inBitStream of the encoder) to obtain the bit stream of the target image. It can be understood that for the time domain layer, since the low-level image does not rely on the high-level image for encoding and decoding, for a given target highest time domain layer number targetTId, the data of the time domain layer with temporal_id greater than targetTId is removed, and the data of the time domain layer with temporal_id less than or equal to targetTId is retained. targetTId can be understood as the maximum value of the time domain layer number in the bit stream during the extraction of the sub-bit stream. The above targetTId can be set by the user according to needs.

[0222] Based on the targetTId input by the user, a target image bitstream is obtained from the video sequence bitstream. It is understood that the target image includes images in the temporal layer whose temporal_id is less than or equal to the targetTId, and each target image includes multiple layers in the spatial layer. Thus, the target image bitstream obtained in S701 includes at least one layer bitstream resulting from layered encoding of the target image (the target image includes one or more images in the temporal domain).

[0223] S702. Construct a target layer list (targetLayerList) corresponding to the target layer (targetLayer). The target layer is the layer to be extracted in the target image, and the target layer list includes the target layer. When at least one layer in the target layer has an interlayer reference layer, the target layer list also includes at least one interlayer reference layer.

[0224] The bitstream processing method provided in the embodiment of the present application can be used to extract the spatial layered bitstream of the target image. The above-mentioned target layer can also be called the target spatial layer, and the target layer list can be called the target spatial layer list or the target spatial layer list.

[0225] The process of constructing a target layer list corresponding to the target layer includes S1-S2:

[0226] S1. Parse a bit stream of a target image to obtain at least one layered independent coding identifier and at least one layered reference layer identifier of the target image.

[0227] A layered layer-independent coding flag is used to indicate whether the layer is to be coded independently or inter-layer dependently. Specifically, first, parse the first NAL unit with a NAL unit type (nal_unit_type) of 7 in the bitstream of the target image to obtain the number of layers (NumOfLayers), the spatial i-th layer independent coding flag (SpsIndependentLayerFlag[i]) and the spatial i-th layer dependent layer number (ref_layer_id[i] or RefLayerId[i]), where i = 0 to (NumOfLayers-1). It can be understood that the first NAL unit with a NAL unit type of 7 in the bitstream includes a sequence parameter set (see Table 4 below), which contains a flag indicating the number of layers. Therefore, the number of layers can be obtained by parsing the first NAL unit with a nal_unit_type of 7 in the bitstream.

[0228] It should be understood that the NAL unit type flag (nal_unit_type) is a 5-bit unsigned integer. It indicates the type of the RBSP data structure in the NAL unit. Referring to Table 4 below, the NAL unit type flag and the type of the RBSP data structure in the NAL unit are shown.

[0229] Table 4. NAL unit type table

[0230] S2. Add the layer identifier of the target layer to the target layer list, and if the layer-independent coding identifier of the target layer indicates that the target layer is to be inter-layer dependently coded, add the reference layer identifier of the target layer to the target layer list.

[0231] After obtaining the number of layers (NumOfLayers), the spatial layer i independent coding flag (SpsIndependentLayerFlag[i]) and the spatial layer i dependent layer number (ref_layer_id[i] or RefLayerId[i]) from the bitstream parsing, the target spatial layer list (targetLayerList) can be constructed based on this information and the target layer. Among them, targetLayerList[k] represents the LayerId of the kth layer in the target spatial layer list. Initialize the number of layers numTargetLayers in the spatial layer list to 0, and perform the following operations to obtain the layers that should be added to the target spatial layer list:

[0232] for(k=targetLayer;k>=0;){

[0233] targetLayerList[numTargetLayers]=k

[0234] numTargetLayers += 1

[0235] if(SpsIndependentLayerFlag[k]==0)

[0236] k = RefLayerId[k]

[0237] else

[0238] break

[0239] }

[0240] The above operation process is actually: when the target layer is independently coded (the layered independent coding identifier indicates independent coding), the target layer is added to the target spatial layer list (specifically, the layer identifier of the target layer is added to the target spatial layer list); when the target layer has an inter-layer reference layer, the inter-layer reference layer of the target layer is determined according to ref_layer_id[i], and the inter-layer reference layer is added to the target spatial layer list (specifically, the layer identifier of the inter-layer reference layer of the target layer is added to the target spatial layer list), and if there is an inter-layer reference in the inter-layer reference frame, the reference frame of the inter-layer reference frame also needs to be added to the target spatial layer list (specifically, the layer identifier of the reference layer of the inter-layer reference layer is added to the target spatial layer list).

[0241] S703. Based on the target layer list, process the bit stream of the target image and output a sub-bit stream; the sub-bit stream includes the bit stream of the layer in the target layer list and second layer information, the second layer information includes third indication information for indicating the number of layers included in the sub-bit stream, and fourth indication information for indicating the layer identifier of the layer included in the sub-bit stream.

[0242] In an embodiment of the present application, the bitstream of the target image is processed based on the target layer list, and the output sub-bitstream includes: taking the bitstream inBitStream (the bitstream of a video sequence), the spatial layer list targetLayerList, the number of layers in the spatial layer list numTargetLayers, and the target highest temporal layer number targetTId as input, calling the following sub-bitstream extraction method to obtain the sub-bitstream outBitStream.

[0243] Follow the steps below to obtain a sub-bitstream that meets the requirements (i.e., perform sub-bitstream extraction):

[0244] Step 1: The decoding end copies the received bit stream (ie, the input bit stream inBitStream, a bit stream of a video sequence), and extracts a sub-bit stream based on the copied bit stream (outBitStream).

[0245] It can be understood that in the embodiment of the present application, the decoding end copies the received bit stream, records the copied bit stream as outBitStream, and removes unnecessary bit streams (or bit streams that do not meet the specified conditions) from the copied bit stream outBitStream through subsequent steps to obtain the final outBitStream, and the final outBitStream is the extracted sub-bitstream.

[0246] Step 2: Remove all NAL units in outBitStream whose temporal_id is greater than targetTId.

[0247] targetTId is the time domain layer number of the target image contained in the layered bitstream to be extracted. Through step 2, the bitstream of the image after the bitstream of the target image in the bitstream is removed, that is, the bitstream of the image with a time domain layer number less than or equal to targetTId is retained.

[0248] The bit stream (outBitStream) input in step 2 is the bit stream obtained by step 1.

[0249] Step 3: Remove from outBitStream (the bitstream of the target image) all NAL units whose LayerId values ​​are not included in targetLayerList and whose nal_unit_type is not 5, 6, 7, 8, 9, 10, 11, or 16. This can also be described as: remove from the bitstream of the target image all NAL units whose NAL unit type is not 5, 6, 7, 8, 9, 10, 11, or 16 in the bitstream of the layers that do not exist in the target layer list.

[0250] For step 3, it can be understood that: it is necessary to retain the NAL units whose LayerId in outBitStream is included in targetLayerList, and for the NAL units in outBitStream whose LayerId is not included in targetLayerList, retain the NAL units whose nal_unit_type is 5, 6, 7, 8, 9, 10, 11, or 16. It can be understood that, with reference to Table 4 above, since the NAL units whose nal_unit_type is 5, 6, 7, 8, 9, 10, 11, or 16 contain common information for decoding the bitstream, they need to be retained (i.e., they need to be extracted into the sub-bitstream).

[0251] The bit stream input in step 3 is the bit stream obtained in step 2.

[0252] Step 4: Remove all NAL units in outBitStream whose LayerId values ​​are not included in targetLayerList and whose nal_unit_type is 6 and whose PayloadType is 19, 25, 26 or 127.

[0253] Step 4 can be understood as: for the NAL unit with nal_unit_type of 6 whose LayerId is not included in the targetLayerList in the outBitStream obtained by step 3, retain the NAL unit with PayloadType of 19, 25, 26 or 127 in the NAL unit with nal_unit_type of 6. The payload with PayloadType of 19 represents the sequence-level privacy protection area (seq_privacy_parameters), and the sequence-level privacy protection area payload contains some sequence-level privacy protection parameters; the payload with PayloadType of 25 represents the supplementary enhancement information carrying layered information; the payload with PayloadType of 26 represents the display indication information for indicating whether the display knowledge image is displayed; the payload with PayloadType of 127 represents the version information parameter. The information in the NAL unit with PayloadType of 19, 25, 26 or 127 is some information related to the video sequence, which cannot be removed and needs to be retained in the sub-bitstream.

[0254] Step 5. If there is a NAL unit with a nal_unit_type of 6 and a PayloadType of 25 in outBitStream, update the layered SEI payload in the NAL unit, set sei_num_layers_minus1 to numTargetLayers-1, and delete the sei_layer_id that is not in the targetLayerList; otherwise (that is, there is no NAL unit with a nal_unit_type of 6 and a PayloadType of 25 in outBitStream), insert a NAL unit with a nal_unit_type of 6 and a PayloadType of 25 before the first coded slice NAL unit of the access unit where each sequence start picture and random access point picture are located, where sei_num_layers_minus1 is set to numTargetLayers-1, and sei_layer_id[i] is set to targetLayerList[numTargetLayers-1-i] (i=0~numTargetLayers-1). It can be understood that in targetLayerList, LayerId is arranged in descending order. By setting sei_layer_id[i] to targetLayerList[numTargetLayers-1-i] (i=0~numTargetLayers-1), sei_layer_id is arranged in ascending order.

[0255] As can be seen from the above step 5, after the sub-bitstream extraction is completed, the first layer information in the original bitstream is updated to the second layer information to indicate the number of layers and layer identifiers in the sub-bitstream.

[0256] Optionally, the access units in the sub-bitstream outBitStream may contain layer units that do not include coded slice NAL units.

[0257] The bitstream of the layer in the target spatial layer list is extracted from the bitstream through steps 1 to 4 to obtain a sub-bitstream. In step 5, the layer information that has changed after the sub-bitstream is extracted is written or updated into the sub-bitstream (i.e., the second layer information is the layer information obtained by updating the first layer information). This indicates the layer status of the sub-bitstream during subsequent decoding or transmission of the sub-bitstream.

[0258] As described above, step 5 adds layer information to the supplemental enhancement information of the sub-bitstream, namely, adds layered supplemental enhancement syntax to indicate the second layer information. The supplemental enhancement information carries third indication information (the layer number flag sei_num_of_layers_minus1) and fourth indication information (the layer identifier sei_layer_id[i]). Combining Tables 3 and 4, the first indication information can be updated to the third indication information, and the second indication information can be updated to the fourth indication information.

[0259] For example, take a target image bitstream and assume that the target image bitstream contains four layers with layer_ids 0, 1, 2, and 3, respectively. After sub-bitstream extraction, layer 1 and layer 2 of the target image are extracted. Then, the number of layers in the sub-bitstream is 2, and sei_num_of_layers_minus1 is 1. sei_layer_id[0] = 1 (i.e., layer 0 in the substream is layer 1 of the target image), and sei_layer_id[1] = 2 (i.e., layer 1 in the substream is layer 2 of the target image).

[0260] In one implementation, the above-mentioned layer information (including the first layer information or the second layer information) is carried in the supplemental enhancement information. Accordingly, the constraints on the access unit and the NAL unit are as follows:

[0261] 1) If there is a NAL unit with nal_unit_type equal to 15 (indicating a coded picture boundary), it must be the starting NAL unit of the access unit, and there can be at most one NAL unit with nal_unit_type equal to 15 in an access unit.

[0262] 2) If there is a NAL unit with nal_unit_type equal to 16 (indicating the end of the coded video sequence) and this NAL unit is not followed by a NAL unit with nal_unit_type equal to 11, then this NAL unit shall be the last NAL unit of the access unit.

[0263] 3) If there is a NAL unit with nal_unit_type equal to 11 (indicating end of stream), this NAL unit shall be the last NAL unit of the access unit.

[0264] 4) If there is a NAL unit with nal_unit_type equal to 19 (indicating a coded slice of a privacy picture), the access order of this NAL unit shall be after the access units with nal_unit_type equal to 0, 1, 2, 12, 14, 17.

[0265] 5) If there is a NAL unit with nal_unit_type equal to 6 (indicating supplementary enhancement information) and PayloadType equal to 127, it should be transmitted in the access unit where each sequence start picture and random access point picture are located, and before the first coded slice NAL unit FirstCrrCpNalUnit of the access unit.

[0266] 6) If there is a NAL unit with nal_unit_type equal to 6 (indicating supplementary enhancement information) and PayloadType equal to 25 (indicating that the NAL unit carries layered information), it should be transmitted in the access unit where each sequence start picture and random access point picture are located, and should be located before the first coded slice NAL unit (FirstCrrCpNalUnit) of the access unit.

[0267] In one implementation, the above-mentioned layered information (including the first layered information or the second layered information) is carried in the supplementary enhancement information, and the encryption method of the layered information can be indicated by an encryption flag (encryption_idc).

[0268] It should be understood that the encryption flag (encryption_idc) is a binary variable. It indicates whether the NAL unit is encrypted. A value of '0' indicates that the RBSP in the NAL unit is not encrypted. A value of '1' indicates that the RBSP in the NAL unit is encrypted as the basic data unit according to the encryption method specified in the security parameter set. The last byte of the RBSP is not encrypted.

[0269] When the nal_unit_type of a NAL unit is 11 (indicating the end of the stream), 15 (indicating the coded picture boundary), or 16 (indicating the end of the coded video sequence), encryption_idc should be 0 (indicating that the RBSP in the NAL unit is not encrypted).

[0270] When the nal_unit_type of a NAL unit is 6 and contains a payload with PayloadType equal to 25 (carrying layer information), encryption_idc should be 0. In other words, the encryption flag of the NAL unit containing the first layer information or the second layer information is the second value (i.e., 0), which is used to indicate that the NAL unit containing the first layer information or the second layer information is not encrypted. Specifically, the second value is used to indicate to the decoder that the encoder did not encrypt the NAL unit containing the first layer information or the second layer information. In this way, the decoder does not need to decrypt the NAL unit containing the first layer information or the second layer information.

[0271] In one implementation, the above-mentioned layer information (including the first layer information or the second layer information) is carried in the supplementary enhancement information, and the authentication method of the layer information can be indicated by an authentication flag (authentication_idc).

[0272] It should be understood that the authentication flag (authentication_idc) is a binary variable. It indicates whether the NAL unit is authenticated. A value of '0' indicates that the NAL unit is unauthenticated, while a value of '1' indicates that the NAL unit is authenticated using the authentication method specified in the security parameter set, and the coded bitstream must carry absolute time extension information to identify the authentication time.

[0273] When the nal_unit_type of a NAL unit is 11, 15, or 16, authentication_idc shall be 0 (indicating that RSRP in these NAL units is not authenticated).

[0274] When the nal_unit_type of a NAL unit is 6 and contains a payload with PayloadType equal to 25 (carrying layer information), authentication_idc should be 0. In other words, the authentication flag of the NAL unit containing the first layer information or the second layer information is the first value (i.e., 0), which is used to indicate that the NAL unit containing the first layer information or the second layer information is not to be authenticated. Specifically, the first value is used to indicate to the decoder that the NAL unit containing the first layer information or the second layer information is not to be authenticated. In this way, the decoder does not need to authenticate the NAL unit containing the first layer information or the second layer information.

[0275] In one implementation, the layer information (including the first layer information or the second layer information) is carried in the supplementary enhancement information, and the layer where the layer information is located can be restricted by a layer identifier.

[0276] It should be understood that the layer identifier (layer_id) is a 2-bit unsigned integer. It indicates the layer identifier of the current picture. The layer identifier value ranges from 0 to MAX_LAYERS. The layer_id of the sequence parameter set and picture parameter set NALU (NALU represents a NAL unit) is 0. The layer_id of the picture header NAL unit and all coded slice NAL units of a coded picture should be the same. The value of layerId is equal to the value of layer_id. Note: MAX_LAYERS is specified by the profile.

[0277] When the nal_unit_type of a NAL unit is 6 and contains a payload with PayloadType equal to 25, the layer_id should be 0 (that is, the layer_id corresponding to the NAL unit containing the layered information is 0).

[0278] In summary, in the bitstream processing method provided in the embodiment of the present application, a target layer list can be created according to the layer to be extracted, and then the bitstream of the layer in the target layer list can be extracted to obtain a sub-bitstream. The layer information after bitstream extraction can be carried in the sub-bitstream, which can smoothly realize the sub-bitstream extraction and clarify the indication method of the layer information.

[0279] It is understandable that, in order to realize the above functions, the bitstream processing device includes hardware and / or software modules corresponding to the execution of each function. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0280] In the embodiments of the present application, the functional modules of the bitstream processing device can be divided according to the above-mentioned method examples. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above-mentioned integrated modules can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical functional division. In actual implementation, other division methods may be used.

[0281] In the case of dividing the functional modules according to their respective functions, FIG8 shows a possible composition diagram of the bit stream processing device involved in the above embodiment. As shown in FIG8 , the bit stream processing device 800 may include: an acquisition module 801, a construction module 802, and a processing module 803.

[0282] The acquisition module 801 , the construction module 802 and the processing module 803 cooperate to execute steps S701 - S703 in the above method embodiment.

[0283] The present application also provides a chip. FIG9 shows a schematic diagram of the structure of a chip 900. The chip 900 includes one or more processors 901 and an interface circuit 902. Optionally, the chip 900 may also include a bus 903.

[0284] The processor 901 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above bit stream processing method can be completed by a hardware integrated logic circuit in the processor 901 or by software instructions.

[0285] Optionally, the processor 901 may be a general-purpose processor, a digital signal processing (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The methods and steps disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or any conventional processor.

[0286] The interface circuit 902 can be used to send or receive data, instructions or information. The processor 901 can use the data, instructions or other information received by the interface circuit 902 to process it, and can send the processing completion information through the interface circuit 902.

[0287] Optionally, the chip also includes a memory, which may include a read-only memory and a random access memory, and provides operating instructions and data to the processor. Part of the memory may also include a non-volatile random access memory (NVRAM).

[0288] Optionally, the memory stores an executable software module or a data structure, and the processor can perform corresponding operations by calling an operation instruction stored in the memory (the operation instruction may be stored in an operating system).

[0289] Optionally, the chip can be used in the encoding device involved in the embodiments of the present application. Optionally, the interface circuit 902 can be used to output the execution result of the processor 901. Regarding the bit stream processing method provided in one or more embodiments of the present application, reference can be made to the aforementioned embodiments and will not be repeated here.

[0290] It should be noted that the corresponding functions of the processor 901 and the interface circuit 902 can be implemented through hardware design, software design, or a combination of hardware and software, and there is no limitation here.

[0291] FIG10 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device 1000 may be a processor or a chip or functional module in a processor. As shown in FIG10 , the electronic device 1000 includes a processor 1001 , a transceiver 1002 , and a communication line 1003 .

[0292] Among them, the processor 1001 is used to execute any step in the bit stream processing method provided in the embodiment of the present application, and in the process of executing any step in the bit stream processing method provided in the embodiment of the present application, the transceiver 1002 and the communication line 1003 can be optionally called to complete the corresponding operation.

[0293] Furthermore, the electronic device 1000 may further include a memory 1004 . The processor 1001 , the memory 1004 and the transceiver 1002 may be connected via a communication line 1003 .

[0294] The processor 1001 is a processor, a general-purpose processor, a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device (PLD), or any combination thereof. The processor 1001 may also be other devices with processing functions, such as circuits, devices, or software modules, without limitation.

[0295] The transceiver 1002 is used to communicate with other devices or other communication networks, such as Ethernet, radio access networks (RAN), wireless local area networks (WLAN), etc. The transceiver 1002 can be a module, a circuit, a transceiver, or any device capable of implementing communication.

[0296] The transceiver 1002 is mainly used for sending and receiving commands and information, and may include a transmitter and a receiver for sending and receiving commands and information, respectively. Operations other than sending and receiving commands and information are implemented by the processor.

[0297] The communication line 1003 is used to transmit information between the components included in the electronic device 1000.

[0298] In one design, the processor can be considered as the logic circuit and the transceiver as the interface circuit.

[0299] The memory 1004 is used to store instructions, where the instructions may be computer programs.

[0300] The memory 1004 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM may be used, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). Memory 1004 may also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, etc. It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0301] It should be noted that the memory 1004 can exist independently of the processor 1001 or can be integrated with the processor 1001. The memory 1004 can be used to store instructions, program code, or some data. The memory 1004 can be located inside the electronic device 1000 or outside the electronic device 1000, without limitation. The processor 1001 is configured to execute the instructions stored in the memory 1004 to implement the methods provided in the above embodiments of the present application.

[0302] In one example, the processor 1001 may include one or more processors, such as processor 0 (CPU0) and processor 1 (CPU1) in FIG. 10 .

[0303] As an optional implementation, the electronic device 1000 includes multiple processors. For example, in addition to the processor 1001 in FIG. 10 , it may also include a processor 1007 .

[0304] As an optional implementation, the electronic device 1000 further includes an output device 1005 and an input device 1006. For example, the input device 1006 is a keyboard, a mouse, a microphone, or a joystick, and the output device 1005 is a display screen, a speaker, or the like.

[0305] It should be pointed out that the electronic device 1000 can be a chip system or a device with a similar structure as shown in Figure 10. Among them, the chip system can be composed of chips, or it can include chips and other discrete devices. The actions, terms, etc. involved in the various embodiments of this application can refer to each other without limitation. The message names or parameter names in the messages exchanged between the various devices in the embodiments of this application are only an example. Other names can also be used in the specific implementation without limitation. In addition, the component structure shown in Figure 10 does not constitute a limitation on the electronic device 1000. In addition to the components shown in Figure 10, the electronic device 1000 may include more or fewer components than those shown in Figure 10, or combine certain components, or arrange the components differently.

[0306] The processor and transceiver described in this application can be implemented on an integrated circuit (IC), an analog IC, a radio frequency integrated circuit, a mixed-signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc. The processor and transceiver can also be manufactured using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (NMOS), P-type metal oxide semiconductor (positive channel metal oxide semiconductor, PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0307] Figure 11 is a schematic diagram of the structure of a bitstream processing device provided in an embodiment of the present application. The bitstream processing device can be applied to the scenario shown in the above method embodiment. For ease of explanation, Figure 11 only shows the main components of the bitstream processing device, including a processor 1101, a memory 1102, a control circuit 1103, and an input / output device 1104. The processor 1101 is mainly used to process communication protocols and communication data, execute software programs, and process data of software programs. The memory 1102 is mainly used to store software programs and data. The control circuit 1103 is mainly used for power supply and transmission of various electrical signals. The input / output device 1104 is mainly used to receive data input by the user and output data to the user.

[0308] When the bitstream processing device is a processor 1101, the control circuit 1103 may be a motherboard, the memory 1102 may include a hard disk, RAM, ROM, or other storage media, and the processor 1101 may include a baseband processor 1101 and a central processing unit. The baseband processor is primarily used to process communication protocols and communication data, while the central processing unit is primarily used to control the entire bitstream processing device, execute software programs, and process software program data. The input and output devices 1104 include a display screen, a keyboard, and a mouse. The control circuit 1103 may further include or be connected to a transceiver circuit or transceiver, such as a network cable interface, for sending or receiving data or signals, such as for data transmission and communication with other devices. Furthermore, an antenna may be included for transmitting and receiving wireless signals for data / signal transmission with other devices.

[0309] An embodiment of the present application further provides a bitstream processing device, which includes: at least one processor, when the at least one processor executes program code or instructions, it implements the above-mentioned related method steps to implement the bitstream processing method in the above embodiment.

[0310] Optionally, the apparatus may further include at least one memory configured to store the program code or instruction.

[0311] An embodiment of the present application further provides a computer storage medium storing computer instructions. When the computer instructions are executed on a bitstream processing device, the bitstream processing device executes the above-mentioned related method steps to implement the bitstream processing method in the above-mentioned embodiment.

[0312] The embodiment of the present application further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the bit stream processing method in the above-mentioned embodiment.

[0313] The present application also provides a bitstream processing device, which can be a chip, integrated circuit, component, or module. Specifically, the device can include a processor and a memory for storing instructions, or the device can include at least one processor configured to retrieve instructions from an external memory. When the device is running, the processor can execute the instructions, causing the chip to perform the bitstream processing methods described in the above-described method embodiments.

[0314] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using a software program, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions in accordance with the embodiments of the present application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (eg, a floppy disk, a magnetic disk, a magnetic tape), an optical medium (eg, a digital video disc (DVD)), or a semiconductor medium (eg, a solid state drive (SSD)).

[0315] Through the description of the above embodiments, those skilled in the art will clearly understand that for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0316] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0317] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0318] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0319] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as flash memory, mobile hard disk, read-only memory, random access memory, magnetic disk or optical disk.

[0320] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A bitstream processing method, characterized in that, Including: Obtain a bitstream of a target image, where the bitstream includes bitstreams of at least one layer after hierarchical coding of the target image; the bitstream includes first layer information, and the first layer information includes first indication information and second indication information. The first indication information is used to indicate the number of layers included in the bitstream, and the second indication information is used to indicate the layer identifier of the layer included in the bitstream. Construct a target layer list corresponding to the target layer; the target layer is the layer to be extracted in the target image, and the target layer list includes the target layer. When there is an inter-layer reference layer in at least one layer of the target layer, the target layer list further includes at least one inter-layer reference layer. Based on the target layer list, process the bitstream of the target image to output a sub-bitstream; the sub-bitstream includes the bitstreams of the layers in the target layer list and second layer information, and the second layer information includes third indication information and fourth indication information; wherein, the third indication information is used to indicate the number of layers included in the sub-bitstream, and the fourth indication information is used to indicate the layer identifier of the layer included in the sub-bitstream.

2. The method according to claim 1, wherein: The first layer information is included in the supplementary enhancement information in the bitstream of the target image; and / or The second layer information is included in the supplementary enhancement information in the sub-bitstream.

3. The method according to claim 1 or 2, wherein: The second layer information is the layer information updated from the first layer information.

4. The method according to any one of claims 1 to 3, characterized in that The constructing a target layer list corresponding to the target layer includes: Parse the bitstream of the target image to obtain the layer independent coding identifier of the at least one layer and the reference layer identifier of the at least one layer; the layer independent coding identifier of a layer is used to indicate independent coding or inter-layer dependent coding of the layer. Add the layer identifier of the target layer to the target layer list. If the layer independent coding identifier of the target layer indicates inter-layer dependent coding of the target layer, add the reference layer identifier of the target layer to the target layer list.

5. The method according to any one of claims 1 to 4, characterized in that, The processing the bitstream of the target image based on the target layer list includes: Remove from the bitstream of the target image the NAL units whose NAL unit types are not 5, 6, 7, 8, 9, 10, 11, or 16 in the bitstreams of the layers that do not exist in the target layer list.

6. The method according to any one of claims 1 to 5, wherein: The authentication flag of the network abstraction layer (NAL) unit including the first layer information or the second layer information is a first value, and the first value is used to indicate that the NAL unit including the first layer information or the second layer information is not authenticated.

7. The method according to any one of claims 1 to 6, wherein: The encryption flag of the Network Abstraction Layer (NAL) unit containing the first layer information or the second layer information is a second value, and the second value is used to indicate that the NAL unit containing the first layer information or the second layer information is not encrypted.

8. The method according to any one of claims 1 to 7, characterized in that The NAL unit containing the first layer information or the second layer information is carried in the bitstream of the first layer of the target image.

9. The method according to claim 6, characterized in that The first value is specifically used to indicate to the decoding end that the NAL unit containing the first layer information or the second layer information is not authenticated.

10. The method according to claim 7, characterized in that The second value is specifically used to indicate to the decoding end that the encoding end has not encrypted the NAL unit containing the first layer information or the second layer information.

11. A bitstream processing device, comprising at least one processor and a memory, characterized in that, The at least one processor executes the program or instruction stored in the memory, so that the device implements the method according to any one of claims 1 to 10 above.

12. A computer-readable storage medium for storing a computer program, characterized in that, When the computer program runs on a computer or a processor, the computer or the processor implements the method according to any one of claims 1 to 10 above.

13. A computer program product comprising instructions, characterized in that, When the instruction runs on a computer or a processor, the computer or the processor implements the method according to any one of claims 1 to 10 above.

14. A chip, comprising at least one processor and a memory, characterized in that, The at least one processor executes the program or instruction stored in the memory, so that the chip implements the method according to any one of claims 1 to 10 above.

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