Storage array and preparation method therefor, memory, and electronic device

Abstract

The present application relates to the technical field of semiconductors, and provides a storage array and a manufacturing method therefor, a memory, and an electronic device, aiming to improve the arrangement density of a storage array. The storage array comprises a plurality of storage units arranged in an array, and each storage unit comprises a capacitor and a transistor. Each capacitor comprises a first electrode, a dielectric layer, and a second electrode, the first electrode is arranged around the second electrode, and the dielectric layer is located between the first electrode and the second electrode. Each transistor is arranged on a corresponding capacitor, the transistor comprises a channel layer, a gate dielectric layer, and a gate layer, the gate layer surrounds the side surface of the channel layer, and the gate dielectric layer is located between the channel layer and the gate layer. Each channel layer is in contact with a corresponding second electrode, the channel layer has a first surface in contact with the second electrode, the second electrode has a second surface in contact with the channel layer, and the boundary of the first surface coincides with the boundary of the second surface. The storage array can be applied to a memory so as to read and write data.

Description

Storage array and preparation method thereof, memory, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 25, 2024, with application number 202410110956.0 and application name “Memory Array and Preparation Method thereof, Memory, Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a memory array and a preparation method thereof, a memory, and an electronic device. Background Art

[0003] Dynamic Random Access Memory (DRAM) has become one of the mainstream memories due to its advantages such as high speed, high density, and low latency.

[0004] Currently, the size reduction of DRAM has reached a bottleneck. How to increase the arrangement density of the storage array in the memory to achieve device size reduction has become an urgent problem to be solved in the field.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a memory array and a preparation method thereof, a memory, and an electronic device, aiming to improve the arrangement density of the memory array.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a memory array is provided, comprising a plurality of memory cells arranged in an array, each memory cell comprising a capacitor and a transistor. The capacitor comprises a first electrode, a dielectric layer, and a second electrode, wherein the first electrode is disposed around the second electrode, and the dielectric layer is located between the first electrode and the second electrode. A transistor is disposed on the capacitor, and comprises a channel layer, a gate dielectric layer, and a gate layer, wherein the gate layer surrounds a side of the channel layer, and the gate dielectric layer is located between the channel layer and the gate layer. The channel layer contacts the second electrode, the channel layer comprises a first surface in contact with the second electrode, the second electrode comprises a second surface in contact with the channel layer, and the boundary of the first surface coincides with the boundary of the second surface.

[0009] The memory array provided in the above-described embodiments of the present application includes a plurality of memory cells arranged in an array. In the capacitor of each memory cell, a first electrode is arranged around a second electrode, and a dielectric layer is located between the first and second electrodes, giving the capacitor a "columnar capacitor structure." A transistor is disposed on the capacitor. The transistor includes a channel layer, a gate dielectric layer, and a gate layer. The gate layer surrounds the side of the channel layer, which helps improve the gate layer's control over the channel layer and increases the transistor's operating voltage window. The gate dielectric layer is located between the channel layer and the gate layer, and the transistor has a "vertical transistor structure."

[0010] The columnar capacitor structure has a smaller planar size than the planar capacitor structure, and the vertical transistor structure has a smaller planar size than the planar transistor structure, which is beneficial to reducing the planar size of the memory cell and increasing the number of memory cells per unit area, thereby improving the arrangement density of the memory array.

[0011] The channel layer of the transistor contacts the second electrode of the capacitor, the channel layer includes a first surface in contact with the second electrode, the second electrode includes a second surface in contact with the channel layer, and the boundary of the first surface coincides with the boundary of the second surface, that is, the end portions of the channel layer and the second electrode in contact are in the same position and have the same size, the channel layer and the second electrode are aligned with high alignment accuracy, thereby ensuring a stable connection between the transistor and the capacitor and facilitating improving the arrangement density of the storage array.

[0012] In some embodiments, the memory array further includes a plurality of word lines, and the plurality of memory cells arranged in an array include a plurality of rows and a plurality of columns. The gate layers of a plurality of transistors in a row of memory cells are connected to form a word line. The word line includes a conductive connection layer located between the gate layers of two adjacent transistors. The surface of the conductive connection layer away from the capacitor is recessed toward the direction close to the capacitor, so that the cross-sectional area of ​​the conductive connection layer is smaller, thereby saving materials used to prepare the word line.

[0013] Alternatively, the conductive connection layer fills the gap between the gate layers of two adjacent transistors, so that the cross-sectional area of ​​the word line is larger, which is beneficial to reducing the resistance of the word line and thus reducing the voltage drop of the voltage signal transmitted on the word line.

[0014] In some embodiments, the memory array further includes a plurality of bit lines, each bit line being arranged on a side of the transistor away from the capacitor, each bit line being electrically connected to the channel layers of a plurality of transistors in a column of memory cells, and the end of the channel layer connected to the bit line being the source of the transistor.

[0015] In some embodiments, the memory array further includes a plate line disposed on a side of the capacitor away from the transistor, and first electrodes of the plurality of capacitors in the plurality of memory cells are electrically connected to the plate line.

[0016] In some embodiments, a memory cell includes multiple capacitors and a transistor. First electrodes of the multiple capacitors are stacked and spaced apart in a direction from the capacitors to the transistors, and second electrodes of the multiple capacitors are connected to form a columnar electrode. A channel layer of the transistor is connected to one end of the columnar electrode.

[0017] In some embodiments, along the direction from the capacitor to the transistor, the memory array includes a plurality of stacked memory structures, each memory structure includes a plurality of memory cells arranged in an array. The three-dimensional stacking of the plurality of memory structures is beneficial to improving the arrangement density of the memory array.

[0018] In some embodiments, the material of the dielectric layer includes a ferroelectric material. In this case, the capacitor formed by the first electrode, the dielectric layer, and the second electrode is a ferroelectric capacitor.

[0019] In a second aspect, a method for preparing a storage array is provided, the method comprising: forming an insulating layer having a plurality of vias on a substrate, wherein the plurality of vias are arranged in an array. A first electrode, a dielectric layer, and a second electrode are formed in the vias, wherein the first electrode is located on the surface of the via, the dielectric layer is located on the inner side of the first electrode, and the second electrode is located on the inner side of the dielectric layer. Relative to the substrate, the surface of the second electrode on the side away from the substrate is lower than the surface of the insulating layer on the side away from the substrate. A blocking layer is formed in the vias, wherein the blocking layer is located on the inner side of the dielectric layer and on the side away from the substrate of the second electrode. The portions of the insulating layer, the first electrode, and the dielectric layer located outside the blocking layer are removed to expose the blocking layer. A gate dielectric layer and a gate layer are formed on the side of the blocking layer.

[0020] The fabrication method provided in the above-mentioned embodiments of the present application forms an insulating layer having multiple vias on a substrate, and forms a first electrode, a dielectric layer, and a second electrode within the vias. The first electrode is located on the surface of the via, and the dielectric layer and the second electrode are located sequentially inside the first electrode. The first electrode, the dielectric layer, and the second electrode constitute a "columnar capacitor structure." Furthermore, the top surface of the second electrode is lower than the top surface of the insulating layer. This means that during the fabrication of the columnar capacitor structure, a cavity is simultaneously formed within the via.

[0021] Then, a barrier layer is formed in the cavity within the via hole. The barrier layer is also located inside the dielectric layer and above the second electrode. Finally, the insulating layer, the first electrode, and the portion of the dielectric layer outside the barrier layer are removed to expose the barrier layer, and a gate dielectric layer and a gate layer are formed on the side of the barrier layer. The barrier layer can be used as the channel layer of the transistor, and the barrier layer, gate dielectric layer, and gate layer form the transistor. Alternatively, the barrier layer can be used as a sacrificial layer and replaced with the channel layer, and the channel layer, gate dielectric layer, and gate layer form the transistor.

[0022] It can be seen that the blocking layer and the second electrode are both located on the inner side of the dielectric layer, and the blocking layer is located above the second electrode. Therefore, in the direction parallel to the substrate, the position and size of the blocking layer and the second electrode are defined by the same dielectric layer, that is, the position and size of the channel layer and the second electrode are defined by the same dielectric layer, so that the channel layer and the second electrode have the same position and size, thereby realizing "automatic alignment" of the channel layer and the second electrode.

[0023] Compared with the exposure and development process, in which channel holes are etched on the gate layer to form a channel layer, the channel holes need to be aligned with the second electrode. In the above-mentioned preparation method of the present application, the process of "automatic alignment" of the channel layer and the second electrode does not require the exposure and development process. The preparation process is relatively simple and controllable, which is conducive to reducing process difficulty and cost.

[0024] In some embodiments, forming a first electrode, a dielectric layer, and a second electrode within a via includes: forming the first electrode on a surface of the via; forming a dielectric layer inside the first electrode; depositing a conductive material and forming a filler layer inside the dielectric layer; removing a portion of the filler layer away from the substrate to form a first cavity within the via; and forming the second electrode in the remaining portion of the filler layer. This allows the first cavity to be simultaneously formed within the via during the fabrication of the columnar capacitor structure.

[0025] Forming a barrier layer in the via hole includes: forming a barrier layer in the first chamber, the barrier layer contacts the second electrode, the barrier layer and the second electrode are positioned at the same position, and the end portion of the barrier layer contacting the second electrode has the same size.

[0026] In some embodiments, forming a gate dielectric layer and a gate layer on the side of the barrier layer includes: forming a gate dielectric film and a gate film on the outer side of the barrier layer, the gate dielectric film including at least a first portion located on the side of the barrier layer away from the substrate and a second portion located on the side of the barrier layer, and the gate film including at least a third portion located on the side of the barrier layer away from the substrate and a fourth portion located on the side of the barrier layer. The third portion of the gate film and the first portion of the gate dielectric film are removed, leaving the second portion as the gate dielectric layer and the fourth portion as the gate layer, exposing the surface of the barrier layer away from the substrate to facilitate subsequent formation of a bit line on the surface of the barrier layer, or replacing the barrier layer with a channel layer.

[0027] In some embodiments, the plurality of vias include multiple rows and columns, and the plurality of barrier layers within the plurality of vias include multiple rows and columns. After forming a gate dielectric layer and a gate layer on the sides of the barrier layers, a first mask layer is formed, the first mask layer having multiple first openings, each of which exposes the gate layer on the sides of a row of barrier layers. A conductive material is deposited, and a conductive connecting layer is formed between the plurality of barrier layers in the same row through the first openings. The conductive connecting layer is connected to the gate layers on the sides of the plurality of barrier layers to form a word line.

[0028] In some embodiments, the gate film further includes a fifth portion located on a surface of the insulating layer, the fifth portion being connected to the gate layer on the sides of the plurality of barrier layers. After the gate dielectric layer and the gate layer are formed on the sides of the barrier layers, a second mask layer is formed, the second mask layer having a plurality of second openings, each second opening exposing an area between two adjacent rows of barrier layers. Portions of the fifth portion of the gate film are removed through the second openings, and the remaining portion of the fifth portion, together with the gate layer on the sides of the same row of barrier layers, form a word line.

[0029] In some embodiments, the barrier layer is directly used as the channel layer of the transistor. The transistor includes a barrier layer, a gate dielectric layer and a gate layer. A bit line can be directly formed on the surface of the barrier layer, simplifying the process steps of preparing the channel layer.

[0030] In some embodiments, a barrier layer is used as a sacrificial layer. After forming a gate dielectric layer and a gate layer on the side of the barrier layer, the barrier layer is removed to form a second chamber. A channel layer of a transistor is formed in the second chamber. The transistor includes a channel layer, a gate dielectric layer, and a gate layer. Replacing the barrier layer with the channel layer avoids pre-forming the channel layer and avoiding etching damage to the channel layer during the process of forming the gate dielectric layer and the gate layer. This helps improve the film quality of the channel layer and enhances the electrical performance of the transistor.

[0031] In a third aspect, a memory is provided, which includes the memory array in any of the above embodiments and a controller electrically connected to the memory array.

[0032] In a fourth aspect, an electronic device is provided, such as a consumer electronic product, a home electronic product, an in-vehicle electronic product, a financial terminal product, or a communication electronic product. The electronic device includes a circuit board and the memory of the above embodiment, the memory being electrically connected to the circuit board.

[0033] It can be understood that the beneficial effects that can be achieved by the memory and electronic device provided by the above embodiments of the present application can be referred to the beneficial effects of the storage array above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings required for use in some embodiments of this application. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, etc. involved in the embodiments of this application.

[0035] FIG1 is a diagram illustrating an electronic device according to an embodiment of the present invention;

[0036] FIG2 is an exploded view of an electronic device provided in an embodiment of the present application;

[0037] FIG3 is an architectural diagram of a memory provided in an embodiment of the present application;

[0038] FIG4 is a circuit diagram of a memory array provided in an embodiment of the present application;

[0039] 5A and 5B are flowcharts of preparing a memory array according to an embodiment of the present application;

[0040] 6A to 6S are structural diagrams corresponding to the steps of a method for manufacturing a memory array provided in an embodiment of the present application;

[0041] 7A to 7D are structural diagrams corresponding to the steps of another method for manufacturing a memory array provided in an embodiment of the present application;

[0042] 8A to 8F are structural diagrams corresponding to the steps of another method for manufacturing a memory array provided in an embodiment of the present application;

[0043] FIG9 is a cross-sectional view along plane XZ of a storage array provided in an embodiment of the present application;

[0044] FIG10 is a cross-sectional view along plane YZ of a storage array provided in an embodiment of the present application;

[0045] FIG11 is a structural diagram of another storage array provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0047] Some embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a rechargeable small household appliance (e.g., a soymilk maker, a sweeping robot), a drone, a radar, aerospace equipment, and a vehicle-mounted device, etc.; the electronic device may also be a network device such as a base station. The embodiments of the present application do not impose any particular restrictions on the specific form of the electronic device.

[0048] FIG1 is an architecture diagram of an electronic device provided in an embodiment of the present application.

[0049] 1 , electronic device 1 includes components such as a storage device 11, a processor 12, an input device 13, and an output device 14. Those skilled in the art will appreciate that the architecture of electronic device 1 shown in FIG. 1 does not limit electronic device 1 . Electronic device 1 may include more or fewer components than those shown in FIG. 1 , may combine some of the components shown in FIG. 1 , or may have a different arrangement than that shown in FIG. 1 .

[0050] The storage device 11 is used to store software programs and modules. The storage device 11 primarily includes a program storage area and a data storage area. The program storage area can store and back up the operating system and at least one application required for a function (such as a sound playback function or an image playback function). The data storage area can store data generated based on the use of the electronic device 1 (such as audio data, image data, a phone book, etc.). Furthermore, the storage device 11 includes an external memory 111 and an internal memory 112. Data stored in the external memory 111 and the internal memory 112 can be transferred between them.

[0051] The external memory 111 may include, for example, a hard disk, a USB flash drive, a floppy disk, etc. The internal memory 112 may include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), resistance random access memory (RRAM), phase change random access memory (PCRAM), ferroelectric random access memory (FeRAM), ferroelectric field-effect transistor (FeFET) memory, ferroelectric tunnel junction (FTJ) memory, NAND flash memory, etc.

[0052] The processor 12 is the control center of the electronic device 1. It connects the various components of the electronic device 1 using various interfaces and circuits. It executes the various functions of the electronic device 1 and processes data by running or executing software programs and / or modules stored in the storage device 11 and accessing data stored in the storage device 11. Optionally, the processor 12 may include one or more processing units. For example, the processor 12 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), etc. The different processing units may be independent devices or integrated into one or more processors. For example, the processor 12 may integrate an application processor and a modem processor, where the application processor primarily processes the operating system, user interface, and application programs, while the modem processor primarily handles wireless communications. It is understood that the modem processor may not be integrated into the processor 12. The application processor may be, for example, a central processing unit (CPU). In Figure 1, the processor 12 is a CPU, which may include an arithmetic unit 121 and a controller 122. The arithmetic unit 121 obtains and processes the data stored in the internal memory 112, and the processed results are usually sent back to the internal memory 112. The controller 122 can control the arithmetic unit 121 to process the data, and the controller 122 can also control the external memory 111 and the internal memory 112 to read or write data.

[0053] The input device 13 is used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the electronic device. For example, the input device 13 may include a touch screen and other input devices. The touch screen, also known as a touch panel, can collect user touch operations on or near the touch screen (such as operations performed by the user using a finger, stylus, or any other suitable object or accessory on or near the touch screen) and drive the corresponding connection device according to a pre-set program. The controller 122 in the above-mentioned processor 12 can also control the input device 13 to receive input signals or not. In addition, the input digital or character information received by the input device 13, and the key signal input related to the user settings and function control of the electronic device can be stored in the internal memory 112.

[0054] The output device 14 is used to output signals corresponding to the inputs of the input device 13 and the data stored in the internal memory 112. For example, the output device 14 outputs an audio signal or a video signal. The controller 122 in the processor 12 can also control the output device 14 to output a signal or not output a signal.

[0055] It should be noted that the thick arrows in Figure 1 are used to represent the transmission of data, and the direction of the thick arrows represents the direction of data transmission. For example, the single arrow between the input device 13 and the internal memory 112 represents that the data received by the input device 13 is transmitted to the internal memory 112. For another example, the double arrow between the operator 121 and the internal memory 112 represents that the data stored in the internal memory 112 can be transmitted to the operator 121, and the data processed by the operator 121 can be transmitted to the internal memory 112. The thin arrows in Figure 1 represent components that can be controlled by the controller 122. For example, the controller 122 can control the external memory 111, the internal memory 112, the operator 121, the input device 13, the output device 14, etc.

[0056] FIG2 is an exploded view of an electronic device provided in an embodiment of the present application.

[0057] Referring to Figure 2, taking the electronic device 1 as a mobile phone as an example, the electronic device 1 includes a middle frame 15, a rear shell 16 and a display screen 17. The rear shell 16 and the display screen 17 are respectively located on opposite sides of the middle frame 15. The middle frame 15 includes a supporting plate 150 and a frame 151 surrounding the supporting plate 150. The supporting plate 150 is used to support the display screen 17.

[0058] Continuing to refer to Figure 2, the electronic device 1 may further include a circuit board 18, which is arranged on a side of the carrier board 150 close to the rear shell 16. The internal memory 112 in the electronic device 1 may be arranged on the circuit board 18, and the internal memory 112 is electrically connected to the circuit board 18.

[0059] Currently, DRAM is one of the mainstream memories and can be used as the internal memory 112. FIG3 is an architecture diagram of the memory provided in an embodiment of the present application.

[0060] 3 , the internal memory 112 includes a memory array 21 , a row decoding circuit 22 , a column decoding circuit 23 , a timing control circuit 24 , a read / write control circuit 25 , and a sense amplifier 26 .

[0061] The memory array 21 includes a plurality of memory cells 210 arranged in an array, wherein the plurality of memory cells 210 include a plurality of rows arranged along a first direction X and a plurality of columns arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, are perpendicular to each other.

[0062] The timing control circuit 24 is electrically connected to the row decoding circuit 22 , the column decoding circuit 23 , the memory array 21 , the read / write control circuit 25 , and the sense amplifier 26 , respectively. The timing control circuit 24 is configured to perform timing control on each circuit.

[0063] The row decoding circuit 22 is electrically connected to the memory array 21 . The row decoding circuit 22 is configured to select the memory cells 210 in the corresponding row according to the row address so as to address the memory cells 210 in the corresponding row.

[0064] The column decoding circuit 23 is electrically connected to the memory array 21. After the memory cells 210 of the corresponding row are selected, the column decoding circuit 23 is configured to address the memory cells 210 of the corresponding column according to the column address, thereby selecting the memory cells 210 that need to be read or written.

[0065] The read / write control circuit 25 is electrically connected to the memory array 21 , and is configured to control the selected memory cell 210 to perform a read operation or a write operation.

[0066] The sense amplifier 26 is electrically connected to the memory array 21. The sense amplifier 26 is configured to read, amplify and output the data information stored in the selected memory cell 210 to implement a data read operation; or input a data signal to the selected memory cell 210 to implement a data write operation.

[0067] FIG4 is a circuit diagram of a memory array provided in an embodiment of the present application.

[0068] 4 , the memory array 21 further includes a plurality of word lines (WL) extending along a direction X, a plurality of bit lines (BL) extending along a direction Y, and a plurality of plate lines (PL) extending along a direction Y. Each row of memory cells 210 is electrically connected to a word line WL, and each column of memory cells 210 is electrically connected to a bit line BL and a plate line PL.

[0069] Continuing with FIG4 , the memory cell 210 may have a 1T1C (1-Transistor-1-Capacitor) structure, that is, the memory cell 210 includes a transistor T and a capacitor C, the gate of the transistor T is electrically connected to the word line WL, the source is electrically connected to the bit line BL, the drain is electrically connected to one electrode of the capacitor C, and the other electrode of the capacitor C is electrically connected to the plate line PL. The circuit architecture of the memory cell 210 in the embodiments of the present application is not limited thereto.

[0070] An embodiment of the present application provides a method for preparing a memory array. Figures 5A and 5B are flow charts of the preparation of a memory array provided in an embodiment of the present application; Figures 6A to 6S are structural diagrams corresponding to the steps of a method for preparing a memory array provided in an embodiment of the present application.

[0071] 5A , the method for preparing a memory array includes the following steps S1 to S5:

[0072] In FIG6A , (b) is a cross-sectional view of (a) along section line AA′; in FIG6B , (b) is a cross-sectional view of (a) along section line BB′.

[0073] S1: Referring to FIG. 6A and FIG. 6B , a first insulating layer 31 having a plurality of vias H is formed on a substrate 30 , wherein the plurality of vias H are arranged in an array. For example, the plurality of vias H include a plurality of rows and a plurality of columns. The vias H in each row are arranged along a direction X, and the vias H in each column are arranged along a direction Y.

[0074] For example, referring to FIG6A , a plate line PL is first formed on a substrate 30, and a first insulating layer 31 is formed above the plate line PL. Then, referring to FIG6B , a photolithography process is used to etch the first insulating layer 31 to form a plurality of via holes H in the first insulating layer 31. The bottoms of the via holes H expose the plate line PL.

[0075] Exemplarily, the plurality of via holes H arranged in an array include a plurality of rows and a plurality of columns, the via holes H in each row are arranged along a direction X, and the via holes H in each column are arranged along a direction Y.

[0076] S2: Referring to FIG. 6C and FIG. 6D , a first electrode 32, a dielectric layer 33, and a second electrode 34 are formed in the via hole H. The first electrode 32 is located on the surface of the via hole H, the dielectric layer 33 is located on the inner side of the first electrode 32, and the second electrode 34 is located on the inner side of the dielectric layer 33. The first electrode 32, the dielectric layer 33, and the second electrode 34 form a capacitor C. The second electrode 34 is surrounded by the first electrode 32. The first electrode 32 can be called a "bottom electrode", and the second electrode 34 can be called a "top electrode". The capacitor C has a "columnar capacitance structure".

[0077] Relative to the substrate 30, the surface P1 of the second electrode 34 on the side away from the substrate 30 is lower than the surface P2 of the first insulating layer 31 on the side away from the substrate 30, that is, relative to the substrate 30, the height of the surface P1 of the second electrode 34 is smaller than the height of the surface P2 of the first insulating layer 31, so as to form a first cavity C1 in the via H.

[0078] In some examples, referring to FIG. 5B , the above-mentioned S2 may include the following S21 to S24:

[0079] S21 : Referring to FIG. 6C , a first electrode 32 is formed on the surface of the via hole H. The first electrode 32 is connected to the plate line PL located at the bottom of the via hole H.

[0080] For example, the electrode material may be deposited on the entire surface to form the first electrode 32 . The first electrode 32 may cover the surface of the via H and may also cover the surface P2 of the first insulating layer 31 away from the substrate 30 .

[0081] S22 : Referring to FIG. 6C , a dielectric layer 33 is formed inside the first electrode 32 .

[0082] For example, a dielectric material may be deposited on the entire surface to form the dielectric layer 33 . The dielectric layer 33 covers the first electrode 32 , and in the via hole H, the dielectric layer 33 is located inside the first electrode 32 .

[0083] By way of example, the material of the dielectric layer 33 may include a dielectric material.

[0084] For example, the material of the dielectric layer 33 may include a ferroelectric material. In this case, the capacitor C formed by the first electrode 32 , the dielectric layer 33 , and the second electrode 34 is a ferroelectric capacitor.

[0085] S23 : Continuing to refer to FIG. 6C , a conductive material is deposited to form a filling layer 340 on the inner side of the dielectric layer 33 to fill the via hole H.

[0086] S24: Referring to FIG. 6C and FIG. 6D , the portion of the filling layer 340 away from the substrate 30 is removed to form a first cavity C1 in the via H, and the portion of the filling layer 340 that is retained forms the second electrode 34 , thereby achieving the simultaneous formation of the first cavity C1 in the via H during the preparation of the capacitor C.

[0087] For example, a recess process can be used to etch the filling layer 340 downward to form a first chamber C1. The first chamber C1 is subsequently used to form a barrier layer (the channel layer of the transistor T). The first chamber C1 defines the size of the channel layer, or in other words, the etching depth of the filling layer 340 depends on the height of the channel layer.

[0088] S3 : referring to FIG. 6E and FIG. 6F , a barrier layer 35 is formed in the via hole H. The barrier layer 35 is located inside the dielectric layer 33 and on a side of the second electrode 34 away from the substrate 30 .

[0089] It can be understood that the plurality of vias H include multiple rows and columns, so that the plurality of barrier layers 35 in the plurality of vias H include multiple rows and columns, each row of barrier layers 35 is arranged along direction X, and each column of barrier layers 35 is arranged along direction Y.

[0090] 6E and 6F , a sacrificial material or channel material may be deposited over the entire surface of the first chamber C1 to form a barrier film 350. A chemical mechanical polishing (CMP) process is then used to polish the upper surface of the barrier film 350 until the surface P2 of the first insulating layer 31, the first electrode 32, and the dielectric layer 33 are exposed. The remaining portion of the barrier film 350 forms the barrier layer 35.

[0091] Continuing with FIG6F , the blocking layer 35 contacts the second electrode 34. The blocking layer 35 includes a first surface M1 in contact with the second electrode 34. The second electrode 34 includes a second surface M2 in contact with the blocking layer 35. The boundary of the first surface M1 coincides with the boundary of the second surface M2, that is, the sizes of the ends of the blocking layer 35 and the second electrode 34 in contact are the same.

[0092] It can be understood that within the same via H, the barrier layer 35 is located inside the dielectric layer 33, and the second electrode 34 is also located inside the dielectric layer 33, with the barrier layer 35 located above the second electrode 34. On the XY plane, the position and size of the barrier layer 35 and the second electrode 34 are defined by the dielectric layer 33 within the same via H, so that the barrier layer 35 and the second electrode 34 have the same position and size, achieving "self-alignment" between the barrier layer 35 and the second electrode 34.

[0093] S4: Referring to FIG. 6F and FIG. 6G , the portion of the first insulating layer 31 outside the barrier layer 35 is removed, the portion of the first electrode 32 outside the barrier layer 35 is removed, and the portion of the dielectric layer 33 outside the barrier layer 35 is removed to expose the barrier layer 35 .

[0094] Illustratively, the first insulating layer 31 is first etched to remove the portion of the first insulating layer 31 outside the barrier layer 35, thereby exposing the portion of the first electrode 32 outside the barrier layer 35. Then, the first electrode 32 is etched to remove the portion of the first electrode 32 outside the barrier layer 35, thereby exposing the portion of the dielectric layer 33 outside the barrier layer 35. Finally, the dielectric layer 33 is etched to remove the portion of the dielectric layer 33 outside the barrier layer 35, thereby exposing the side surfaces of the barrier layer 35.

[0095] It can be understood that the material of the blocking layer 35 has a large etching selectivity ratio with the material of the first insulating layer 31, the first electrode 32 and the dielectric layer 33. Therefore, during the etching process of the first insulating layer 31, the first electrode 32 and the dielectric layer 33, the blocking layer 35 will not be etched and damaged, so as to retain the blocking layer 35.

[0096] S5 : referring to FIG. 6H to FIG. 6L , a gate dielectric layer 36 and a gate layer 37 are formed on the side of the barrier layer 35 .

[0097] For example, referring to FIG. 6H , an atomic layer deposition (Atomic Layer Deposition) process is used to deposit a gate dielectric material on the entire surface to form a gate dielectric film 360 on the outer side of the barrier layer 35 .

[0098] 6I , a conductive material is deposited over the entire surface to form a gate film 370 on the surface of the gate dielectric film 360. The gate dielectric film 360 includes a first portion a1 located on the side of the barrier layer 35 away from the substrate 30, and a second portion a2 located on the side of the barrier layer 35. The gate film 370 includes a third portion a3 located on the side of the barrier layer 35 away from the substrate 30, and a fourth portion a4 located on the side of the barrier layer 35.

[0099] 6I and 6J , the third portion a3 of the gate film 370 is removed, and the fourth portion a4 of the gate film 370 forms a gate layer 37 . The gate layer 37 surrounds the side of the barrier layer 35 . After the channel layer of the transistor T is subsequently formed, the gate layer 37 has the ability to control the channel layer, thereby increasing the operating voltage window of the transistor T.

[0100] For example, a dry etching process can be used to etch the gate film 370 downward. In the process of removing the third part a3 of the gate film 370, the part of the gate film 370 located on the surface of the first insulating layer 31 is also removed, so that the gate layers 37 located on the sides of the multiple blocking layers 35 are disconnected.

[0101] 6K , a dielectric material is deposited on the entire surface to form a second insulating layer 38 outside the barrier layer 35 . The second insulating layer 38 serves to fill and level the surface, facilitating subsequent grinding.

[0102] 6K and 6L , a chemical mechanical polishing process is used to polish the upper surface of the second insulating layer 38 and the first portion a1 of the gate dielectric film 360. The first portion a1 of the gate dielectric film 360 is removed to expose the surface of the barrier layer 35 away from the substrate 30. The second portion a2 of the gate dielectric film 360 serves as the gate dielectric layer 36. Furthermore, the remaining portion of the second insulating layer 38 covers the gate layer 37.

[0103] In FIG6M , (b) is a cross-sectional view of (a) along section line CC′.

[0104] After S5, referring to FIG6M, a first mask layer 39 is formed on the second insulating layer 38. For example, the first mask layer 39 may be a photoresist. The first mask layer 39 may be exposed and developed to form a plurality of first openings K1 on the first mask layer 39. Each first opening K1 extends along the direction X. Each first opening K1 exposes a row of barrier layers 35 in the direction X and exposes a portion of the second insulating layer 38 between the plurality of barrier layers 35 in the same row.

[0105] In FIG6N , (b) is a cross-sectional view of (a) along the section line DD′.

[0106] 6M and 6N , portions of the second insulating layer 38 located between the multiple barrier layers 35 in the same row are etched through the first opening K1 of the first mask layer 39 , and portions of the second insulating layer 38 located between the multiple barrier layers 35 in the same row are removed, so that each first opening K1 exposes the gate layer 37 on the side of a row of barrier layers 35 .

[0107] In FIG6O , (b) is a cross-sectional view of (a) along section line EE′.

[0108] 6O , a conductive material is deposited on the entire surface through the first opening K1 of the first mask layer 39 , and the conductive material fills the gap area G between the multiple barrier layers 35 in the same row to form a conductive connection layer 40 . The conductive connection layer 40 is connected to the gate layer 37 on the side of the multiple barrier layers 35 .

[0109] In FIG6P , (b) is a cross-sectional view of (a) along the section line FF′.

[0110] 6P , an etch-back process is adopted to etch the conductive connection layer 40 downward, leaving the portion of the conductive connection layer 40 filling between two adjacent barrier layers 35. The conductive connection layer 40 is connected in series with the gate layer 37 on the side of the barrier layer 35 in the same row to form a word line WL extending along the direction X. The width W of the word line WL depends on the width of the first opening K1. In the direction Y, the width of the first opening K1 can be greater than the size of the barrier layer 35, can be equal to the size of the barrier layer 35, or can be smaller than the size of the barrier layer 35, so that the width W of the word line WL can be greater than, equal to, or smaller than the size of the barrier layer 35.

[0111] Since the conductive connection layer 40 fills the gap area G between the multiple blocking layers 35, the surface P3 of the word line WL away from the capacitor C is flush, and the cross-sectional area of ​​the word line WL in the Y direction is larger, which is beneficial to reducing the resistance of the word line WL, thereby reducing the voltage drop of the voltage signal transmitted on the word line WL.

[0112] In FIG6Q , (b) is a cross-sectional view of (a) along section line GG′; (c) is a cross-sectional view of (a) along section line HH′.

[0113] 6Q , a dielectric material is deposited on the entire surface to form a third insulating layer 41 . The third insulating layer 41 covers the plurality of word lines WL.

[0114] In FIG6R , (b) is a cross-sectional view of (a) along section line II′; (c) is a cross-sectional view of (a) along section line JJ′.

[0115] 6Q and 6R , a chemical mechanical polishing process is used to grind the upper surface of the third insulating layer 41 until the upper surface of the barrier layer 35 is exposed.

[0116] In FIG6S , (b) is a cross-sectional view of (a) along section line KK′; (c) is a cross-sectional view of (a) along section line LL′.

[0117] 6S , a plurality of bit lines BL are formed, each bit line BL extends along a direction Y, and each bit line BL is connected to the same column barrier layer 35 .

[0118] For example, dielectric material is first deposited on the entire surface to form the fourth insulating layer 42. Then, an exposure and development process is used to etch the fourth insulating layer 42 to form a via hole, which exposes the barrier layer 35. Finally, a bit line BL is formed in the via hole of the fourth insulating layer 42.

[0119] It is understandable that the material of the barrier layer 35 is selected from a suitable channel material, and the barrier layer 35 can be directly used as the channel layer of the transistor T, which can simplify the process steps for preparing the channel layer.

[0120] The transistor T includes a barrier layer 35, a gate dielectric layer 36 and a gate layer 37. The barrier layer 35 is a vertical channel structure extending along the direction Z. The gate layer 37 is located on the side of the barrier layer 35. The gate dielectric layer 36 is located between the barrier layer 35 and the gate layer 37. The transistor T has a "vertical transistor structure".

[0121] The gate layer 37 serves as the gate of the transistor T. The gate layer 37 is part of the word line WL, meaning that the gate of the transistor T is electrically connected to the word line WL. The end of the barrier layer 35 connected to the bit line BL serves as the source of the transistor T. The barrier layer 35 is connected to the second electrode 34, and the end of the barrier layer 35 connected to the second electrode 34 serves as the drain of the transistor T. The transistor T is connected to the capacitor C to form a memory cell 210.

[0122] As described above, the blocking layer 35 and the second electrode 34 have the same position and size, and the blocking layer 35 and the second electrode 34 are "automatically aligned". Since the blocking layer 35 can directly serve as the channel layer of the transistor T, the channel layer and the second electrode 34 have the same position and size, thereby achieving "automatic alignment" between the channel layer and the second electrode 34, and the alignment accuracy between the channel layer and the second electrode 34 is high, thereby ensuring a stable connection between the transistor T and the capacitor C.

[0123] Compared to using an exposure and development process to etch a channel hole on the gate layer to form a channel layer, it is necessary to align the channel hole with the second electrode. In the above-mentioned preparation method of the present application, the capacitor C has a columnar capacitor structure. The columnar capacitor structure occupies a smaller area on the plane XY than the planar capacitor structure. The transistor T has a vertical transistor structure. The vertical transistor structure occupies a smaller area on the plane XY than the planar transistor structure, which is beneficial to reducing the area occupied by the memory cell 210 on the plane XY. The channel layer of the transistor T and the second electrode 34 are "automatically aligned" with high accuracy, which is beneficial to increasing the number of memory cells 210 per unit area on the plane XY, and increasing the arrangement density of the memory array 21, so that the memory array 21 reaches a 4F2 unit size, where "F" is the minimum feature size (Feature Size) of the chip manufacturing process, and "4F2 unit size" refers to twice the square of the minimum feature size (4F2=2F×2F).

[0124] Moreover, the process of "automatically aligning" the channel layer and the second electrode 34 does not require an exposure and development process. Only two exposure and development processes are used in the process of preparing the word line WL and the bit line BL. The preparation process is relatively simple and controllable, which helps to reduce process difficulty and cost.

[0125] An embodiment of the present application further provides another method for manufacturing a memory array. FIG. 7A to FIG. 7D are structural diagrams corresponding to the steps of another method for manufacturing a memory array provided in an embodiment of the present application.

[0126] In Figure 7A, (b) is a cross-sectional view of (a) along section line AA'; (c) is a cross-sectional view of (a) along section line BB'; in Figure 7B, (b) is a cross-sectional view of (a) along section line CC'; (c) is a cross-sectional view of (a) along section line DD'.

[0127] 7A , the structure shown in FIG. 7A may be formed by using the preparation steps of FIG. 6A to FIG. 6R in the aforementioned preparation method, with the upper surface of the barrier layer 35 exposed.

[0128] Unlike the fabrication method shown in Figures 6A to 6S , the material of barrier layer 35 in this embodiment is not a material that can be used as a channel layer, but rather a sacrificial material. For example, barrier layer 35 may include silicon nitride. Therefore, referring to Figures 7A and 7B , barrier layer 35 is removed, using it as a sacrificial layer to form second cavity C2, exposing second electrode 34 thereunder.

[0129] It is understood that the material of the blocking layer 35 has a large etching selectivity to the materials of the second insulating layer 38 and the third insulating layer 41 . Therefore, during the etching process of the blocking layer 35 , the second insulating layer 38 and the third insulating layer 41 will not be damaged.

[0130] In FIG7C , (b) is a cross-sectional view of (a) along section line EE′; (c) is a cross-sectional view of (a) along section line FF′.

[0131] 7C , a channel layer 43 of the transistor T is formed in the second chamber C2 . The channel layer 43 is connected to the second electrode 34 . The channel layer 43 , the gate dielectric layer 36 , and the gate layer 37 form the transistor T.

[0132] In FIG7D , (b) is a cross-sectional view of (a) along section line GG′; (c) is a cross-sectional view of (a) along section line HH′.

[0133] 7D , a plurality of bit lines BL are formed, each of which extends along a direction Y and is connected to the same column of channel layers 43 .

[0134] It is understandable that the film quality of the channel layer 43 will affect the electrical performance of the transistor T. The better the film quality of the channel layer 43 is, the better the electrical performance of the transistor T is.

[0135] By using the barrier layer 35 as a sacrificial layer, after forming the gate dielectric layer 36 and the gate layer 37 on the side of the barrier layer 35, the barrier layer 35 is removed to form the second chamber C2, and the channel layer 43 is formed in the second chamber C2. This achieves the replacement of the barrier layer 35 with the channel layer 43, and avoids pre-formation of the channel layer 43. Etching damage to the channel layer 43 during the process of forming the gate dielectric layer 36 and the gate layer 37 is avoided, which is beneficial to improving the film quality of the channel layer 43 and improving the electrical performance of the transistor T.

[0136] An embodiment of the present application further provides another method for preparing a memory array. FIG. 8A to FIG. 8F are structural diagrams corresponding to the steps of another method for preparing a memory array provided in an embodiment of the present application. Unlike the preparation method shown in FIG. 6A to FIG. 6S , this embodiment provides another method for preparing a word line WL.

[0137] Referring to FIG. 8A , the structure shown in FIG. 8A can be formed using the steps of FIG. 6A to FIG. 6I in the aforementioned fabrication method. A gate dielectric film 360 and a gate film 370 are formed outside the barrier layer 35. The gate dielectric film 360 includes a first portion a1 located on the side of the barrier layer 35 away from the substrate 30, and a second portion a2 located on the side of the barrier layer 35. The gate film 370 includes a third portion a3 located on the side of the barrier layer 35 away from the substrate 30, a fourth portion a4 located on the side of the barrier layer 35, and a fifth portion a5 located on the surface of the first insulating layer 31. The fifth portion a5 is connected to the fourth portion a4.

[0138] 8B , a dielectric material is deposited on the entire surface to form a fifth insulating layer 44 covering the gate film 370 . The fifth insulating layer 44 serves to fill and level the gate film 370 , facilitating subsequent polishing.

[0139] 8B and 8C , a chemical mechanical polishing process is used to polish the upper surface of the fifth insulating layer 44, the third portion a3 of the gate film 370, and the first portion a1 of the gate dielectric film 360. The third portion a3 of the gate film 370 and the first portion a1 of the gate dielectric film 360 are removed to expose the upper surface of the barrier layer 35. The fourth portion a4 of the gate film 370 serves as the gate layer 37, and the second portion a2 of the gate dielectric film 360 serves as the gate dielectric layer 36.

[0140] In FIG8D , (b) is a cross-sectional view of (a) along the section line AA′.

[0141] 8D , a second mask layer 45 is formed. For example, the second mask layer 45 may be a photoresist. The second mask layer 45 may be exposed and developed to form a plurality of second openings K2 on the second mask layer 45. Each second opening K2 extends along a direction X, and each second opening K2 exposes an area (fifth insulating layer 44) between two adjacent rows of blocking layers 35.

[0142] In FIG8E , (b) is a cross-sectional view of (a) along section line BB′; and (c) is a cross-sectional view of (a) along section line CC′.

[0143] 8D and 8E , the fifth insulating layer 44 is etched through the second opening K2 of the second mask layer 45 to expose the fourth portion a4 and the fifth portion a5 of the gate film 370. Then, the fifth portion a5 of the gate film 370 is etched through the second opening K2 of the second mask layer 45 to remove a portion of the fifth portion a5 of the gate film 370, thereby disconnecting the gate film 370 in the direction Y. The remaining portion of the fifth portion a5 serves as a conductive connection layer, which together with the fourth portion a4 (the gate layer 37 on the side of the same row of barrier layer 35) forms a plurality of word lines WL extending in the direction X. A surface P3 of the fifth portion a5, away from the capacitor C, is recessed in the direction V toward the capacitor C, resulting in a smaller cross-sectional area of ​​the word lines WL in the Y direction, thereby saving material used in forming the word lines.

[0144] In FIG8F , (b) is a cross-sectional view of (a) along section line DD′; (c) is a cross-sectional view of (a) along section line EE′.

[0145] Referring to FIG8F , a dielectric material is first deposited over the entire surface to form a sixth insulating layer 46 covering the barrier layer 35 and the gate layer 37. Subsequently, a plurality of vias 47 are formed in the sixth insulating layer 46, exposing the upper surface of the barrier layer 35. Finally, a plurality of bit lines BL are formed, each extending in a direction Y and connected to the same column of barrier layers 35.

[0146] The preparation method provided in the above-mentioned embodiment of the present application adopts a chemical mechanical polishing process to grind the gate film 370 to form a gate layer 37, and disconnects the gate layer 37 in the direction Y by etching to form multiple word lines WL, which simplifies the preparation process of the word lines WL and helps to reduce process costs.

[0147] An embodiment of the present application further provides a storage array. FIG9 is a cross-sectional view of a storage array provided in an embodiment of the present application along plane XZ; FIG10 is a cross-sectional view of a storage array provided in an embodiment of the present application along plane YZ.

[0148] 9 and 10 , along direction Z, the storage array 21 includes a plurality of storage structures 211 stacked together. Any one or more of the plurality of storage structures 211 can be prepared using the preparation method described above.

[0149] The storage array 21 is a three-dimensional storage array. Each storage structure 211 includes a plurality of storage units 210 arranged in an array. The three-dimensional stacking is beneficial to increase the number of storage units 210 per unit area on the plane XY, thereby improving the arrangement density of the storage array 21.

[0150] 9 , the memory array 21 further includes a word line connection structure 48 that extends through the stacked plurality of memory structures 211. Along direction Z, the word lines WL in the plurality of memory structures 211 correspond to each other, and the corresponding word lines WL are connected by the word line connection structure 48.

[0151] Similarly, referring to FIG10 , memory array 21 further includes a bit line connection structure 49 that extends through the stacked plurality of memory structures 211. Along direction Z, the plurality of bit lines BL in the plurality of memory structures 211 correspond to each other, and the corresponding plurality of bit lines BL are connected together by bit line connection structure 49.

[0152] An embodiment of the present application further provides a storage array. FIG11 is a structural diagram of another storage array provided in an embodiment of the present application.

[0153] 11 , the memory array 21 includes a plurality of memory cells 210 arranged in an array. The memory cell 210 may have a 1TnC (1-Transistor-n-Capacitor) structure, where n is an integer greater than 1, i.e., the memory cell 210 includes a transistor T and a plurality of capacitors C.

[0154] Along the direction Z, the first electrodes 32 of the plurality of capacitors C are stacked and spaced apart. The second electrode 34 of each capacitor C extends through its first electrode 32, and the second electrodes 34 of the plurality of capacitors C are connected. For example, the second electrodes 34 of the plurality of capacitors C are integrally arranged to form a columnar electrode 50. The channel layer 43 of the transistor T is connected to the second electrodes 34 of the plurality of capacitors C (the top ends of the columnar electrodes 50).

[0155] It is understandable that the above-mentioned storage array 21 can also be prepared using the preparation method described above. On the plane XY, the position and size of the channel layer 43 and the columnar electrode 50 are defined by the same dielectric layer 33, so that the channel layer 43 and the columnar electrode 50 have the same position and size, thereby achieving "automatic alignment" of the channel layer 43 and the columnar electrode 50.

[0156] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A storage array, characterized in that, The storage array includes a plurality of memory cells arranged in an array, and the memory cell includes a capacitor and a transistor; The capacitor includes a first electrode, a dielectric layer, and a second electrode. The first electrode is disposed around the second electrode, and the dielectric layer is located between the first electrode and the second electrode; The transistor is disposed on the capacitor. The transistor includes a channel layer, a gate dielectric layer, and a gate electrode layer. The gate electrode layer surrounds the side surface of the channel layer, and the gate dielectric layer is located between the channel layer and the gate electrode layer; Wherein, the channel layer is in contact with the second electrode. The channel layer includes a first surface in contact with the second electrode, and the second electrode includes a second surface in contact with the channel layer. The boundary of the first surface coincides with the boundary of the second surface.

2. The storage array according to claim 1, wherein The storage array further includes a plurality of word lines; The plurality of memory cells arranged in an array include multiple rows and multiple columns. The gate electrode layers of the multiple transistors in one row of memory cells are connected together to form one of the word lines; The word line includes a conductive connection layer located between the gate electrode layers of two adjacent transistors. The surface of the conductive connection layer away from the capacitor is recessed in a direction close to the capacitor, or the conductive connection layer fills the gap region between the gate electrode layers of two adjacent transistors.

3. The storage array according to claim 1 or 2, wherein The storage array further includes a plurality of bit lines, and the bit lines are disposed on a side of the transistor away from the capacitor; The plurality of memory cells arranged in an array include multiple rows and multiple columns. Each bit line is electrically connected to the channel layers of multiple transistors in one column of memory cells.

4. The storage array according to any one of claims 1 to 3, characterized in that, The storage array further includes a plate line, and the plate line is disposed on a side of the capacitor away from the transistor; The first electrodes of the multiple capacitors in the plurality of memory cells are electrically connected to the plate line.

5. The storage array according to any one of claims 1 to 4, characterized in that, The memory cell includes a plurality of the capacitors and one transistor; Along the direction from the capacitor to the transistor, the first electrodes of the plurality of capacitors are stacked and spaced apart, and the second electrodes of the plurality of capacitors are connected together to form a columnar electrode; The channel layer of the transistor is connected to one end of the columnar electrode.

6. The storage array according to any one of claims 1 to 5, characterized in that, Along the direction from the capacitor to the transistor, the storage array includes a plurality of storage structures stacked. Each storage structure includes a plurality of the memory cells arranged in an array.

7. The storage array according to any one of claims 1 to 6, characterized in that The material of the dielectric layer includes a ferroelectric material.

8. A method for preparing a storage array, characterized in that, Including: Forming an insulating layer having a plurality of vias on a substrate, and the plurality of vias are arranged in an array; Forming a first electrode, a dielectric layer, and a second electrode in the via. The first electrode is located on the surface of the via, the dielectric layer is located inside the first electrode, and the second electrode is located inside the dielectric layer; Relative to the substrate, the surface of the second electrode away from the substrate is lower than the surface of the insulating layer away from the substrate; Forming a barrier layer in the via. The barrier layer is located inside the dielectric layer and on a side of the second electrode away from the substrate; Remove the part of the insulating layer outside the barrier layer, remove the part of the first electrode outside the barrier layer, and remove the part of the dielectric layer outside the barrier layer to expose the barrier layer; Form a gate dielectric layer and a gate layer on the side of the barrier layer.

9. The preparation method according to claim 8, characterized in that, Form a first electrode, a dielectric layer, and a second electrode in the via, including: Form the first electrode on the surface of the via; Form the dielectric layer inside the first electrode; Deposit a conductive material to form a filling layer inside the dielectric layer; Remove the part of the filling layer away from the substrate to form a first chamber in the via, and the remaining part of the filling layer forms the second electrode; Form a barrier layer in the via, including: Form the barrier layer in the first chamber.

10. The preparation method according to claim 8 or 9, characterized in that, Form a gate dielectric layer and a gate layer on the side of the barrier layer, including: Form a gate dielectric thin film and a gate thin film on the outside of the barrier layer. The gate dielectric thin film at least includes a first part on the side of the barrier layer away from the substrate and a second part on the side of the barrier layer; the gate thin film at least includes a third part on the side of the barrier layer away from the substrate and a fourth part on the side of the barrier layer; Remove the third part of the gate thin film and remove the first part of the gate dielectric thin film to expose the surface of the barrier layer away from the substrate; Wherein, the second part serves as the gate dielectric layer, and the fourth part serves as the gate layer.

11. The preparation method according to claim 10, characterized in that, The multiple vias include multiple rows and multiple columns, and the multiple barrier layers in the multiple vias include multiple rows and multiple columns; After forming a gate dielectric layer and a gate layer on the side of the barrier layer, the manufacturing method further includes: Form a first mask layer, the first mask layer having a plurality of first openings, each first opening exposing the gate layer on the side of a row of barrier layers; Deposit a conductive material, and through the first opening, form a conductive connection layer between the multiple barrier layers in the same row. The conductive connection layer is connected to the gate layers on the sides of the multiple barrier layers to form a word line.

12. The preparation method according to claim 10, wherein, The multiple vias include multiple rows and multiple columns, and the multiple barrier layers in the multiple vias include multiple rows and multiple columns; The gate thin film further includes a fifth part on the surface of the insulating layer, and the fifth part is connected to the gate layers on the sides of the multiple barrier layers; After forming a gate dielectric layer and a gate layer on the side of the barrier layer, the manufacturing method further includes: Form a second mask layer, the second mask layer having a plurality of second openings, each second opening exposing the region between adjacent two rows of barrier layers; Through the second opening, remove a part of the fifth part of the gate thin film, and the remaining part of the fifth part and the gate layers on the sides of the barrier layers in the same row together form a word line.

13. The preparation method according to any one of claims 8 to 12, characterized in that, The barrier layer serves as the channel layer of the transistor, and the transistor includes the barrier layer, the gate dielectric layer, and the gate layer.

14. The preparation method according to any one of claims 8 to 12, characterized in that, The barrier layer serves as a sacrificial layer. After forming a gate dielectric layer and a gate layer on the side of the barrier layer, the manufacturing method further includes: Remove the barrier layer to form a second chamber; A channel layer of a transistor is formed in the second chamber, and the transistor includes the channel layer, the gate dielectric layer, and the gate layer.

15. A memory, characterized in that, Comprising: The memory array according to any one of claims 1 to 7; A controller, the memory array being electrically connected to the controller.

16. An electronic device, characterized in that, Comprising: The memory according to claim 15; A circuit board, the memory being electrically connected to the circuit board.

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