Multilayer ceramic capacitor

Abstract

A portion of a second end surface (B) of at least one of a plurality of first via conductors (140) and a plurality of second via conductors (150) is recessed toward a first main surface (101) side in a stacking direction. A region of a second main surface (102) that overlaps an inner layer part (E) in the stacking direction is defined as a first region (A1), a region of the second main surface (102) that does not overlap the inner layer part (E) is defined as a second region (A2), and a region of the second main surface (102) that overlaps the at least one of the plurality of first via conductors (140) and the plurality of second via conductors (150) is defined as a third region (A3). In the second region (A2), a recessed part (C) recessed in the stacking direction is formed. A maximum thickness (G1) in the stacking direction of a second outer layer part (112) positioned between the third region (A3) and the second end surface (B) is greater than a minimum thickness (G2) in the stacking direction of the second outer layer part (112) positioned between the third region (A3) and an internal electrode layer positioned closest to the third region (A3) in the stacking direction among a plurality of first internal electrode layers (120) and a plurality of second internal electrode layers (130).

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Japanese Patent Laid-Open Publication No. 2021-48261 (Patent Document 1) is a prior art document disclosing the configuration of a multilayer capacitor. The multilayer capacitor described in Patent Document 1 includes a laminate, a plurality of first external electrodes, a plurality of second external electrodes, a plurality of first via conductors, and a plurality of second via conductors. In the laminate, a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are stacked. The plurality of first external electrodes and a plurality of second external electrodes are formed on the outer surface of the laminate. The plurality of first via conductors electrically connect the first external electrode and the plurality of first internal electrodes. The plurality of second via conductors electrically connect the second external electrode and the plurality of second internal electrodes. A through hole is formed in the second internal electrode, and the first via conductor passes through the through hole while being insulated from the second internal electrode. A through hole is formed in the first internal electrode, and the second via conductor passes through the through hole while being insulated from the first internal electrode. Neither the first external electrode nor the second external electrode is formed on one of the main surfaces, but only on the other main surface.

[0003] Japanese Patent Application Laid-Open No. 2021-48261

[0004] Multilayer ceramic capacitors are required to be thinner and have higher capacitance. From the viewpoint of achieving thinner thickness and higher capacitance, the dielectric layers that form the outer layers have been formed thinner. If the dielectric layers that form the outer layers are too thin to ensure the mechanical durability of the dielectric layers in the portions covering the first via conductors and the second via conductors, cracks are likely to occur in the dielectric layers in those portions. These cracks may become a path for moisture to penetrate into the interior of the laminate through the first via conductors and the second via conductors, thereby reducing the moisture resistance reliability of the multilayer ceramic capacitor.

[0005] The present invention has been made in consideration of the above-mentioned problems, and aims to provide a multilayer ceramic capacitor that can be made thinner and have a higher capacity while improving the mechanical durability and moisture resistance reliability of the dielectric layer covering the first via conductor and the second via conductor.

[0006] A multilayer ceramic capacitor according to the present invention comprises a laminate, a plurality of first via conductors, and a plurality of second via conductors. The laminate includes a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately stacked in a stacking direction with a dielectric layer sandwiched therebetween, and has a first main surface and a second main surface located on the opposite side of the first main surface in the stacking direction. The plurality of first via conductors are provided inside the laminate and electrically connected to the plurality of first internal electrode layers. The plurality of second via conductors are provided inside the laminate and electrically connected to the plurality of second internal electrode layers. The laminate includes an internal layer portion, a first external layer portion, and a second external layer portion. In the internal layer portion, opposing portions of the first internal electrode layers and the second internal electrode layers are stacked in the stacking direction. The first external layer portion is adjacent to the internal layer portion in the stacking direction and forms the first main surface. The second external layer portion is adjacent to the internal layer portion in the stacking direction and forms the second main surface. A first end face of each of the plurality of first via conductors and the plurality of second via conductors on the first principal surface side is exposed to the first principal surface, a second end face of each of the plurality of first via conductors and the plurality of second via conductors on the second principal surface side is covered by a second outer layer portion, and a portion of the second end face of at least one of the plurality of first via conductors and the plurality of second via conductors is recessed toward the first principal surface in the stacking direction. On the second main surface, if the region overlapping with the inner layer portion in the stacking direction is defined as the first region, the region not overlapping with the inner layer portion is defined as the second region, and the region overlapping with at least one of the plurality of first via conductors and the plurality of second via conductors is defined as the third region, a recess recessed in the stacking direction is formed within the second region, and the maximum thickness in the stacking direction of the second outer layer portion located between the third region and the second end face is thicker than the minimum thickness in the stacking direction of the second outer layer portion located between the internal electrode layer located closest to the third region in the stacking direction among the plurality of first internal electrode layers and the plurality of second internal electrode layers.

[0007] According to the present invention, it is possible to reduce the thickness and increase the capacitance of a multilayer ceramic capacitor while improving the mechanical durability and moisture resistance reliability of the dielectric layer in the portion covering the first via conductor and the second via conductor.

[0008] 1 is a plan view of a multilayer ceramic capacitor according to an embodiment of the present invention, viewed from the first main surface side; FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1, viewed from the direction of the arrows along line II-II; FIG. 3 is a bottom view of a multilayer ceramic capacitor according to an embodiment of the present invention, viewed from the second main surface side; FIG. 4 is a cross-sectional view showing an enlarged view of the periphery of a second via conductor in FIG. 2; FIG. 5 is a flowchart showing a manufacturing method of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 6 is an image obtained by enlarging the periphery of a first via conductor in a multilayer ceramic capacitor according to an example; and FIG. 7 is a plan view of a multilayer ceramic capacitor according to a modified embodiment of the present invention, viewed from the first main surface side.

[0009] A multilayer ceramic capacitor according to an embodiment of the present invention will now be described with reference to the drawings. In the following description of the embodiment, the same or corresponding parts in the drawings will be designated by the same reference numerals, and description thereof will not be repeated.

[0010] Fig. 1 is a plan view of a multilayer ceramic capacitor according to an embodiment of the present invention, viewed from the first main surface side. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1, viewed from the direction of the arrows along line II-II. Fig. 3 is a bottom view of the multilayer ceramic capacitor according to an embodiment of the present invention, viewed from the second main surface side. Fig. 4 is an enlarged cross-sectional view showing the periphery of a second via conductor in Fig. 2.

[0011] As shown in FIGS. 1 to 4, a multilayer ceramic capacitor 100 according to one embodiment of the present invention includes a laminate 10, a plurality of first via conductors 140, and a plurality of second via conductors 150.

[0012] As shown in Figures 2 and 4, the laminate 10 includes a plurality of first internal electrode layers 120 and a plurality of second internal electrode layers 130 alternately stacked in the stacking direction with dielectric layers 110 sandwiched between them, and has a first main surface 101 and a second main surface 102 located on the opposite side of the first main surface 101 in the stacking direction.

[0013] The dielectric layer 110 may be made of any material, such as a ceramic material containing BaTiO, CaTiO, SrTiO, SrZrO, or CaZrO as a main component. A minor component selected from the group consisting of a Mn compound, an Fe compound, a Cr compound, a Co compound, and a Ni compound may be added to the main component in a smaller amount than the main component.

[0014] The laminate 10 may have any shape. In this embodiment, the laminate 10 has a rectangular parallelepiped shape as a whole. A rectangular parallelepiped shape as a whole refers to a shape that is not a perfect rectangular parallelepiped shape, such as a shape in which the corners and ridges of a rectangular parallelepiped are rounded, but has six surfaces and can be considered as a rectangular parallelepiped as a whole. Therefore, the laminate 10 has a first main surface 101, a second main surface 102, a first side surface 103, a second side surface 104, a third side surface 105, and a fourth side surface 106.

[0015] The first side surface 103 to the fourth side surface 106 of the laminate 10 constitute four side surfaces of the surface of the laminate 10 other than the first main surface 101 and the second main surface 102. That is, the laminate 10 further has the first side surface 103 to the fourth side surface 106, which are four side surfaces connecting the first main surface 101 and the second main surface 102. The first side surface 103 faces the second side surface 104, and the third side surface 105 faces the fourth side surface 106. In this embodiment, the first side surface 103 to the fourth side surface 106 of the laminate 10 are orthogonal to the first main surface 101 and the second main surface 102, respectively, but they do not have to be orthogonal.

[0016] The dimensions of the laminate 10 are arbitrary, but for example, when viewed from the first main surface 101 side, the vertical dimension of the rectangle can be 0.3 mm to 3.0 mm, the horizontal dimension can be 0.3 mm to 3.0 mm, and the dimensions in the stacking direction of the dielectric layers 110, the first internal electrode layers 120 and the second internal electrode layers 130 can be 50 μm to 200 μm. The dimension of the laminate 10 in the stacking direction refers to the maximum thickness of the laminate 10.

[0017] Each of the plurality of first internal electrode layers 120 and the plurality of second internal electrode layers 130 has a rectangular outer shape. As shown in Figures 2 and 4, each of the plurality of first internal electrode layers 120 has a plurality of first through holes 120h formed therein for inserting a plurality of second via conductors 150 therethrough. Each of the plurality of second internal electrode layers 130 has a plurality of second through holes 130h formed therein for inserting a plurality of first via conductors 140 therethrough.

[0018] The material of the first internal electrode layer 120 and the second internal electrode layer 130 is arbitrary, and for example, contains a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or an alloy containing these metals, as a main component. The first internal electrode layer 120 and the second internal electrode layer 130 may contain, as a common material, the same ceramic material as the dielectric ceramic contained in the dielectric layer 110. In that case, the ratio of the common material contained in the first internal electrode layer 120 and the second internal electrode layer 130 is, for example, 20 vol % or less.

[0019] The thickness of each of the first internal electrode layers 120 and the second internal electrode layers 130 is arbitrary, but can be, for example, about 0.3 μm or more and 1.0 μm or less. The number of layers of the first internal electrode layers 120 and the second internal electrode layers 130 is arbitrary, but can be, for example, about 10 layers or more and 150 layers or less in total.

[0020] 2 and 4 , the laminate 10 includes an inner layer portion E, a first outer layer portion 111, and a second outer layer portion 112. In the inner layer portion E, opposing portions of the first internal electrode layer 120 and the second internal electrode layer 130 are stacked in the stacking direction. The first outer layer portion 111 is adjacent to the inner layer portion E in the stacking direction and constitutes the first main surface 101. The second outer layer portion 112 is adjacent to the inner layer portion E in the stacking direction and constitutes the second main surface 102. Each of the first outer layer portion 111 and the second outer layer portion 112 is composed of a dielectric layer 110.

[0021] The plurality of first via conductors 140 are provided inside the laminate 10 and are electrically connected to the plurality of first internal electrode layers 120. The plurality of first via conductors 140 are inserted through second through holes 130h formed in each of the plurality of second internal electrode layers 130 and are insulated from the plurality of second internal electrode layers 130. As shown in Fig. 1 , in this embodiment, the plurality of first via conductors 140 are arranged in a zigzag pattern along the sides of the first main surface 101 when viewed from the stacking direction. The first internal electrode layer 120 is electrically connected to four first via conductors 140 arranged in two rows.

[0022] The plurality of second via conductors 150 are provided inside the laminate 10 and are electrically connected to the plurality of second internal electrode layers 130. The plurality of second via conductors 150 are inserted through first through holes 120h formed in each of the plurality of first internal electrode layers 120 and are insulated from the plurality of first internal electrode layers 120. In this embodiment, the plurality of second via conductors 150 are arranged in a zigzag pattern along the sides of the first main surface 101 when viewed from the stacking direction. The first via conductors 140 and the second via conductors 150 are arranged side by side in a matrix. The second internal electrode layer 130 is electrically connected to five second via conductors 150.

[0023] Each of the plurality of first via conductors 140 and the plurality of second via conductors 150 is provided inside the laminate 10 in a manner extending in the stacking direction from the first main surface 101 to the second main surface 102 of the laminate 10. That is, each of the plurality of first via conductors 140 and the plurality of second via conductors 150 is exposed on the first main surface 101 of the laminate 10 but not on the second main surface 102. Specifically, a first end face T on the first main surface 101 side of each of the plurality of first via conductors 140 and the plurality of second via conductors 150 is exposed on the first main surface 101. A second end face B on the second main surface 102 side of each of the plurality of first via conductors 140 and the plurality of second via conductors 150 is covered by the second outer layer portion 112. This makes it possible to prevent a short circuit from occurring between the multilayer ceramic capacitor 100 and an electronic component arranged on the second main surface 102 side.

[0024] By arranging the multiple first via conductors 140 and the multiple second via conductors 150 in an alternating zigzag pattern as described above, the magnetic fields induced by the currents flowing through the first via conductors 140 and the second via conductors 150 cancel each other out, thereby reducing the equivalent series inductance (ESL) of the multilayer ceramic capacitor 100.

[0025] The first via conductor 140 and the second via conductor 150 may have any shape, for example, a cylindrical shape. In this case, the diameter of each of the first via conductor 140 and the second via conductor 150 is, for example, 35 μm or more and 70 μm or less. The distance between adjacent first via conductors 140 and second via conductors 150, more specifically, the distance between the centers of the first via conductors 140 and second via conductors 150, is, for example, approximately 50 μm or more and 500 μm or less.

[0026] The material of the first via conductor 140 and the second via conductor 150 is arbitrary, and for example, metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals, can be used.

[0027] 2 and 4 , a portion of the second end face B of at least one of the plurality of first via conductors 140 and the plurality of second via conductors 150 is recessed toward the first main surface 101 in the stacking direction. It is preferable that a portion of the second end face B of all of the plurality of first via conductors 140 and the plurality of second via conductors 150 is recessed toward the first main surface 101 in the stacking direction.

[0028] In this embodiment, the central portion of the second end face B is recessed toward the first main surface 101 in the stacking direction. Specifically, the second end face B is curved in a concave shape toward the first main surface 101 in the stacking direction. Note that only the central portion of the second end face B may be recessed toward the first main surface 101 in the stacking direction, or only the entire or partial portion of the portion between the edge and the central portion of the second end face B may be recessed toward the first main surface 101 in the stacking direction.

[0029] 2 to 4, on the second main surface 102, the region overlapping with the inner layer portion E in the stacking direction is defined as the first region A1, the region not overlapping with the inner layer portion E is defined as the second region A2, and the region overlapping with at least one of the plurality of first via conductors 140 and the plurality of second via conductors 150 is defined as the third region A3. A recess C recessed in the stacking direction is formed within the second region A2, and as shown in FIGS. 2 and 4, the maximum thickness G1 in the stacking direction of the second outer layer portion 112 located between the third region A3 and the second end face B is thicker than the minimum thickness G2 in the stacking direction of the second outer layer portion 112 located between the third region A3 and the internal electrode layer located closest to the third region A3 in the stacking direction among the plurality of first internal electrode layers 120 and the plurality of second internal electrode layers 130. The third region A3 is included in the second region A2.

[0030] 4, the dimension of the maximum depth D of the recess C in the stacking direction is, for example, 1 μm or more and 2.5 μm or less. The difference between the maximum thickness G1 and the minimum thickness G2 is, for example, 2 μm or more. The ratio of the difference between the maximum thickness G1 and the minimum thickness G2 to the dimension of the maximum depth D is, for example, 0.8 or more. Note that the above dimensions and dimensional relationships need only be satisfied in at least one recess C in any longitudinal cross section.

[0031] A plurality of external electrodes connected to the first via conductors 140 and the second via conductors 150 may be formed on the first main surface 101. The material of the external electrodes is arbitrary. For example, the external electrodes are plated electrodes formed by a plating process using a rotary plating method. Examples of materials that constitute the plated electrodes include Cu, Ni, and Sn. The plated electrodes may be composed of a single layer or multiple layers. The external electrodes may be formed by firing a metal paste applied to the first main surface 101. The metal paste may contain a glassy inorganic material as a co-material.

[0032] Here, a method for manufacturing the multilayer ceramic capacitor 100 according to one embodiment of the present invention will be described.

[0033] 5 is a flowchart showing a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention. As shown in FIG. 5, first, an intermediate laminate is prepared (S1) in which ceramic green sheets that will become the inner layer portion E and the first outer layer portion 111 are laminated. The ceramic green sheets that will become the inner layer portion E are coated with a conductive paste that will become the first internal electrode layer 120 and the second internal electrode layer 130, while the ceramic green sheets that will become the first outer layer portion 111 are not coated with the conductive paste.

[0034] Next, the intermediate laminate is pressed from both sides in the stacking direction (S2). At this time, an elastic body arranged on a rigid body abuts against the first main surface 101 side, and an elastic body arranged on a rigid body abuts against the second main surface 102 side. The rigid body is made of metal, and the elastic body is made of resin. The elastic body is, for example, a polyethylene terephthalate (PET) film. Compared to the inner layer portion E, there are fewer layers of conductive paste that will become the first internal electrode layers 120 and second internal electrode layers 130 around the first via conductors 140 and second via conductors 150. Therefore, when pressed, the surrounding areas of the first via conductors 140 and second via conductors 150 are pressed against the elastic body and pushed into the inside of the intermediate laminate.

[0035] Next, through holes for via conductors are formed in the intermediate laminate at positions where first via conductors 140 and second via conductors 150 are to be formed (S3). The through holes for via conductors are formed, for example, by irradiation with laser light.

[0036] Next, the via conductor through holes are filled with conductive paste to become the first via conductors 140 and the second via conductors 150 (S4). At this time, the filling rate of the conductive paste in the via conductor through holes is reduced to a range of 90% to 95% of the normal filling rate. The normal filling rate is a filling rate that is set so that the via conductor through holes are filled with the first via conductors 140 and the second via conductors 150 just enough after firing, which will be described later.

[0037] Next, a ceramic green sheet that will become second outer layer portion 112 is attached to the intermediate laminate to form an unsintered laminate (S5). This blocks one end of the via conductor through hole on the second main surface 102 side. At this time, the conductive paste that will become first via conductors 140 and second via conductors 150 and the ceramic green sheet that will become second outer layer portion 112 may be in contact with each other or may be spaced apart from each other.

[0038] Next, the green laminate is pressed from both sides in the stacking direction (S6). At this time, an elastic body arranged on a rigid body abuts against the first main surface 101 side, and an elastic body arranged on a rigid body abuts against the second main surface 102 side. The rigid body is made of metal, and the elastic body is made of resin. The elastic body is, for example, a PET film. Because the conductive paste layers that form the first internal electrode layers 120 and second internal electrode layers 130 around the first via conductors 140 and second via conductors 150 are smaller than those in the internal layer portion E, the ceramic green sheets that form the second external layer portions 112 covering the first via conductors 140 and second via conductors 150 are pressed against the elastic body and pushed into the green laminate. As a result, a recess C is formed in the second region A2 of the second main surface 102.

[0039] The first end faces T of the first via conductors 140 and the second via conductors 150 that are in contact with the elastic body are substantially flat, but the second outer layer portion 112 is pressed into parts of the second end faces B of the first via conductors 140 and the second via conductors 150 by an amount corresponding to a decrease in the filling rate of the conductive paste in the via conductor through holes. As a result, parts of the second end faces B of the first via conductors 140 and the second via conductors 150 are recessed toward the first main surface 101 in the stacking direction. In this embodiment, the second end faces B of the first via conductors 140 and the second via conductors 150 are curved in a concave shape toward the first main surface 101 in the stacking direction.

[0040] Next, the green laminate is fired (S7), which sinters both the dielectric material contained in the ceramic green sheets and the conductive material contained in the conductive paste.

[0041] The above manufacturing method produces the multilayer ceramic capacitor 100. When external electrodes are to be formed, a conductive paste that will become the external electrodes may be applied before firing, or the external electrodes may be formed by plating after firing.

[0042] In the multilayer ceramic capacitor 100 according to this embodiment, a portion of the second end face B of at least one of the plurality of first via conductors 140 and the plurality of second via conductors 150 is recessed toward the first main surface 101 in the stacking direction. On the second main surface 102, if the region overlapping with the inner layer portion E in the stacking direction is defined as the first region A1, the region not overlapping with the inner layer portion E is defined as the second region A2, and the region overlapping with at least one of the plurality of first via conductors 140 and the plurality of second via conductors 150 is defined as the third region A3, a recess C recessed in the stacking direction is formed within the second region A2, and the maximum thickness G1 in the stacking direction of the second outer layer portion 112 located between the third region A3 and the second end face B is thicker than the minimum thickness G2 in the stacking direction of the second outer layer portion 112 located between the third region A3 and the internal electrode layer among the plurality of first internal electrode layers 120 and the plurality of second internal electrode layers 130 that is located closest to the third region A3 in the stacking direction.

[0043] This allows the multilayer ceramic capacitor 100 to be made thinner and have a higher capacity, while improving the mechanical durability and moisture resistance reliability of the second outer layer portion 112, which is the portion of the dielectric layer 110 covering at least one of the multiple first via conductors 140 and the multiple second via conductors 150.

[0044] Hereinafter, a multilayer ceramic capacitor according to an example will be described. Fig. 6 is an enlarged image of the periphery of a first via conductor in the multilayer ceramic capacitor according to the example. The enlarged image shown in Fig. 6 was captured using a digital microscope (VHX-8000) manufactured by Keyence Corporation.

[0045] 6 , a portion of the second end face B of the first via conductor 140 is recessed toward the first main surface 101 in the stacking direction. In the example, the diameter of each of the first via conductor 140 and the second via conductor 150 is 40 μm, which is within a range of 35 μm to 70 μm. The maximum depth D of the recess C in the stacking direction is 2 μm, which is within a range of 1 μm to 2.5 μm.

[0046] The second outer layer portion 112 located between the third region A3 and the second end face B has a maximum thickness G1 of 16 μm in the stacking direction, and the second outer layer portion 112 located between the third region A3 and the first inner electrode layer 120 that is located closest to the third region A3 in the stacking direction among the first inner electrode layer 120 and the second inner electrode layer 130 has a minimum thickness G2 of 10.8 μm in the stacking direction. Note that it is sufficient that the relationship G1 > G2 is satisfied, and within the range in which the relationship G1 > G2 is satisfied, the maximum thickness G1 is, for example, 12 μm or more and 16 μm or less, and the minimum thickness G2 is, for example, 8 μm or more and 12 μm or less.

[0047] In this example, the difference between the maximum thickness G1 and the minimum thickness G2 is 5.2 μm, which is within the range of 2 μm or more. The ratio of the difference between the maximum thickness G1 and the minimum thickness G2 to the dimension of the maximum depth D is 2.6, which is within the range of 0.8 or more.

[0048] The multilayer ceramic capacitor according to the example satisfies the above-mentioned numerical ranges for the dimensions and dimensional relationships, thereby improving the mechanical durability of the second outer layer portion 112 in the portion covering the first via conductor 140 and the second via conductor 150. This makes it difficult for cracks to occur in the second outer layer portion 112 in this portion, thereby improving the moisture resistance reliability of the multilayer ceramic capacitor while achieving a thinner and higher capacitance. It is preferable that the above-mentioned dimensions and dimensional relationships are satisfied for all recesses C in any longitudinal cross section.

[0049] The arrangement of the first via conductors 140 and the second via conductors 150 is not limited to the arrangements shown in the above-described embodiments and examples. FIG. 7 is a plan view of a multilayer ceramic capacitor according to a modified example of an embodiment of the present invention, viewed from the first main surface side. As shown in FIG. 7 , in a multilayer ceramic capacitor 100a according to a modified example of an embodiment of the present invention, the multiple first via conductors 140 are arranged in a zigzag pattern along the diagonal of the outline of the first main surface 101, as viewed from the stacking direction. The multiple second via conductors 150 are arranged in a zigzag pattern along the diagonal of the outline of the first main surface 101, as viewed from the stacking direction. The first via conductors 140 and the second via conductors 150 are arranged side by side in a matrix. By arranging the multiple first via conductors 140 and the multiple second via conductors 150 alternately as described above, magnetic fields induced by currents flowing through the first via conductors 140 and the second via conductors 150 cancel each other out, thereby reducing the equivalent series inductance (ESL) of the multilayer ceramic capacitor 100a.

[0050] In the above-described embodiments and examples, configurations that can be combined may be combined with each other.

[0051] The embodiments and examples disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0052] 10 laminate, 100 multilayer ceramic capacitor, 101 first main surface, 102 second main surface, 103 first side surface, 104 second side surface, 105 third side surface, 106 fourth side surface, 110 dielectric layer, 111 first outer layer portion, 112 second outer layer portion, 120 first internal electrode layer, 120h first through hole, 130 second internal electrode layer, 130h second through hole, 140 first via conductor, 150 second via conductor, A1 first region, A2 second region, A3 third region, B second end face, C recess, D maximum depth, E internal layer portion, G1 maximum thickness, G2 minimum thickness, T first end face.

Claims

1. A stacked body including a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately stacked in a stacking direction with a dielectric layer interposed therebetween, and having a first main surface and a second main surface located on the opposite side of the stacking direction from the first main surface; a plurality of first via conductors provided inside the stacked body and electrically connected to the plurality of first internal electrode layers; and a plurality of second via conductors provided inside the stacked body and electrically connected to the plurality of second internal electrode layers. The stacked body includes an inner layer portion in which opposing portions of the first internal electrode layer and the second internal electrode layer facing each other are stacked in the stacking direction, a first outer layer portion adjacent to the inner layer portion in the stacking direction and constituting the first main surface, and a second outer layer portion adjacent to the inner layer portion in the stacking direction and constituting the second main surface. The first end surfaces on the first main surface side of each of the plurality of first via conductors and the plurality of second via conductors are exposed on the first main surface. The second end surfaces on the second main surface side of each of the plurality of first via conductors and the plurality of second via conductors are covered by the second outer layer portion. A part of at least one of the second end surfaces of the plurality of first via conductors and the plurality of second via conductors is recessed toward the first main surface side in the stacking direction. On the second main surface, in the stacking direction, a region overlapping the inner layer portion is defined as a first region, a region not overlapping the inner layer portion is defined as a second region, and a region overlapping at least one of the plurality of first via conductors and the plurality of second via conductors is defined as a third region. A recess recessed in the stacking direction is formed in the second region. The maximum thickness in the stacking direction of the second outer layer portion located between the third region and the second end surface is greater than the minimum thickness in the stacking direction of the second outer layer portion located between the internal electrode layer closest to the third region in the stacking direction among the plurality of first internal electrode layers and the plurality of second internal electrode layers and the third region. A multilayer ceramic capacitor.

2. The multilayer ceramic capacitor according to claim 1, wherein the dimension of the maximum depth of the recess in the stacking direction is 1 μm or more and 2.5 μm or less.

3. The multilayer ceramic capacitor according to claim 2, wherein the difference between the maximum thickness and the minimum thickness is 2 μm or more.

4. The ratio of the difference between the maximum thickness and the minimum thickness to the dimension of the maximum depth of the recess in the stacking direction is 0.8 or more. The multilayer ceramic capacitor according to claim 1.

5. The diameter of each of the plurality of first via conductors and the plurality of second via conductors is 35 μm or more and 70 μm or less. The multilayer ceramic capacitor according to any one of claims 1 to 4.

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