Member for semiconductor manufacturing apparatus

Abstract

The present invention provides a member for a semiconductor manufacturing apparatus having a wafer mounting surface which is less likely to generate particles even when a wafer slides thereon. A member for a semiconductor manufacturing apparatus includes a ceramic substrate having an upper surface with a plurality of protrusions for mounting a wafer, each of the plurality of protrusions having a top end surface, at least one of the top end surfaces having a patterned uneven shape.

Description

Semiconductor manufacturing equipment components

[0001] The present invention relates to a member for a semiconductor manufacturing device.

[0002] Conventionally, semiconductor manufacturing equipment components have been known that are used for holding wafers, controlling their temperature, transporting them, etc. These types of semiconductor manufacturing equipment components are also called wafer mounting tables, electrostatic chucks, susceptors, etc., and generally have the function of applying electrostatic attraction power to a built-in electrode to attract the wafer by electrostatic force, and some are also known to have the function of controlling the wafer temperature by flowing gas between the wafer mounting surface and the wafer to be attracted.

[0003] A known example of a semiconductor manufacturing equipment component is a ceramic substrate having an upper surface on which a wafer can be placed and a lower surface, and incorporating electrodes, and a base plate located on the lower surface of the ceramic substrate and incorporating a coolant flow path. The upper surface on which the wafer can be placed is provided with multiple protrusions for supporting the wafer.

[0004] Patent Document 1 describes that a plurality of convex portions (corresponding to "protrusions") are formed on a substrate-facing surface (corresponding to an "upper surface on which a wafer can be placed") of a chuck body (corresponding to a "ceramic substrate") formed of first ceramic particles. Patent Document 1 also describes that at least a portion of the convex portions, excluding a tip-side layer, is formed of second ceramic particles having a particle major axis of 20 μm to 2000 μm and has a porosity of 0.1% to 1.0%. Patent Document 1 further describes that the surface roughness of the leading-edge surface of the convex portions is 0.01 μm or less in arithmetic mean roughness Ra, that the tip-side layer of each convex portion is a light-transmitting single crystal plate or polycrystalline plate, and that each convex portion, including the tip-side layer, is entirely formed of second ceramic particles having a particle major axis of 20 μm to 2000 μm and has a porosity of 0.1% to 1.0%.

[0005] Patent Document 1 describes the effects of the invention as follows: The base-side layer of each protrusion is densely formed from large ceramic particles. Large ceramic particles result in wide grain interfaces, and dense particles with low porosity result in strong inter-particle bonding. Therefore, when dry cleaning of a plasma processing chamber is performed using plasma, the ceramic particles constituting the base-side layer can be prevented from falling off, thereby suppressing particle generation from the electrostatic chuck. When the surface roughness of the leading edge surface, which serves as the substrate support surface, is 0.01 μm or less in arithmetic mean roughness Ra, the protrusions can be prevented from being damaged by a large localized force applied from the substrate W to the substrate support surface when the substrate W is electrostatically attracted to the electrostatic chuck. Furthermore, the contact state between the protrusions and the substrate W, which would otherwise change due to damage, can be prevented from changing the thermal conductivity between the substrate W and the electrostatic chuck. When the convex portion, including the leading edge surface, is formed of relatively large second ceramic particles having a particle length of 20 μm or more and 2000 μm or less, the particle interface of the ceramic particles is wide, so that it is possible to suppress particle shedding from the leading edge surface due to contact between the leading edge surface and the substrate W or dry cleaning inside the plasma processing chamber using plasma.

[0006] Japanese Patent Application Laid-Open No. 2023-31112

[0007] When the wafer is in contact with the upper end surfaces of the protrusions, the wafer may slide against the upper end surfaces of the protrusions due to thermal expansion or the like, which may cause ceramic particles constituting the upper end surfaces of the protrusions to fall off. When the ceramic particles fall off, they adhere to the wafer as particles, which may affect the quality of the semiconductor and reduce the yield. Patent Document 1 aims to suppress the generation of particles from the electrostatic chuck by focusing on the surface roughness of the leading edge of the protrusions (convex portions) that support the wafer, the major axis of the particles in the convex portions, and the porosity of the convex portions, but there is still room for improvement.

[0008] In view of the above circumstances, an object of one embodiment of the present invention is to provide a semiconductor manufacturing equipment member having a wafer mounting surface that is less likely to generate particles even when a wafer slides on it.

[0009] The present inventors have conducted extensive research to solve the above problems and have created the present invention, which is exemplified below.

[0010] [Aspect 1] A semiconductor manufacturing equipment member comprising a ceramic substrate having an upper surface with a plurality of protrusions for mounting a wafer, the plurality of protrusions each having an upper end surface, at least one of the upper end surfaces having a patterned uneven shape. [Aspect 2] The semiconductor manufacturing equipment member according to Aspect 1, wherein at least one of the upper end surfaces having the patterned uneven shape has a pattern consisting of a plurality of streak-like protrusions extending from the center of gravity of the upper surface of the ceramic substrate toward the periphery. [Aspect 3] The semiconductor manufacturing equipment member according to Aspect 1, wherein at least one of the upper end surfaces having the patterned uneven shape has a pattern consisting of a plurality of dot-like protrusions. [Aspect 4] The semiconductor manufacturing equipment member according to Aspect 1, wherein at least one of the upper end surfaces having the patterned uneven shape has a pattern consisting of a plurality of dimples. [Aspect 5] The semiconductor manufacturing equipment member according to Aspect 1, wherein at least one of the upper end surfaces having the patterned uneven shape has a pattern consisting of a network-like protrusions in which a plurality of linear protrusions intersect. [Aspect 6] The semiconductor manufacturing equipment member according to any one of Aspects 1 to 5, wherein the patterned uneven shape has convex regions and concave regions that are lower in height than the convex regions, and a ratio of the convex regions on at least one of the upper end faces to a projected area of ​​the relevant upper end face is 50% or less. [Aspect 7] The semiconductor manufacturing equipment member according to any one of Aspects 1 to 6, wherein a ratio of a total projected area of ​​upper end faces of the plurality of protrusions to a projected area of ​​the upper face of the ceramic substrate is 3% or less. [Aspect 8] A semiconductor manufacturing equipment member comprising a ceramic substrate having an upper surface for mounting a wafer, the upper surface having one or more of the following patterned uneven shapes i) to iv): i) a pattern formed of a plurality of streak-like convex portions extending from the center of gravity of the upper surface of the ceramic substrate toward the periphery, ii) a pattern formed of a plurality of dot-like convex portions, iii) a pattern formed of a plurality of dimples, or iv) a pattern formed of a network-like convex portion in which a plurality of linear convex portions intersect.

[0011] According to a semiconductor manufacturing equipment member according to one embodiment of the present invention, particles are unlikely to be generated even when a wafer slides on a wafer-mounting surface, which contributes to improving the stability of semiconductor quality and increasing yield.

[0012] 1A is a schematic partial longitudinal sectional view of a semiconductor manufacturing equipment member according to one embodiment of the present invention (a partial sectional view when cut along a plane including the central axis of the semiconductor manufacturing equipment member). FIG. 1B is a schematic partial longitudinal sectional view of a semiconductor manufacturing equipment member according to one embodiment of the present invention (a partial sectional view when cut along a plane including the central axis of the semiconductor manufacturing equipment member). FIG. 1A is a schematic partial enlarged view of the vicinity of the area surrounded by the thick frame shown in FIG. 1B. FIG. 1B is a schematic partial enlarged view of the vicinity of the area surrounded by the thick frame shown in FIG. 1A. FIG. 1B is a schematic plan view of a wafer-mounting surface of a ceramic substrate according to one embodiment. FIG. 1C shows an example of a patterned uneven shape provided on the upper end surface of a protrusion. FIG. 1D is a manufacturing process diagram of a semiconductor manufacturing equipment member according to one embodiment of the present invention.

[0013] Next, embodiments of the present invention will be described in detail with reference to the drawings. It should be understood that the present invention is not limited to the following embodiments, and that appropriate design changes, improvements, and the like may be made based on the common knowledge of those skilled in the art without departing from the spirit of the present invention. Furthermore, in this specification, "upper" and "lower" are used for convenience to represent the relative positional relationship when the semiconductor manufacturing equipment component's ceramic substrate is placed on a horizontal surface with the upper surface facing up, and do not represent absolute positional relationships. Therefore, depending on the orientation of the semiconductor manufacturing equipment component, "upper" and "lower" may become "lower" and "upper," "left" and "right," or "front" and "rear."

[0014] 1A , a semiconductor manufacturing equipment member 10A according to one embodiment of the present invention can be used when performing processes such as CVD and etching on a wafer W using plasma. The semiconductor manufacturing equipment member 10A includes a ceramic substrate 20 having an upper surface 21 on which the wafer W can be placed and a lower surface 23, and incorporating an electrode 26. The semiconductor manufacturing equipment member 10A also includes a base plate 30 located on the lower surface 23 of the ceramic substrate 20 and incorporating a coolant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded together via a bonding layer 40.

[0015] The ceramic substrate 20 includes a central portion 20a having a circular upper surface 21 in a planar view, and an outer peripheral portion 20b having an annular upper surface 27 in a planar view, surrounding the central portion 20a. The central portion 20a of the ceramic substrate 20 may have a diameter of 190 to 450 mm and a thickness of 1 to 5 mm, for example. A wafer W can be placed on the upper surface 21 of the central portion 20a, and a focus ring can be placed on the upper surface 27 of the outer peripheral portion 20b. Hereinafter, the focus ring may be abbreviated as "FR." The upper surface 27 of the outer peripheral portion 20b is one step lower than the upper surface 21 of the central portion 20a. The lower surfaces 23 of the central portion 20a and the outer peripheral portion 20b may be flush with each other. The illustrated ceramic substrate 20 may have a central portion 20a but no outer peripheral portion 20b, i.e., it may not have the one-step lower upper surface 27.

[0016] The upper surface 21 of the ceramic substrate 20, on which a wafer W can be placed, is provided with a plurality of protrusions 22 for placing the wafer W. A seal band 25 may also be formed along the outer edge of the upper surface 21. In this case, the wafer W may be supported by the upper end surface 21c of the seal band 25 and the upper end surfaces 21a of the plurality of protrusions 22. It is preferable that the seal band 25 and the plurality of protrusions 22 have the same height. As shown in FIG. 3 , in one embodiment, a ring-shaped seal band 25 is formed along the outer edge of the upper surface 21 of the ceramic substrate 20, and a plurality of protrusions 22 are formed over the entire inner surface of the seal band 25.

[0017] 2A is a schematic enlarged partial view of the vicinity of the area surrounded by the thick frame shown in FIG. 1A, and shows a schematic structure of the protrusions 22 provided on the upper surface 21 of the ceramic substrate 20. The number density per unit area of ​​the protrusions 22 in a plan view is, for example, 1 to 150 pieces / mm 2 and the number of particles per mm can be set to 10 to 150. 2 The shape of the protrusions 22 is not limited, but may be, for example, a columnar shape such as a cylinder or a rectangular pillar. The height h of the protrusions 22 is, for example, 5 to 100 μm, and typically 10 to 30 μm. The diameter d of the protrusions 22 is, for example, 0.3 to 3.0 mm, and typically 0.8 to 2.2 mm. Here, the diameter d of the protrusions 22 refers to the circle-equivalent diameter when the protrusions 22 are viewed in plan. The portion of the upper surface 21 of the central portion 20a of the ceramic substrate 20 on which the seal band 25 and the protrusions 22 are not provided is referred to as the reference surface 21b.

[0018] Each of the plurality of protrusions 22 has an upper end surface 21a, and at least one upper end surface 21a, preferably 50% or more of the total number of protrusions 22, more preferably 80% or more of the total number of protrusions 22, and even more preferably all of the protrusions 22 have a patterned uneven shape. The patterned uneven shape can have a convex region that forms the same plane as the upper end surface 21a and a concave region that forms an area relatively lower in height than the convex region. Here, the convex region is considered to be an area that acts to contact the wafer W when a flat wafer W is placed on the upper surface 21 of the ceramic substrate 20. The concave region is considered to be an area that is relatively lower in height than the convex region and acts to prevent the wafer W from contacting the concave region when a flat wafer W is placed on the upper surface 21 of the ceramic substrate 20. Since the upper end surface 21a has a patterned uneven shape, the contact area when the wafer W comes into contact with the upper end surface 21a of the protrusions 22 is reduced, which is thought to suppress the shedding of ceramic particles constituting the protrusions 22 when the wafer W slides against the upper end surface 21a of the protrusions 22 due to thermal expansion or the like, thereby suppressing the generation of particles. For the same reason, it is preferable that the upper end surface 21c of the seal band 25 also has a patterned uneven shape.

[0019] There are no particular limitations on the structure of the patterned uneven shape, as long as the contact area between the upper end surface 21 a of the protrusions 22 and the wafer W is reduced compared to when the upper end surface 21 a of the protrusions 22 is flat. Figure 4 shows five specific examples of the patterned uneven shape when the upper end surface 21 a of the protrusions 22 is viewed in plan. The same uneven shapes as these can also be used for the upper end surface 21 c of the seal band 25.

[0020] The uneven shape of No. 1 has a pattern consisting of multiple streak-like convex portions extending from the center of gravity of the upper surface 21 of the ceramic substrate 20 toward the outer periphery. The line width of each streak-like convex portion (corresponding to the convex portion region) in a plan view can be, for example, 20 to 200 μm. When the wafer W placed on the upper surface 21 of the ceramic substrate 20 thermally expands, the wafer W tends to slide in the radial direction. Therefore, when the upper end surface 21 a of the protrusions 22 has an uneven shape with such a pattern, in addition to the effect of reducing the contact area with the wafer W, an additional effect of effectively reducing friction during sliding is also obtained.

[0021] The uneven shape of No. 2 has a pattern made up of a plurality of dot-like protrusions. Each dot-like protrusion in No. 2 is relatively small. It is preferable that the plurality of dot-like protrusions are arranged evenly on the upper end surface 21a. The area per dot-like protrusion (corresponding to a protrusion region) in a plan view is, for example, 200 to 25,000 μm 2 When the upper end surfaces 21 a of the protrusions 22 have such an uneven pattern, in addition to the effect of reducing the contact area with the wafer W, an additional effect of reducing friction during sliding of the wafer W can be obtained regardless of the sliding direction of the wafer W.

[0022] The uneven shape of No. 3 also has a pattern made up of a plurality of dot-like protrusions. Each dot-like protrusion in No. 3 is relatively large. It is preferable that the plurality of dot-like protrusions are arranged evenly on the upper end surface 21a. The area of ​​each of the plurality of dot-like protrusions (corresponding to the protrusion region) in a plan view is, for example, 2000 to 250000 μm 2 When the upper end surfaces 21 a of the protrusions 22 have such a pattern of unevenness, in addition to the effect of reducing the contact area with the wafer W, there is also the additional effect of reducing friction during sliding regardless of the sliding direction of the wafer W. The unevenness shapes of No. 2 and No. 3 differ in the area of ​​each dot-like protrusion when viewed in plan.

[0023] The uneven shape of No. 4 has a pattern consisting of a reference surface (corresponding to a convex region) and a plurality of dimples (point-like concave portions) provided on the reference surface. The plurality of dimples are preferably arranged evenly on the upper end surface 21a. The area per dimple in a plan view is, for example, 200 to 25,000 μm 2 When the upper end surface 21 a of the protrusions 22 has such a pattern of unevenness, in addition to the effect of reducing the contact area with the wafer W, there is also an additional effect of reducing friction during sliding regardless of the sliding direction of the wafer W. It is also considered that when particles fall off, the inside of the dimples serves as an escape route, making it less likely for the particles to adhere to the wafer W.

[0024] The uneven shape of No. 5 has a pattern composed of a network of convex portions in which a plurality of linear convex portions (corresponding to convex portion regions) intersect. In the illustrated embodiment, each mesh of the network of convex portions is hexagonal (honeycomb-shaped), but each mesh of the network of convex portions may be other polygonal shapes such as triangles, squares, pentagons, and octagons, or may be a combination of multiple polygonal shapes such as pentagons and triangles. The line width per linear convex portion in plan view can be, for example, 20 to 200 μm. The area of ​​each mesh in plan view can be, for example, 2,000 to 250,000 μm. 2 When the upper end surfaces 21 a of the protrusions 22 have such an uneven pattern, in addition to the effect of reducing the contact area with the wafer W, an additional effect of reducing friction during sliding of the wafer W can be obtained regardless of the sliding direction of the wafer W.

[0025] With regard to the patterned uneven shape on the upper end surfaces 21a of the plurality of protrusions 22, from the viewpoint of suppressing shedding of ceramic particles constituting the protrusions 22 by reducing the contact area with the wafer W, the ratio of the convex region on at least one upper end surface 21a to the projected area of ​​the upper end surface 21a is preferably 50% or less, more preferably 40% or less, and even more preferably 35% or less. On the other hand, with regard to the patterned uneven shape on the upper end surfaces 21a of the plurality of protrusions 22, from the viewpoint of suppressing shedding of ceramic particles by preventing excessive surface pressure when the wafer W is placed on the upper end surfaces 21a, and from the viewpoint of effectively utilizing the protrusions 22, the ratio of the convex region on at least one upper end surface 21a to the projected area of ​​the upper end surface 21a is preferably 10% or more, more preferably 20% or more, and even more preferably 25% or more. Therefore, the ratio of the convex region on at least one upper end surface 21a to the projected area of ​​the upper end surface 21a is, for example, preferably 10 to 50%, more preferably 20 to 40%, and even more preferably 25 to 35%.

[0026] It is desirable that the upper end surface 21a of at least one of the multiple protrusions 22, preferably the upper end surfaces 21a of 50% or more of the total number of protrusions 22, more preferably the upper end surfaces 21a of 80% or more of the total number of protrusions 22, and even more preferably the upper end surfaces 21a of all protrusions 22 each satisfy the area ratio of the convex region described above.

[0027] The projected area of ​​the upper end surface 21a of the protrusion 22 is defined by identifying the area of ​​the protrusion 22 to be measured that protrudes above the reference surface 21b of the upper surface 21 of the ceramic substrate 20, and is defined as the area enclosed by that area when viewed in a plane.

[0028] From the viewpoint of suppressing shedding of ceramic particles constituting the protrusions 22 by reducing the contact area with the wafer W, it is desirable that the ratio of the total projected area of ​​the upper end faces 21a of the multiple protrusions 22 to the projected area of ​​the upper surface 21 of the ceramic substrate 20 be small. Specifically, this ratio is preferably 3% or less, and may be 2.5% or less, or may be 2% or less. On the other hand, from the viewpoint of suppressing shedding of ceramic particles by preventing excessive surface pressure when the wafer W is placed on the protrusions 22, this ratio is preferably 0.5% or more, more preferably 0.7% or more, and even more preferably 1% or more. Therefore, the ratio of the total projected area of ​​the upper end faces 21a of the multiple protrusions 22 to the projected area of ​​the upper surface 21 of the ceramic substrate 20 may be, for example, 0.5 to 3%, 0.7 to 2.5%, or 1 to 2%.

[0029] At least the upper end surfaces 21 a of the plurality of protrusions 22 may be covered with a coating film. Examples of the coating film include a coating film containing at least one selected from silicon carbide, diamond-like carbon, amorphous silicon, molybdenum, chromium, and tantalum.

[0030] The ceramic substrate 20, including the protrusions 22 and the seal band 25, can be formed from a ceramic material such as alumina or aluminum nitride. In a preferred embodiment, the ceramic particles constituting the plurality of protrusions 22 contain one or two types selected from alumina and aluminum nitride. In a more preferred embodiment, the ceramic particles constituting the plurality of protrusions 22 contain 80 mass % or more of one or two types selected from alumina and aluminum nitride. In an even more preferred embodiment, the ceramic particles constituting the plurality of protrusions 22 contain 95 mass % or more of one or two types selected from alumina and aluminum nitride.

[0031] The electrode 26 is a planar electrode used as an electrostatic electrode and is connected to an external DC power supply via a power supply member (not shown). The electrode 26 is formed of a material containing, for example, W, Mo, WC, or MoC. A low-pass filter may be disposed midway along the power supply member. The power supply member is electrically insulated from the bonding layer 40 and the base plate 30. When a DC voltage is applied to the electrode 26, the wafer W is attracted and fixed to the wafer mounting surface, specifically, the upper end surface 21 c of the seal band 25 and the upper end surface 21 a of the protrusions 22, by electrostatic attraction. When the application of the DC voltage is stopped, the wafer W is released from the wafer mounting surface.

[0032] Instead of or in addition to an electrode for electrostatic attraction, a heater electrode (resistance heating element) or an RF electrode for generating plasma may be built in as the electrode 26. In this case, a heater power supply is connected to the heater electrode, and an RF power supply is connected to the RF electrode. The ceramic substrate 20 may have one layer of the electrode 26 built in, or two or more layers of the electrode 26 built in with gaps between them.

[0033] The base plate 30 may be, for example, disk-shaped. The base plate 30 may have an annular flange portion on its lower surface that is used to clamp the semiconductor manufacturing equipment member 10A to a jig in the chamber. The thickness of the base plate 30 may be 20 to 40 mm, typically 25 to 35 mm. The base plate 30 is connected to a radio frequency (RF) power source and can also be used as an RF electrode.

[0034] The base plate 30 may be a circular plate (having the same diameter as or larger than the ceramic substrate 20) with good electrical and thermal conductivity. A refrigerant flow path 32 through which a refrigerant circulates may be formed within the base plate 30. The refrigerant flowing through the refrigerant flow path 32 is preferably a liquid, preferably electrically insulating. Examples of electrically insulating liquids include a fluorine-based inert liquid. The refrigerant flow path 32 may be formed, for example, in a single stroke across the entire base plate 30 in a plan view from one end (inlet) to the other end (outlet). One end and the other end of the refrigerant flow path 32 are connected to a supply port and a recovery port of an external refrigerant device (not shown), respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, has its temperature adjusted, and is then supplied again from the supply port to one end of the refrigerant flow path 32.

[0035] The base plate 30 can be made of, for example, a metal material or a composite material of metal and ceramic. Examples of metal materials include Al, Ti, Mo, and alloys thereof. Examples of composite materials of metal and ceramic include metal matrix composites (MMCs) and ceramic matrix composites (CMCs). Specific examples of such composite materials include a material containing Si, SiC, and Ti (also known as SiSiCTi), a material in which porous SiC is impregnated with Al and / or Si, and a composite material of Al2O3 and TiC. A material in which porous SiC is impregnated with Al is called AlSiC, and a material in which porous SiC is impregnated with Si is called SiSiC. It is preferable to select a material for the base plate 30 that has a thermal expansion coefficient similar to that of the material for the ceramic substrate 20. For example, if the ceramic substrate 20 is made of alumina, the base plate 30 is preferably made of SiSiCTi or AlSiC, which have a thermal expansion coefficient similar to that of alumina.

[0036] As shown in FIG. 1A , the upper surface 31 of the base plate 30 is bonded to the lower surface 23 of the ceramic substrate 20 via a bonding layer 40. The bonding layer 40 bonds the lower surface 23 of the ceramic substrate 20 to the upper surface 31 of the base plate 30. The bonding layer 40 may be formed, for example, by a metal layer made of solder or a metal brazing material. The bonding layer 40 may be formed, for example, by thermal compression bonding (TCB). TCB refers to a known method in which a metal bonding material is sandwiched between two components to be bonded and the two components are pressure-bonded while heated to a temperature below the solidus temperature of the metal bonding material. The bonding layer 40 is not limited to a metal layer. For example, a resin bonding layer may be used instead of the metal layer. The resin bonding layer may be formed, for example, by a cured product of a silicone resin adhesive, an epoxy resin adhesive, an acrylic resin adhesive, or a urethane resin adhesive.

[0037] At least one of the side surface of the ceramic substrate 20, the outer periphery of the bonding layer 40, and the side surface of the base plate 30 can be covered with an insulating film 60. Examples of the insulating film 60 include a thermally sprayed film of alumina, yttria, or the like.

[0038] In the above-described embodiment, the semiconductor manufacturing equipment component 10A may have multiple holes penetrating the semiconductor manufacturing equipment component 10A in the vertical direction. Examples of such holes include multiple gas holes 50 opening in the upper surface 21 and lift pin holes for inserting lift pins that move the wafer W up and down relative to the upper surface 21. Multiple gas holes 50 can be provided at appropriate positions when the upper surface 21 is viewed from above (see FIG. 3 ). A thermally conductive gas such as He gas is supplied to the gas holes 50. Typically, the gas holes 50 are provided so as to open to a portion of the upper surface 21 where the seal band 25 and multiple protrusions 22 are not provided (reference surface 21b). When the thermally conductive gas is supplied to the gas holes 50, the thermally conductive gas fills the space on the backside of the wafer W placed on the upper surface 21. A plug 55 having a gas flow path may be embedded in the gas holes 50. A plurality of lift pin holes can be provided at equal intervals along concentric circles on the upper surface 21 when the upper surface 21 is viewed in plan view.

[0039] 2. Method of Using the Semiconductor Manufacturing Equipment Member Next, an example of how to use the semiconductor manufacturing equipment member 10A will be described. First, with the semiconductor manufacturing equipment member 10A installed in a chamber (not shown), a wafer W is placed on the upper surface 21 of the ceramic substrate 20. The chamber is then depressurized using a vacuum pump to adjust the chamber to a predetermined degree of vacuum, and a voltage is applied to the electrodes 26 of the ceramic substrate 20 to generate an electrostatic adsorption force, thereby adsorbing and fixing the wafer W to the wafer mounting surface (specifically, the upper end surfaces 21c of the seal bands 25 and the upper end surfaces 21a of the protrusions 22).

[0040] Next, the chamber is filled with a reactive gas atmosphere at a predetermined pressure (for example, several tens to several hundreds of Pa), and in this state, a high-frequency voltage such as an RF voltage is applied between an upper electrode (not shown) provided on the ceiling of the chamber and the base plate 30 of the semiconductor manufacturing equipment member 10A to generate plasma. The surface of the wafer W is processed by the generated plasma.

[0041] 3. Manufacturing Example of a Semiconductor Manufacturing Equipment Component Next, a manufacturing example of a semiconductor manufacturing equipment component 10A will be described with reference to FIG. 5. First, a disk-shaped ceramic sintered body 120, which is the base of the ceramic substrate 20, is produced by hot-press sintering a ceramic powder compact (FIG. 5A). The compact may be produced by stacking multiple tape compacts, by mold casting, or by compressing ceramic powder. The ceramic sintered body 120 has an electrode 26 built in.

[0042] Next, a plurality of protrusions 22 are provided on the upper surface of the ceramic sintered body 120 by laser processing ( FIG. 5B ). A patterned uneven shape is formed on the upper end surface 21 a of each protrusion 22 by laser processing. The timing for forming the plurality of protrusions 22 may be after the ceramic substrate 20 and the base plate 30 are bonded together.

[0043] In parallel with this, two MMC disk members 131 and 136 are fabricated ( FIG. 5C ). Then, grooves 132 that will ultimately become the coolant flow paths 32 are formed in the lower surface of the upper MMC disk member 131 by machining ( FIG. 5D ). Through-holes 133 for introducing the coolant and through-holes 134 for discharging the coolant are drilled in the lower MMC disk member 136. When the ceramic sintered body 120 is made of alumina, the MMC disk members 131 and 136 are preferably made of SiSiCTi or AlSiC. This is because the thermal expansion coefficient of alumina is roughly the same as that of SiSiCTi or AlSiC.

[0044] The SiSiCTi disk member can be fabricated, for example, as follows: First, silicon carbide, metallic Si, and metallic Ti are mixed to prepare a powder mixture. Next, the resulting powder mixture is subjected to uniaxial pressing to produce a disk-shaped compact, which is then hot-press sintered in an inert atmosphere to obtain the SiSiCTi disk member.

[0045] Next, a metal bonding material 135 is placed between the lower surface of the upper MMC disk member 131 and the upper surface of the lower MMC disk member 136, and a metal bonding material 137 is placed on the upper surface of the upper MMC disk member 131. The ceramic sintered body 120 is then placed on the metal bonding material 137 placed on the upper surface of the upper MMC disk member 131. This results in a laminate 110 in which the lower MMC disk member 136, the metal bonding material 135, the upper MMC disk member 131, the metal bonding material 137, and the ceramic sintered body 120 are stacked in this order from bottom to top ( FIG. 5E ). This laminate 110 is then heated and pressurized (TCB) to obtain a bonded body. The bonded body is composed of the ceramic sintered body 120 bonded to the upper surface of the MMC block 130, which will become the base plate 30, via a metal bonding layer. The MMC block 130 is formed by joining an upper MMC disk member 131 and a lower MMC disk member 136 via a metal joining layer. The MMC block 130 has a coolant flow path 32, a coolant inlet 36, and a coolant outlet 38.

[0046] TCB is performed, for example, as follows. That is, the laminate is pressed and bonded at a temperature below the solidus temperature of the metal bonding material (for example, a temperature equal to or higher than the solidus temperature minus 20°C and lower than the solidus temperature), and then returned to room temperature. As a result, the metal bonding material becomes a metal bonding layer. As the metal bonding material, an Al-Mg based bonding material or an Al-Si-Mg based bonding material can be used. For example, when TCB is performed using an Al-Si-Mg based bonding material, the laminate is pressed while heated in a vacuum atmosphere. It is preferable to use a metal bonding material with a thickness of about 100 μm.

[0047] Next, the outer periphery of the ceramic sintered body 120 is cut to form a step, thereby forming a ceramic substrate 20 having a central portion 20a and an outer periphery 20b, thereby obtaining a semiconductor manufacturing equipment member 10A (FIG. 5F).

[0048] 1A is shown as an integrated product, it may have a structure in which two members are bonded with a metal bonding layer, or a structure in which three or more members are bonded with a metal bonding layer, as shown in FIG. 5F. When forming the bonding layer 40 using a metal bonding material 137, the insulating film 60 can be formed on the base plate 30 by thermal spraying either before or after bonding to the ceramic substrate 20. When forming the bonding layer 40 using a resin adhesive sheet, the resin melts, so the insulating film 60 is formed by thermal spraying before bonding to the ceramic substrate 20.

[0049] 4. Other Embodiments In the semiconductor manufacturing equipment member 10A according to the embodiment described above, the upper surface 21 of the ceramic substrate 20 has a plurality of protrusions 22, and the patterned uneven shape is formed on the upper end surfaces of the protrusions 22, but the patterned uneven shape can also be formed without providing the protrusions 22. Referring to Figures 1B and 2B, the semiconductor manufacturing equipment member 10B according to one embodiment of the present invention is a ceramic substrate 20 having an upper surface 21 on which a wafer W is placed, and the upper surface 21 has a patterned uneven shape.

[0050] The upper surface 21 is not provided with protrusions 22, but instead has one or more of the following patterned uneven shapes i) to iv): i) a pattern consisting of a plurality of streak-like protrusions extending from the center of gravity of the upper surface 21 of the ceramic substrate 20 toward the periphery; ii) a pattern consisting of a plurality of dot-like protrusions; iii) a pattern consisting of a plurality of dimples; and iv) a pattern consisting of a network-like protrusion in which a plurality of linear protrusions intersect.

[0051] The patterned uneven shape can have convex regions that form the same plane as the upper surface 21 and concave regions that form regions that are relatively lower in height than the convex regions. Here, the convex regions are considered to be regions that act to contact the wafer W when a flat wafer W is placed on the upper surface 21 of the ceramic substrate 20. The concave regions are considered to be regions that are relatively lower in height than the convex regions and act to prevent the wafer W from contacting the concave regions when a flat wafer W is placed on the upper surface 21 of the ceramic substrate 20. Since the upper surface 21 has a patterned uneven shape, the contact area when the wafer W comes into contact with the upper surface 21 of the protrusions 22 is reduced, and it is thought that shedding of ceramic particles that form the upper surface 21 is suppressed when the wafer W slides against the upper surface 21 due to thermal expansion, etc., and the generation of particles is suppressed.

[0052] With regard to the patterned uneven shape on the upper surface 21, from the viewpoint of reducing the contact area with the wafer W and thereby suppressing the shedding of ceramic particles constituting the upper surface 21, the ratio of the convex region on the upper surface 21 to the projected area of ​​the upper surface 21 is preferably 50% or less, more preferably 30% or less, and even more preferably 10% or less. On the other hand, with regard to the patterned uneven shape on the upper surface 21, from the viewpoint of preventing the shedding of ceramic particles by preventing the surface pressure from becoming too high when the wafer W is placed on the upper surface 21, the ratio of the convex region on the upper surface 21 to the projected area of ​​the upper surface 21 is preferably 3% or more, more preferably 5% or more, and even more preferably 7% or more. Therefore, the ratio of the convex region on the upper surface 21 to the projected area of ​​the upper surface 21 is, for example, preferably 3 to 50%, more preferably 5 to 30%, and even more preferably 7 to 10%.

[0053] i) A pattern consisting of a plurality of streak-like protrusions extending from the center of gravity of the upper surface 21 of the ceramic substrate 20 toward the periphery is exemplified by the uneven shape No. 1 in Fig. 4. The line width of each streak-like protrusion (corresponding to the protrusion region) in a plan view can be, for example, 20 to 200 µm.

[0054] ii) A pattern consisting of a plurality of dot-like protrusions is exemplified by the uneven shapes of No. 2 and No. 3 in Fig. 4. Each dot-like protrusion in No. 2 is relatively small. It is preferable that the plurality of dot-like protrusions are arranged evenly on the upper surface 21. The number density of the dot-like protrusions per unit area in a plan view is, for example, 0.05 to 7 pieces / mm 2 Each of the point-like protrusions in No. 3 is relatively large. It is preferable that the plurality of point-like protrusions are arranged evenly on the upper surface 21. The number density of the point-like protrusions per unit area in a plan view is, for example, 0.003 to 0.15 pieces / mm 2 It can be said that:

[0055] iii) A pattern consisting of a plurality of dimples is exemplified by the uneven shape No. 4 in Figure 4. The uneven shape No. 4 has a pattern consisting of a reference surface (corresponding to a convex region) and a plurality of dimples (point-like concave portions) provided on the reference surface. The plurality of dimples are preferably arranged evenly on the top surface 21. The number density of the dimples per unit area in a plan view is, for example, 0.05 to 7 dimples / mm. 2 It can be said that:

[0056] iv) A pattern consisting of a network-like convex portion in which a plurality of linear convex portions (corresponding to convex portion regions) intersect is exemplified by the uneven shape No. 5 in Figure 4. In the illustrated embodiment, each mesh of the network-like convex portion is hexagonal (honeycomb-shaped), but each mesh of the network-like convex portion may be other polygonal shapes such as triangles, squares, pentagons, and octagons, or may be a combination of multiple polygonal shapes such as pentagons and triangles. The line width per linear convex portion in plan view can be, for example, 20 to 200 μm. The number density per unit area of ​​each mesh in plan view can be, for example, 0.003 to 0.15 pieces / mm 2 It can be said that:

[0057] The semiconductor manufacturing equipment member 10B according to this embodiment is similar to the semiconductor manufacturing equipment member 10A according to the above embodiment except for the structure of the upper surface 21 of the ceramic substrate 20, and therefore a duplicated description will be omitted.

[0058] DESCRIPTION OF SYMBOLS 10A: Semiconductor manufacturing equipment member 10B: Semiconductor manufacturing equipment member 20: Ceramic substrate 20a: Central portion 20b: Peripheral portion 21: Upper surface 21a: Upper end surface 21b: Reference surface 21c: Upper end surface 22: Protrusion 23: Lower surface 25: Seal band 26: Electrode 27: Upper surface 30: Base plate 31: Upper surface 32: Coolant flow path 36: Coolant inlet portion 38: Coolant outlet portion 40: Bonding layer 50: Gas hole 55: Plug 60: Insulating film 110: Laminated body 120: Ceramic sintered body 130: MMC block 131: MMC disc member 132: Groove 133: Through hole 134: Through hole 135: Metal bonding material 136: Disk member 137: Metal bonding material W: Wafer

Claims

1. A ceramic substrate having an upper surface with a plurality of protrusions for placing a wafer, wherein each of the plurality of protrusions has an upper end surface, and at least one of the upper end surfaces has a patterned concavo-convex shape, and the member for a semiconductor manufacturing apparatus includes the ceramic substrate.

2. The member for a semiconductor manufacturing apparatus according to claim 1, wherein at least one of the upper end surfaces having the patterned concavo-convex shape has a pattern composed of a plurality of rib-shaped convex portions extending from the center of gravity of the upper surface of the ceramic substrate toward the outer periphery.

3. The member for a semiconductor manufacturing apparatus according to claim 1, wherein at least one of the upper end surfaces having the patterned concavo-convex shape has a pattern composed of a plurality of dot-shaped convex portions.

4. The member for a semiconductor manufacturing apparatus according to claim 1, wherein at least one of the upper end surfaces having the patterned concavo-convex shape has a pattern composed of a plurality of dimples.

5. The member for a semiconductor manufacturing apparatus according to claim 1, wherein at least one of the upper end surfaces having the patterned concavo-convex shape has a pattern composed of a network-shaped convex portion in which a plurality of linear convex portions intersect.

6. The patterned concavo-convex shape has a convex portion region and a concave portion region having a height lower than that of the convex portion region, and the ratio of the convex portion region in the upper end surface to the projected area of the upper end surface is 50% or less with respect to the projected area of at least one of the upper end surfaces. The member for a semiconductor manufacturing apparatus according to any one of claims 1 to 5.

7. The member for a semiconductor manufacturing apparatus according to any one of claims 1 to 5, wherein the ratio of the total projected area of the upper end surfaces of the plurality of protrusions to the projected area of the upper surface of the ceramic substrate is 3% or less.

8. A ceramic substrate having an upper surface for placing a wafer, wherein the upper surface has a patterned concavo-convex shape of any one or two or more of the following i) to iv), and the member for a semiconductor manufacturing apparatus includes the ceramic substrate: i) a pattern composed of a plurality of rib-shaped convex portions extending from the center of gravity of the upper surface of the ceramic substrate toward the outer periphery; ii) a pattern composed of a plurality of dot-shaped convex portions; iii) a pattern composed of a plurality of dimples; iv) a pattern composed of a network-shaped convex portion in which a plurality of linear convex portions intersect.

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